eth_ocm/eth_random.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  eth_random.v                                                ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects/ethmac/                   ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Igor Mohor (igorM@opencores.org)                      ////
  10 ////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
  11 ////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
  12 ////                                                              ////
  13 ////  All additional information is avaliable in the Readme.txt   ////
  14 ////  file.                                                       ////
  15 ////                                                              ////
  16 //////////////////////////////////////////////////////////////////////
  17 ////                                                              ////
  18 //// Copyright (C) 2001 Authors                                   ////
  19 ////                                                              ////
  20 //// This source file may be used and distributed without         ////
  21 //// restriction provided that this copyright statement is not    ////
  22 //// removed from the file and that any derivative work contains  ////
  23 //// the original copyright notice and the associated disclaimer. ////
  24 ////                                                              ////
  25 //// This source file is free software; you can redistribute it   ////
  26 //// and/or modify it under the terms of the GNU Lesser General   ////
  27 //// Public License as published by the Free Software Foundation; ////
  28 //// either version 2.1 of the License, or (at your option) any   ////
  29 //// later version.                                               ////
  30 ////                                                              ////
  31 //// This source is distributed in the hope that it will be       ////
  32 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  33 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  34 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  35 //// details.                                                     ////
  36 ////                                                              ////
  37 //// You should have received a copy of the GNU Lesser General    ////
  38 //// Public License along with this source; if not, download it   ////
  39 //// from http://www.opencores.org/lgpl.shtml                     ////
  40 ////                                                              ////
  41 //////////////////////////////////////////////////////////////////////
  42 //
  43 // CVS Revision History
  44 //
  45 // $Log: eth_random.v,v $
  46 // Revision 1.4  2003/06/13 11:26:08  mohor
  47 // Binary operator used instead of unary (xnor).
  48 //
  49 // Revision 1.3  2002/01/23 10:28:16  mohor
  50 // Link in the header changed.
  51 //
  52 // Revision 1.2  2001/10/19 08:43:51  mohor
  53 // eth_timescale.v changed to timescale.v This is done because of the
  54 // simulation of the few cores in a one joined project.
  55 //
  56 // Revision 1.1  2001/08/06 14:44:29  mohor
  57 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
  58 // Include files fixed to contain no path.
  59 // File names and module names changed ta have a eth_ prologue in the name.
  60 // File eth_timescale.v is used to define timescale
  61 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
  62 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
  63 // and Mdo_OE. The bidirectional signal must be created on the top level. This
  64 // is done due to the ASIC tools.
  65 //
  66 // Revision 1.1  2001/07/30 21:23:42  mohor
  67 // Directory structure changed. Files checked and joind together.
  68 //
  69 // Revision 1.3  2001/06/19 18:16:40  mohor
  70 // TxClk changed to MTxClk (as discribed in the documentation).
  71 // Crc changed so only one file can be used instead of two.
  72 //
  73 // Revision 1.2  2001/06/19 10:38:07  mohor
  74 // Minor changes in header.
  75 //
  76 // Revision 1.1  2001/06/19 10:27:57  mohor
  77 // TxEthMAC initial release.
  78 //
  79 //
  80 //
  81 //
  82
  83 `include "timescale.v"
  84
  85 module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
  86                    RandomEq0, RandomEqByteCnt);
  87
  88 parameter Tp = 1;
  89
  90 input MTxClk;
  91 input Reset;
  92 input StateJam;
  93 input StateJam_q;
  94 input [3:0] RetryCnt;
  95 input [15:0] NibCnt;
  96 input [9:0] ByteCnt;
  97 output RandomEq0;
  98 output RandomEqByteCnt;
  99
 100 wire Feedback;
 101 reg [9:0] x;
 102 wire [9:0] Random;
 103 reg  [9:0] RandomLatched;
 104
 105
 106 always @ (posedge MTxClk or posedge Reset)
 107 begin
 108   if(Reset)
 109     x[9:0] <= #Tp 0;
 110   else
 111     x[9:0] <= #Tp {x[8:0], Feedback};
 112 end
 113
 114 assign Feedback = ~(x[2] ^ x[9]);
 115
 116 assign Random [0] = x[0];
 117 assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0;
 118 assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0;
 119 assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0;
 120 assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0;
 121 assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0;
 122 assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0;
 123 assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0;
 124 assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0;
 125 assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0;
 126
 127
 128 always @ (posedge MTxClk or posedge Reset)
 129 begin
 130   if(Reset)
 131     RandomLatched <= #Tp 10'h000;
 132   else
 133     begin
 134       if(StateJam & StateJam_q)
 135         RandomLatched <= #Tp Random;
 136     end
 137 end
 138
 139 // Random Number == 0      IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
 140 assign RandomEq0 = RandomLatched == 10'h0;
 141
 142 assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]);
 143
 144 endmodule