eth_ocm/eth_avalon_bd_ram.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  eth_avalon_bd_ram.v                                         ////
   4 ////                                                              ////
   5 ////  This file is a patch used in conjunction with the           ////
   6 ////  Ethernet IP core project.                                   ////
   7 ////  http://www.opencores.org/projects/ethmac/                   ////
   8 ////                                                              ////
   9 ////  Author(s):                                                  ////
  10 ////      - Jakob Jones (jrjonsie@gmail.com)                      ////
  11 ////                                                              ////
  12 ////  All additional information is available in the Readme.txt   ////
  13 ////  file.                                                       ////
  14 ////                                                              ////
  15 //////////////////////////////////////////////////////////////////////
  16 module eth_avalon_bd_ram #( parameter   DEPTH=128   ) (
  17     input                           clock,
  18     //port A
  19     input                           wren_a,
  20     input       [clogb2(DEPTH-1):0] address_a,
  21     input       [31:0]              data_a,
  22     output      [31:0]              q_a,
  23     //port B
  24     input                           wren_b,
  25     input       [clogb2(DEPTH-1):0] address_b,
  26     input       [31:0]              data_b,
  27     output      [31:0]              q_b
  28     );
  29
  30 `include "eth_avalon_functions.v"
  31
  32 altsyncram  altsyncram_component (
  33     .wren_a         (wren_a     ),
  34     .clock0         (clock      ),
  35     .wren_b         (wren_b     ),
  36     .address_a      (address_a  ),
  37     .address_b      (address_b  ),
  38     .data_a         (data_a     ),
  39     .data_b         (data_b     ),
  40     .q_a            (q_a        ),
  41     .q_b            (q_b        ),
  42     .aclr0          (1'b0       ),
  43     .aclr1          (1'b0       ),
  44     .addressstall_a (1'b0       ),
  45     .addressstall_b (1'b0       ),
  46     .byteena_a      (1'b1       ),
  47     .byteena_b      (1'b1       ),
  48     .clock1         (1'b1       ),
  49     .clocken0       (1'b1       ),
  50     .clocken1       (1'b1       ),
  51     .clocken2       (1'b1       ),
  52     .clocken3       (1'b1       ),
  53     .eccstatus      (           ),
  54     .rden_a         (1'b1       ),
  55     .rden_b         (1'b1       )
  56 );
  57
  58     defparam
  59         altsyncram_component.address_reg_b = "CLOCK0",
  60         altsyncram_component.clock_enable_input_a = "BYPASS",
  61         altsyncram_component.clock_enable_input_b = "BYPASS",
  62         altsyncram_component.clock_enable_output_a = "BYPASS",
  63         altsyncram_component.clock_enable_output_b = "BYPASS",
  64         altsyncram_component.indata_reg_b = "CLOCK0",
  65         altsyncram_component.intended_device_family = "Cyclone II",
  66         altsyncram_component.lpm_type = "altsyncram",
  67         altsyncram_component.numwords_a = DEPTH,
  68         altsyncram_component.numwords_b = DEPTH,
  69         altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
  70         altsyncram_component.outdata_aclr_a = "NONE",
  71         altsyncram_component.outdata_aclr_b = "NONE",
  72         altsyncram_component.outdata_reg_a = "UNREGISTERED",
  73         altsyncram_component.outdata_reg_b = "UNREGISTERED",
  74         altsyncram_component.power_up_uninitialized = "FALSE",
  75         altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
  76         altsyncram_component.widthad_a = clogb2(DEPTH-1),
  77         altsyncram_component.widthad_b = clogb2(DEPTH-1),
  78         altsyncram_component.width_a = 32,
  79         altsyncram_component.width_b = 32,
  80         altsyncram_component.width_byteena_a = 1,
  81         altsyncram_component.width_byteena_b = 1,
  82         altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
  83
  84
  85 endmodule
  86
  87 // ============================================================
  88 // CNX file retrieval info
  89 // ============================================================
  90 // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
  91 // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
  92 // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
  93 // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
  94 // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
  95 // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
  96 // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
  97 // Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
  98 // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
  99 // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
 100 // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
 101 // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
 102 // Retrieval info: PRIVATE: CLRdata NUMERIC "0"
 103 // Retrieval info: PRIVATE: CLRq NUMERIC "0"
 104 // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
 105 // Retrieval info: PRIVATE: CLRrren NUMERIC "0"
 106 // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
 107 // Retrieval info: PRIVATE: CLRwren NUMERIC "0"
 108 // Retrieval info: PRIVATE: Clock NUMERIC "0"
 109 // Retrieval info: PRIVATE: Clock_A NUMERIC "0"
 110 // Retrieval info: PRIVATE: Clock_B NUMERIC "0"
 111 // Retrieval info: PRIVATE: ECC NUMERIC "0"
 112 // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
 113 // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
 114 // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
 115 // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
 116 // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
 117 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
 118 // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
 119 // Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
 120 // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
 121 // Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
 122 // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
 123 // Retrieval info: PRIVATE: MIFfilename STRING ""
 124 // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
 125 // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
 126 // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
 127 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 128 // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
 129 // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
 130 // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
 131 // Retrieval info: PRIVATE: REGdata NUMERIC "1"
 132 // Retrieval info: PRIVATE: REGq NUMERIC "0"
 133 // Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
 134 // Retrieval info: PRIVATE: REGrren NUMERIC "0"
 135 // Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
 136 // Retrieval info: PRIVATE: REGwren NUMERIC "1"
 137 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 138 // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
 139 // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
 140 // Retrieval info: PRIVATE: VarWidth NUMERIC "0"
 141 // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
 142 // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
 143 // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
 144 // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
 145 // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
 146 // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
 147 // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
 148 // Retrieval info: PRIVATE: enable NUMERIC "0"
 149 // Retrieval info: PRIVATE: rden NUMERIC "0"
 150 // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
 151 // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
 152 // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
 153 // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
 154 // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
 155 // Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
 156 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
 157 // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
 158 // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
 159 // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "128"
 160 // Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
 161 // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
 162 // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
 163 // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
 164 // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
 165 // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
 166 // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
 167 // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
 168 // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"
 169 // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
 170 // Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
 171 // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
 172 // Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
 173 // Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
 174 // Retrieval info: USED_PORT: address_a 0 0 7 0 INPUT NODEFVAL address_a[6..0]
 175 // Retrieval info: USED_PORT: address_b 0 0 7 0 INPUT NODEFVAL address_b[6..0]
 176 // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
 177 // Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL data_a[31..0]
 178 // Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL data_b[31..0]
 179 // Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL q_a[31..0]
 180 // Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL q_b[31..0]
 181 // Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
 182 // Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
 183 // Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
 184 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
 185 // Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
 186 // Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
 187 // Retrieval info: CONNECT: @address_a 0 0 7 0 address_a 0 0 7 0
 188 // Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
 189 // Retrieval info: CONNECT: @address_b 0 0 7 0 address_b 0 0 7 0
 190 // Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
 191 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
 192 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 193 // Retrieval info: GEN_FILE: TYPE_NORMAL eth_avalon_bd_ram.v TRUE
 194 // Retrieval info: GEN_FILE: TYPE_NORMAL eth_avalon_bd_ram.inc FALSE
 195 // Retrieval info: GEN_FILE: TYPE_NORMAL eth_avalon_bd_ram.cmp FALSE
 196 // Retrieval info: GEN_FILE: TYPE_NORMAL eth_avalon_bd_ram.bsf FALSE
 197 // Retrieval info: GEN_FILE: TYPE_NORMAL eth_avalon_bd_ram_inst.v FALSE
 198 // Retrieval info: GEN_FILE: TYPE_NORMAL eth_avalon_bd_ram_bb.v FALSE
 199 // Retrieval info: GEN_FILE: TYPE_NORMAL eth_avalon_bd_ram_waveforms.html FALSE
 200 // Retrieval info: GEN_FILE: TYPE_NORMAL eth_avalon_bd_ram_wave*.jpg FALSE
 201 // Retrieval info: LIB_FILE: altera_mf