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flash: use uncached flash to avoid problems
[nios2ecos.git] / eth_ocm / eth_avalon_txdma.v
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1 //////////////////////////////////////////////////////////////////////
2 //// ////
3 //// eth_avalon_txdma.v ////
4 //// ////
5 //// This file is a patch used in conjunction with the ////
6 //// Ethernet IP core project. ////
7 //// http://www.opencores.org/projects/ethmac/ ////
8 //// ////
9 //// Author(s): ////
10 //// - Jakob Jones (jrjonsie@gmail.com) ////
11 //// ////
12 //// All additional information is available in the Readme.txt ////
13 //// file. ////
14 //// ////
15 //////////////////////////////////////////////////////////////////////
16 // History:
17 // 07/03/08 - Repaired bug with determining number of valid
18 // bytes corresponding to last data read from
19 // memory. Code was examining length field from
20 // descriptor input rather than registered
21 // descriptor data.
22 //
23 // 08/12/08 - Added logic to prevent FIFO overflows when
24 // Avalon BUS has large latency.
25 //
26 module eth_avalon_txdma #(parameter FIFO_DEPTH=128) (
27 //Commaon signals
28 input clk, // System clock
29 input reset,
30
31 //Descriptor ram interface
32 input [6:0] max_tx_bd, // Highest index RX Descriptor
33 input [31:0] bd_desc, // Descriptor Control data input
34 input [31:0] bd_ptr, // Descriptor pointer input
35 input bd_wait, // Descriptor RAM is busy
36
37 output bd_write, // write control data to BD RAM
38 output bd_read, // read control and pointer data from BD RAM
39 output reg [6:0] bd_index, // Which descriptor to read
40 output [31:0] bd_writedata, // Control data to be written to descriptor
41
42 //Memory port interface
43 input av_waitrequest, // Memory port is busy
44 input [31:0] av_readdata, // Memory port readdata
45 input av_readdatavalid, // Memory port readdata valid signal
46
47 output reg av_read, // Memory port read
48 output reg [31:0] av_address, // Memory port address
49
50 //Streaming interface
51 input TxEn, // Enable transmit
52 input txclk, // Transmit clock
53 output [7:0] tx_data, // output data
54 output tx_dv, // qualifies dataout, startofpacket, and endofpacket
55 output tx_sop, // start of data packet
56 output tx_eop, // end of data packet
57 input tx_ack, // Acknowledge TX data
58 input [8:0] tx_stat, // Status bits
59 input tx_stat_valid, // Status is valid
60 output tx_stat_ack,
61 input tx_retry,
62
63 output PerPacketPad, // Per packet pad
64 output PerPacketCrc, // Per packet crc
65 output TxUnderRun, // An underrun occured
66
67 //Interrupt outputs
68 output reg TxB_IRQ,
69 output reg TxE_IRQ
70 );
71
72 //Some useful constant functions
73 `include "eth_avalon_functions.v"
74
75 localparam MINFD = max(FIFO_DEPTH,128); // Minimum 128 byte FIFO depth
76 localparam RFD = nextPow2(MINFD)>>2; // FIFO depth next power of 2 (and divide by 4)
77
78 localparam FIFO_MARGIN = 5; // Cushion between FIFO depth and our perceived depth
79 localparam FIFO_THRESHOLD = RFD - FIFO_MARGIN;
80
81 //Bit descriptions for TX descriptor
82 localparam BIT_LEN_H = 31, // Upper bit of length field
83 BIT_LEN_L = 16, // Lower bit of length field
84 //Control bits
85 BIT_READY = 15, // Ready control bit (1=READY Controller can write to it)
86 BIT_IRQ = 14, // Generate an interrupt at end of TX
87 BIT_WRAP = 13, // Wrap to first RX descriptor after this one
88 BIT_PAD = 12, // Add Padding to small frames
89 BIT_CRC = 11, // Add CRC
90 BIT_RSVD_H = 10, // Upper bit of reserved field
91 BIT_RSVD_L = 9, // Lower bit of reserved field
92 //Status bits
93 BIT_UR = 8, // Buffer Underrun
94 BIT_RTRY_H = 7, // Upper bit of retry count
95 BIT_RTRY_L = 4, // Lower bit of retry count
96 BIT_RL = 3, // Retransmission Limit
97 BIT_LC = 2, // Late Collision
98 BIT_DF = 1, // Defer Indication
99 BIT_CS = 0; // Carrier Sense Lost
100
101 //State bits
102 localparam ST_IDLE = 0,
103 ST_BD_RD = 1, // Read Descriptor
104 ST_DMA1 = 2, // Transfer first word
105 ST_DMA2 = 3, // Wait for data to be written to FIFO
106 ST_STAT = 4, // Wait for status from MAC
107 ST_BD_WR = 5; // Write status back to MAC
108
109 //TX State machine bits
110 localparam TX_IDLE = 0, // Waiting for data to transmit
111 TX_SEND = 1, // Sending transmit data
112 TX_WAIT = 2; // Waiting for status from MAC
113
114 wire pre_av_read; // pre-registered avalon read signal
115 wire [31:0] pre_av_address; // pre_registered avalon address
116 wire valid_tx_rd; // Avalon bus acknowledged read
117
118 reg [5:0] state; // State machine bits
119 wire [15:0] bd_len; // Frame length from descriptor
120
121 reg [31:0] ptr; // Memory read pointer
122 reg [31:0] desc; // Registered bd_desc
123 wire [15:0] desc_len; // Frame length from stored descriptor
124
125 wire [1:0] valid_cnt; // Number of valid bytes in current data word
126 reg [1:0] first_valid_cnt;// Number of valid bytes in first data word
127 reg [1:0] last_valid_cnt; // Number of valid bytes in last data word
128
129 reg [13:0] tg_cnt; // target count (number of words to read from memory)
130 reg [13:0] rd_cnt; // read count (number of words read from memory)
131 reg [13:0] wr_cnt; // write count (number of words written to FIFO)
132 reg [13:0] rd_pending; // Number of reads pending (used to gate reads for FIFO protection)
133 reg pipe_hold; // Hold the pipeline until some of the reads have come back
134 wire [15:0] next_tg_cnt; // intentionally 2 bits larger
135 wire [13:0] next_rd_cnt; // next value of rd_cnt
136 wire [13:0] next_wr_cnt; // next value of wr_cnt
137
138 wire last_read; // Last read from memory
139 reg last_read_r; // Registered last_read
140 wire first_write; // First write to FIFO
141 wire last_write; // Last write to FIFO
142
143 reg [31:0] rdata; // registered av_readdata
144 reg valid_rdata; // registered av_readdatavalid
145
146 wire stat_ready; // Status ready from TX
147 reg [BIT_UR:BIT_CS] stat;
148 wire stat_error; // Status indicates error
149
150
151 wire dff_clear; // Data FIFO clear
152 wire [clogb2(RFD-1)-1:0] dff_wrused; // Amount of space used in data FIFO
153 reg [clogb2(RFD-1):0] dff_used_la;// Future value of dff_wrused when all reads are finished
154 wire dff_full; // Data FIFO full
155 wire dff_write; // Data FIFO write
156 wire [35:0] dff_din; // Data FIFO data input
157
158 wire dff_read; // Data FIFO read
159 wire dff_empty; // Data FIFO empty
160 wire [35:0] dff_dout; // Data FIFO data output
161
162 reg [2:0] tx_state; // Transmit state machine bits
163 reg tx_stat_valid_r;// Registered tx_stat_valid
164 wire tx_start; // Start signal to transmit state machine
165 wire last_byte; // Indicates last valid byte of current data word
166 wire [7:0] tx_ff_data [0:3];// Transmit bytes from data FIFO
167 wire [1:0] byte_cnt; // Indicates how many bytes are valid from data FIFO
168 reg [1:0] byte_index; // Indexes tx_ff_data for byte transmission
169
170 //Avalon bus
171 assign pre_av_address = {ptr[31:2],2'b00};
172 assign pre_av_read = state[ST_DMA1 ] & ~pipe_hold;
173 assign valid_tx_rd = pre_av_read & ~av_waitrequest;
174
175 //Descriptor bus
176 assign bd_read = state[ST_BD_RD];
177 assign bd_write = state[ST_BD_WR];
178 //Descriptor writeback data
179 assign bd_writedata[BIT_LEN_H:BIT_LEN_L] = desc[BIT_LEN_H:BIT_LEN_L]; //No modification to length
180 assign bd_writedata[BIT_READY] = 1'b0; // Clear ready flag
181 assign bd_writedata[BIT_IRQ] = desc[BIT_IRQ]; //leave IRQ
182 assign bd_writedata[BIT_WRAP] = desc[BIT_WRAP]; //leave WRAP
183 assign bd_writedata[BIT_PAD] = desc[BIT_PAD]; //leave PAD
184 assign bd_writedata[BIT_CRC] = desc[BIT_CRC]; //leave CRC
185 assign bd_writedata[BIT_RSVD_H:BIT_RSVD_L] = desc[BIT_RSVD_H:BIT_RSVD_L]; //leave reserved field
186 assign bd_writedata[BIT_UR:BIT_CS] = stat[BIT_UR:BIT_CS]; //set status flags
187
188 assign bd_len = bd_desc[BIT_LEN_H:BIT_LEN_L];
189 assign desc_len = desc[BIT_LEN_H:BIT_LEN_L];
190
191
192 //Add a pipeline stage for Avalon reads
193 always @(posedge clk or posedge reset)
194 if(reset) av_read <= 1'b0;
195 else if(~av_waitrequest) av_read <= pre_av_read;
196
197 always @(posedge clk)
198 if(~av_waitrequest) av_address <= pre_av_address;
199
200 always @(posedge clk or posedge reset)
201 if(reset) state <= 6'd1;
202 else begin state <= 6'd0;
203 //This really is a parallel case
204 case(1'b1) // synopsys parallel_case
205 state[ST_IDLE ]: // do nothing
206 if(TxEn & ~stat_ready) state[ST_BD_RD] <= 1'b1;
207 else state[ST_IDLE] <= 1'b1;
208 state[ST_BD_RD]: // read descriptor
209 if(~bd_wait & bd_desc[BIT_READY]) state[ST_DMA1 ] <= 1'b1;
210 else state[ST_BD_RD] <= 1'b1;
211 state[ST_DMA1 ]: // issue all reads
212 if(valid_tx_rd & last_read)
213 state[ST_DMA2 ] <= 1'b1;
214 else state[ST_DMA1 ] <= 1'b1;
215 state[ST_DMA2 ]: // wait here for stat
216 if(last_write & valid_rdata) state[ST_STAT ] <= 1'b1;
217 else state[ST_DMA2 ] <= 1'b1;
218 state[ST_STAT ]: begin // wait for status
219 if(stat_ready) begin
220 if(tx_retry) state[ST_IDLE ] <= 1'b1;
221 else state[ST_BD_WR] <= 1'b1;
222 end else state[ST_STAT ] <= 1'b1;
223 end
224 state[ST_BD_WR]: // write descriptor
225 if(~bd_wait) state[ST_IDLE ] <= 1'b1;
226 else state[ST_BD_WR] <= 1'b1;
227 endcase
228 end
229
230
231 assign next_tg_cnt = bd_len + ({1'b0,ptr[1:0]} + 3'd3);
232 assign next_rd_cnt = rd_cnt + 14'd1;
233 assign next_wr_cnt = wr_cnt + 14'd1;
234 assign last_read = (next_rd_cnt >= tg_cnt) | stat_ready;
235 assign first_write = !wr_cnt;
236 assign last_write = last_read_r & (next_wr_cnt >= rd_cnt);
237 assign valid_cnt = first_write ? first_valid_cnt:
238 last_write ? last_valid_cnt:
239 2'd3;
240
241 //Register last read signal
242 always @(posedge clk) begin
243 valid_rdata <= av_readdatavalid;
244 rdata <= av_readdata;
245 rd_pending <= rd_cnt - wr_cnt; // 1 clock lag
246 dff_used_la <= dff_wrused + rd_pending; // 1 clock lag
247 if(valid_rdata) wr_cnt <= next_wr_cnt;
248 //This really is a parallel case
249 case(1'b1) // synopsys parallel_case
250 state[ST_IDLE]: begin
251 last_read_r <= 1'b0; //clear last read flag
252 rd_cnt <= 14'd0; //clear read count
253 wr_cnt <= 14'd0; //clear write count
254 TxB_IRQ <= 1'b0; //clear irq
255 TxE_IRQ <= 1'b0; //clear error irq
256 pipe_hold <= 1'b0; //clear pipe hold flag
257 if(~TxEn) bd_index <= 7'd0; //clear the BD indexer
258 end //state[ST_IDLE ]
259
260 state[ST_BD_RD]: begin
261 if(~bd_wait & bd_desc[BIT_READY]) begin
262 tg_cnt <= next_tg_cnt[15:2]; //load target count
263 {ptr,desc} <= {bd_ptr,bd_desc}; //load pointer and descriptor
264 end
265 end //state[ST_BD_RD]
266
267 state[ST_DMA1 ]: begin
268 first_valid_cnt <= (3'd3 - {1'b0,ptr[1:0]});
269 last_valid_cnt <= (desc_len[2:0] + {1'b0,ptr[1:0]}) - 3'd1;
270 pipe_hold <= dff_used_la > FIFO_THRESHOLD; // 1 clock lag
271 if(valid_tx_rd) begin
272 ptr[31:2] <= ptr[31:2] + 30'd1; //increment read address
273 last_read_r <= last_read; //set last read flag
274 rd_cnt <= next_rd_cnt; //increment read count
275 end
276 end //state[ST_DMA1 ]
277
278 state[ST_BD_WR]:
279 if(~bd_wait) begin
280 TxB_IRQ <= desc[BIT_IRQ] & ~stat_error;
281 TxE_IRQ <= desc[BIT_IRQ] & stat_error;
282 if(desc[BIT_WRAP] | (bd_index == max_tx_bd))
283 bd_index <= 7'd0;
284 else bd_index <= bd_index + 7'd1;
285 end
286
287 endcase
288 end
289
290
291 //***************************************************************************
292 //*************************** Data FIFO *************************************
293 assign dff_clear = reset | state[ST_IDLE];
294 assign dff_write = valid_rdata & ~stat_ready;
295 assign dff_din[35] = first_write;
296 assign dff_din[34] = last_write;
297 assign dff_din[33:32] = valid_cnt;
298 assign dff_din[31:0] = first_write? (rdata >> {ptr[1:0],3'd0}): rdata;
299
300 //We'll read from the FIFO everytime there is a word ready or if something
301 //happened to put us into the WAIT state. We do this to flush the FIFO so
302 //any pending incoming reads from the avalon bus will make it into the FIFO
303 assign dff_read = tx_state[TX_WAIT] | (tx_state[TX_SEND] & last_byte & tx_ack);
304 eth_avalon_dma_fifo #( .DEPTH(RFD),
305 .WIDTH(36)) data_fifo(
306 .aclr (dff_clear ),
307
308 .wrclk (clk ),
309 .data (dff_din ),
310 .wrreq (dff_write ),
311 .wrfull (dff_full ),
312 .wrusedw (dff_wrused ),
313
314 .rdclk (txclk ),
315 .rdreq (dff_read&~dff_empty ),
316 .rdempty (dff_empty ),
317 .rdusedw ( ),
318 .q (dff_dout )
319 );
320
321 //Send stat_ready signal from TX to Avalon
322 eth_dc_reg stat_ready_dc_reg(
323 .d (tx_state[TX_WAIT] & tx_stat_valid_r),
324 .inclk (txclk ),
325 .outclk (clk ),
326 .reset (reset ),
327 .q (stat_ready )
328 );
329
330 //Send stat_ack signal from Avalon to TX
331 eth_dc_reg stat_ack_dc_reg(
332 .d (state[ST_IDLE] ),
333 .inclk (clk ),
334 .outclk (txclk ),
335 .reset (reset ),
336 .q (tx_stat_ack )
337 );
338
339 //Send tx_start signal from Avalon to TX
340 //We start sending the data when there is either
341 //words in the FIFO or when the DMA transfer
342 //has finished.
343 eth_dc_reg tx_start_dc_reg(
344 .d ((dff_wrused >= 8) | (state[ST_DMA2] & ~first_write) ),
345 .inclk (clk ),
346 .outclk (txclk ),
347 .reset (reset ),
348 .q (tx_start )
349 );
350
351 //************************* End Data FIFO ***********************************
352 //***************************************************************************
353
354 //***************************************************************************
355 //************************* Streaming Interface *****************************
356 assign stat_error = |{stat[BIT_UR],stat[BIT_RL:BIT_CS]};
357
358
359 assign tx_ff_data[0] = dff_dout[7:0];
360 assign tx_ff_data[1] = dff_dout[15:8];
361 assign tx_ff_data[2] = dff_dout[23:16];
362 assign tx_ff_data[3] = dff_dout[31:24];
363 assign byte_cnt = dff_dout[33:32];
364 assign last_byte = (byte_index == byte_cnt);
365
366 assign tx_data = tx_ff_data[byte_index];
367 assign tx_dv = tx_state[TX_SEND];
368 assign tx_sop = tx_state[TX_SEND] & !byte_index & dff_dout[35];
369 assign tx_eop = tx_state[TX_SEND] & last_byte & dff_dout[34];
370
371 assign PerPacketPad = desc[BIT_PAD];
372 assign PerPacketCrc = desc[BIT_CRC];
373 assign TxUnderRun = tx_state[TX_SEND] & tx_ack & dff_empty;
374
375 always @(posedge txclk or posedge reset)
376 if(reset) tx_state <= 3'd1;
377 else begin
378 /*default case-->*/ tx_state <= 3'd0;
379 case(1'b1) // synopsys parallel_case
380 tx_state[TX_IDLE]:// Wait for start
381 if(tx_start) tx_state[TX_SEND] <= 1'b1;
382 else tx_state[TX_IDLE] <= 1'b1;
383
384 tx_state[TX_SEND]:// Send all data
385 if((last_byte & dff_dout[34] & tx_ack) | tx_stat_valid)
386 tx_state[TX_WAIT] <= 1'b1;
387 else tx_state[TX_SEND] <= 1'b1;
388
389
390 tx_state[TX_WAIT]:// Wait for status
391 if(tx_stat_ack) tx_state[TX_IDLE] <= 1'b1;
392 else tx_state[TX_WAIT] <= 1'b1;
393
394 endcase
395 end
396
397 always @(posedge txclk)
398 if(tx_stat_valid) stat <= tx_stat;
399
400 always @(posedge txclk)
401 if(tx_state[TX_IDLE]) tx_stat_valid_r <= 1'b0;
402 else if(tx_stat_valid) tx_stat_valid_r <= 1'b1;
403
404 always @(posedge txclk)
405 case(1'b1)
406 tx_state[TX_IDLE]: begin
407 byte_index <= 2'd0;
408 end
409
410 tx_state[TX_SEND]: begin
411 if(tx_ack) begin
412 if(last_byte) byte_index <= 2'd0;
413 else byte_index <= byte_index + 2'd1;
414 end
415 end
416 endcase
417 //*********************** End Streaming Interface ***************************
418 //***************************************************************************
419
420 endmodule
421
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