eth_ocm/eth_clockgen.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  eth_clockgen.v                                              ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects/ethmac/                   ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Igor Mohor (igorM@opencores.org)                      ////
  10 ////                                                              ////
  11 ////  All additional information is avaliable in the Readme.txt   ////
  12 ////  file.                                                       ////
  13 ////                                                              ////
  14 //////////////////////////////////////////////////////////////////////
  15 ////                                                              ////
  16 //// Copyright (C) 2001 Authors                                   ////
  17 ////                                                              ////
  18 //// This source file may be used and distributed without         ////
  19 //// restriction provided that this copyright statement is not    ////
  20 //// removed from the file and that any derivative work contains  ////
  21 //// the original copyright notice and the associated disclaimer. ////
  22 ////                                                              ////
  23 //// This source file is free software; you can redistribute it   ////
  24 //// and/or modify it under the terms of the GNU Lesser General   ////
  25 //// Public License as published by the Free Software Foundation; ////
  26 //// either version 2.1 of the License, or (at your option) any   ////
  27 //// later version.                                               ////
  28 ////                                                              ////
  29 //// This source is distributed in the hope that it will be       ////
  30 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  31 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  32 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  33 //// details.                                                     ////
  34 ////                                                              ////
  35 //// You should have received a copy of the GNU Lesser General    ////
  36 //// Public License along with this source; if not, download it   ////
  37 //// from http://www.opencores.org/lgpl.shtml                     ////
  38 ////                                                              ////
  39 //////////////////////////////////////////////////////////////////////
  40 //
  41 // CVS Revision History
  42 //
  43 // $Log: eth_clockgen.v,v $
  44 // Revision 1.4  2005/02/21 12:48:05  igorm
  45 // Warning fixes.
  46 //
  47 // Revision 1.3  2002/01/23 10:28:16  mohor
  48 // Link in the header changed.
  49 //
  50 // Revision 1.2  2001/10/19 08:43:51  mohor
  51 // eth_timescale.v changed to timescale.v This is done because of the
  52 // simulation of the few cores in a one joined project.
  53 //
  54 // Revision 1.1  2001/08/06 14:44:29  mohor
  55 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
  56 // Include files fixed to contain no path.
  57 // File names and module names changed ta have a eth_ prologue in the name.
  58 // File eth_timescale.v is used to define timescale
  59 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
  60 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
  61 // and Mdo_OE. The bidirectional signal must be created on the top level. This
  62 // is done due to the ASIC tools.
  63 //
  64 // Revision 1.1  2001/07/30 21:23:42  mohor
  65 // Directory structure changed. Files checked and joind together.
  66 //
  67 // Revision 1.3  2001/06/01 22:28:55  mohor
  68 // This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
  69 //
  70 //
  71
  72 `include "timescale.v"
  73
  74 module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
  75
  76 parameter Tp=1;
  77
  78 input       Clk;              // Input clock (Host clock)
  79 input       Reset;            // Reset signal
  80 input [7:0] Divider;          // Divider (input clock will be divided by the Divider[7:0])
  81
  82 output      Mdc;              // Output clock
  83 output      MdcEn;            // Enable signal is asserted for one Clk period before Mdc rises.
  84 output      MdcEn_n;          // Enable signal is asserted for one Clk period before Mdc falls.
  85
  86 reg         Mdc;
  87 reg   [7:0] Counter;
  88
  89 wire        CountEq0;
  90 wire  [7:0] CounterPreset;
  91 wire  [7:0] TempDivider;
  92
  93
  94 assign TempDivider[7:0]   = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
  95 assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1;           // We are counting half of period
  96
  97
  98 // Counter counts half period
  99 always @ (posedge Clk or posedge Reset)
 100 begin
 101   if(Reset)
 102     Counter[7:0] <= #Tp 8'h1;
 103   else
 104     begin
 105       if(CountEq0)
 106         begin
 107           Counter[7:0] <= #Tp CounterPreset[7:0];
 108         end
 109       else
 110         Counter[7:0] <= #Tp Counter - 8'h1;
 111     end
 112 end
 113
 114
 115 // Mdc is asserted every other half period
 116 always @ (posedge Clk or posedge Reset)
 117 begin
 118   if(Reset)
 119     Mdc <= #Tp 1'b0;
 120   else
 121     begin
 122       if(CountEq0)
 123         Mdc <= #Tp ~Mdc;
 124     end
 125 end
 126
 127
 128 assign CountEq0 = Counter == 8'h0;
 129 assign MdcEn = CountEq0 & ~Mdc;
 130 assign MdcEn_n = CountEq0 & Mdc;
 131
 132 endmodule
 133
 134