eth_ocm/eth_dc_reg.v

   1 module eth_dc_reg(
   2         input   d,
   3         input   inclk,
   4         input   outclk,
   5         input   reset,
   6         output  q
   7 );
   8 reg     q1, q2, q3, q4;
   9 wire    q1_reset;
  10
  11 assign  q1_reset = (~q1 & q3) | reset;
  12 assign  q = q4;
  13
  14 //q1 output decoder (simply latch the input to the input clock domain
  15 always @(posedge inclk or posedge reset)
  16         if(reset)               q1 <= 1'b0;
  17         else                    q1 <= d;
  18
  19 //q2 output decoder based on async q1 input
  20 always @(posedge q1 or posedge q1_reset)
  21         if(q1_reset)    q2 <= 1'b0;
  22         else                    q2 <= 1'b1;
  23
  24 //q2 and q3 output decoders
  25 always @(posedge outclk or posedge reset)
  26         if(reset)               {q3, q4} <= 2'b00;
  27         else                    {q3, q4} <= {q2, q3};
  28
  29 endmodule
  30