eth_ocm/eth_rxstatem.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  eth_rxstatem.v                                              ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects/ethmac/                   ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Igor Mohor (igorM@opencores.org)                      ////
  10 ////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
  11 ////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
  12 ////                                                              ////
  13 ////  All additional information is avaliable in the Readme.txt   ////
  14 ////  file.                                                       ////
  15 ////                                                              ////
  16 //////////////////////////////////////////////////////////////////////
  17 ////                                                              ////
  18 //// Copyright (C) 2001 Authors                                   ////
  19 ////                                                              ////
  20 //// This source file may be used and distributed without         ////
  21 //// restriction provided that this copyright statement is not    ////
  22 //// removed from the file and that any derivative work contains  ////
  23 //// the original copyright notice and the associated disclaimer. ////
  24 ////                                                              ////
  25 //// This source file is free software; you can redistribute it   ////
  26 //// and/or modify it under the terms of the GNU Lesser General   ////
  27 //// Public License as published by the Free Software Foundation; ////
  28 //// either version 2.1 of the License, or (at your option) any   ////
  29 //// later version.                                               ////
  30 ////                                                              ////
  31 //// This source is distributed in the hope that it will be       ////
  32 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  33 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  34 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  35 //// details.                                                     ////
  36 ////                                                              ////
  37 //// You should have received a copy of the GNU Lesser General    ////
  38 //// Public License along with this source; if not, download it   ////
  39 //// from http://www.opencores.org/lgpl.shtml                     ////
  40 ////                                                              ////
  41 //////////////////////////////////////////////////////////////////////
  42 //
  43 // CVS Revision History
  44 //
  45 // $Log: eth_rxstatem.v,v $
  46 // Revision 1.6  2002/11/13 22:28:26  tadejm
  47 // StartIdle state changed (not important the size of the packet).
  48 // StartData1 activates only while ByteCnt is smaller than the MaxFrame.
  49 //
  50 // Revision 1.5  2002/01/23 10:28:16  mohor
  51 // Link in the header changed.
  52 //
  53 // Revision 1.4  2001/10/19 08:43:51  mohor
  54 // eth_timescale.v changed to timescale.v This is done because of the
  55 // simulation of the few cores in a one joined project.
  56 //
  57 // Revision 1.3  2001/10/18 12:07:11  mohor
  58 // Status signals changed, Adress decoding changed, interrupt controller
  59 // added.
  60 //
  61 // Revision 1.2  2001/09/11 14:17:00  mohor
  62 // Few little NCSIM warnings fixed.
  63 //
  64 // Revision 1.1  2001/08/06 14:44:29  mohor
  65 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
  66 // Include files fixed to contain no path.
  67 // File names and module names changed ta have a eth_ prologue in the name.
  68 // File eth_timescale.v is used to define timescale
  69 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
  70 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
  71 // and Mdo_OE. The bidirectional signal must be created on the top level. This
  72 // is done due to the ASIC tools.
  73 //
  74 // Revision 1.1  2001/07/30 21:23:42  mohor
  75 // Directory structure changed. Files checked and joind together.
  76 //
  77 // Revision 1.2  2001/07/03 12:55:41  mohor
  78 // Minor changes because of the synthesys warnings.
  79 //
  80 //
  81 // Revision 1.1  2001/06/27 21:26:19  mohor
  82 // Initial release of the RxEthMAC module.
  83 //
  84 //
  85 //
  86 //
  87
  88
  89 `include "timescale.v"
  90
  91
  92 module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
  93                      IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
  94                      StateDrop
  95                     );
  96
  97 parameter Tp = 1;
  98
  99 input         MRxClk;
 100 input         Reset;
 101 input         MRxDV;
 102 input         ByteCntEq0;
 103 input         ByteCntGreat2;
 104 input         MRxDEq5;
 105 input         Transmitting;
 106 input         MRxDEqD;
 107 input         IFGCounterEq24;
 108 input         ByteCntMaxFrame;
 109
 110 output [1:0]  StateData;
 111 output        StateIdle;
 112 output        StateDrop;
 113 output        StatePreamble;
 114 output        StateSFD;
 115
 116 reg           StateData0;
 117 reg           StateData1;
 118 reg           StateIdle;
 119 reg           StateDrop;
 120 reg           StatePreamble;
 121 reg           StateSFD;
 122
 123 wire          StartIdle;
 124 wire          StartDrop;
 125 wire          StartData0;
 126 wire          StartData1;
 127 wire          StartPreamble;
 128 wire          StartSFD;
 129
 130
 131 // Defining the next state
 132 assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData));
 133
 134 assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
 135
 136 assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
 137
 138 assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
 139
 140 assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
 141
 142 assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 &  MRxDEqD
 143                          |  StateData0 &  ByteCntMaxFrame
 144                            );
 145
 146 // Rx State Machine
 147 always @ (posedge MRxClk or posedge Reset)
 148 begin
 149   if(Reset)
 150     begin
 151       StateIdle     <= #Tp 1'b0;
 152       StateDrop     <= #Tp 1'b1;
 153       StatePreamble <= #Tp 1'b0;
 154       StateSFD      <= #Tp 1'b0;
 155       StateData0    <= #Tp 1'b0;
 156       StateData1    <= #Tp 1'b0;
 157     end
 158   else
 159     begin
 160       if(StartPreamble | StartSFD | StartDrop)
 161         StateIdle <= #Tp 1'b0;
 162       else
 163       if(StartIdle)
 164         StateIdle <= #Tp 1'b1;
 165
 166       if(StartIdle)
 167         StateDrop <= #Tp 1'b0;
 168       else
 169       if(StartDrop)
 170         StateDrop <= #Tp 1'b1;
 171
 172       if(StartSFD | StartIdle | StartDrop)
 173         StatePreamble <= #Tp 1'b0;
 174       else
 175       if(StartPreamble)
 176         StatePreamble <= #Tp 1'b1;
 177
 178       if(StartPreamble | StartIdle | StartData0 | StartDrop)
 179         StateSFD <= #Tp 1'b0;
 180       else
 181       if(StartSFD)
 182         StateSFD <= #Tp 1'b1;
 183
 184       if(StartIdle | StartData1 | StartDrop)
 185         StateData0 <= #Tp 1'b0;
 186       else
 187       if(StartData0)
 188         StateData0 <= #Tp 1'b1;
 189
 190       if(StartIdle | StartData0 | StartDrop)
 191         StateData1 <= #Tp 1'b0;
 192       else
 193       if(StartData1)
 194         StateData1 <= #Tp 1'b1;
 195     end
 196 end
 197
 198 assign StateData[1:0] = {StateData1, StateData0};
 199
 200 endmodule