eth_ocm/eth_txcounters.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  eth_txcounters.v                                            ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects/ethmac/                   ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Igor Mohor (igorM@opencores.org)                      ////
  10 ////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
  11 ////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
  12 ////                                                              ////
  13 ////  All additional information is avaliable in the Readme.txt   ////
  14 ////  file.                                                       ////
  15 ////                                                              ////
  16 //////////////////////////////////////////////////////////////////////
  17 ////                                                              ////
  18 //// Copyright (C) 2001 Authors                                   ////
  19 ////                                                              ////
  20 //// This source file may be used and distributed without         ////
  21 //// restriction provided that this copyright statement is not    ////
  22 //// removed from the file and that any derivative work contains  ////
  23 //// the original copyright notice and the associated disclaimer. ////
  24 ////                                                              ////
  25 //// This source file is free software; you can redistribute it   ////
  26 //// and/or modify it under the terms of the GNU Lesser General   ////
  27 //// Public License as published by the Free Software Foundation; ////
  28 //// either version 2.1 of the License, or (at your option) any   ////
  29 //// later version.                                               ////
  30 ////                                                              ////
  31 //// This source is distributed in the hope that it will be       ////
  32 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  33 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  34 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  35 //// details.                                                     ////
  36 ////                                                              ////
  37 //// You should have received a copy of the GNU Lesser General    ////
  38 //// Public License along with this source; if not, download it   ////
  39 //// from http://www.opencores.org/lgpl.shtml                     ////
  40 ////                                                              ////
  41 //////////////////////////////////////////////////////////////////////
  42 //
  43 // CVS Revision History
  44 //
  45 // $Log: eth_txcounters.v,v $
  46 // Revision 1.6  2005/02/21 11:25:27  igorm
  47 // Delayed CRC fixed.
  48 //
  49 // Revision 1.5  2002/04/22 14:54:14  mohor
  50 // FCS should not be included in NibbleMinFl.
  51 //
  52 // Revision 1.4  2002/01/23 10:28:16  mohor
  53 // Link in the header changed.
  54 //
  55 // Revision 1.3  2001/10/19 08:43:51  mohor
  56 // eth_timescale.v changed to timescale.v This is done because of the
  57 // simulation of the few cores in a one joined project.
  58 //
  59 // Revision 1.2  2001/09/11 14:17:00  mohor
  60 // Few little NCSIM warnings fixed.
  61 //
  62 // Revision 1.1  2001/08/06 14:44:29  mohor
  63 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
  64 // Include files fixed to contain no path.
  65 // File names and module names changed ta have a eth_ prologue in the name.
  66 // File eth_timescale.v is used to define timescale
  67 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
  68 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
  69 // and Mdo_OE. The bidirectional signal must be created on the top level. This
  70 // is done due to the ASIC tools.
  71 //
  72 // Revision 1.1  2001/07/30 21:23:42  mohor
  73 // Directory structure changed. Files checked and joind together.
  74 //
  75 // Revision 1.4  2001/06/27 21:27:45  mohor
  76 // Few typos fixed.
  77 //
  78 // Revision 1.2  2001/06/19 10:38:07  mohor
  79 // Minor changes in header.
  80 //
  81 // Revision 1.1  2001/06/19 10:27:57  mohor
  82 // TxEthMAC initial release.
  83 //
  84 //
  85 //
  86
  87
  88 `include "timescale.v"
  89
  90
  91 module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
  92                        StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS,
  93                        StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
  94                        ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
  95                        ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
  96                       );
  97
  98 parameter Tp = 1;
  99
 100 input MTxClk;             // Tx clock
 101 input Reset;              // Reset
 102 input StatePreamble;      // Preamble state
 103 input StateIPG;           // IPG state
 104 input [1:0] StateData;    // Data state
 105 input StatePAD;           // PAD state
 106 input StateFCS;           // FCS state
 107 input StateJam;           // Jam state
 108 input StateBackOff;       // Backoff state
 109 input StateDefer;         // Defer state
 110 input StateIdle;          // Idle state
 111 input StateSFD;           // SFD state
 112 input StartDefer;         // Defer state will be activated in next clock
 113 input StartIPG;           // IPG state will be activated in next clock
 114 input StartFCS;           // FCS state will be activated in next clock
 115 input StartJam;           // Jam state will be activated in next clock
 116 input StartBackoff;       // Backoff state will be activated in next clock
 117 input TxStartFrm;         // Tx start frame
 118 input [15:0] MinFL;       // Minimum frame length (in bytes)
 119 input [15:0] MaxFL;       // Miximum frame length (in bytes)
 120 input HugEn;              // Pakets bigger then MaxFL enabled
 121 input ExDfrEn;            // Excessive deferral enabled
 122 input PacketFinished_q;
 123 input DlyCrcEn;           // Delayed CRC enabled
 124
 125 output [15:0] ByteCnt;    // Byte counter
 126 output [15:0] NibCnt;     // Nibble counter
 127 output ExcessiveDefer;    // Excessive Deferral occuring
 128 output NibCntEq7;         // Nibble counter is equal to 7
 129 output NibCntEq15;        // Nibble counter is equal to 15
 130 output MaxFrame;          // Maximum frame occured
 131 output NibbleMinFl;       // Nibble counter is greater than the minimum frame length
 132 output [2:0] DlyCrcCnt;   // Delayed CRC Count
 133
 134 wire ExcessiveDeferCnt;
 135 wire ResetNibCnt;
 136 wire IncrementNibCnt;
 137 wire ResetByteCnt;
 138 wire IncrementByteCnt;
 139 wire ByteCntMax;
 140
 141 reg [15:0] NibCnt;
 142 reg [15:0] ByteCnt;
 143 reg  [2:0] DlyCrcCnt;
 144
 145
 146
 147 assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) | StatePAD
 148                        | StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm;
 149
 150
 151 assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15
 152                    | StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam;
 153
 154 // Nibble Counter
 155 always @ (posedge MTxClk or posedge Reset)
 156 begin
 157   if(Reset)
 158     NibCnt <= #Tp 16'h0;
 159   else
 160     begin
 161       if(ResetNibCnt)
 162         NibCnt <= #Tp 16'h0;
 163       else
 164       if(IncrementNibCnt)
 165         NibCnt <= #Tp NibCnt + 1'b1;
 166      end
 167 end
 168
 169
 170 assign NibCntEq7   = &NibCnt[2:0];
 171 assign NibCntEq15  = &NibCnt[3:0];
 172
 173 assign NibbleMinFl = NibCnt >= (((MinFL-3'h4)<<1) -1);  // FCS should not be included in NibbleMinFl
 174
 175 assign ExcessiveDeferCnt = NibCnt[13:0] == 16'h17b7;
 176
 177 assign ExcessiveDefer  = NibCnt[13:0] == 16'h17b7 & ~ExDfrEn;   // 6071 nibbles
 178
 179 assign IncrementByteCnt = StateData[1] & ~ByteCntMax
 180                         | StateBackOff & (&NibCnt[6:0])
 181                         | (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax;
 182
 183 assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q;
 184
 185
 186 // Transmit Byte Counter
 187 always @ (posedge MTxClk or posedge Reset)
 188 begin
 189   if(Reset)
 190     ByteCnt[15:0] <= #Tp 16'h0;
 191   else
 192     begin
 193       if(ResetByteCnt)
 194         ByteCnt[15:0] <= #Tp 16'h0;
 195       else
 196       if(IncrementByteCnt)
 197         ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
 198     end
 199 end
 200
 201
 202 assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
 203
 204 assign ByteCntMax = &ByteCnt[15:0];
 205
 206
 207 // Delayed CRC counter
 208 always @ (posedge MTxClk or posedge Reset)
 209 begin
 210   if(Reset)
 211     DlyCrcCnt <= #Tp 3'h0;
 212   else
 213     begin
 214       if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
 215         DlyCrcCnt <= #Tp 3'h0;
 216       else
 217       if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
 218         DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
 219     end
 220 end
 221
 222
 223
 224 endmodule