| blob | c38ad74a0287790de9f7b8564dc74dff70c4f907 |
1 SYSTEM cycloneIII_3c25_niosII_standard_sopc\r
2 {\r
3 System_Wizard_Version = "8.00";\r
4 System_Wizard_Build = "215";\r
5 Builder_Application = "sopc_builder_ca";\r
6 WIZARD_SCRIPT_ARGUMENTS \r
7 {\r
8 hdl_language = "verilog";\r
9 device_family = "CYCLONEIII";\r
10 device_family_id = "CYCLONEIII";\r
11 generate_sdk = "0";\r
12 do_build_sim = "0";\r
13 hardcopy_compatible = "0";\r
14 CLOCKS \r
15 {\r
16 CLOCK clk\r
17 {\r
18 frequency = "50000000";\r
19 source = "External";\r
20 Is_Clock_Source = "0";\r
21 display_name = "clk";\r
22 pipeline = "0";\r
23 clock_module_connection_point_for_c2h = "clk.clk";\r
24 }\r
25 CLOCK pll_c0\r
26 {\r
27 frequency = "100000000";\r
28 source = "";\r
29 Is_Clock_Source = "1";\r
30 display_name = "c0 from pll";\r
31 pipeline = "0";\r
32 clock_module_connection_point_for_c2h = "pll.c0";\r
33 }\r
34 CLOCK pll_c0_out\r
35 {\r
36 frequency = "100000000";\r
37 source = "pll_c0";\r
38 Is_Clock_Source = "0";\r
39 display_name = "pll_c0_out";\r
40 }\r
41 CLOCK pll_c1\r
42 {\r
43 frequency = "100000000";\r
44 source = "";\r
45 Is_Clock_Source = "1";\r
46 display_name = "c1 from pll";\r
47 pipeline = "0";\r
48 clock_module_connection_point_for_c2h = "pll.c1";\r
49 }\r
50 CLOCK pll_c1_out\r
51 {\r
52 frequency = "100000000";\r
53 source = "pll_c1";\r
54 Is_Clock_Source = "0";\r
55 display_name = "pll_c1_out";\r
56 }\r
57 CLOCK pll_c2\r
58 {\r
59 frequency = "60000000";\r
60 source = "";\r
61 Is_Clock_Source = "1";\r
62 display_name = "c2 from pll";\r
63 pipeline = "0";\r
64 clock_module_connection_point_for_c2h = "pll.c2";\r
65 }\r
66 CLOCK pll_c2_out\r
67 {\r
68 frequency = "60000000";\r
69 source = "pll_c2";\r
70 Is_Clock_Source = "0";\r
71 display_name = "pll_c2_out";\r
72 }\r
73 CLOCK pll_c3\r
74 {\r
75 frequency = "40000000";\r
76 source = "";\r
77 Is_Clock_Source = "1";\r
78 display_name = "c3 from pll";\r
79 pipeline = "0";\r
80 clock_module_connection_point_for_c2h = "pll.c3";\r
81 }\r
82 CLOCK pll_c3_out\r
83 {\r
84 frequency = "40000000";\r
85 source = "pll_c3";\r
86 Is_Clock_Source = "0";\r
87 display_name = "pll_c3_out";\r
88 }\r
89 CLOCK ddr_sdram_phy_clk\r
90 {\r
91 frequency = "66500000";\r
92 source = "";\r
93 Is_Clock_Source = "1";\r
94 display_name = "phy_clk from ddr_sdram";\r
95 pipeline = "0";\r
96 clock_module_connection_point_for_c2h = "ddr_sdram.sysclk";\r
97 }\r
98 CLOCK ddr_sdram_phy_clk_out\r
99 {\r
100 frequency = "66500000";\r
101 source = "ddr_sdram_phy_clk";\r
102 Is_Clock_Source = "0";\r
103 display_name = "ddr_sdram_phy_clk_out";\r
104 }\r
105 CLOCK ddr_sdram_aux_full_rate_clk\r
106 {\r
107 frequency = "133000000";\r
108 source = "";\r
109 Is_Clock_Source = "1";\r
110 display_name = "aux_full_rate_clk from ddr_sdram";\r
111 pipeline = "0";\r
112 clock_module_connection_point_for_c2h = "ddr_sdram.auxfull";\r
113 }\r
114 CLOCK ddr_sdram_aux_full_rate_clk_out\r
115 {\r
116 frequency = "133000000";\r
117 source = "ddr_sdram_aux_full_rate_clk";\r
118 Is_Clock_Source = "0";\r
119 display_name = "ddr_sdram_aux_full_rate_clk_out";\r
120 }\r
121 CLOCK ddr_sdram_aux_half_rate_clk\r
122 {\r
123 frequency = "66500000";\r
124 source = "";\r
125 Is_Clock_Source = "1";\r
126 display_name = "aux_half_rate_clk from ddr_sdram";\r
127 pipeline = "0";\r
128 clock_module_connection_point_for_c2h = "ddr_sdram.auxhalf";\r
129 }\r
130 CLOCK ddr_sdram_aux_half_rate_clk_out\r
131 {\r
132 frequency = "66500000";\r
133 source = "ddr_sdram_aux_half_rate_clk";\r
134 Is_Clock_Source = "0";\r
135 display_name = "ddr_sdram_aux_half_rate_clk_out";\r
136 }\r
137 }\r
138 clock_freq = "50000000";\r
139 clock_freq = "50000000";\r
140 board_class = "";\r
141 view_master_columns = "1";\r
142 view_master_priorities = "0";\r
143 generate_hdl = "";\r
144 bustype_column_width = "0";\r
145 clock_column_width = "80";\r
146 name_column_width = "75";\r
147 desc_column_width = "75";\r
148 base_column_width = "75";\r
149 end_column_width = "75";\r
150 BOARD_INFO \r
151 {\r
152 altera_avalon_cfi_flash \r
153 {\r
154 reference_designators = "";\r
155 }\r
156 }\r
157 do_log_history = "0";\r
158 }\r
159 MODULE pll\r
160 {\r
161 SLAVE s1\r
162 {\r
163 PORT_WIRING \r
164 {\r
165 PORT inclk0\r
166 {\r
167 type = "clk";\r
168 width = "1";\r
169 direction = "input";\r
170 Is_Enabled = "0";\r
171 }\r
172 PORT reset_n\r
173 {\r
174 type = "reset_n";\r
175 width = "1";\r
176 direction = "input";\r
177 Is_Enabled = "1";\r
178 }\r
179 PORT resetrequest\r
180 {\r
181 type = "resetrequest";\r
182 width = "1";\r
183 direction = "output";\r
184 Is_Enabled = "1";\r
185 }\r
186 PORT address\r
187 {\r
188 type = "address";\r
189 width = "3";\r
190 direction = "input";\r
191 Is_Enabled = "1";\r
192 }\r
193 PORT chipselect\r
194 {\r
195 type = "chipselect";\r
196 width = "1";\r
197 direction = "input";\r
198 Is_Enabled = "1";\r
199 }\r
200 PORT read\r
201 {\r
202 type = "read";\r
203 width = "1";\r
204 direction = "input";\r
205 Is_Enabled = "1";\r
206 }\r
207 PORT readdata\r
208 {\r
209 type = "readdata";\r
210 width = "16";\r
211 direction = "output";\r
212 Is_Enabled = "1";\r
213 }\r
214 PORT write\r
215 {\r
216 type = "write";\r
217 width = "1";\r
218 direction = "input";\r
219 Is_Enabled = "1";\r
220 }\r
221 PORT writedata\r
222 {\r
223 type = "writedata";\r
224 width = "16";\r
225 direction = "input";\r
226 Is_Enabled = "1";\r
227 }\r
228 PORT clk\r
229 {\r
230 direction = "input";\r
231 type = "clk";\r
232 width = "1";\r
233 Is_Enabled = "1";\r
234 }\r
235 PORT c0\r
236 {\r
237 Is_Enabled = "1";\r
238 direction = "output";\r
239 type = "out_clk";\r
240 width = "1";\r
241 }\r
242 PORT c1\r
243 {\r
244 Is_Enabled = "1";\r
245 direction = "output";\r
246 type = "out_clk";\r
247 width = "1";\r
248 }\r
249 PORT c2\r
250 {\r
251 Is_Enabled = "1";\r
252 direction = "output";\r
253 type = "out_clk";\r
254 width = "1";\r
255 }\r
256 PORT c3\r
257 {\r
258 Is_Enabled = "1";\r
259 direction = "output";\r
260 type = "out_clk";\r
261 width = "1";\r
262 }\r
263 }\r
264 SYSTEM_BUILDER_INFO \r
265 {\r
266 Bus_Type = "avalon";\r
267 Write_Wait_States = "0cycles";\r
268 Read_Wait_States = "1cycles";\r
269 Hold_Time = "0cycles";\r
270 Setup_Time = "0cycles";\r
271 Is_Printable_Device = "0";\r
272 Address_Alignment = "native";\r
273 Well_Behaved_Waitrequest = "0";\r
274 Is_Nonvolatile_Storage = "0";\r
275 Read_Latency = "0";\r
276 Is_Memory_Device = "0";\r
277 Maximum_Pending_Read_Transactions = "0";\r
278 Minimum_Uninterrupted_Run_Length = "1";\r
279 Accepts_Internal_Connections = "1";\r
280 Write_Latency = "0";\r
281 Is_Flash = "0";\r
282 Data_Width = "16";\r
283 Address_Width = "3";\r
284 Maximum_Burst_Size = "1";\r
285 Register_Incoming_Signals = "0";\r
286 Register_Outgoing_Signals = "0";\r
287 Interleave_Bursts = "0";\r
288 Linewrap_Bursts = "0";\r
289 Burst_On_Burst_Boundaries_Only = "0";\r
290 Always_Burst_Max_Burst = "0";\r
291 Is_Big_Endian = "0";\r
292 Is_Enabled = "1";\r
293 Clock_Source = "clk";\r
294 Has_Clock = "1";\r
295 MASTERED_BY slow_peripheral_bridge/m1\r
296 {\r
297 priority = "1";\r
298 Offset_Address = "0x00001140";\r
299 }\r
300 Base_Address = "0x08001140";\r
301 Has_IRQ = "0";\r
302 Date_Modified = "";\r
303 Instantiate_In_System_Module = "1";\r
304 Requires_Internal_Clock_Promotion = "Yes";\r
305 Is_Clock_Source = "1";\r
306 Address_Group = "0";\r
307 }\r
308 }\r
309 PORT_WIRING \r
310 {\r
311 PORT c0\r
312 {\r
313 type = "out_clk";\r
314 width = "1";\r
315 direction = "output";\r
316 Is_Enabled = "0";\r
317 }\r
318 PORT c1\r
319 {\r
320 type = "out_clk";\r
321 width = "1";\r
322 direction = "output";\r
323 Is_Enabled = "0";\r
324 }\r
325 PORT c2\r
326 {\r
327 type = "out_clk";\r
328 width = "1";\r
329 direction = "output";\r
330 Is_Enabled = "0";\r
331 }\r
332 PORT c3\r
333 {\r
334 type = "out_clk";\r
335 width = "1";\r
336 direction = "output";\r
337 Is_Enabled = "0";\r
338 }\r
339 PORT areset\r
340 {\r
341 Is_Enabled = "0";\r
342 direction = "input";\r
343 width = "1";\r
344 }\r
345 PORT locked\r
346 {\r
347 Is_Enabled = "0";\r
348 direction = "output";\r
349 width = "1";\r
350 }\r
351 PORT pfdena\r
352 {\r
353 Is_Enabled = "0";\r
354 direction = "input";\r
355 width = "1";\r
356 }\r
357 PORT pllena\r
358 {\r
359 Is_Enabled = "0";\r
360 direction = "input";\r
361 width = "1";\r
362 }\r
363 }\r
364 WIZARD_SCRIPT_ARGUMENTS \r
365 {\r
366 areset = "None";\r
367 pfdena = "None";\r
368 locked = "None";\r
369 pllena = "None";\r
370 scanclk = "None";\r
371 scandata = "None";\r
372 scanread = "None";\r
373 scanwrite = "None";\r
374 scanclkena = "None";\r
375 scanaclr = "None";\r
376 scandataout = "None";\r
377 scandone = "None";\r
378 configupdate = "None";\r
379 phasecounterselect = "None";\r
380 phasedone = "None";\r
381 phaseupdown = "None";\r
382 phasestep = "None";\r
383 UI_CONTROL \r
384 {\r
385 pllena_port_exist = "0";\r
386 areset_port_exist = "0";\r
387 pfdena_port_exist = "0";\r
388 locked_port_exist = "0";\r
389 }\r
390 ALTPLL_PORTS \r
391 {\r
392 PORT inclk0\r
393 {\r
394 Is_Enabled = "1";\r
395 direction = "input";\r
396 width = "1";\r
397 }\r
398 PORT c0\r
399 {\r
400 Is_Enabled = "1";\r
401 direction = "output";\r
402 type = "out_clk";\r
403 width = "1";\r
404 }\r
405 PORT c1\r
406 {\r
407 Is_Enabled = "1";\r
408 direction = "output";\r
409 type = "out_clk";\r
410 width = "1";\r
411 }\r
412 PORT c2\r
413 {\r
414 Is_Enabled = "1";\r
415 direction = "output";\r
416 type = "out_clk";\r
417 width = "1";\r
418 }\r
419 PORT c3\r
420 {\r
421 Is_Enabled = "1";\r
422 direction = "output";\r
423 type = "out_clk";\r
424 width = "1";\r
425 }\r
426 }\r
427 CLOCK_SOURCES \r
428 {\r
429 CLOCK c0\r
430 {\r
431 DIVIDE_BY = "1";\r
432 DUTY_CYCLE = "50";\r
433 MULTIPLY_BY = "2";\r
434 PHASE_SHIFT = "0";\r
435 clk_index = "0";\r
436 clock_freq = "100000000";\r
437 clock_unit = "MHz";\r
438 type = "out_clk";\r
439 }\r
440 CLOCK c1\r
441 {\r
442 DIVIDE_BY = "1";\r
443 DUTY_CYCLE = "50";\r
444 MULTIPLY_BY = "2";\r
445 PHASE_SHIFT = "-2000";\r
446 clk_index = "1";\r
447 clock_freq = "100000000";\r
448 clock_unit = "MHz";\r
449 type = "out_clk";\r
450 }\r
451 CLOCK c2\r
452 {\r
453 DIVIDE_BY = "5";\r
454 DUTY_CYCLE = "50";\r
455 MULTIPLY_BY = "6";\r
456 PHASE_SHIFT = "0";\r
457 clk_index = "2";\r
458 clock_freq = "60000000";\r
459 clock_unit = "MHz";\r
460 type = "out_clk";\r
461 }\r
462 CLOCK c3\r
463 {\r
464 DIVIDE_BY = "5";\r
465 DUTY_CYCLE = "50";\r
466 MULTIPLY_BY = "4";\r
467 PHASE_SHIFT = "0";\r
468 clk_index = "3";\r
469 clock_freq = "40000000";\r
470 clock_unit = "MHz";\r
471 type = "out_clk";\r
472 }\r
473 }\r
474 CLOCK_INFO \r
475 {\r
476 CLOCK inclk0\r
477 {\r
478 clock_freq = "50000000";\r
479 clock_unit = "MHz";\r
480 type = "in_clk";\r
481 }\r
482 }\r
483 CNX_INFO \r
484 {\r
485 CONSTANT \r
486 {\r
487 STRING \r
488 {\r
489 BANDWIDTH_TYPE = "AUTO";\r
490 COMPENSATE_CLOCK = "CLK0";\r
491 INTENDED_DEVICE_FAMILY = "CYCLONEIII";\r
492 LPM_TYPE = "altpll";\r
493 OPERATION_MODE = "NO_COMPENSATION";\r
494 PLL_TYPE = "AUTO";\r
495 PORT_ACTIVECLOCK = "PORT_UNUSED";\r
496 PORT_ARESET = "PORT_UNUSED";\r
497 PORT_CLKBAD0 = "PORT_UNUSED";\r
498 PORT_CLKBAD1 = "PORT_UNUSED";\r
499 PORT_CLKLOSS = "PORT_UNUSED";\r
500 PORT_CLKSWITCH = "PORT_UNUSED";\r
501 PORT_FBIN = "PORT_UNUSED";\r
502 PORT_INCLK0 = "PORT_USED";\r
503 PORT_INCLK1 = "PORT_UNUSED";\r
504 PORT_LOCKED = "PORT_UNUSED";\r
505 PORT_PFDENA = "PORT_UNUSED";\r
506 PORT_PLLENA = "PORT_UNUSED";\r
507 PORT_SCANACLR = "PORT_UNUSED";\r
508 PORT_SCANCLK = "PORT_UNUSED";\r
509 PORT_SCANDATA = "PORT_UNUSED";\r
510 PORT_SCANDATAOUT = "PORT_UNUSED";\r
511 PORT_SCANDONE = "PORT_UNUSED";\r
512 PORT_SCANREAD = "PORT_UNUSED";\r
513 PORT_SCANWRITE = "PORT_UNUSED";\r
514 PORT_clk0 = "PORT_USED";\r
515 PORT_clk1 = "PORT_USED";\r
516 PORT_clk2 = "PORT_USED";\r
517 PORT_clk3 = "PORT_USED";\r
518 PORT_clk4 = "PORT_UNUSED";\r
519 PORT_clk5 = "PORT_UNUSED";\r
520 PORT_clkena0 = "PORT_UNUSED";\r
521 PORT_clkena1 = "PORT_UNUSED";\r
522 PORT_clkena2 = "PORT_UNUSED";\r
523 PORT_clkena3 = "PORT_UNUSED";\r
524 PORT_clkena4 = "PORT_UNUSED";\r
525 PORT_clkena5 = "PORT_UNUSED";\r
526 PORT_enable0 = "PORT_UNUSED";\r
527 PORT_enable1 = "PORT_UNUSED";\r
528 PORT_extclk0 = "PORT_UNUSED";\r
529 PORT_extclk1 = "PORT_UNUSED";\r
530 PORT_extclk2 = "PORT_UNUSED";\r
531 PORT_extclk3 = "PORT_UNUSED";\r
532 PORT_extclkena0 = "PORT_UNUSED";\r
533 PORT_extclkena1 = "PORT_UNUSED";\r
534 PORT_extclkena2 = "PORT_UNUSED";\r
535 PORT_extclkena3 = "PORT_UNUSED";\r
536 PORT_sclkout0 = "PORT_UNUSED";\r
537 PORT_sclkout1 = "PORT_UNUSED";\r
538 }\r
539 NUMERIC \r
540 {\r
541 INCLK0_INPUT_FREQUENCY = "20000";\r
542 INVALID_LOCK_MULTIPLIER = "5";\r
543 SPREAD_FREQUENCY = "0";\r
544 VALID_LOCK_MULTIPLIER = "1";\r
545 CLK0_MULTIPLY_BY = "2";\r
546 CLK0_DIVIDE_BY = "1";\r
547 CLK0_PHASE_SHIFT = "0.0";\r
548 CLK1_MULTIPLY_BY = "2";\r
549 CLK1_DIVIDE_BY = "1";\r
550 CLK1_PHASE_SHIFT = "-2000.0";\r
551 CLK2_MULTIPLY_BY = "6";\r
552 CLK2_DIVIDE_BY = "5";\r
553 CLK2_PHASE_SHIFT = "0.0";\r
554 CLK3_MULTIPLY_BY = "4";\r
555 CLK3_DIVIDE_BY = "5";\r
556 CLK3_PHASE_SHIFT = "0.0";\r
557 }\r
558 }\r
559 GEN_FILE \r
560 {\r
561 TYPE_NORMAL \r
562 {\r
563 TRUE \r
564 {\r
565 File1 = ".v";\r
566 File2 = ".ppf";\r
567 }\r
568 FALSE \r
569 {\r
570 File3 = ".inc";\r
571 File4 = ".cmp";\r
572 File5 = ".bsf";\r
573 File6 = "_inst.v";\r
574 File7 = "_bb.v";\r
575 File8 = "_waveforms.html";\r
576 File9 = "_wave*.jpg";\r
577 }\r
578 }\r
579 }\r
580 LIBRARY = "altera_mf altera_mf.altera_mf_components.all";\r
581 PRIVATE \r
582 {\r
583 STRING \r
584 {\r
585 ACTIVECLK_CHECK = "0";\r
586 BANDWIDTH = "1.000";\r
587 BANDWIDTH_FEATURE_ENABLED = "1";\r
588 BANDWIDTH_FREQ_UNIT = "MHz";\r
589 BANDWIDTH_PRESET = "Low";\r
590 BANDWIDTH_USE_AUTO = "1";\r
591 BANDWIDTH_USE_CUSTOM = "0";\r
592 BANDWIDTH_USE_PRESET = "0";\r
593 CLKBAD_SWITCHOVER_CHECK = "0";\r
594 CLKLOSS_CHECK = "0";\r
595 CLKSWITCH_CHECK = "0";\r
596 CNX_NO_COMPENSATE_RADIO = "1";\r
597 CREATE_CLKBAD_CHECK = "0";\r
598 CREATE_INCLK1_CHECK = "0";\r
599 CUR_DEDICATED_CLK = "c0";\r
600 CUR_FBIN_CLK = "e0";\r
601 DEVICE_SPEED_GRADE = "Any";\r
602 EXT_FEEDBACK_RADIO = "0";\r
603 GLOCKED_COUNTER_EDIT_CHANGED = "1";\r
604 GLOCKED_FEATURE_ENABLED = "0";\r
605 GLOCKED_MODE_CHECK = "0";\r
606 HAS_MANUAL_SWITCHOVER = "1";\r
607 INCLK0_FREQ_EDIT = "50.0";\r
608 INCLK0_FREQ_UNIT_COMBO = "MHz";\r
609 INCLK1_FREQ_EDIT = "100.000";\r
610 INCLK1_FREQ_EDIT_CHANGED = "1";\r
611 INCLK1_FREQ_UNIT_CHANGED = "1";\r
612 INCLK1_FREQ_UNIT_COMBO = "MHz";\r
613 INTENDED_DEVICE_FAMILY = "Cyclone III";\r
614 INT_FEEDBACK__MODE_RADIO = "1";\r
615 LOCKED_OUTPUT_CHECK = "0";\r
616 LOCK_LOSS_SWITCHOVER_CHECK = "0";\r
617 LONG_SCAN_RADIO = "1";\r
618 LVDS_MODE_DATA_RATE = "Not Available";\r
619 NORMAL_MODE_RADIO = "1";\r
620 PLL_ADVANCED_PARAM_CHECK = "0";\r
621 PLL_ARESET_CHECK = "0";\r
622 PLL_ENA_CHECK = "0";\r
623 PLL_PFDENA_CHECK = "0";\r
624 PRIMARY_CLK_COMBO = "inclk0";\r
625 SACN_INPUTS_CHECK = "0";\r
626 SCAN_FEATURE_ENABLED = "1";\r
627 SELF_RESET_LOCK_LOSS = "0";\r
628 SHORT_SCAN_RADIO = "0";\r
629 SPREAD_FEATURE_ENABLED = "1";\r
630 SPREAD_FREQ = "50.000";\r
631 SPREAD_FREQ_UNIT = "KHz";\r
632 SPREAD_PERCENT = "0.500";\r
633 SPREAD_USE = "0";\r
634 SRC_SYNCH_COMP_RADIO = "0";\r
635 SWITCHOVER_FEATURE_ENABLED = "1";\r
636 ZERO_DELAY_RADIO = "0";\r
637 }\r
638 NUMERIC \r
639 {\r
640 GLOCK_COUNTER_EDIT = "1048575";\r
641 LVDS_MODE_DATA_RATE_DIRTY = "0";\r
642 PLL_AUTOPLL_CHECK = "1";\r
643 PLL_ENHPLL_CHECK = "0";\r
644 PLL_FASTPLL_CHECK = "0";\r
645 PLL_LVDS_PLL_CHECK = "0";\r
646 PLL_TARGET_HARCOPY_CHECK = "0";\r
647 SWITCHOVER_COUNT_EDIT = "1";\r
648 }\r
649 }\r
650 USED_PORT \r
651 {\r
652 inclk0 \r
653 {\r
654 VALUE_1 = "0";\r
655 VALUE_2 = "0";\r
656 VALUE_3 = "0";\r
657 VALUE_4 = "0";\r
658 VALUE_5 = "INPUT_CLK_EXT";\r
659 VALUE_6 = "GND";\r
660 VALUE_7 = "inclk0";\r
661 }\r
662 c0 \r
663 {\r
664 VALUE_1 = "0";\r
665 VALUE_2 = "0";\r
666 VALUE_3 = "0";\r
667 VALUE_4 = "0";\r
668 VALUE_5 = "OUTPUT_CLK_EXT";\r
669 VALUE_6 = "VCC";\r
670 VALUE_7 = "c0";\r
671 }\r
672 c1 \r
673 {\r
674 VALUE_1 = "0";\r
675 VALUE_2 = "0";\r
676 VALUE_3 = "0";\r
677 VALUE_4 = "0";\r
678 VALUE_5 = "OUTPUT_CLK_EXT";\r
679 VALUE_6 = "VCC";\r
680 VALUE_7 = "c1";\r
681 }\r
682 c2 \r
683 {\r
684 VALUE_1 = "0";\r
685 VALUE_2 = "0";\r
686 VALUE_3 = "0";\r
687 VALUE_4 = "0";\r
688 VALUE_5 = "OUTPUT_CLK_EXT";\r
689 VALUE_6 = "VCC";\r
690 VALUE_7 = "c2";\r
691 }\r
692 c3 \r
693 {\r
694 VALUE_1 = "0";\r
695 VALUE_2 = "0";\r
696 VALUE_3 = "0";\r
697 VALUE_4 = "0";\r
698 VALUE_5 = "OUTPUT_CLK_EXT";\r
699 VALUE_6 = "VCC";\r
700 VALUE_7 = "c3";\r
701 }\r
702 }\r
703 }\r
704 Config_Done = "0";\r
705 }\r
706 SYSTEM_BUILDER_INFO \r
707 {\r
708 Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIII,STRATIXIIGX,CYCLONE,CYCLONEII,CYCLONEIII,ARRIAGX,STRATIXIIGXLITE,STRATIXIV";\r
709 Instantiate_In_System_Module = "1";\r
710 Is_Enabled = "1";\r
711 Default_Module_Name = "pll";\r
712 Top_Level_Ports_Are_Enumerated = "1";\r
713 Clock_Source = "clk";\r
714 View \r
715 {\r
716 MESSAGES \r
717 {\r
718 }\r
719 Settings_Summary = " Avalon PLL: <br>
720 input clock configured: <b>clk</b>
721 ";\r
722 }\r
723 }\r
724 class = "altera_avalon_pll";\r
725 class_version = "7.08";\r
726 HDL_INFO \r
727 {\r
728 Precompiled_Simulation_Library_Files = "";\r
729 Simulation_HDL_Files = "";\r
730 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/pll.v, __PROJECT_DIRECTORY__/altpllpll.v";\r
731 Synthesis_Only_Files = "";\r
732 }\r
733 }\r
734 MODULE cpu\r
735 {\r
736 MASTER instruction_master\r
737 {\r
738 PORT_WIRING \r
739 {\r
740 PORT clk\r
741 {\r
742 type = "clk";\r
743 width = "1";\r
744 direction = "input";\r
745 Is_Enabled = "1";\r
746 }\r
747 PORT reset_n\r
748 {\r
749 type = "reset_n";\r
750 width = "1";\r
751 direction = "input";\r
752 Is_Enabled = "0";\r
753 }\r
754 PORT i_address\r
755 {\r
756 type = "address";\r
757 width = "27";\r
758 direction = "output";\r
759 Is_Enabled = "1";\r
760 }\r
761 PORT i_read\r
762 {\r
763 type = "read";\r
764 width = "1";\r
765 direction = "output";\r
766 Is_Enabled = "1";\r
767 }\r
768 PORT i_readdata\r
769 {\r
770 type = "readdata";\r
771 width = "32";\r
772 direction = "input";\r
773 Is_Enabled = "1";\r
774 }\r
775 PORT i_readdatavalid\r
776 {\r
777 type = "readdatavalid";\r
778 width = "1";\r
779 direction = "input";\r
780 Is_Enabled = "1";\r
781 }\r
782 PORT i_waitrequest\r
783 {\r
784 type = "waitrequest";\r
785 width = "1";\r
786 direction = "input";\r
787 Is_Enabled = "1";\r
788 }\r
789 }\r
790 SYSTEM_BUILDER_INFO \r
791 {\r
792 Bus_Type = "avalon";\r
793 Is_Asynchronous = "0";\r
794 DBS_Big_Endian = "0";\r
795 Adapts_To = "";\r
796 Do_Stream_Reads = "0";\r
797 Do_Stream_Writes = "0";\r
798 Max_Address_Width = "32";\r
799 Data_Width = "32";\r
800 Address_Width = "27";\r
801 Maximum_Burst_Size = "1";\r
802 Register_Incoming_Signals = "0";\r
803 Register_Outgoing_Signals = "0";\r
804 Interleave_Bursts = "";\r
805 Linewrap_Bursts = "";\r
806 Burst_On_Burst_Boundaries_Only = "";\r
807 Always_Burst_Max_Burst = "";\r
808 Is_Big_Endian = "0";\r
809 Is_Enabled = "1";\r
810 Is_Instruction_Master = "1";\r
811 Is_Readable = "1";\r
812 Is_Writeable = "0";\r
813 Address_Group = "0";\r
814 Has_IRQ = "0";\r
815 Irq_Scheme = "individual_requests";\r
816 Interrupt_Range = "0-0";\r
817 }\r
818 MEMORY_MAP \r
819 {\r
820 Entry cpu_ddr_clock_bridge/s1\r
821 {\r
822 address = "0x00000000";\r
823 span = "0x02000000";\r
824 is_bridge = "1";\r
825 }\r
826 Entry ddr_sdram/s1\r
827 {\r
828 address = "0x00000000";\r
829 span = "0x02000000";\r
830 is_bridge = "0";\r
831 }\r
832 Entry cpu/jtag_debug_module\r
833 {\r
834 address = "0x02000800";\r
835 span = "0x00000800";\r
836 is_bridge = "0";\r
837 }\r
838 Entry flash_ssram_pipeline_bridge/s1\r
839 {\r
840 address = "0x04000000";\r
841 span = "0x02000000";\r
842 is_bridge = "1";\r
843 }\r
844 Entry pipeline_bridge_before_tristate_bridge/s1\r
845 {\r
846 address = "0x04000000";\r
847 span = "0x02000000";\r
848 is_bridge = "1";\r
849 }\r
850 Entry ext_flash/s1\r
851 {\r
852 address = "0x04000000";\r
853 span = "0x01000000";\r
854 is_bridge = "0";\r
855 }\r
856 Entry ssram/s1\r
857 {\r
858 address = "0x05000000";\r
859 span = "0x00100000";\r
860 is_bridge = "0";\r
861 }\r
862 }\r
863 }\r
864 MASTER custom_instruction_master\r
865 {\r
866 SYSTEM_BUILDER_INFO \r
867 {\r
868 Bus_Type = "nios_custom_instruction";\r
869 Data_Width = "32";\r
870 Address_Width = "8";\r
871 Is_Custom_Instruction = "1";\r
872 Is_Enabled = "0";\r
873 Max_Address_Width = "8";\r
874 Base_Address = "N/A";\r
875 Is_Visible = "0";\r
876 }\r
877 PORT_WIRING \r
878 {\r
879 PORT dataa\r
880 {\r
881 type = "dataa";\r
882 width = "32";\r
883 direction = "output";\r
884 }\r
885 PORT datab\r
886 {\r
887 type = "datab";\r
888 width = "32";\r
889 direction = "output";\r
890 }\r
891 PORT result\r
892 {\r
893 type = "result";\r
894 width = "32";\r
895 direction = "input";\r
896 }\r
897 PORT clk_en\r
898 {\r
899 type = "clk_en";\r
900 width = "1";\r
901 direction = "output";\r
902 }\r
903 PORT reset\r
904 {\r
905 type = "reset";\r
906 width = "1";\r
907 direction = "output";\r
908 }\r
909 PORT start\r
910 {\r
911 type = "start";\r
912 width = "1";\r
913 direction = "output";\r
914 }\r
915 PORT done\r
916 {\r
917 type = "done";\r
918 width = "1";\r
919 direction = "input";\r
920 }\r
921 PORT n\r
922 {\r
923 type = "n";\r
924 width = "8";\r
925 direction = "output";\r
926 }\r
927 PORT a\r
928 {\r
929 type = "a";\r
930 width = "5";\r
931 direction = "output";\r
932 }\r
933 PORT b\r
934 {\r
935 type = "b";\r
936 width = "5";\r
937 direction = "output";\r
938 }\r
939 PORT c\r
940 {\r
941 type = "c";\r
942 width = "5";\r
943 direction = "output";\r
944 }\r
945 PORT readra\r
946 {\r
947 type = "readra";\r
948 width = "1";\r
949 direction = "output";\r
950 }\r
951 PORT readrb\r
952 {\r
953 type = "readrb";\r
954 width = "1";\r
955 direction = "output";\r
956 }\r
957 PORT writerc\r
958 {\r
959 type = "writerc";\r
960 width = "1";\r
961 direction = "output";\r
962 }\r
963 }\r
964 }\r
965 SLAVE jtag_debug_module\r
966 {\r
967 SYSTEM_BUILDER_INFO \r
968 {\r
969 Bus_Type = "avalon";\r
970 Write_Wait_States = "0cycles";\r
971 Read_Wait_States = "1cycles";\r
972 Hold_Time = "0cycles";\r
973 Setup_Time = "0cycles";\r
974 Is_Printable_Device = "0";\r
975 Address_Alignment = "dynamic";\r
976 Well_Behaved_Waitrequest = "0";\r
977 Is_Nonvolatile_Storage = "0";\r
978 Address_Span = "2048";\r
979 Read_Latency = "0";\r
980 Is_Memory_Device = "1";\r
981 Maximum_Pending_Read_Transactions = "0";\r
982 Minimum_Uninterrupted_Run_Length = "1";\r
983 Accepts_Internal_Connections = "1";\r
984 Write_Latency = "0";\r
985 Is_Flash = "0";\r
986 Data_Width = "32";\r
987 Address_Width = "9";\r
988 Maximum_Burst_Size = "1";\r
989 Register_Incoming_Signals = "0";\r
990 Register_Outgoing_Signals = "0";\r
991 Interleave_Bursts = "0";\r
992 Linewrap_Bursts = "0";\r
993 Burst_On_Burst_Boundaries_Only = "0";\r
994 Always_Burst_Max_Burst = "0";\r
995 Is_Big_Endian = "0";\r
996 Is_Enabled = "1";\r
997 Accepts_External_Connections = "1";\r
998 Requires_Internal_Connections = "";\r
999 MASTERED_BY cpu/data_master\r
1000 {\r
1001 priority = "1";\r
1002 Offset_Address = "0x02000800";\r
1003 }\r
1004 MASTERED_BY cpu/instruction_master\r
1005 {\r
1006 priority = "1";\r
1007 Offset_Address = "0x02000800";\r
1008 }\r
1009 Base_Address = "0x02000800";\r
1010 Is_Readable = "1";\r
1011 Is_Writeable = "1";\r
1012 Uses_Tri_State_Data_Bus = "0";\r
1013 Has_IRQ = "0";\r
1014 JTAG_Hub_Base_Id = "1118278";\r
1015 JTAG_Hub_Instance_Id = "0";\r
1016 Address_Group = "0";\r
1017 IRQ_MASTER cpu/data_master\r
1018 {\r
1019 IRQ_Number = "NC";\r
1020 }\r
1021 }\r
1022 PORT_WIRING \r
1023 {\r
1024 PORT jtag_debug_module_address\r
1025 {\r
1026 type = "address";\r
1027 width = "9";\r
1028 direction = "input";\r
1029 Is_Enabled = "1";\r
1030 }\r
1031 PORT jtag_debug_module_begintransfer\r
1032 {\r
1033 type = "begintransfer";\r
1034 width = "1";\r
1035 direction = "input";\r
1036 Is_Enabled = "1";\r
1037 }\r
1038 PORT jtag_debug_module_byteenable\r
1039 {\r
1040 type = "byteenable";\r
1041 width = "4";\r
1042 direction = "input";\r
1043 Is_Enabled = "1";\r
1044 }\r
1045 PORT jtag_debug_module_clk\r
1046 {\r
1047 type = "clk";\r
1048 width = "1";\r
1049 direction = "input";\r
1050 Is_Enabled = "1";\r
1051 }\r
1052 PORT jtag_debug_module_debugaccess\r
1053 {\r
1054 type = "debugaccess";\r
1055 width = "1";\r
1056 direction = "input";\r
1057 Is_Enabled = "1";\r
1058 }\r
1059 PORT jtag_debug_module_readdata\r
1060 {\r
1061 type = "readdata";\r
1062 width = "32";\r
1063 direction = "output";\r
1064 Is_Enabled = "1";\r
1065 }\r
1066 PORT jtag_debug_module_reset\r
1067 {\r
1068 type = "reset";\r
1069 width = "1";\r
1070 direction = "input";\r
1071 Is_Enabled = "1";\r
1072 }\r
1073 PORT jtag_debug_module_resetrequest\r
1074 {\r
1075 type = "resetrequest";\r
1076 width = "1";\r
1077 direction = "output";\r
1078 Is_Enabled = "1";\r
1079 }\r
1080 PORT jtag_debug_module_select\r
1081 {\r
1082 type = "chipselect";\r
1083 width = "1";\r
1084 direction = "input";\r
1085 Is_Enabled = "1";\r
1086 }\r
1087 PORT jtag_debug_module_write\r
1088 {\r
1089 type = "write";\r
1090 width = "1";\r
1091 direction = "input";\r
1092 Is_Enabled = "1";\r
1093 }\r
1094 PORT jtag_debug_module_writedata\r
1095 {\r
1096 type = "writedata";\r
1097 width = "32";\r
1098 direction = "input";\r
1099 Is_Enabled = "1";\r
1100 }\r
1101 PORT reset_n\r
1102 {\r
1103 Is_Enabled = "1";\r
1104 direction = "input";\r
1105 type = "reset_n";\r
1106 width = "1";\r
1107 }\r
1108 }\r
1109 }\r
1110 MASTER data_master\r
1111 {\r
1112 SYSTEM_BUILDER_INFO \r
1113 {\r
1114 Has_IRQ = "1";\r
1115 Irq_Scheme = "individual_requests";\r
1116 Bus_Type = "avalon";\r
1117 Is_Asynchronous = "0";\r
1118 DBS_Big_Endian = "0";\r
1119 Adapts_To = "";\r
1120 Do_Stream_Reads = "0";\r
1121 Do_Stream_Writes = "0";\r
1122 Max_Address_Width = "32";\r
1123 Data_Width = "32";\r
1124 Address_Width = "28";\r
1125 Maximum_Burst_Size = "1";\r
1126 Register_Incoming_Signals = "0";\r
1127 Register_Outgoing_Signals = "0";\r
1128 Interleave_Bursts = "0";\r
1129 Linewrap_Bursts = "0";\r
1130 Burst_On_Burst_Boundaries_Only = "";\r
1131 Always_Burst_Max_Burst = "0";\r
1132 Is_Big_Endian = "0";\r
1133 Is_Enabled = "1";\r
1134 Is_Data_Master = "1";\r
1135 Address_Group = "0";\r
1136 Is_Readable = "1";\r
1137 Is_Writeable = "1";\r
1138 Interrupt_Range = "0-31";\r
1139 }\r
1140 PORT_WIRING \r
1141 {\r
1142 PORT d_irq\r
1143 {\r
1144 type = "irq";\r
1145 width = "32";\r
1146 direction = "input";\r
1147 Is_Enabled = "1";\r
1148 }\r
1149 PORT d_address\r
1150 {\r
1151 type = "address";\r
1152 width = "28";\r
1153 direction = "output";\r
1154 Is_Enabled = "1";\r
1155 }\r
1156 PORT d_byteenable\r
1157 {\r
1158 type = "byteenable";\r
1159 width = "4";\r
1160 direction = "output";\r
1161 Is_Enabled = "1";\r
1162 }\r
1163 PORT d_read\r
1164 {\r
1165 type = "read";\r
1166 width = "1";\r
1167 direction = "output";\r
1168 Is_Enabled = "1";\r
1169 }\r
1170 PORT d_readdata\r
1171 {\r
1172 type = "readdata";\r
1173 width = "32";\r
1174 direction = "input";\r
1175 Is_Enabled = "1";\r
1176 }\r
1177 PORT d_readdatavalid\r
1178 {\r
1179 type = "readdatavalid";\r
1180 width = "1";\r
1181 direction = "input";\r
1182 Is_Enabled = "1";\r
1183 }\r
1184 PORT d_waitrequest\r
1185 {\r
1186 type = "waitrequest";\r
1187 width = "1";\r
1188 direction = "input";\r
1189 Is_Enabled = "1";\r
1190 }\r
1191 PORT d_write\r
1192 {\r
1193 type = "write";\r
1194 width = "1";\r
1195 direction = "output";\r
1196 Is_Enabled = "1";\r
1197 }\r
1198 PORT d_writedata\r
1199 {\r
1200 type = "writedata";\r
1201 width = "32";\r
1202 direction = "output";\r
1203 Is_Enabled = "1";\r
1204 }\r
1205 PORT jtag_debug_module_debugaccess_to_roms\r
1206 {\r
1207 type = "debugaccess";\r
1208 width = "1";\r
1209 direction = "output";\r
1210 Is_Enabled = "1";\r
1211 }\r
1212 }\r
1213 MEMORY_MAP \r
1214 {\r
1215 Entry cpu_ddr_clock_bridge/s1\r
1216 {\r
1217 address = "0x00000000";\r
1218 span = "0x02000000";\r
1219 is_bridge = "1";\r
1220 }\r
1221 Entry ddr_sdram/s1\r
1222 {\r
1223 address = "0x00000000";\r
1224 span = "0x02000000";\r
1225 is_bridge = "0";\r
1226 }\r
1227 Entry cpu/jtag_debug_module\r
1228 {\r
1229 address = "0x02000800";\r
1230 span = "0x00000800";\r
1231 is_bridge = "0";\r
1232 }\r
1233 Entry flash_ssram_pipeline_bridge/s1\r
1234 {\r
1235 address = "0x04000000";\r
1236 span = "0x02000000";\r
1237 is_bridge = "1";\r
1238 }\r
1239 Entry pipeline_bridge_before_tristate_bridge/s1\r
1240 {\r
1241 address = "0x04000000";\r
1242 span = "0x02000000";\r
1243 is_bridge = "1";\r
1244 }\r
1245 Entry ext_flash/s1\r
1246 {\r
1247 address = "0x04000000";\r
1248 span = "0x01000000";\r
1249 is_bridge = "0";\r
1250 }\r
1251 Entry ssram/s1\r
1252 {\r
1253 address = "0x05000000";\r
1254 span = "0x00100000";\r
1255 is_bridge = "0";\r
1256 }\r
1257 Entry slow_peripheral_bridge/s1\r
1258 {\r
1259 address = "0x08000000";\r
1260 span = "0x00004000";\r
1261 is_bridge = "1";\r
1262 }\r
1263 Entry button_pio/s1\r
1264 {\r
1265 address = "0x08001180";\r
1266 span = "0x00000010";\r
1267 is_bridge = "0";\r
1268 }\r
1269 Entry high_res_timer/s1\r
1270 {\r
1271 address = "0x08001100";\r
1272 span = "0x00000020";\r
1273 is_bridge = "0";\r
1274 }\r
1275 Entry jtag_uart/avalon_jtag_slave\r
1276 {\r
1277 address = "0x080011a0";\r
1278 span = "0x00000008";\r
1279 is_bridge = "0";\r
1280 }\r
1281 Entry led_pio/s1\r
1282 {\r
1283 address = "0x08001190";\r
1284 span = "0x00000010";\r
1285 is_bridge = "0";\r
1286 }\r
1287 Entry performance_counter/control_slave\r
1288 {\r
1289 address = "0x08001120";\r
1290 span = "0x00000020";\r
1291 is_bridge = "0";\r
1292 }\r
1293 Entry pll/s1\r
1294 {\r
1295 address = "0x08001140";\r
1296 span = "0x00000020";\r
1297 is_bridge = "0";\r
1298 }\r
1299 Entry remote_update/s1\r
1300 {\r
1301 address = "0x08001000";\r
1302 span = "0x00000100";\r
1303 is_bridge = "0";\r
1304 }\r
1305 Entry sys_clk_timer/s1\r
1306 {\r
1307 address = "0x08001160";\r
1308 span = "0x00000020";\r
1309 is_bridge = "0";\r
1310 }\r
1311 Entry sysid/control_slave\r
1312 {\r
1313 address = "0x080011a8";\r
1314 span = "0x00000008";\r
1315 is_bridge = "0";\r
1316 }\r
1317 Entry ocm/control_port\r
1318 {\r
1319 address = "0x08002000";\r
1320 span = "0x00001000";\r
1321 is_bridge = "0";\r
1322 }\r
1323 }\r
1324 }\r
1325 WIZARD_SCRIPT_ARGUMENTS \r
1326 {\r
1327 cache_has_dcache = "1";\r
1328 cache_dcache_size = "2048";\r
1329 cache_dcache_line_size = "32";\r
1330 cache_dcache_bursts = "0";\r
1331 cache_dcache_ram_block_type = "AUTO";\r
1332 num_tightly_coupled_data_masters = "0";\r
1333 gui_num_tightly_coupled_data_masters = "0";\r
1334 gui_include_tightly_coupled_data_masters = "0";\r
1335 gui_omit_avalon_data_master = "0";\r
1336 cache_has_icache = "1";\r
1337 cache_icache_size = "4096";\r
1338 cache_icache_line_size = "32";\r
1339 cache_icache_ram_block_type = "AUTO";\r
1340 cache_icache_bursts = "0";\r
1341 num_tightly_coupled_instruction_masters = "0";\r
1342 gui_num_tightly_coupled_instruction_masters = "0";\r
1343 gui_include_tightly_coupled_instruction_masters = "0";\r
1344 debug_level = "2";\r
1345 include_oci = "1";\r
1346 oci_sbi_enabled = "1";\r
1347 oci_num_xbrk = "0";\r
1348 oci_num_dbrk = "0";\r
1349 oci_dbrk_trace = "0";\r
1350 oci_dbrk_pairs = "0";\r
1351 oci_onchip_trace = "0";\r
1352 oci_offchip_trace = "0";\r
1353 oci_data_trace = "0";\r
1354 include_third_party_debug_port = "0";\r
1355 oci_trace_addr_width = "7";\r
1356 oci_trigger_arming = "1";\r
1357 oci_debugreq_signals = "0";\r
1358 oci_embedded_pll = "0";\r
1359 oci_num_pm = "0";\r
1360 oci_pm_width = "32";\r
1361 performance_counters_present = "0";\r
1362 performance_counters_width = "32";\r
1363 always_encrypt = "1";\r
1364 debug_simgen = "0";\r
1365 activate_model_checker = "0";\r
1366 activate_test_end_checker = "0";\r
1367 activate_trace = "1";\r
1368 activate_monitors = "1";\r
1369 clear_x_bits_ld_non_bypass = "1";\r
1370 bit_31_bypass_dcache = "1";\r
1371 hdl_sim_caches_cleared = "1";\r
1372 hbreak_test = "0";\r
1373 allow_full_address_range = "0";\r
1374 extra_exc_info = "0";\r
1375 branch_prediction_type = "Dynamic";\r
1376 bht_ptr_sz = "8";\r
1377 bht_index_pc_only = "0";\r
1378 gui_branch_prediction_type = "Automatic";\r
1379 full_waveform_signals = "0";\r
1380 export_pcb = "0";\r
1381 avalon_debug_port_present = "0";\r
1382 illegal_instructions_trap = "0";\r
1383 illegal_memory_access_detection = "0";\r
1384 illegal_mem_exc = "0";\r
1385 slave_access_error_exc = "0";\r
1386 division_error_exc = "0";\r
1387 advanced_exc = "0";\r
1388 gui_mmu_present = "0";\r
1389 mmu_present = "0";\r
1390 process_id_num_bits = "8";\r
1391 tlb_ptr_sz = "7";\r
1392 tlb_num_ways = "16";\r
1393 udtlb_num_entries = "6";\r
1394 uitlb_num_entries = "4";\r
1395 fast_tlb_miss_exc_slave = "";\r
1396 fast_tlb_miss_exc_offset = "0x00000000";\r
1397 mpu_present = "0";\r
1398 mpu_num_data_regions = "8";\r
1399 mpu_num_inst_regions = "8";\r
1400 mpu_min_data_region_size_log2 = "12";\r
1401 mpu_min_inst_region_size_log2 = "12";\r
1402 mpu_use_limit = "0";\r
1403 hardware_divide_present = "0";\r
1404 gui_hardware_divide_setting = "0";\r
1405 hardware_multiply_present = "1";\r
1406 hardware_multiply_impl = "embedded_mul";\r
1407 shift_rot_impl = "fast_le_shift";\r
1408 gui_hardware_multiply_setting = "embedded_mul_fast_le_shift";\r
1409 reset_slave = "ext_flash/s1";\r
1410 break_slave = "cpu/jtag_debug_module";\r
1411 exc_slave = "ssram/s1";\r
1412 reset_offset = "0x00000000";\r
1413 break_offset = "0x00000020";\r
1414 exc_offset = "0x00000020";\r
1415 cpu_reset = "0";\r
1416 CPU_Implementation = "fast";\r
1417 cpu_selection = "f";\r
1418 device_family_id = "CYCLONEIII";\r
1419 address_stall_present = "1";\r
1420 dsp_block_supports_shift = "0";\r
1421 mrams_present = "0";\r
1422 do_generate = "1";\r
1423 cpuid_value = "0";\r
1424 cpuid_sz = "1";\r
1425 dont_overwrite_cpuid = "1";\r
1426 allow_legacy_sdk = "1";\r
1427 legacy_sdk_support = "1";\r
1428 inst_addr_width = "27";\r
1429 data_addr_width = "28";\r
1430 asp_debug = "0";\r
1431 asp_core_debug = "0";\r
1432 CPU_Architecture = "nios2";\r
1433 cache_icache_burst_type = "none";\r
1434 include_debug = "0";\r
1435 include_trace = "0";\r
1436 hardware_multiply_uses_les = "0";\r
1437 hardware_multiply_omits_msw = "1";\r
1438 big_endian = "0";\r
1439 break_slave_override = "";\r
1440 break_offset_override = "0x20";\r
1441 altera_show_unreleased_features = "0";\r
1442 altera_show_unpublished_features = "0";\r
1443 altera_internal_test = "0";\r
1444 alt_log_port_base = "";\r
1445 alt_log_port_type = "";\r
1446 gui_illegal_instructions_trap = "0";\r
1447 atomic_mem_present = "0";\r
1448 nmi_present = "0";\r
1449 fast_intr_present = "0";\r
1450 num_shadow_regs = "0";\r
1451 gui_illegal_memory_access_detection = "0";\r
1452 cache_omit_dcache = "0";\r
1453 cache_omit_icache = "0";\r
1454 omit_instruction_master = "0";\r
1455 omit_data_master = "0";\r
1456 ras_ptr_sz = "4";\r
1457 jtb_ptr_sz = "5";\r
1458 ibuf_ptr_sz = "4";\r
1459 always_bypass_dcache = "0";\r
1460 iss_trace_on = "0";\r
1461 iss_trace_warning = "1";\r
1462 iss_trace_info = "1";\r
1463 iss_trace_disassembly = "0";\r
1464 iss_trace_registers = "0";\r
1465 iss_trace_instr_count = "0";\r
1466 iss_software_debug = "0";\r
1467 iss_software_debug_port = "9996";\r
1468 iss_memory_dump_start = "";\r
1469 iss_memory_dump_end = "";\r
1470 Boot_Copier = "boot_loader_cfi.srec";\r
1471 Boot_Copier_EPCS = "boot_loader_epcs.srec";\r
1472 Boot_Copier_EPCS_SII_SIII_CIII = "boot_loader_epcs_sii_siii_ciii.srec";\r
1473 Boot_Copier_BE = "boot_loader_cfi_be.srec";\r
1474 Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec";\r
1475 Boot_Copier_EPCS_SII_SIII_CIII_BE = "boot_loader_epcs_sii_siii_ciii_be.srec";\r
1476 CONSTANTS \r
1477 {\r
1478 CONSTANT __nios_catch_irqs__\r
1479 {\r
1480 value = "1";\r
1481 comment = "Include panic handler for all irqs (needs uart)";\r
1482 }\r
1483 CONSTANT __nios_use_constructors__\r
1484 {\r
1485 value = "1";\r
1486 comment = "Call c++ static constructors";\r
1487 }\r
1488 CONSTANT __nios_use_small_printf__\r
1489 {\r
1490 value = "1";\r
1491 comment = "Smaller non-ANSI printf, with no floating point";\r
1492 }\r
1493 CONSTANT nasys_has_icache\r
1494 {\r
1495 value = "1";\r
1496 comment = "True if instruction cache present";\r
1497 }\r
1498 CONSTANT nasys_icache_size\r
1499 {\r
1500 value = "4096";\r
1501 comment = "Size in bytes of instruction cache";\r
1502 }\r
1503 CONSTANT nasys_icache_line_size\r
1504 {\r
1505 value = "32";\r
1506 comment = "Size in bytes of each icache line";\r
1507 }\r
1508 CONSTANT nasys_icache_line_size_log2\r
1509 {\r
1510 value = "5";\r
1511 comment = "Log2 size in bytes of each icache line";\r
1512 }\r
1513 CONSTANT nasys_has_dcache\r
1514 {\r
1515 value = "1";\r
1516 comment = "True if instruction cache present";\r
1517 }\r
1518 CONSTANT nasys_dcache_size\r
1519 {\r
1520 value = "2048";\r
1521 comment = "Size in bytes of data cache";\r
1522 }\r
1523 CONSTANT nasys_dcache_line_size\r
1524 {\r
1525 value = "32";\r
1526 comment = "Size in bytes of each dcache line";\r
1527 }\r
1528 CONSTANT nasys_dcache_line_size_log2\r
1529 {\r
1530 value = "5";\r
1531 comment = "Log2 size in bytes of each dcache line";\r
1532 }\r
1533 }\r
1534 license_status = "ocp";\r
1535 mainmem_slave = "";\r
1536 datamem_slave = "";\r
1537 maincomm_slave = "";\r
1538 germs_monitor_id = "";\r
1539 }\r
1540 class = "altera_nios2";\r
1541 class_version = "7.08";\r
1542 SYSTEM_BUILDER_INFO \r
1543 {\r
1544 Is_Enabled = "1";\r
1545 Clock_Source = "pll_c0_out";\r
1546 Has_Clock = "1";\r
1547 Parameters_Signature = "";\r
1548 Is_CPU = "1";\r
1549 Instantiate_In_System_Module = "1";\r
1550 Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIIGXLITE,STRATIXIII,STRATIXIV,CYCLONE,CYCLONEII,CYCLONEIII";\r
1551 Default_Module_Name = "cpu";\r
1552 Top_Level_Ports_Are_Enumerated = "1";\r
1553 View \r
1554 {\r
1555 Settings_Summary = "Nios II/f
1556 <br> 4-Kbyte Instruction Cache
1557 <br> 2-Kbyte Data Cache
1558 <br> JTAG Debug Module
1559 ";\r
1560 MESSAGES \r
1561 {\r
1562 }\r
1563 }\r
1564 }\r
1565 iss_model_name = "altera_nios2";\r
1566 HDL_INFO \r
1567 {\r
1568 PLI_Files = "";\r
1569 Precompiled_Simulation_Library_Files = "";\r
1570 Simulation_HDL_Files = "";\r
1571 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_test_bench.v, __PROJECT_DIRECTORY__/cpu_mult_cell.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_tck.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_sysclk.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/cpu.v";\r
1572 Synthesis_Only_Files = "";\r
1573 }\r
1574 MASTER tightly_coupled_instruction_master_0\r
1575 {\r
1576 PORT_WIRING \r
1577 {\r
1578 }\r
1579 SYSTEM_BUILDER_INFO \r
1580 {\r
1581 Register_Incoming_Signals = "0";\r
1582 Bus_Type = "avalon";\r
1583 Data_Width = "32";\r
1584 Max_Address_Width = "31";\r
1585 Address_Width = "8";\r
1586 Is_Instruction_Master = "1";\r
1587 Has_IRQ = "0";\r
1588 Is_Enabled = "0";\r
1589 Is_Big_Endian = "0";\r
1590 Connection_Limit = "1";\r
1591 Is_Channel = "1";\r
1592 }\r
1593 }\r
1594 MASTER tightly_coupled_instruction_master_1\r
1595 {\r
1596 PORT_WIRING \r
1597 {\r
1598 }\r
1599 SYSTEM_BUILDER_INFO \r
1600 {\r
1601 Register_Incoming_Signals = "0";\r
1602 Bus_Type = "avalon";\r
1603 Data_Width = "32";\r
1604 Max_Address_Width = "31";\r
1605 Address_Width = "8";\r
1606 Address_Group = "0";\r
1607 Is_Instruction_Master = "1";\r
1608 Is_Readable = "1";\r
1609 Is_Writeable = "0";\r
1610 Has_IRQ = "0";\r
1611 Is_Enabled = "0";\r
1612 Is_Big_Endian = "0";\r
1613 Connection_Limit = "1";\r
1614 Is_Channel = "1";\r
1615 }\r
1616 }\r
1617 MASTER tightly_coupled_instruction_master_2\r
1618 {\r
1619 PORT_WIRING \r
1620 {\r
1621 }\r
1622 SYSTEM_BUILDER_INFO \r
1623 {\r
1624 Register_Incoming_Signals = "0";\r
1625 Bus_Type = "avalon";\r
1626 Data_Width = "32";\r
1627 Max_Address_Width = "31";\r
1628 Address_Width = "8";\r
1629 Address_Group = "0";\r
1630 Is_Instruction_Master = "1";\r
1631 Is_Readable = "1";\r
1632 Is_Writeable = "0";\r
1633 Has_IRQ = "0";\r
1634 Is_Enabled = "0";\r
1635 Is_Big_Endian = "0";\r
1636 Connection_Limit = "1";\r
1637 Is_Channel = "1";\r
1638 }\r
1639 }\r
1640 MASTER tightly_coupled_instruction_master_3\r
1641 {\r
1642 PORT_WIRING \r
1643 {\r
1644 }\r
1645 SYSTEM_BUILDER_INFO \r
1646 {\r
1647 Register_Incoming_Signals = "0";\r
1648 Bus_Type = "avalon";\r
1649 Data_Width = "32";\r
1650 Max_Address_Width = "31";\r
1651 Address_Width = "8";\r
1652 Address_Group = "0";\r
1653 Is_Instruction_Master = "1";\r
1654 Is_Readable = "1";\r
1655 Is_Writeable = "0";\r
1656 Has_IRQ = "0";\r
1657 Is_Enabled = "0";\r
1658 Is_Big_Endian = "0";\r
1659 Connection_Limit = "1";\r
1660 Is_Channel = "1";\r
1661 }\r
1662 }\r
1663 MASTER data_master2\r
1664 {\r
1665 PORT_WIRING \r
1666 {\r
1667 }\r
1668 SYSTEM_BUILDER_INFO \r
1669 {\r
1670 Register_Incoming_Signals = "1";\r
1671 Bus_Type = "avalon";\r
1672 Data_Width = "32";\r
1673 Max_Address_Width = "31";\r
1674 Address_Width = "8";\r
1675 Address_Group = "0";\r
1676 Is_Data_Master = "1";\r
1677 Is_Readable = "1";\r
1678 Is_Writeable = "1";\r
1679 Has_IRQ = "0";\r
1680 Is_Enabled = "0";\r
1681 Is_Big_Endian = "0";\r
1682 }\r
1683 }\r
1684 MASTER tightly_coupled_data_master_0\r
1685 {\r
1686 PORT_WIRING \r
1687 {\r
1688 }\r
1689 SYSTEM_BUILDER_INFO \r
1690 {\r
1691 Register_Incoming_Signals = "0";\r
1692 Bus_Type = "avalon";\r
1693 Data_Width = "32";\r
1694 Max_Address_Width = "31";\r
1695 Address_Width = "8";\r
1696 Address_Group = "0";\r
1697 Is_Data_Master = "1";\r
1698 Is_Readable = "1";\r
1699 Is_Writeable = "1";\r
1700 Has_IRQ = "0";\r
1701 Is_Enabled = "0";\r
1702 Is_Big_Endian = "0";\r
1703 Connection_Limit = "1";\r
1704 Is_Channel = "1";\r
1705 }\r
1706 }\r
1707 MASTER tightly_coupled_data_master_1\r
1708 {\r
1709 PORT_WIRING \r
1710 {\r
1711 }\r
1712 SYSTEM_BUILDER_INFO \r
1713 {\r
1714 Register_Incoming_Signals = "0";\r
1715 Bus_Type = "avalon";\r
1716 Data_Width = "32";\r
1717 Max_Address_Width = "31";\r
1718 Address_Width = "8";\r
1719 Address_Group = "0";\r
1720 Is_Data_Master = "1";\r
1721 Is_Readable = "1";\r
1722 Is_Writeable = "1";\r
1723 Has_IRQ = "0";\r
1724 Is_Enabled = "0";\r
1725 Is_Big_Endian = "0";\r
1726 Connection_Limit = "1";\r
1727 Is_Channel = "1";\r
1728 }\r
1729 }\r
1730 MASTER tightly_coupled_data_master_2\r
1731 {\r
1732 PORT_WIRING \r
1733 {\r
1734 }\r
1735 SYSTEM_BUILDER_INFO \r
1736 {\r
1737 Register_Incoming_Signals = "0";\r
1738 Bus_Type = "avalon";\r
1739 Data_Width = "32";\r
1740 Max_Address_Width = "31";\r
1741 Address_Width = "8";\r
1742 Address_Group = "0";\r
1743 Is_Data_Master = "1";\r
1744 Is_Readable = "1";\r
1745 Is_Writeable = "1";\r
1746 Has_IRQ = "0";\r
1747 Is_Enabled = "0";\r
1748 Is_Big_Endian = "0";\r
1749 Connection_Limit = "1";\r
1750 Is_Channel = "1";\r
1751 }\r
1752 }\r
1753 MASTER tightly_coupled_data_master_3\r
1754 {\r
1755 PORT_WIRING \r
1756 {\r
1757 }\r
1758 SYSTEM_BUILDER_INFO \r
1759 {\r
1760 Register_Incoming_Signals = "0";\r
1761 Bus_Type = "avalon";\r
1762 Data_Width = "32";\r
1763 Max_Address_Width = "31";\r
1764 Address_Width = "8";\r
1765 Address_Group = "0";\r
1766 Is_Data_Master = "1";\r
1767 Is_Readable = "1";\r
1768 Is_Writeable = "1";\r
1769 Has_IRQ = "0";\r
1770 Is_Enabled = "0";\r
1771 Is_Big_Endian = "0";\r
1772 Connection_Limit = "1";\r
1773 Is_Channel = "1";\r
1774 }\r
1775 }\r
1776 PORT_WIRING \r
1777 {\r
1778 PORT jtag_debug_trigout\r
1779 {\r
1780 width = "1";\r
1781 direction = "output";\r
1782 Is_Enabled = "0";\r
1783 }\r
1784 PORT jtag_debug_offchip_trace_clk\r
1785 {\r
1786 width = "1";\r
1787 direction = "output";\r
1788 Is_Enabled = "0";\r
1789 }\r
1790 PORT jtag_debug_offchip_trace_data\r
1791 {\r
1792 width = "18";\r
1793 direction = "output";\r
1794 Is_Enabled = "0";\r
1795 }\r
1796 PORT clkx2\r
1797 {\r
1798 width = "1";\r
1799 direction = "input";\r
1800 Is_Enabled = "0";\r
1801 visible = "0";\r
1802 }\r
1803 }\r
1804 SIMULATION \r
1805 {\r
1806 DISPLAY \r
1807 {\r
1808 SIGNAL aaa\r
1809 {\r
1810 format = "Logic";\r
1811 name = "i_readdata";\r
1812 radix = "hexadecimal";\r
1813 }\r
1814 SIGNAL aab\r
1815 {\r
1816 format = "Logic";\r
1817 name = "i_readdatavalid";\r
1818 radix = "hexadecimal";\r
1819 }\r
1820 SIGNAL aac\r
1821 {\r
1822 format = "Logic";\r
1823 name = "i_waitrequest";\r
1824 radix = "hexadecimal";\r
1825 }\r
1826 SIGNAL aad\r
1827 {\r
1828 format = "Logic";\r
1829 name = "i_address";\r
1830 radix = "hexadecimal";\r
1831 }\r
1832 SIGNAL aae\r
1833 {\r
1834 format = "Logic";\r
1835 name = "i_read";\r
1836 radix = "hexadecimal";\r
1837 }\r
1838 SIGNAL aaf\r
1839 {\r
1840 format = "Logic";\r
1841 name = "clk";\r
1842 radix = "hexadecimal";\r
1843 }\r
1844 SIGNAL aag\r
1845 {\r
1846 format = "Logic";\r
1847 name = "reset_n";\r
1848 radix = "hexadecimal";\r
1849 }\r
1850 SIGNAL aah\r
1851 {\r
1852 format = "Logic";\r
1853 name = "d_readdata";\r
1854 radix = "hexadecimal";\r
1855 }\r
1856 SIGNAL aai\r
1857 {\r
1858 format = "Logic";\r
1859 name = "d_waitrequest";\r
1860 radix = "hexadecimal";\r
1861 }\r
1862 SIGNAL aaj\r
1863 {\r
1864 format = "Logic";\r
1865 name = "d_irq";\r
1866 radix = "hexadecimal";\r
1867 }\r
1868 SIGNAL aak\r
1869 {\r
1870 format = "Logic";\r
1871 name = "d_address";\r
1872 radix = "hexadecimal";\r
1873 }\r
1874 SIGNAL aal\r
1875 {\r
1876 format = "Logic";\r
1877 name = "d_byteenable";\r
1878 radix = "hexadecimal";\r
1879 }\r
1880 SIGNAL aam\r
1881 {\r
1882 format = "Logic";\r
1883 name = "d_read";\r
1884 radix = "hexadecimal";\r
1885 }\r
1886 SIGNAL aan\r
1887 {\r
1888 format = "Logic";\r
1889 name = "d_write";\r
1890 radix = "hexadecimal";\r
1891 }\r
1892 SIGNAL aao\r
1893 {\r
1894 format = "Logic";\r
1895 name = "d_writedata";\r
1896 radix = "hexadecimal";\r
1897 }\r
1898 SIGNAL aap\r
1899 {\r
1900 format = "Logic";\r
1901 name = "d_readdatavalid";\r
1902 radix = "hexadecimal";\r
1903 }\r
1904 SIGNAL aaq\r
1905 {\r
1906 format = "Divider";\r
1907 name = "base pipeline";\r
1908 radix = "";\r
1909 }\r
1910 SIGNAL aar\r
1911 {\r
1912 format = "Logic";\r
1913 name = "clk";\r
1914 radix = "hexadecimal";\r
1915 }\r
1916 SIGNAL aas\r
1917 {\r
1918 format = "Logic";\r
1919 name = "reset_n";\r
1920 radix = "hexadecimal";\r
1921 }\r
1922 SIGNAL aat\r
1923 {\r
1924 format = "Logic";\r
1925 name = "D_stall";\r
1926 radix = "hexadecimal";\r
1927 }\r
1928 SIGNAL aau\r
1929 {\r
1930 format = "Logic";\r
1931 name = "A_stall";\r
1932 radix = "hexadecimal";\r
1933 }\r
1934 SIGNAL aav\r
1935 {\r
1936 format = "Logic";\r
1937 name = "F_pcb_nxt";\r
1938 radix = "hexadecimal";\r
1939 }\r
1940 SIGNAL aaw\r
1941 {\r
1942 format = "Logic";\r
1943 name = "F_pcb";\r
1944 radix = "hexadecimal";\r
1945 }\r
1946 SIGNAL aax\r
1947 {\r
1948 format = "Logic";\r
1949 name = "D_pcb";\r
1950 radix = "hexadecimal";\r
1951 }\r
1952 SIGNAL aay\r
1953 {\r
1954 format = "Logic";\r
1955 name = "E_pcb";\r
1956 radix = "hexadecimal";\r
1957 }\r
1958 SIGNAL aaz\r
1959 {\r
1960 format = "Logic";\r
1961 name = "M_pcb";\r
1962 radix = "hexadecimal";\r
1963 }\r
1964 SIGNAL aba\r
1965 {\r
1966 format = "Logic";\r
1967 name = "A_pcb";\r
1968 radix = "hexadecimal";\r
1969 }\r
1970 SIGNAL abb\r
1971 {\r
1972 format = "Logic";\r
1973 name = "W_pcb";\r
1974 radix = "hexadecimal";\r
1975 }\r
1976 SIGNAL abc\r
1977 {\r
1978 format = "Logic";\r
1979 name = "F_vinst";\r
1980 radix = "ascii";\r
1981 }\r
1982 SIGNAL abd\r
1983 {\r
1984 format = "Logic";\r
1985 name = "D_vinst";\r
1986 radix = "ascii";\r
1987 }\r
1988 SIGNAL abe\r
1989 {\r
1990 format = "Logic";\r
1991 name = "E_vinst";\r
1992 radix = "ascii";\r
1993 }\r
1994 SIGNAL abf\r
1995 {\r
1996 format = "Logic";\r
1997 name = "M_vinst";\r
1998 radix = "ascii";\r
1999 }\r
2000 SIGNAL abg\r
2001 {\r
2002 format = "Logic";\r
2003 name = "A_vinst";\r
2004 radix = "ascii";\r
2005 }\r
2006 SIGNAL abh\r
2007 {\r
2008 format = "Logic";\r
2009 name = "W_vinst";\r
2010 radix = "ascii";\r
2011 }\r
2012 SIGNAL abi\r
2013 {\r
2014 format = "Logic";\r
2015 name = "F_inst_ram_hit";\r
2016 radix = "hexadecimal";\r
2017 }\r
2018 SIGNAL abj\r
2019 {\r
2020 format = "Logic";\r
2021 name = "F_issue";\r
2022 radix = "hexadecimal";\r
2023 }\r
2024 SIGNAL abk\r
2025 {\r
2026 format = "Logic";\r
2027 name = "F_kill";\r
2028 radix = "hexadecimal";\r
2029 }\r
2030 SIGNAL abl\r
2031 {\r
2032 format = "Logic";\r
2033 name = "D_kill";\r
2034 radix = "hexadecimal";\r
2035 }\r
2036 SIGNAL abm\r
2037 {\r
2038 format = "Logic";\r
2039 name = "D_refetch";\r
2040 radix = "hexadecimal";\r
2041 }\r
2042 SIGNAL abn\r
2043 {\r
2044 format = "Logic";\r
2045 name = "D_issue";\r
2046 radix = "hexadecimal";\r
2047 }\r
2048 SIGNAL abo\r
2049 {\r
2050 format = "Logic";\r
2051 name = "D_valid";\r
2052 radix = "hexadecimal";\r
2053 }\r
2054 SIGNAL abp\r
2055 {\r
2056 format = "Logic";\r
2057 name = "E_valid";\r
2058 radix = "hexadecimal";\r
2059 }\r
2060 SIGNAL abq\r
2061 {\r
2062 format = "Logic";\r
2063 name = "M_valid";\r
2064 radix = "hexadecimal";\r
2065 }\r
2066 SIGNAL abr\r
2067 {\r
2068 format = "Logic";\r
2069 name = "A_valid";\r
2070 radix = "hexadecimal";\r
2071 }\r
2072 SIGNAL abs\r
2073 {\r
2074 format = "Logic";\r
2075 name = "W_valid";\r
2076 radix = "hexadecimal";\r
2077 }\r
2078 SIGNAL abt\r
2079 {\r
2080 format = "Logic";\r
2081 name = "W_wr_dst_reg";\r
2082 radix = "hexadecimal";\r
2083 }\r
2084 SIGNAL abu\r
2085 {\r
2086 format = "Logic";\r
2087 name = "W_dst_regnum";\r
2088 radix = "hexadecimal";\r
2089 }\r
2090 SIGNAL abv\r
2091 {\r
2092 format = "Logic";\r
2093 name = "W_wr_data";\r
2094 radix = "hexadecimal";\r
2095 }\r
2096 SIGNAL abw\r
2097 {\r
2098 format = "Logic";\r
2099 name = "D_en";\r
2100 radix = "hexadecimal";\r
2101 }\r
2102 SIGNAL abx\r
2103 {\r
2104 format = "Logic";\r
2105 name = "E_en";\r
2106 radix = "hexadecimal";\r
2107 }\r
2108 SIGNAL aby\r
2109 {\r
2110 format = "Logic";\r
2111 name = "M_en";\r
2112 radix = "hexadecimal";\r
2113 }\r
2114 SIGNAL abz\r
2115 {\r
2116 format = "Logic";\r
2117 name = "A_en";\r
2118 radix = "hexadecimal";\r
2119 }\r
2120 SIGNAL aca\r
2121 {\r
2122 format = "Logic";\r
2123 name = "F_iw";\r
2124 radix = "hexadecimal";\r
2125 }\r
2126 SIGNAL acb\r
2127 {\r
2128 format = "Logic";\r
2129 name = "D_iw";\r
2130 radix = "hexadecimal";\r
2131 }\r
2132 SIGNAL acc\r
2133 {\r
2134 format = "Logic";\r
2135 name = "E_iw";\r
2136 radix = "hexadecimal";\r
2137 }\r
2138 SIGNAL acd\r
2139 {\r
2140 format = "Logic";\r
2141 name = "M_pipe_flush";\r
2142 radix = "hexadecimal";\r
2143 }\r
2144 SIGNAL ace\r
2145 {\r
2146 format = "Logic";\r
2147 name = "M_pipe_flush_baddr";\r
2148 radix = "hexadecimal";\r
2149 }\r
2150 SIGNAL acf\r
2151 {\r
2152 format = "Logic";\r
2153 name = "A_ienable_reg";\r
2154 radix = "hexadecimal";\r
2155 }\r
2156 SIGNAL acg\r
2157 {\r
2158 format = "Logic";\r
2159 name = "A_status_reg_pie";\r
2160 radix = "hexadecimal";\r
2161 }\r
2162 SIGNAL ach\r
2163 {\r
2164 format = "Logic";\r
2165 name = "intr_req";\r
2166 radix = "hexadecimal";\r
2167 }\r
2168 SIGNAL aci\r
2169 {\r
2170 format = "Logic";\r
2171 name = "E_valid_prior_to_hbreak";\r
2172 radix = "hexadecimal";\r
2173 }\r
2174 }\r
2175 }\r
2176 }\r
2177 MODULE flash_ssram_pipeline_bridge\r
2178 {\r
2179 SLAVE s1\r
2180 {\r
2181 PORT_WIRING \r
2182 {\r
2183 PORT clk\r
2184 {\r
2185 type = "clk";\r
2186 width = "1";\r
2187 direction = "input";\r
2188 Is_Enabled = "1";\r
2189 }\r
2190 PORT reset_n\r
2191 {\r
2192 type = "reset_n";\r
2193 width = "1";\r
2194 direction = "input";\r
2195 Is_Enabled = "1";\r
2196 }\r
2197 PORT s1_address\r
2198 {\r
2199 type = "address";\r
2200 width = "23";\r
2201 direction = "input";\r
2202 Is_Enabled = "1";\r
2203 }\r
2204 PORT s1_nativeaddress\r
2205 {\r
2206 type = "nativeaddress";\r
2207 width = "23";\r
2208 direction = "input";\r
2209 Is_Enabled = "1";\r
2210 }\r
2211 PORT s1_burstcount\r
2212 {\r
2213 type = "burstcount";\r
2214 width = "1";\r
2215 direction = "input";\r
2216 Is_Enabled = "1";\r
2217 }\r
2218 PORT s1_byteenable\r
2219 {\r
2220 type = "byteenable";\r
2221 width = "4";\r
2222 direction = "input";\r
2223 Is_Enabled = "1";\r
2224 }\r
2225 PORT s1_chipselect\r
2226 {\r
2227 type = "chipselect";\r
2228 width = "1";\r
2229 direction = "input";\r
2230 Is_Enabled = "1";\r
2231 }\r
2232 PORT s1_debugaccess\r
2233 {\r
2234 type = "debugaccess";\r
2235 width = "1";\r
2236 direction = "input";\r
2237 Is_Enabled = "1";\r
2238 }\r
2239 PORT s1_read\r
2240 {\r
2241 type = "read";\r
2242 width = "1";\r
2243 direction = "input";\r
2244 Is_Enabled = "1";\r
2245 }\r
2246 PORT s1_write\r
2247 {\r
2248 type = "write";\r
2249 width = "1";\r
2250 direction = "input";\r
2251 Is_Enabled = "1";\r
2252 }\r
2253 PORT s1_writedata\r
2254 {\r
2255 type = "writedata";\r
2256 width = "32";\r
2257 direction = "input";\r
2258 Is_Enabled = "1";\r
2259 }\r
2260 PORT s1_endofpacket\r
2261 {\r
2262 type = "endofpacket";\r
2263 width = "1";\r
2264 direction = "output";\r
2265 Is_Enabled = "1";\r
2266 }\r
2267 PORT s1_readdata\r
2268 {\r
2269 type = "readdata";\r
2270 width = "32";\r
2271 direction = "output";\r
2272 Is_Enabled = "1";\r
2273 }\r
2274 PORT s1_readdatavalid\r
2275 {\r
2276 type = "readdatavalid";\r
2277 width = "1";\r
2278 direction = "output";\r
2279 Is_Enabled = "1";\r
2280 }\r
2281 PORT s1_waitrequest\r
2282 {\r
2283 type = "waitrequest";\r
2284 width = "1";\r
2285 direction = "output";\r
2286 Is_Enabled = "1";\r
2287 }\r
2288 PORT s1_arbiterlock\r
2289 {\r
2290 Is_Enabled = "1";\r
2291 direction = "input";\r
2292 type = "arbiterlock";\r
2293 width = "1";\r
2294 }\r
2295 PORT s1_arbiterlock2\r
2296 {\r
2297 Is_Enabled = "1";\r
2298 direction = "input";\r
2299 type = "arbiterlock2";\r
2300 width = "1";\r
2301 }\r
2302 PORT s1_clk\r
2303 {\r
2304 Is_Enabled = "0";\r
2305 direction = "input";\r
2306 type = "clk";\r
2307 width = "1";\r
2308 }\r
2309 PORT s1_flush\r
2310 {\r
2311 Is_Enabled = "0";\r
2312 direction = "input";\r
2313 type = "flush";\r
2314 width = "1";\r
2315 }\r
2316 PORT s1_reset_n\r
2317 {\r
2318 Is_Enabled = "0";\r
2319 direction = "input";\r
2320 type = "reset_n";\r
2321 width = "1";\r
2322 }\r
2323 }\r
2324 SYSTEM_BUILDER_INFO \r
2325 {\r
2326 Bus_Type = "avalon";\r
2327 Read_Wait_States = "peripheral_controlled";\r
2328 Write_Wait_States = "peripheral_controlled";\r
2329 Hold_Time = "0cycles";\r
2330 Setup_Time = "0cycles";\r
2331 Is_Printable_Device = "0";\r
2332 Address_Alignment = "dynamic";\r
2333 Well_Behaved_Waitrequest = "0";\r
2334 Is_Nonvolatile_Storage = "0";\r
2335 Address_Span = "33554432";\r
2336 Read_Latency = "0";\r
2337 Is_Memory_Device = "0";\r
2338 Maximum_Pending_Read_Transactions = "10";\r
2339 Minimum_Uninterrupted_Run_Length = "1";\r
2340 Accepts_Internal_Connections = "1";\r
2341 Write_Latency = "0";\r
2342 Is_Flash = "0";\r
2343 Data_Width = "32";\r
2344 Address_Width = "23";\r
2345 Opaque_Bridges_To = "m1";\r
2346 Maximum_Burst_Size = "1";\r
2347 Register_Incoming_Signals = "0";\r
2348 Register_Outgoing_Signals = "0";\r
2349 Interleave_Bursts = "0";\r
2350 Linewrap_Bursts = "0";\r
2351 Burst_On_Burst_Boundaries_Only = "0";\r
2352 Always_Burst_Max_Burst = "0";\r
2353 Is_Big_Endian = "0";\r
2354 Is_Enabled = "1";\r
2355 MASTERED_BY cpu/data_master\r
2356 {\r
2357 priority = "1";\r
2358 Offset_Address = "0x04000000";\r
2359 }\r
2360 MASTERED_BY cpu/instruction_master\r
2361 {\r
2362 priority = "1";\r
2363 Offset_Address = "0x04000000";\r
2364 }\r
2365 Base_Address = "0x04000000";\r
2366 Has_IRQ = "0";\r
2367 Address_Group = "0";\r
2368 IRQ_MASTER cpu/data_master\r
2369 {\r
2370 IRQ_Number = "NC";\r
2371 }\r
2372 }\r
2373 }\r
2374 MASTER m1\r
2375 {\r
2376 SYSTEM_BUILDER_INFO \r
2377 {\r
2378 Bus_Type = "avalon";\r
2379 Is_Asynchronous = "0";\r
2380 DBS_Big_Endian = "0";\r
2381 Adapts_To = "";\r
2382 Do_Stream_Reads = "0";\r
2383 Do_Stream_Writes = "0";\r
2384 Max_Address_Width = "32";\r
2385 Data_Width = "32";\r
2386 Address_Width = "25";\r
2387 Opaque_Bridges_To = "s1";\r
2388 Maximum_Burst_Size = "1";\r
2389 Register_Incoming_Signals = "0";\r
2390 Register_Outgoing_Signals = "0";\r
2391 Interleave_Bursts = "0";\r
2392 Linewrap_Bursts = "0";\r
2393 Burst_On_Burst_Boundaries_Only = "0";\r
2394 Always_Burst_Max_Burst = "0";\r
2395 Is_Big_Endian = "0";\r
2396 Is_Enabled = "1";\r
2397 }\r
2398 PORT_WIRING \r
2399 {\r
2400 PORT m1_address\r
2401 {\r
2402 type = "address";\r
2403 width = "25";\r
2404 direction = "output";\r
2405 Is_Enabled = "1";\r
2406 }\r
2407 PORT m1_nativeaddress\r
2408 {\r
2409 type = "nativeaddress";\r
2410 width = "23";\r
2411 direction = "output";\r
2412 Is_Enabled = "0";\r
2413 }\r
2414 PORT m1_burstcount\r
2415 {\r
2416 type = "burstcount";\r
2417 width = "1";\r
2418 direction = "output";\r
2419 Is_Enabled = "1";\r
2420 }\r
2421 PORT m1_byteenable\r
2422 {\r
2423 type = "byteenable";\r
2424 width = "4";\r
2425 direction = "output";\r
2426 Is_Enabled = "1";\r
2427 }\r
2428 PORT m1_chipselect\r
2429 {\r
2430 type = "chipselect";\r
2431 width = "1";\r
2432 direction = "output";\r
2433 Is_Enabled = "1";\r
2434 }\r
2435 PORT m1_debugaccess\r
2436 {\r
2437 type = "debugaccess";\r
2438 width = "1";\r
2439 direction = "output";\r
2440 Is_Enabled = "1";\r
2441 }\r
2442 PORT m1_read\r
2443 {\r
2444 type = "read";\r
2445 width = "1";\r
2446 direction = "output";\r
2447 Is_Enabled = "1";\r
2448 }\r
2449 PORT m1_write\r
2450 {\r
2451 type = "write";\r
2452 width = "1";\r
2453 direction = "output";\r
2454 Is_Enabled = "1";\r
2455 }\r
2456 PORT m1_writedata\r
2457 {\r
2458 type = "writedata";\r
2459 width = "32";\r
2460 direction = "output";\r
2461 Is_Enabled = "1";\r
2462 }\r
2463 PORT m1_endofpacket\r
2464 {\r
2465 type = "endofpacket";\r
2466 width = "1";\r
2467 direction = "input";\r
2468 Is_Enabled = "1";\r
2469 }\r
2470 PORT m1_readdata\r
2471 {\r
2472 type = "readdata";\r
2473 width = "32";\r
2474 direction = "input";\r
2475 Is_Enabled = "1";\r
2476 }\r
2477 PORT m1_readdatavalid\r
2478 {\r
2479 type = "readdatavalid";\r
2480 width = "1";\r
2481 direction = "input";\r
2482 Is_Enabled = "1";\r
2483 }\r
2484 PORT m1_waitrequest\r
2485 {\r
2486 type = "waitrequest";\r
2487 width = "1";\r
2488 direction = "input";\r
2489 Is_Enabled = "1";\r
2490 }\r
2491 PORT m1_arbiterlock\r
2492 {\r
2493 Is_Enabled = "0";\r
2494 direction = "output";\r
2495 type = "arbiterlock";\r
2496 width = "1";\r
2497 }\r
2498 PORT m1_arbiterlock2\r
2499 {\r
2500 Is_Enabled = "0";\r
2501 direction = "output";\r
2502 type = "arbiterlock2";\r
2503 width = "1";\r
2504 }\r
2505 PORT m1_clk\r
2506 {\r
2507 Is_Enabled = "0";\r
2508 direction = "input";\r
2509 type = "clk";\r
2510 width = "1";\r
2511 }\r
2512 PORT m1_reset_n\r
2513 {\r
2514 Is_Enabled = "0";\r
2515 direction = "input";\r
2516 type = "reset_n";\r
2517 width = "1";\r
2518 }\r
2519 }\r
2520 MEMORY_MAP \r
2521 {\r
2522 Entry pipeline_bridge_before_tristate_bridge/s1\r
2523 {\r
2524 address = "0x00000000";\r
2525 span = "0x02000000";\r
2526 is_bridge = "1";\r
2527 }\r
2528 Entry ext_flash/s1\r
2529 {\r
2530 address = "0x00000000";\r
2531 span = "0x01000000";\r
2532 is_bridge = "0";\r
2533 }\r
2534 Entry ssram/s1\r
2535 {\r
2536 address = "0x01000000";\r
2537 span = "0x00100000";\r
2538 is_bridge = "0";\r
2539 }\r
2540 }\r
2541 }\r
2542 WIZARD_SCRIPT_ARGUMENTS \r
2543 {\r
2544 Is_Downstream = "1";\r
2545 Is_Upstream = "1";\r
2546 Is_Waitrequest = "1";\r
2547 Enable_Arbiterlock = "0";\r
2548 }\r
2549 class = "altera_avalon_pipeline_bridge";\r
2550 class_version = "7.08";\r
2551 SYSTEM_BUILDER_INFO \r
2552 {\r
2553 Is_Enabled = "1";\r
2554 Clock_Source = "pll_c0_out";\r
2555 Has_Clock = "1";\r
2556 Instantiate_In_System_Module = "1";\r
2557 Is_Bridge = "1";\r
2558 Top_Level_Ports_Are_Enumerated = "1";\r
2559 View \r
2560 {\r
2561 MESSAGES \r
2562 {\r
2563 }\r
2564 }\r
2565 }\r
2566 HDL_INFO \r
2567 {\r
2568 Precompiled_Simulation_Library_Files = "";\r
2569 Simulation_HDL_Files = "";\r
2570 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/flash_ssram_pipeline_bridge.v";\r
2571 Synthesis_Only_Files = "";\r
2572 }\r
2573 PORT_WIRING \r
2574 {\r
2575 }\r
2576 }\r
2577 MODULE pipeline_bridge_before_tristate_bridge\r
2578 {\r
2579 SLAVE s1\r
2580 {\r
2581 PORT_WIRING \r
2582 {\r
2583 PORT clk\r
2584 {\r
2585 type = "clk";\r
2586 width = "1";\r
2587 direction = "input";\r
2588 Is_Enabled = "1";\r
2589 }\r
2590 PORT reset_n\r
2591 {\r
2592 type = "reset_n";\r
2593 width = "1";\r
2594 direction = "input";\r
2595 Is_Enabled = "1";\r
2596 }\r
2597 PORT s1_address\r
2598 {\r
2599 type = "address";\r
2600 width = "23";\r
2601 direction = "input";\r
2602 Is_Enabled = "1";\r
2603 }\r
2604 PORT s1_nativeaddress\r
2605 {\r
2606 type = "nativeaddress";\r
2607 width = "23";\r
2608 direction = "input";\r
2609 Is_Enabled = "1";\r
2610 }\r
2611 PORT s1_burstcount\r
2612 {\r
2613 type = "burstcount";\r
2614 width = "1";\r
2615 direction = "input";\r
2616 Is_Enabled = "1";\r
2617 }\r
2618 PORT s1_byteenable\r
2619 {\r
2620 type = "byteenable";\r
2621 width = "4";\r
2622 direction = "input";\r
2623 Is_Enabled = "1";\r
2624 }\r
2625 PORT s1_chipselect\r
2626 {\r
2627 type = "chipselect";\r
2628 width = "1";\r
2629 direction = "input";\r
2630 Is_Enabled = "1";\r
2631 }\r
2632 PORT s1_debugaccess\r
2633 {\r
2634 type = "debugaccess";\r
2635 width = "1";\r
2636 direction = "input";\r
2637 Is_Enabled = "1";\r
2638 }\r
2639 PORT s1_read\r
2640 {\r
2641 type = "read";\r
2642 width = "1";\r
2643 direction = "input";\r
2644 Is_Enabled = "1";\r
2645 }\r
2646 PORT s1_write\r
2647 {\r
2648 type = "write";\r
2649 width = "1";\r
2650 direction = "input";\r
2651 Is_Enabled = "1";\r
2652 }\r
2653 PORT s1_writedata\r
2654 {\r
2655 type = "writedata";\r
2656 width = "32";\r
2657 direction = "input";\r
2658 Is_Enabled = "1";\r
2659 }\r
2660 PORT s1_endofpacket\r
2661 {\r
2662 type = "endofpacket";\r
2663 width = "1";\r
2664 direction = "output";\r
2665 Is_Enabled = "1";\r
2666 }\r
2667 PORT s1_readdata\r
2668 {\r
2669 type = "readdata";\r
2670 width = "32";\r
2671 direction = "output";\r
2672 Is_Enabled = "1";\r
2673 }\r
2674 PORT s1_readdatavalid\r
2675 {\r
2676 type = "readdatavalid";\r
2677 width = "1";\r
2678 direction = "output";\r
2679 Is_Enabled = "1";\r
2680 }\r
2681 PORT s1_waitrequest\r
2682 {\r
2683 type = "waitrequest";\r
2684 width = "1";\r
2685 direction = "output";\r
2686 Is_Enabled = "1";\r
2687 }\r
2688 PORT s1_arbiterlock\r
2689 {\r
2690 Is_Enabled = "1";\r
2691 direction = "input";\r
2692 type = "arbiterlock";\r
2693 width = "1";\r
2694 }\r
2695 PORT s1_arbiterlock2\r
2696 {\r
2697 Is_Enabled = "1";\r
2698 direction = "input";\r
2699 type = "arbiterlock2";\r
2700 width = "1";\r
2701 }\r
2702 PORT s1_clk\r
2703 {\r
2704 Is_Enabled = "0";\r
2705 direction = "input";\r
2706 type = "clk";\r
2707 width = "1";\r
2708 }\r
2709 PORT s1_flush\r
2710 {\r
2711 Is_Enabled = "0";\r
2712 direction = "input";\r
2713 type = "flush";\r
2714 width = "1";\r
2715 }\r
2716 PORT s1_reset_n\r
2717 {\r
2718 Is_Enabled = "0";\r
2719 direction = "input";\r
2720 type = "reset_n";\r
2721 width = "1";\r
2722 }\r
2723 }\r
2724 SYSTEM_BUILDER_INFO \r
2725 {\r
2726 Bus_Type = "avalon";\r
2727 Read_Wait_States = "peripheral_controlled";\r
2728 Write_Wait_States = "peripheral_controlled";\r
2729 Hold_Time = "0cycles";\r
2730 Setup_Time = "0cycles";\r
2731 Is_Printable_Device = "0";\r
2732 Address_Alignment = "dynamic";\r
2733 Well_Behaved_Waitrequest = "0";\r
2734 Is_Nonvolatile_Storage = "0";\r
2735 Address_Span = "33554432";\r
2736 Read_Latency = "0";\r
2737 Is_Memory_Device = "0";\r
2738 Maximum_Pending_Read_Transactions = "7";\r
2739 Minimum_Uninterrupted_Run_Length = "1";\r
2740 Accepts_Internal_Connections = "1";\r
2741 Write_Latency = "0";\r
2742 Is_Flash = "0";\r
2743 Data_Width = "32";\r
2744 Address_Width = "23";\r
2745 Opaque_Bridges_To = "m1";\r
2746 Maximum_Burst_Size = "1";\r
2747 Register_Incoming_Signals = "0";\r
2748 Register_Outgoing_Signals = "0";\r
2749 Interleave_Bursts = "0";\r
2750 Linewrap_Bursts = "0";\r
2751 Burst_On_Burst_Boundaries_Only = "0";\r
2752 Always_Burst_Max_Burst = "0";\r
2753 Is_Big_Endian = "0";\r
2754 Is_Enabled = "1";\r
2755 MASTERED_BY flash_ssram_pipeline_bridge/m1\r
2756 {\r
2757 priority = "8";\r
2758 Offset_Address = "0x00000000";\r
2759 }\r
2760 Base_Address = "0x04000000";\r
2761 Has_IRQ = "0";\r
2762 Address_Group = "0";\r
2763 }\r
2764 }\r
2765 MASTER m1\r
2766 {\r
2767 SYSTEM_BUILDER_INFO \r
2768 {\r
2769 Bus_Type = "avalon";\r
2770 Is_Asynchronous = "0";\r
2771 DBS_Big_Endian = "0";\r
2772 Adapts_To = "";\r
2773 Do_Stream_Reads = "0";\r
2774 Do_Stream_Writes = "0";\r
2775 Max_Address_Width = "32";\r
2776 Data_Width = "32";\r
2777 Address_Width = "25";\r
2778 Opaque_Bridges_To = "s1";\r
2779 Maximum_Burst_Size = "1";\r
2780 Register_Incoming_Signals = "0";\r
2781 Register_Outgoing_Signals = "0";\r
2782 Interleave_Bursts = "0";\r
2783 Linewrap_Bursts = "0";\r
2784 Burst_On_Burst_Boundaries_Only = "0";\r
2785 Always_Burst_Max_Burst = "0";\r
2786 Is_Big_Endian = "0";\r
2787 Is_Enabled = "1";\r
2788 }\r
2789 PORT_WIRING \r
2790 {\r
2791 PORT m1_address\r
2792 {\r
2793 type = "address";\r
2794 width = "25";\r
2795 direction = "output";\r
2796 Is_Enabled = "1";\r
2797 }\r
2798 PORT m1_nativeaddress\r
2799 {\r
2800 type = "nativeaddress";\r
2801 width = "23";\r
2802 direction = "output";\r
2803 Is_Enabled = "0";\r
2804 }\r
2805 PORT m1_burstcount\r
2806 {\r
2807 type = "burstcount";\r
2808 width = "1";\r
2809 direction = "output";\r
2810 Is_Enabled = "1";\r
2811 }\r
2812 PORT m1_byteenable\r
2813 {\r
2814 type = "byteenable";\r
2815 width = "4";\r
2816 direction = "output";\r
2817 Is_Enabled = "1";\r
2818 }\r
2819 PORT m1_chipselect\r
2820 {\r
2821 type = "chipselect";\r
2822 width = "1";\r
2823 direction = "output";\r
2824 Is_Enabled = "1";\r
2825 }\r
2826 PORT m1_debugaccess\r
2827 {\r
2828 type = "debugaccess";\r
2829 width = "1";\r
2830 direction = "output";\r
2831 Is_Enabled = "1";\r
2832 }\r
2833 PORT m1_read\r
2834 {\r
2835 type = "read";\r
2836 width = "1";\r
2837 direction = "output";\r
2838 Is_Enabled = "1";\r
2839 }\r
2840 PORT m1_write\r
2841 {\r
2842 type = "write";\r
2843 width = "1";\r
2844 direction = "output";\r
2845 Is_Enabled = "1";\r
2846 }\r
2847 PORT m1_writedata\r
2848 {\r
2849 type = "writedata";\r
2850 width = "32";\r
2851 direction = "output";\r
2852 Is_Enabled = "1";\r
2853 }\r
2854 PORT m1_endofpacket\r
2855 {\r
2856 type = "endofpacket";\r
2857 width = "1";\r
2858 direction = "input";\r
2859 Is_Enabled = "1";\r
2860 }\r
2861 PORT m1_readdata\r
2862 {\r
2863 type = "readdata";\r
2864 width = "32";\r
2865 direction = "input";\r
2866 Is_Enabled = "1";\r
2867 }\r
2868 PORT m1_readdatavalid\r
2869 {\r
2870 type = "readdatavalid";\r
2871 width = "1";\r
2872 direction = "input";\r
2873 Is_Enabled = "1";\r
2874 }\r
2875 PORT m1_waitrequest\r
2876 {\r
2877 type = "waitrequest";\r
2878 width = "1";\r
2879 direction = "input";\r
2880 Is_Enabled = "1";\r
2881 }\r
2882 PORT m1_arbiterlock\r
2883 {\r
2884 Is_Enabled = "0";\r
2885 direction = "output";\r
2886 type = "arbiterlock";\r
2887 width = "1";\r
2888 }\r
2889 PORT m1_arbiterlock2\r
2890 {\r
2891 Is_Enabled = "0";\r
2892 direction = "output";\r
2893 type = "arbiterlock2";\r
2894 width = "1";\r
2895 }\r
2896 PORT m1_clk\r
2897 {\r
2898 Is_Enabled = "0";\r
2899 direction = "input";\r
2900 type = "clk";\r
2901 width = "1";\r
2902 }\r
2903 PORT m1_reset_n\r
2904 {\r
2905 Is_Enabled = "0";\r
2906 direction = "input";\r
2907 type = "reset_n";\r
2908 width = "1";\r
2909 }\r
2910 }\r
2911 MEMORY_MAP \r
2912 {\r
2913 Entry ext_flash/s1\r
2914 {\r
2915 address = "0x00000000";\r
2916 span = "0x01000000";\r
2917 is_bridge = "0";\r
2918 }\r
2919 Entry ssram/s1\r
2920 {\r
2921 address = "0x01000000";\r
2922 span = "0x00100000";\r
2923 is_bridge = "0";\r
2924 }\r
2925 }\r
2926 }\r
2927 WIZARD_SCRIPT_ARGUMENTS \r
2928 {\r
2929 Is_Downstream = "1";\r
2930 Is_Upstream = "1";\r
2931 Is_Waitrequest = "1";\r
2932 Enable_Arbiterlock = "0";\r
2933 }\r
2934 class = "altera_avalon_pipeline_bridge";\r
2935 class_version = "7.08";\r
2936 SYSTEM_BUILDER_INFO \r
2937 {\r
2938 Is_Enabled = "1";\r
2939 Clock_Source = "pll_c0_out";\r
2940 Has_Clock = "1";\r
2941 Instantiate_In_System_Module = "1";\r
2942 Is_Bridge = "1";\r
2943 Top_Level_Ports_Are_Enumerated = "1";\r
2944 View \r
2945 {\r
2946 MESSAGES \r
2947 {\r
2948 }\r
2949 }\r
2950 }\r
2951 HDL_INFO \r
2952 {\r
2953 Precompiled_Simulation_Library_Files = "";\r
2954 Simulation_HDL_Files = "";\r
2955 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/pipeline_bridge_before_tristate_bridge.v";\r
2956 Synthesis_Only_Files = "";\r
2957 }\r
2958 PORT_WIRING \r
2959 {\r
2960 }\r
2961 }\r
2962 MODULE flash_ssram_tristate_bridge\r
2963 {\r
2964 SLAVE avalon_slave\r
2965 {\r
2966 PORT_WIRING \r
2967 {\r
2968 }\r
2969 SYSTEM_BUILDER_INFO \r
2970 {\r
2971 Bus_Type = "avalon";\r
2972 Write_Wait_States = "0cycles";\r
2973 Read_Wait_States = "1cycles";\r
2974 Hold_Time = "0cycles";\r
2975 Setup_Time = "0cycles";\r
2976 Is_Printable_Device = "0";\r
2977 Address_Alignment = "dynamic";\r
2978 Well_Behaved_Waitrequest = "0";\r
2979 Is_Nonvolatile_Storage = "0";\r
2980 Address_Span = "1";\r
2981 Read_Latency = "0";\r
2982 Is_Memory_Device = "0";\r
2983 Maximum_Pending_Read_Transactions = "0";\r
2984 Minimum_Uninterrupted_Run_Length = "1";\r
2985 Accepts_Internal_Connections = "1";\r
2986 Write_Latency = "0";\r
2987 Is_Flash = "0";\r
2988 Maximum_Burst_Size = "1";\r
2989 Register_Incoming_Signals = "1";\r
2990 Register_Outgoing_Signals = "1";\r
2991 Interleave_Bursts = "0";\r
2992 Linewrap_Bursts = "0";\r
2993 Burst_On_Burst_Boundaries_Only = "0";\r
2994 Always_Burst_Max_Burst = "0";\r
2995 Is_Big_Endian = "0";\r
2996 Is_Enabled = "1";\r
2997 MASTERED_BY pipeline_bridge_before_tristate_bridge/m1\r
2998 {\r
2999 priority = "1";\r
3000 Offset_Address = "0x00000000";\r
3001 }\r
3002 Bridges_To = "tristate_master";\r
3003 Base_Address = "N/A";\r
3004 Has_IRQ = "0";\r
3005 IRQ = "N/A";\r
3006 Address_Group = "0";\r
3007 }\r
3008 }\r
3009 MASTER tristate_master\r
3010 {\r
3011 SYSTEM_BUILDER_INFO \r
3012 {\r
3013 Bus_Type = "avalon_tristate";\r
3014 Is_Asynchronous = "0";\r
3015 DBS_Big_Endian = "0";\r
3016 Adapts_To = "";\r
3017 Maximum_Burst_Size = "1";\r
3018 Register_Incoming_Signals = "0";\r
3019 Register_Outgoing_Signals = "0";\r
3020 Interleave_Bursts = "0";\r
3021 Linewrap_Bursts = "0";\r
3022 Burst_On_Burst_Boundaries_Only = "0";\r
3023 Always_Burst_Max_Burst = "0";\r
3024 Is_Big_Endian = "0";\r
3025 Is_Enabled = "1";\r
3026 Bridges_To = "avalon_slave";\r
3027 }\r
3028 PORT_WIRING \r
3029 {\r
3030 }\r
3031 MEMORY_MAP \r
3032 {\r
3033 Entry ext_flash/s1\r
3034 {\r
3035 address = "0x00000000";\r
3036 span = "0x01000000";\r
3037 is_bridge = "0";\r
3038 }\r
3039 Entry ssram/s1\r
3040 {\r
3041 address = "0x01000000";\r
3042 span = "0x00100000";\r
3043 is_bridge = "0";\r
3044 }\r
3045 }\r
3046 }\r
3047 WIZARD_SCRIPT_ARGUMENTS \r
3048 {\r
3049 }\r
3050 class = "altera_avalon_tri_state_bridge";\r
3051 class_version = "7.08";\r
3052 SYSTEM_BUILDER_INFO \r
3053 {\r
3054 Is_Enabled = "1";\r
3055 Clock_Source = "pll_c0_out";\r
3056 Has_Clock = "1";\r
3057 Instantiate_In_System_Module = "1";\r
3058 Is_Bridge = "1";\r
3059 Top_Level_Ports_Are_Enumerated = "1";\r
3060 View \r
3061 {\r
3062 MESSAGES \r
3063 {\r
3064 }\r
3065 }\r
3066 }\r
3067 }\r
3068 MODULE ssram\r
3069 {\r
3070 SLAVE s1\r
3071 {\r
3072 PORT_WIRING \r
3073 {\r
3074 PORT clk\r
3075 {\r
3076 type = "clk";\r
3077 width = "1";\r
3078 direction = "input";\r
3079 Is_Enabled = "1";\r
3080 is_shared = "1";\r
3081 visible = "0";\r
3082 }\r
3083 PORT address\r
3084 {\r
3085 type = "address";\r
3086 width = "18";\r
3087 direction = "input";\r
3088 Is_Enabled = "1";\r
3089 is_shared = "1";\r
3090 }\r
3091 PORT adsc_n\r
3092 {\r
3093 type = "begintransfer_n";\r
3094 width = "1";\r
3095 direction = "input";\r
3096 Is_Enabled = "1";\r
3097 is_shared = "0";\r
3098 }\r
3099 PORT bw_n\r
3100 {\r
3101 type = "byteenable_n";\r
3102 width = "4";\r
3103 direction = "input";\r
3104 Is_Enabled = "1";\r
3105 is_shared = "0";\r
3106 }\r
3107 PORT bwe_n\r
3108 {\r
3109 type = "write_n";\r
3110 width = "1";\r
3111 direction = "input";\r
3112 Is_Enabled = "1";\r
3113 is_shared = "0";\r
3114 }\r
3115 PORT chipenable1_n\r
3116 {\r
3117 type = "chipselect_n";\r
3118 width = "1";\r
3119 direction = "input";\r
3120 Is_Enabled = "1";\r
3121 is_shared = "0";\r
3122 }\r
3123 PORT data\r
3124 {\r
3125 type = "data";\r
3126 width = "32";\r
3127 direction = "inout";\r
3128 Is_Enabled = "1";\r
3129 is_shared = "1";\r
3130 }\r
3131 PORT outputenable_n\r
3132 {\r
3133 type = "outputenable_n";\r
3134 width = "1";\r
3135 direction = "input";\r
3136 Is_Enabled = "1";\r
3137 is_shared = "0";\r
3138 }\r
3139 }\r
3140 SYSTEM_BUILDER_INFO \r
3141 {\r
3142 Bus_Type = "avalon_tristate";\r
3143 Write_Wait_States = "0cycles";\r
3144 Read_Wait_States = "0cycles";\r
3145 Hold_Time = "0cycles";\r
3146 Setup_Time = "0cycles";\r
3147 Is_Printable_Device = "0";\r
3148 Address_Alignment = "dynamic";\r
3149 Well_Behaved_Waitrequest = "0";\r
3150 Is_Nonvolatile_Storage = "0";\r
3151 Address_Span = "1048576";\r
3152 Read_Latency = "2";\r
3153 Is_Memory_Device = "1";\r
3154 Maximum_Pending_Read_Transactions = "0";\r
3155 Minimum_Uninterrupted_Run_Length = "1";\r
3156 Accepts_Internal_Connections = "1";\r
3157 Write_Latency = "0";\r
3158 Is_Flash = "0";\r
3159 Active_CS_Through_Read_Latency = "1";\r
3160 Data_Width = "32";\r
3161 Address_Width = "18";\r
3162 Maximum_Burst_Size = "1";\r
3163 Register_Incoming_Signals = "0";\r
3164 Register_Outgoing_Signals = "0";\r
3165 Interleave_Bursts = "0";\r
3166 Linewrap_Bursts = "0";\r
3167 Burst_On_Burst_Boundaries_Only = "0";\r
3168 Always_Burst_Max_Burst = "0";\r
3169 Is_Big_Endian = "0";\r
3170 Is_Enabled = "1";\r
3171 MASTERED_BY flash_ssram_tristate_bridge/tristate_master\r
3172 {\r
3173 priority = "8";\r
3174 Offset_Address = "0x01000000";\r
3175 }\r
3176 Base_Address = "0x05000000";\r
3177 Has_IRQ = "0";\r
3178 Address_Group = "0";\r
3179 }\r
3180 }\r
3181 WIZARD_SCRIPT_ARGUMENTS \r
3182 {\r
3183 sram_memory_size = "1";\r
3184 sram_memory_units = "1048576";\r
3185 ssram_data_width = "32";\r
3186 ssram_read_latency = "2";\r
3187 simulation_model_num_lanes = "4";\r
3188 MAKE \r
3189 {\r
3190 TARGET delete_placeholder_warning\r
3191 {\r
3192 ssram \r
3193 {\r
3194 Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";\r
3195 Is_Phony = "1";\r
3196 Target_File = "do_delete_placeholder_warning";\r
3197 }\r
3198 }\r
3199 TARGET sim\r
3200 {\r
3201 ssram \r
3202 {\r
3203 Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";\r
3204 Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";\r
3205 Command3 = "touch $(SIMDIR)/dummy_file";\r
3206 Dependency = "$(ELF)";\r
3207 Target_File = "$(SIMDIR)/dummy_file";\r
3208 }\r
3209 }\r
3210 }\r
3211 }\r
3212 class = "altera_avalon_cy7c1380_ssram";\r
3213 class_version = "7.08";\r
3214 SYSTEM_BUILDER_INFO \r
3215 {\r
3216 Is_Enabled = "1";\r
3217 Clock_Source = "pll_c0_out";\r
3218 Has_Clock = "1";\r
3219 Instantiate_In_System_Module = "0";\r
3220 Default_Module_Name = "ssram";\r
3221 Make_Memory_Model = "1";\r
3222 Top_Level_Ports_Are_Enumerated = "1";\r
3223 View \r
3224 {\r
3225 MESSAGES \r
3226 {\r
3227 }\r
3228 }\r
3229 }\r
3230 iss_model_name = "altera_memory";\r
3231 HDL_INFO \r
3232 {\r
3233 }\r
3234 }\r
3235 MODULE ext_flash\r
3236 {\r
3237 SLAVE s1\r
3238 {\r
3239 PORT_WIRING \r
3240 {\r
3241 PORT data\r
3242 {\r
3243 type = "data";\r
3244 width = "16";\r
3245 direction = "inout";\r
3246 Is_Enabled = "1";\r
3247 is_shared = "1";\r
3248 }\r
3249 PORT address\r
3250 {\r
3251 type = "address";\r
3252 width = "23";\r
3253 direction = "input";\r
3254 Is_Enabled = "1";\r
3255 is_shared = "1";\r
3256 }\r
3257 PORT read_n\r
3258 {\r
3259 type = "read_n";\r
3260 width = "1";\r
3261 direction = "input";\r
3262 Is_Enabled = "1";\r
3263 is_shared = "0";\r
3264 }\r
3265 PORT write_n\r
3266 {\r
3267 type = "write_n";\r
3268 width = "1";\r
3269 direction = "input";\r
3270 Is_Enabled = "1";\r
3271 is_shared = "0";\r
3272 }\r
3273 PORT select_n\r
3274 {\r
3275 type = "chipselect_n";\r
3276 width = "1";\r
3277 direction = "input";\r
3278 Is_Enabled = "1";\r
3279 is_shared = "0";\r
3280 }\r
3281 }\r
3282 SYSTEM_BUILDER_INFO \r
3283 {\r
3284 Bus_Type = "avalon_tristate";\r
3285 Write_Wait_States = "100ns";\r
3286 Read_Wait_States = "100ns";\r
3287 Hold_Time = "20ns";\r
3288 Setup_Time = "25ns";\r
3289 Is_Printable_Device = "0";\r
3290 Address_Alignment = "dynamic";\r
3291 Well_Behaved_Waitrequest = "0";\r
3292 Is_Nonvolatile_Storage = "1";\r
3293 Address_Span = "16777216";\r
3294 Read_Latency = "0";\r
3295 Is_Memory_Device = "1";\r
3296 Maximum_Pending_Read_Transactions = "0";\r
3297 Minimum_Uninterrupted_Run_Length = "1";\r
3298 Accepts_Internal_Connections = "1";\r
3299 Write_Latency = "0";\r
3300 Is_Flash = "1";\r
3301 Active_CS_Through_Read_Latency = "0";\r
3302 Data_Width = "16";\r
3303 Address_Width = "23";\r
3304 Maximum_Burst_Size = "1";\r
3305 Register_Incoming_Signals = "0";\r
3306 Register_Outgoing_Signals = "0";\r
3307 Interleave_Bursts = "0";\r
3308 Linewrap_Bursts = "0";\r
3309 Burst_On_Burst_Boundaries_Only = "0";\r
3310 Always_Burst_Max_Burst = "0";\r
3311 Is_Big_Endian = "0";\r
3312 Is_Enabled = "1";\r
3313 MASTERED_BY flash_ssram_tristate_bridge/tristate_master\r
3314 {\r
3315 priority = "1";\r
3316 Offset_Address = "0x00000000";\r
3317 }\r
3318 Base_Address = "0x04000000";\r
3319 Has_IRQ = "0";\r
3320 Simulation_Num_Lanes = "1";\r
3321 Convert_Xs_To_0 = "1";\r
3322 Address_Group = "0";\r
3323 }\r
3324 WIZARD_SCRIPT_ARGUMENTS \r
3325 {\r
3326 class = "altera_avalon_cfi_flash";\r
3327 Supports_Flash_File_System = "1";\r
3328 flash_reference_designator = "";\r
3329 }\r
3330 }\r
3331 WIZARD_SCRIPT_ARGUMENTS \r
3332 {\r
3333 Setup_Value = "25";\r
3334 Wait_Value = "100";\r
3335 Hold_Value = "20";\r
3336 Timing_Units = "ns";\r
3337 Unit_Multiplier = "1";\r
3338 Size = "16777216";\r
3339 MAKE \r
3340 {\r
3341 MACRO \r
3342 {\r
3343 EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(EXT_FLASH_FLASHTARGET_TMP1:0=)";\r
3344 EXT_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";\r
3345 }\r
3346 MASTER cpu\r
3347 {\r
3348 MACRO \r
3349 {\r
3350 BOOT_COPIER = "boot_loader_cfi.srec";\r
3351 CPU_CLASS = "altera_nios2";\r
3352 CPU_RESET_ADDRESS = "0x4000000";\r
3353 }\r
3354 }\r
3355 TARGET delete_placeholder_warning\r
3356 {\r
3357 ext_flash \r
3358 {\r
3359 Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";\r
3360 Is_Phony = "1";\r
3361 Target_File = "do_delete_placeholder_warning";\r
3362 }\r
3363 }\r
3364 TARGET flashfiles\r
3365 {\r
3366 ext_flash \r
3367 {\r
3368 Command1 = "@echo Post-processing to create $(notdir $@)";\r
3369 Command2 = "elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER)$(DBL_QUOTE) --outfile=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x4000000 --end=0x4FFFFFF --reset=$(CPU_RESET_ADDRESS) ";\r
3370 Dependency = "$(ELF)";\r
3371 Target_File = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";\r
3372 }\r
3373 }\r
3374 TARGET sim\r
3375 {\r
3376 ext_flash \r
3377 {\r
3378 Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";\r
3379 Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";\r
3380 Command3 = "touch $(SIMDIR)/dummy_file";\r
3381 Dependency = "$(ELF)";\r
3382 Target_File = "$(SIMDIR)/dummy_file";\r
3383 }\r
3384 }\r
3385 }\r
3386 }\r
3387 SYSTEM_BUILDER_INFO \r
3388 {\r
3389 Simulation_Num_Lanes = "2";\r
3390 Is_Enabled = "1";\r
3391 Clock_Source = "pll_c0_out";\r
3392 Has_Clock = "1";\r
3393 Make_Memory_Model = "1";\r
3394 Instantiate_In_System_Module = "0";\r
3395 Top_Level_Ports_Are_Enumerated = "1";\r
3396 View \r
3397 {\r
3398 MESSAGES \r
3399 {\r
3400 }\r
3401 }\r
3402 }\r
3403 class = "altera_avalon_cfi_flash";\r
3404 class_version = "7.08";\r
3405 iss_model_name = "altera_avalon_flash";\r
3406 HDL_INFO \r
3407 {\r
3408 }\r
3409 }\r
3410 MODULE ddr_sdram\r
3411 {\r
3412 PORT_WIRING \r
3413 {\r
3414 PORT pll_ref_clk\r
3415 {\r
3416 type = "clk";\r
3417 width = "1";\r
3418 direction = "input";\r
3419 Is_Enabled = "1";\r
3420 }\r
3421 PORT soft_reset_n\r
3422 {\r
3423 type = "reset_n";\r
3424 width = "1";\r
3425 direction = "input";\r
3426 Is_Enabled = "1";\r
3427 }\r
3428 PORT aux_full_rate_clk\r
3429 {\r
3430 type = "out_clk";\r
3431 width = "1";\r
3432 direction = "output";\r
3433 Is_Enabled = "1";\r
3434 }\r
3435 PORT aux_half_rate_clk\r
3436 {\r
3437 type = "out_clk";\r
3438 width = "1";\r
3439 direction = "output";\r
3440 Is_Enabled = "1";\r
3441 }\r
3442 PORT mem_clk\r
3443 {\r
3444 type = "export";\r
3445 width = "1";\r
3446 direction = "inout";\r
3447 Is_Enabled = "1";\r
3448 declare_one_bit_as_std_logic_vector = "1";\r
3449 }\r
3450 PORT mem_clk_n\r
3451 {\r
3452 type = "export";\r
3453 width = "1";\r
3454 direction = "inout";\r
3455 Is_Enabled = "1";\r
3456 declare_one_bit_as_std_logic_vector = "1";\r
3457 }\r
3458 PORT mem_cs_n\r
3459 {\r
3460 type = "export";\r
3461 width = "1";\r
3462 direction = "output";\r
3463 Is_Enabled = "1";\r
3464 declare_one_bit_as_std_logic_vector = "1";\r
3465 }\r
3466 PORT mem_cke\r
3467 {\r
3468 type = "export";\r
3469 width = "1";\r
3470 direction = "output";\r
3471 Is_Enabled = "1";\r
3472 declare_one_bit_as_std_logic_vector = "1";\r
3473 }\r
3474 PORT mem_addr\r
3475 {\r
3476 type = "export";\r
3477 width = "13";\r
3478 direction = "output";\r
3479 Is_Enabled = "1";\r
3480 }\r
3481 PORT mem_ba\r
3482 {\r
3483 type = "export";\r
3484 width = "2";\r
3485 direction = "output";\r
3486 Is_Enabled = "1";\r
3487 }\r
3488 PORT mem_ras_n\r
3489 {\r
3490 type = "export";\r
3491 width = "1";\r
3492 direction = "output";\r
3493 Is_Enabled = "1";\r
3494 }\r
3495 PORT mem_cas_n\r
3496 {\r
3497 type = "export";\r
3498 width = "1";\r
3499 direction = "output";\r
3500 Is_Enabled = "1";\r
3501 }\r
3502 PORT mem_we_n\r
3503 {\r
3504 type = "export";\r
3505 width = "1";\r
3506 direction = "output";\r
3507 Is_Enabled = "1";\r
3508 }\r
3509 PORT mem_dq\r
3510 {\r
3511 type = "export";\r
3512 width = "16";\r
3513 direction = "inout";\r
3514 Is_Enabled = "1";\r
3515 }\r
3516 PORT mem_dqs\r
3517 {\r
3518 type = "export";\r
3519 width = "2";\r
3520 direction = "inout";\r
3521 Is_Enabled = "1";\r
3522 }\r
3523 PORT mem_dm\r
3524 {\r
3525 type = "export";\r
3526 width = "2";\r
3527 direction = "output";\r
3528 Is_Enabled = "1";\r
3529 }\r
3530 PORT local_refresh_ack\r
3531 {\r
3532 type = "export";\r
3533 width = "1";\r
3534 direction = "output";\r
3535 Is_Enabled = "1";\r
3536 }\r
3537 PORT local_wdata_req\r
3538 {\r
3539 type = "export";\r
3540 width = "1";\r
3541 direction = "output";\r
3542 Is_Enabled = "1";\r
3543 }\r
3544 PORT local_init_done\r
3545 {\r
3546 type = "export";\r
3547 width = "1";\r
3548 direction = "output";\r
3549 Is_Enabled = "1";\r
3550 }\r
3551 PORT reset_phy_clk_n\r
3552 {\r
3553 type = "export";\r
3554 width = "1";\r
3555 direction = "output";\r
3556 Is_Enabled = "1";\r
3557 }\r
3558 PORT global_reset_n\r
3559 {\r
3560 type = "export";\r
3561 width = "1";\r
3562 direction = "input";\r
3563 Is_Enabled = "1";\r
3564 }\r
3565 }\r
3566 SLAVE s1\r
3567 {\r
3568 PORT_WIRING \r
3569 {\r
3570 PORT phy_clk\r
3571 {\r
3572 type = "out_clk";\r
3573 width = "1";\r
3574 direction = "output";\r
3575 Is_Enabled = "1";\r
3576 }\r
3577 PORT local_address\r
3578 {\r
3579 type = "address";\r
3580 width = "22";\r
3581 direction = "input";\r
3582 Is_Enabled = "1";\r
3583 }\r
3584 PORT local_write_req\r
3585 {\r
3586 type = "write";\r
3587 width = "1";\r
3588 direction = "input";\r
3589 Is_Enabled = "1";\r
3590 }\r
3591 PORT local_read_req\r
3592 {\r
3593 type = "read";\r
3594 width = "1";\r
3595 direction = "input";\r
3596 Is_Enabled = "1";\r
3597 }\r
3598 PORT local_burstbegin\r
3599 {\r
3600 type = "beginbursttransfer";\r
3601 width = "1";\r
3602 direction = "input";\r
3603 Is_Enabled = "1";\r
3604 }\r
3605 PORT local_ready\r
3606 {\r
3607 type = "waitrequest_n";\r
3608 width = "1";\r
3609 direction = "output";\r
3610 Is_Enabled = "1";\r
3611 }\r
3612 PORT local_rdata\r
3613 {\r
3614 type = "readdata";\r
3615 width = "64";\r
3616 direction = "output";\r
3617 Is_Enabled = "1";\r
3618 }\r
3619 PORT local_rdata_valid\r
3620 {\r
3621 type = "readdatavalid";\r
3622 width = "1";\r
3623 direction = "output";\r
3624 Is_Enabled = "1";\r
3625 }\r
3626 PORT local_wdata\r
3627 {\r
3628 type = "writedata";\r
3629 width = "64";\r
3630 direction = "input";\r
3631 Is_Enabled = "1";\r
3632 }\r
3633 PORT local_be\r
3634 {\r
3635 type = "byteenable";\r
3636 width = "8";\r
3637 direction = "input";\r
3638 Is_Enabled = "1";\r
3639 }\r
3640 PORT local_size\r
3641 {\r
3642 type = "burstcount";\r
3643 width = "1";\r
3644 direction = "input";\r
3645 Is_Enabled = "1";\r
3646 }\r
3647 PORT reset_request_n\r
3648 {\r
3649 type = "resetrequest_n";\r
3650 width = "1";\r
3651 direction = "output";\r
3652 Is_Enabled = "1";\r
3653 }\r
3654 }\r
3655 SYSTEM_BUILDER_INFO \r
3656 {\r
3657 Bus_Type = "avalon";\r
3658 Read_Wait_States = "peripheral_controlled";\r
3659 Write_Wait_States = "peripheral_controlled";\r
3660 Hold_Time = "0cycles";\r
3661 Setup_Time = "0cycles";\r
3662 Is_Printable_Device = "0";\r
3663 Address_Alignment = "dynamic";\r
3664 Well_Behaved_Waitrequest = "0";\r
3665 Is_Nonvolatile_Storage = "0";\r
3666 Address_Span = "33554432";\r
3667 Read_Latency = "0";\r
3668 Is_Memory_Device = "1";\r
3669 Maximum_Pending_Read_Transactions = "32";\r
3670 Minimum_Uninterrupted_Run_Length = "1";\r
3671 Accepts_Internal_Connections = "1";\r
3672 Write_Latency = "0";\r
3673 Is_Flash = "0";\r
3674 Data_Width = "64";\r
3675 Address_Width = "22";\r
3676 Maximum_Burst_Size = "1";\r
3677 Register_Incoming_Signals = "0";\r
3678 Register_Outgoing_Signals = "0";\r
3679 Interleave_Bursts = "0";\r
3680 Linewrap_Bursts = "0";\r
3681 Burst_On_Burst_Boundaries_Only = "0";\r
3682 Always_Burst_Max_Burst = "0";\r
3683 Is_Big_Endian = "0";\r
3684 Is_Enabled = "1";\r
3685 Clock_Source = "ddr_sdram_phy_clk_out";\r
3686 Has_Clock = "1";\r
3687 MASTERED_BY cpu_ddr_clock_bridge/m1\r
3688 {\r
3689 priority = "8";\r
3690 Offset_Address = "0x00000000";\r
3691 }\r
3692 MASTERED_BY slow_ddr_clock_bridge/m1\r
3693 {\r
3694 priority = "1";\r
3695 Offset_Address = "0x00000000";\r
3696 }\r
3697 Base_Address = "0x00000000";\r
3698 Address_Group = "0";\r
3699 }\r
3700 }\r
3701 iss_model_name = "altera_memory";\r
3702 class = "ddr_high_perf";\r
3703 WIZARD_SCRIPT_ARGUMENTS \r
3704 {\r
3705 device_family = "Cyclone III";\r
3706 datawidth = "16";\r
3707 memtype = "DDR SDRAM";\r
3708 local_burst_length = "1";\r
3709 num_chipselects = "1";\r
3710 cas_latency = "3.0";\r
3711 addr_width = "22";\r
3712 ba_width = "2";\r
3713 row_width = "13";\r
3714 col_width = "9";\r
3715 clockspeed = "7518";\r
3716 data_width_ratio = "4";\r
3717 reg_dimm = "false";\r
3718 dq_per_dqs = "8";\r
3719 }\r
3720 SYSTEM_BUILDER_INFO \r
3721 {\r
3722 Instantiate_In_System_Module = "1";\r
3723 Is_Enabled = "1";\r
3724 Clock_Source = "clk";\r
3725 Has_Clock = "1";\r
3726 Default_Module_Name = "altmemddr";\r
3727 Required_Device_Family = "STRATIXIIGXLITE,STRATIXIIGX,STRATIXII,STRATIXIII,CYCLONEIII,STRATIXIV";\r
3728 Pins_Assigned_Automatically = "1";\r
3729 View \r
3730 {\r
3731 MESSAGES \r
3732 {\r
3733 }\r
3734 }\r
3735 }\r
3736 class_version = "8.0";\r
3737 SIMULATION \r
3738 {\r
3739 DISPLAY \r
3740 {\r
3741 SIGNAL a\r
3742 {\r
3743 name = "pll_ref_clk";\r
3744 radix = "hexadecimal";\r
3745 format = "Logic";\r
3746 }\r
3747 SIGNAL b\r
3748 {\r
3749 name = "soft_reset_n";\r
3750 radix = "hexadecimal";\r
3751 format = "Logic";\r
3752 }\r
3753 SIGNAL c\r
3754 {\r
3755 name = "global_reset_n";\r
3756 radix = "hexadecimal";\r
3757 format = "Logic";\r
3758 }\r
3759 SIGNAL d\r
3760 {\r
3761 name = "reset_phy_clk_n";\r
3762 radix = "hexadecimal";\r
3763 format = "Logic";\r
3764 }\r
3765 SIGNAL e\r
3766 {\r
3767 name = "reset_request_n";\r
3768 radix = "hexadecimal";\r
3769 format = "Logic";\r
3770 }\r
3771 SIGNAL f\r
3772 {\r
3773 name = "phy_clk";\r
3774 radix = "hexadecimal";\r
3775 format = "Logic";\r
3776 }\r
3777 SIGNAL g\r
3778 {\r
3779 name = "local_address";\r
3780 radix = "hexadecimal";\r
3781 format = "Logic";\r
3782 }\r
3783 SIGNAL h\r
3784 {\r
3785 name = "local_size";\r
3786 radix = "hexadecimal";\r
3787 format = "Logic";\r
3788 }\r
3789 SIGNAL i\r
3790 {\r
3791 name = "local_burstbegin";\r
3792 radix = "hexadecimal";\r
3793 format = "Logic";\r
3794 }\r
3795 SIGNAL j\r
3796 {\r
3797 name = "local_read_req";\r
3798 radix = "hexadecimal";\r
3799 format = "Logic";\r
3800 }\r
3801 SIGNAL k\r
3802 {\r
3803 name = "local_write_req";\r
3804 radix = "hexadecimal";\r
3805 format = "Logic";\r
3806 }\r
3807 SIGNAL l\r
3808 {\r
3809 name = "local_ready";\r
3810 radix = "hexadecimal";\r
3811 format = "Logic";\r
3812 }\r
3813 SIGNAL m\r
3814 {\r
3815 name = "local_wdata";\r
3816 radix = "hexadecimal";\r
3817 format = "Logic";\r
3818 }\r
3819 SIGNAL n\r
3820 {\r
3821 name = "local_be";\r
3822 radix = "hexadecimal";\r
3823 format = "Logic";\r
3824 }\r
3825 SIGNAL o\r
3826 {\r
3827 name = "local_rdata_valid";\r
3828 radix = "hexadecimal";\r
3829 format = "Logic";\r
3830 }\r
3831 SIGNAL p\r
3832 {\r
3833 name = "local_rdata";\r
3834 radix = "hexadecimal";\r
3835 format = "Logic";\r
3836 }\r
3837 SIGNAL q\r
3838 {\r
3839 name = "mem_clk";\r
3840 radix = "hexadecimal";\r
3841 format = "Logic";\r
3842 }\r
3843 SIGNAL r\r
3844 {\r
3845 name = "mem_cs_n";\r
3846 radix = "hexadecimal";\r
3847 format = "Logic";\r
3848 }\r
3849 SIGNAL s\r
3850 {\r
3851 name = "mem_addr";\r
3852 radix = "hexadecimal";\r
3853 format = "Logic";\r
3854 }\r
3855 SIGNAL t\r
3856 {\r
3857 name = "mem_ba";\r
3858 radix = "hexadecimal";\r
3859 format = "Logic";\r
3860 }\r
3861 SIGNAL u\r
3862 {\r
3863 name = "mem_ras_n";\r
3864 radix = "hexadecimal";\r
3865 format = "Logic";\r
3866 }\r
3867 SIGNAL v\r
3868 {\r
3869 name = "mem_cas_n";\r
3870 radix = "hexadecimal";\r
3871 format = "Logic";\r
3872 }\r
3873 SIGNAL w\r
3874 {\r
3875 name = "mem_we_n";\r
3876 radix = "hexadecimal";\r
3877 format = "Logic";\r
3878 }\r
3879 SIGNAL x\r
3880 {\r
3881 name = "mem_dm";\r
3882 radix = "hexadecimal";\r
3883 format = "Logic";\r
3884 }\r
3885 SIGNAL y\r
3886 {\r
3887 name = "mem_dq";\r
3888 radix = "hexadecimal";\r
3889 format = "Logic";\r
3890 }\r
3891 SIGNAL z\r
3892 {\r
3893 name = "mem_dqs";\r
3894 radix = "hexadecimal";\r
3895 format = "Logic";\r
3896 }\r
3897 SIGNAL aa\r
3898 {\r
3899 name = "mem_cke";\r
3900 radix = "hexadecimal";\r
3901 format = "Logic";\r
3902 }\r
3903 }\r
3904 }\r
3905 }\r
3906 MODULE cpu_ddr_clock_bridge\r
3907 {\r
3908 SLAVE s1\r
3909 {\r
3910 PORT_WIRING \r
3911 {\r
3912 PORT slave_clk\r
3913 {\r
3914 type = "clk";\r
3915 width = "1";\r
3916 direction = "input";\r
3917 Is_Enabled = "1";\r
3918 }\r
3919 PORT slave_reset_n\r
3920 {\r
3921 type = "reset_n";\r
3922 width = "1";\r
3923 direction = "input";\r
3924 Is_Enabled = "1";\r
3925 }\r
3926 PORT slave_address\r
3927 {\r
3928 type = "address";\r
3929 width = "23";\r
3930 direction = "input";\r
3931 Is_Enabled = "1";\r
3932 }\r
3933 PORT slave_nativeaddress\r
3934 {\r
3935 type = "nativeaddress";\r
3936 width = "23";\r
3937 direction = "input";\r
3938 Is_Enabled = "1";\r
3939 }\r
3940 PORT slave_read\r
3941 {\r
3942 type = "read";\r
3943 width = "1";\r
3944 direction = "input";\r
3945 Is_Enabled = "1";\r
3946 }\r
3947 PORT slave_write\r
3948 {\r
3949 type = "write";\r
3950 width = "1";\r
3951 direction = "input";\r
3952 Is_Enabled = "1";\r
3953 }\r
3954 PORT slave_writedata\r
3955 {\r
3956 type = "writedata";\r
3957 width = "32";\r
3958 direction = "input";\r
3959 Is_Enabled = "1";\r
3960 }\r
3961 PORT slave_readdata\r
3962 {\r
3963 type = "readdata";\r
3964 width = "32";\r
3965 direction = "output";\r
3966 Is_Enabled = "1";\r
3967 }\r
3968 PORT slave_readdatavalid\r
3969 {\r
3970 type = "readdatavalid";\r
3971 width = "1";\r
3972 direction = "output";\r
3973 Is_Enabled = "1";\r
3974 }\r
3975 PORT slave_waitrequest\r
3976 {\r
3977 type = "waitrequest";\r
3978 width = "1";\r
3979 direction = "output";\r
3980 Is_Enabled = "1";\r
3981 }\r
3982 PORT slave_byteenable\r
3983 {\r
3984 type = "byteenable";\r
3985 width = "4";\r
3986 direction = "input";\r
3987 Is_Enabled = "1";\r
3988 }\r
3989 PORT slave_endofpacket\r
3990 {\r
3991 Is_Enabled = "1";\r
3992 direction = "output";\r
3993 type = "endofpacket";\r
3994 width = "1";\r
3995 }\r
3996 }\r
3997 SYSTEM_BUILDER_INFO \r
3998 {\r
3999 Bus_Type = "avalon";\r
4000 Read_Wait_States = "peripheral_controlled";\r
4001 Write_Wait_States = "peripheral_controlled";\r
4002 Hold_Time = "0cycles";\r
4003 Setup_Time = "0cycles";\r
4004 Is_Printable_Device = "0";\r
4005 Address_Alignment = "dynamic";\r
4006 Well_Behaved_Waitrequest = "0";\r
4007 Is_Nonvolatile_Storage = "0";\r
4008 Address_Span = "33554432";\r
4009 Read_Latency = "0";\r
4010 Is_Memory_Device = "0";\r
4011 Maximum_Pending_Read_Transactions = "48";\r
4012 Minimum_Uninterrupted_Run_Length = "1";\r
4013 Accepts_Internal_Connections = "1";\r
4014 Write_Latency = "0";\r
4015 Is_Flash = "0";\r
4016 Data_Width = "32";\r
4017 Address_Width = "23";\r
4018 Opaque_Bridges_To = "m1";\r
4019 Maximum_Burst_Size = "1";\r
4020 Register_Incoming_Signals = "0";\r
4021 Register_Outgoing_Signals = "0";\r
4022 Interleave_Bursts = "0";\r
4023 Linewrap_Bursts = "0";\r
4024 Burst_On_Burst_Boundaries_Only = "0";\r
4025 Always_Burst_Max_Burst = "0";\r
4026 Is_Big_Endian = "0";\r
4027 Is_Enabled = "1";\r
4028 MASTERED_BY cpu/data_master\r
4029 {\r
4030 priority = "8";\r
4031 Offset_Address = "0x00000000";\r
4032 }\r
4033 MASTERED_BY cpu/instruction_master\r
4034 {\r
4035 priority = "8";\r
4036 Offset_Address = "0x00000000";\r
4037 }\r
4038 Clock_Source = "pll_c0_out";\r
4039 Has_Clock = "1";\r
4040 Base_Address = "0x00000000";\r
4041 Address_Group = "0";\r
4042 IRQ_MASTER cpu/data_master\r
4043 {\r
4044 IRQ_Number = "NC";\r
4045 }\r
4046 }\r
4047 }\r
4048 MASTER m1\r
4049 {\r
4050 PORT_WIRING \r
4051 {\r
4052 PORT master_clk\r
4053 {\r
4054 type = "clk";\r
4055 width = "1";\r
4056 direction = "input";\r
4057 Is_Enabled = "1";\r
4058 }\r
4059 PORT master_reset_n\r
4060 {\r
4061 type = "reset_n";\r
4062 width = "1";\r
4063 direction = "input";\r
4064 Is_Enabled = "1";\r
4065 }\r
4066 PORT master_address\r
4067 {\r
4068 type = "address";\r
4069 width = "25";\r
4070 direction = "output";\r
4071 Is_Enabled = "1";\r
4072 }\r
4073 PORT master_nativeaddress\r
4074 {\r
4075 type = "nativeaddress";\r
4076 width = "23";\r
4077 direction = "output";\r
4078 Is_Enabled = "1";\r
4079 }\r
4080 PORT master_read\r
4081 {\r
4082 type = "read";\r
4083 width = "1";\r
4084 direction = "output";\r
4085 Is_Enabled = "1";\r
4086 }\r
4087 PORT master_write\r
4088 {\r
4089 type = "write";\r
4090 width = "1";\r
4091 direction = "output";\r
4092 Is_Enabled = "1";\r
4093 }\r
4094 PORT master_writedata\r
4095 {\r
4096 type = "writedata";\r
4097 width = "32";\r
4098 direction = "output";\r
4099 Is_Enabled = "1";\r
4100 }\r
4101 PORT master_readdata\r
4102 {\r
4103 type = "readdata";\r
4104 width = "32";\r
4105 direction = "input";\r
4106 Is_Enabled = "1";\r
4107 }\r
4108 PORT master_readdatavalid\r
4109 {\r
4110 type = "readdatavalid";\r
4111 width = "1";\r
4112 direction = "input";\r
4113 Is_Enabled = "1";\r
4114 }\r
4115 PORT master_waitrequest\r
4116 {\r
4117 type = "waitrequest";\r
4118 width = "1";\r
4119 direction = "input";\r
4120 Is_Enabled = "1";\r
4121 }\r
4122 PORT master_byteenable\r
4123 {\r
4124 type = "byteenable";\r
4125 width = "4";\r
4126 direction = "output";\r
4127 Is_Enabled = "1";\r
4128 }\r
4129 PORT master_endofpacket\r
4130 {\r
4131 Is_Enabled = "1";\r
4132 direction = "input";\r
4133 type = "endofpacket";\r
4134 width = "1";\r
4135 }\r
4136 }\r
4137 SYSTEM_BUILDER_INFO \r
4138 {\r
4139 Bus_Type = "avalon";\r
4140 Is_Asynchronous = "0";\r
4141 DBS_Big_Endian = "0";\r
4142 Adapts_To = "";\r
4143 Do_Stream_Reads = "0";\r
4144 Do_Stream_Writes = "0";\r
4145 Max_Address_Width = "32";\r
4146 Data_Width = "32";\r
4147 Address_Width = "25";\r
4148 Opaque_Bridges_To = "s1";\r
4149 Maximum_Burst_Size = "1";\r
4150 Register_Incoming_Signals = "0";\r
4151 Register_Outgoing_Signals = "0";\r
4152 Interleave_Bursts = "0";\r
4153 Linewrap_Bursts = "0";\r
4154 Burst_On_Burst_Boundaries_Only = "0";\r
4155 Always_Burst_Max_Burst = "0";\r
4156 Is_Big_Endian = "0";\r
4157 Is_Enabled = "1";\r
4158 Clock_Source = "ddr_sdram_phy_clk_out";\r
4159 Has_Clock = "1";\r
4160 }\r
4161 MEMORY_MAP \r
4162 {\r
4163 Entry ddr_sdram/s1\r
4164 {\r
4165 address = "0x00000000";\r
4166 span = "0x02000000";\r
4167 is_bridge = "0";\r
4168 }\r
4169 }\r
4170 }\r
4171 class = "altera_avalon_clock_crossing";\r
4172 class_version = "7.08";\r
4173 iss_model_name = "altera_avalon_clock_crossing";\r
4174 WIZARD_SCRIPT_ARGUMENTS \r
4175 {\r
4176 Upstream_FIFO_Depth = "64";\r
4177 Downstream_FIFO_Depth = "8";\r
4178 Data_Width = "32";\r
4179 Native_Address_Width = "23";\r
4180 Use_Byte_Enable = "1";\r
4181 Use_Burst_Count = "0";\r
4182 Maximum_Burst_Size = "8";\r
4183 Upstream_Use_Register = "0";\r
4184 Downstream_Use_Register = "0";\r
4185 Device_Family = "CYCLONEIII";\r
4186 }\r
4187 SYSTEM_BUILDER_INFO \r
4188 {\r
4189 Instantiate_In_System_Module = "1";\r
4190 Is_Enabled = "1";\r
4191 Top_Level_Ports_Are_Enumerated = "1";\r
4192 Has_Clock = "0";\r
4193 Is_Bridge = "1";\r
4194 Clock_Source = "clk";\r
4195 View \r
4196 {\r
4197 MESSAGES \r
4198 {\r
4199 }\r
4200 }\r
4201 }\r
4202 HDL_INFO \r
4203 {\r
4204 Precompiled_Simulation_Library_Files = "";\r
4205 Simulation_HDL_Files = "";\r
4206 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_ddr_clock_bridge.v";\r
4207 Synthesis_Only_Files = "";\r
4208 }\r
4209 PORT_WIRING \r
4210 {\r
4211 }\r
4212 }\r
4213 MODULE slow_peripheral_bridge\r
4214 {\r
4215 SLAVE s1\r
4216 {\r
4217 PORT_WIRING \r
4218 {\r
4219 PORT slave_clk\r
4220 {\r
4221 type = "clk";\r
4222 width = "1";\r
4223 direction = "input";\r
4224 Is_Enabled = "1";\r
4225 }\r
4226 PORT slave_reset_n\r
4227 {\r
4228 type = "reset_n";\r
4229 width = "1";\r
4230 direction = "input";\r
4231 Is_Enabled = "1";\r
4232 }\r
4233 PORT slave_address\r
4234 {\r
4235 type = "address";\r
4236 width = "12";\r
4237 direction = "input";\r
4238 Is_Enabled = "1";\r
4239 }\r
4240 PORT slave_nativeaddress\r
4241 {\r
4242 type = "nativeaddress";\r
4243 width = "12";\r
4244 direction = "input";\r
4245 Is_Enabled = "1";\r
4246 }\r
4247 PORT slave_read\r
4248 {\r
4249 type = "read";\r
4250 width = "1";\r
4251 direction = "input";\r
4252 Is_Enabled = "1";\r
4253 }\r
4254 PORT slave_write\r
4255 {\r
4256 type = "write";\r
4257 width = "1";\r
4258 direction = "input";\r
4259 Is_Enabled = "1";\r
4260 }\r
4261 PORT slave_writedata\r
4262 {\r
4263 type = "writedata";\r
4264 width = "32";\r
4265 direction = "input";\r
4266 Is_Enabled = "1";\r
4267 }\r
4268 PORT slave_readdata\r
4269 {\r
4270 type = "readdata";\r
4271 width = "32";\r
4272 direction = "output";\r
4273 Is_Enabled = "1";\r
4274 }\r
4275 PORT slave_readdatavalid\r
4276 {\r
4277 type = "readdatavalid";\r
4278 width = "1";\r
4279 direction = "output";\r
4280 Is_Enabled = "1";\r
4281 }\r
4282 PORT slave_waitrequest\r
4283 {\r
4284 type = "waitrequest";\r
4285 width = "1";\r
4286 direction = "output";\r
4287 Is_Enabled = "1";\r
4288 }\r
4289 PORT slave_byteenable\r
4290 {\r
4291 type = "byteenable";\r
4292 width = "4";\r
4293 direction = "input";\r
4294 Is_Enabled = "1";\r
4295 }\r
4296 PORT slave_endofpacket\r
4297 {\r
4298 Is_Enabled = "1";\r
4299 direction = "output";\r
4300 type = "endofpacket";\r
4301 width = "1";\r
4302 }\r
4303 }\r
4304 SYSTEM_BUILDER_INFO \r
4305 {\r
4306 Bus_Type = "avalon";\r
4307 Read_Wait_States = "peripheral_controlled";\r
4308 Write_Wait_States = "peripheral_controlled";\r
4309 Hold_Time = "0cycles";\r
4310 Setup_Time = "0cycles";\r
4311 Is_Printable_Device = "0";\r
4312 Address_Alignment = "dynamic";\r
4313 Well_Behaved_Waitrequest = "0";\r
4314 Is_Nonvolatile_Storage = "0";\r
4315 Address_Span = "16384";\r
4316 Read_Latency = "0";\r
4317 Is_Memory_Device = "0";\r
4318 Maximum_Pending_Read_Transactions = "34";\r
4319 Minimum_Uninterrupted_Run_Length = "1";\r
4320 Accepts_Internal_Connections = "1";\r
4321 Write_Latency = "0";\r
4322 Is_Flash = "0";\r
4323 Data_Width = "32";\r
4324 Address_Width = "12";\r
4325 Opaque_Bridges_To = "m1";\r
4326 Maximum_Burst_Size = "1";\r
4327 Register_Incoming_Signals = "0";\r
4328 Register_Outgoing_Signals = "0";\r
4329 Interleave_Bursts = "0";\r
4330 Linewrap_Bursts = "0";\r
4331 Burst_On_Burst_Boundaries_Only = "0";\r
4332 Always_Burst_Max_Burst = "0";\r
4333 Is_Big_Endian = "0";\r
4334 Is_Enabled = "1";\r
4335 MASTERED_BY cpu/data_master\r
4336 {\r
4337 priority = "8";\r
4338 Offset_Address = "0x08000000";\r
4339 }\r
4340 Clock_Source = "pll_c0_out";\r
4341 Has_Clock = "1";\r
4342 Base_Address = "0x08000000";\r
4343 Address_Group = "0";\r
4344 IRQ_MASTER cpu/data_master\r
4345 {\r
4346 IRQ_Number = "NC";\r
4347 }\r
4348 }\r
4349 }\r
4350 MASTER m1\r
4351 {\r
4352 PORT_WIRING \r
4353 {\r
4354 PORT master_clk\r
4355 {\r
4356 type = "clk";\r
4357 width = "1";\r
4358 direction = "input";\r
4359 Is_Enabled = "1";\r
4360 }\r
4361 PORT master_reset_n\r
4362 {\r
4363 type = "reset_n";\r
4364 width = "1";\r
4365 direction = "input";\r
4366 Is_Enabled = "1";\r
4367 }\r
4368 PORT master_address\r
4369 {\r
4370 type = "address";\r
4371 width = "14";\r
4372 direction = "output";\r
4373 Is_Enabled = "1";\r
4374 }\r
4375 PORT master_nativeaddress\r
4376 {\r
4377 type = "nativeaddress";\r
4378 width = "12";\r
4379 direction = "output";\r
4380 Is_Enabled = "1";\r
4381 }\r
4382 PORT master_read\r
4383 {\r
4384 type = "read";\r
4385 width = "1";\r
4386 direction = "output";\r
4387 Is_Enabled = "1";\r
4388 }\r
4389 PORT master_write\r
4390 {\r
4391 type = "write";\r
4392 width = "1";\r
4393 direction = "output";\r
4394 Is_Enabled = "1";\r
4395 }\r
4396 PORT master_writedata\r
4397 {\r
4398 type = "writedata";\r
4399 width = "32";\r
4400 direction = "output";\r
4401 Is_Enabled = "1";\r
4402 }\r
4403 PORT master_readdata\r
4404 {\r
4405 type = "readdata";\r
4406 width = "32";\r
4407 direction = "input";\r
4408 Is_Enabled = "1";\r
4409 }\r
4410 PORT master_readdatavalid\r
4411 {\r
4412 type = "readdatavalid";\r
4413 width = "1";\r
4414 direction = "input";\r
4415 Is_Enabled = "1";\r
4416 }\r
4417 PORT master_waitrequest\r
4418 {\r
4419 type = "waitrequest";\r
4420 width = "1";\r
4421 direction = "input";\r
4422 Is_Enabled = "1";\r
4423 }\r
4424 PORT master_byteenable\r
4425 {\r
4426 type = "byteenable";\r
4427 width = "4";\r
4428 direction = "output";\r
4429 Is_Enabled = "1";\r
4430 }\r
4431 PORT master_endofpacket\r
4432 {\r
4433 Is_Enabled = "1";\r
4434 direction = "input";\r
4435 type = "endofpacket";\r
4436 width = "1";\r
4437 }\r
4438 }\r
4439 SYSTEM_BUILDER_INFO \r
4440 {\r
4441 Bus_Type = "avalon";\r
4442 Is_Asynchronous = "0";\r
4443 DBS_Big_Endian = "0";\r
4444 Adapts_To = "";\r
4445 Do_Stream_Reads = "0";\r
4446 Do_Stream_Writes = "0";\r
4447 Max_Address_Width = "32";\r
4448 Data_Width = "32";\r
4449 Address_Width = "14";\r
4450 Opaque_Bridges_To = "s1";\r
4451 Maximum_Burst_Size = "1";\r
4452 Register_Incoming_Signals = "0";\r
4453 Register_Outgoing_Signals = "0";\r
4454 Interleave_Bursts = "0";\r
4455 Linewrap_Bursts = "0";\r
4456 Burst_On_Burst_Boundaries_Only = "0";\r
4457 Always_Burst_Max_Burst = "0";\r
4458 Is_Big_Endian = "0";\r
4459 Is_Enabled = "1";\r
4460 Clock_Source = "pll_c2_out";\r
4461 Has_Clock = "1";\r
4462 }\r
4463 MEMORY_MAP \r
4464 {\r
4465 Entry button_pio/s1\r
4466 {\r
4467 address = "0x00001180";\r
4468 span = "0x00000010";\r
4469 is_bridge = "0";\r
4470 }\r
4471 Entry high_res_timer/s1\r
4472 {\r
4473 address = "0x00001100";\r
4474 span = "0x00000020";\r
4475 is_bridge = "0";\r
4476 }\r
4477 Entry jtag_uart/avalon_jtag_slave\r
4478 {\r
4479 address = "0x000011a0";\r
4480 span = "0x00000008";\r
4481 is_bridge = "0";\r
4482 }\r
4483 Entry led_pio/s1\r
4484 {\r
4485 address = "0x00001190";\r
4486 span = "0x00000010";\r
4487 is_bridge = "0";\r
4488 }\r
4489 Entry performance_counter/control_slave\r
4490 {\r
4491 address = "0x00001120";\r
4492 span = "0x00000020";\r
4493 is_bridge = "0";\r
4494 }\r
4495 Entry pll/s1\r
4496 {\r
4497 address = "0x00001140";\r
4498 span = "0x00000020";\r
4499 is_bridge = "0";\r
4500 }\r
4501 Entry remote_update/s1\r
4502 {\r
4503 address = "0x00001000";\r
4504 span = "0x00000100";\r
4505 is_bridge = "0";\r
4506 }\r
4507 Entry sys_clk_timer/s1\r
4508 {\r
4509 address = "0x00001160";\r
4510 span = "0x00000020";\r
4511 is_bridge = "0";\r
4512 }\r
4513 Entry sysid/control_slave\r
4514 {\r
4515 address = "0x000011a8";\r
4516 span = "0x00000008";\r
4517 is_bridge = "0";\r
4518 }\r
4519 Entry ocm/control_port\r
4520 {\r
4521 address = "0x00002000";\r
4522 span = "0x00001000";\r
4523 is_bridge = "0";\r
4524 }\r
4525 }\r
4526 }\r
4527 class = "altera_avalon_clock_crossing";\r
4528 class_version = "7.08";\r
4529 iss_model_name = "altera_avalon_clock_crossing";\r
4530 WIZARD_SCRIPT_ARGUMENTS \r
4531 {\r
4532 Upstream_FIFO_Depth = "64";\r
4533 Downstream_FIFO_Depth = "16";\r
4534 Data_Width = "32";\r
4535 Native_Address_Width = "12";\r
4536 Use_Byte_Enable = "1";\r
4537 Use_Burst_Count = "0";\r
4538 Maximum_Burst_Size = "8";\r
4539 Upstream_Use_Register = "0";\r
4540 Downstream_Use_Register = "0";\r
4541 Device_Family = "CYCLONEIII";\r
4542 }\r
4543 SYSTEM_BUILDER_INFO \r
4544 {\r
4545 Instantiate_In_System_Module = "1";\r
4546 Is_Enabled = "1";\r
4547 Top_Level_Ports_Are_Enumerated = "1";\r
4548 Has_Clock = "0";\r
4549 Is_Bridge = "1";\r
4550 Clock_Source = "clk";\r
4551 View \r
4552 {\r
4553 MESSAGES \r
4554 {\r
4555 }\r
4556 }\r
4557 }\r
4558 HDL_INFO \r
4559 {\r
4560 Precompiled_Simulation_Library_Files = "";\r
4561 Simulation_HDL_Files = "";\r
4562 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/slow_peripheral_bridge.v";\r
4563 Synthesis_Only_Files = "";\r
4564 }\r
4565 PORT_WIRING \r
4566 {\r
4567 }\r
4568 }\r
4569 MODULE sys_clk_timer\r
4570 {\r
4571 SLAVE s1\r
4572 {\r
4573 PORT_WIRING \r
4574 {\r
4575 PORT clk\r
4576 {\r
4577 type = "clk";\r
4578 width = "1";\r
4579 direction = "input";\r
4580 Is_Enabled = "1";\r
4581 }\r
4582 PORT reset_n\r
4583 {\r
4584 type = "reset_n";\r
4585 width = "1";\r
4586 direction = "input";\r
4587 Is_Enabled = "1";\r
4588 }\r
4589 PORT irq\r
4590 {\r
4591 type = "irq";\r
4592 width = "1";\r
4593 direction = "output";\r
4594 Is_Enabled = "1";\r
4595 }\r
4596 PORT address\r
4597 {\r
4598 type = "address";\r
4599 width = "3";\r
4600 direction = "input";\r
4601 Is_Enabled = "1";\r
4602 }\r
4603 PORT writedata\r
4604 {\r
4605 type = "writedata";\r
4606 width = "16";\r
4607 direction = "input";\r
4608 Is_Enabled = "1";\r
4609 }\r
4610 PORT readdata\r
4611 {\r
4612 type = "readdata";\r
4613 width = "16";\r
4614 direction = "output";\r
4615 Is_Enabled = "1";\r
4616 }\r
4617 PORT chipselect\r
4618 {\r
4619 type = "chipselect";\r
4620 width = "1";\r
4621 direction = "input";\r
4622 Is_Enabled = "1";\r
4623 }\r
4624 PORT write_n\r
4625 {\r
4626 type = "write_n";\r
4627 width = "1";\r
4628 direction = "input";\r
4629 Is_Enabled = "1";\r
4630 }\r
4631 }\r
4632 SYSTEM_BUILDER_INFO \r
4633 {\r
4634 Has_IRQ = "1";\r
4635 Bus_Type = "avalon";\r
4636 Write_Wait_States = "0cycles";\r
4637 Read_Wait_States = "1cycles";\r
4638 Hold_Time = "0cycles";\r
4639 Setup_Time = "0cycles";\r
4640 Is_Printable_Device = "0";\r
4641 Address_Alignment = "native";\r
4642 Well_Behaved_Waitrequest = "0";\r
4643 Is_Nonvolatile_Storage = "0";\r
4644 Read_Latency = "0";\r
4645 Is_Memory_Device = "0";\r
4646 Maximum_Pending_Read_Transactions = "0";\r
4647 Minimum_Uninterrupted_Run_Length = "1";\r
4648 Accepts_Internal_Connections = "1";\r
4649 Write_Latency = "0";\r
4650 Is_Flash = "0";\r
4651 Data_Width = "16";\r
4652 Address_Width = "3";\r
4653 Maximum_Burst_Size = "1";\r
4654 Register_Incoming_Signals = "0";\r
4655 Register_Outgoing_Signals = "0";\r
4656 Interleave_Bursts = "0";\r
4657 Linewrap_Bursts = "0";\r
4658 Burst_On_Burst_Boundaries_Only = "0";\r
4659 Always_Burst_Max_Burst = "0";\r
4660 Is_Big_Endian = "0";\r
4661 Is_Enabled = "1";\r
4662 IRQ_MASTER cpu/data_master\r
4663 {\r
4664 IRQ_Number = "8";\r
4665 }\r
4666 MASTERED_BY slow_peripheral_bridge/m1\r
4667 {\r
4668 priority = "1";\r
4669 Offset_Address = "0x00001160";\r
4670 }\r
4671 Base_Address = "0x08001160";\r
4672 Address_Group = "0";\r
4673 }\r
4674 }\r
4675 class = "altera_avalon_timer";\r
4676 class_version = "7.08";\r
4677 iss_model_name = "altera_avalon_timer";\r
4678 SYSTEM_BUILDER_INFO \r
4679 {\r
4680 Instantiate_In_System_Module = "1";\r
4681 Is_Enabled = "1";\r
4682 Top_Level_Ports_Are_Enumerated = "1";\r
4683 View \r
4684 {\r
4685 Settings_Summary = "Timer with 10 ms timeout period.";\r
4686 Is_Collapsed = "1";\r
4687 MESSAGES \r
4688 {\r
4689 }\r
4690 }\r
4691 Clock_Source = "pll_c2_out";\r
4692 Has_Clock = "1";\r
4693 }\r
4694 WIZARD_SCRIPT_ARGUMENTS \r
4695 {\r
4696 always_run = "0";\r
4697 fixed_period = "0";\r
4698 snapshot = "1";\r
4699 period = "10.0";\r
4700 period_units = "ms";\r
4701 reset_output = "0";\r
4702 timeout_pulse_output = "0";\r
4703 load_value = "599999";\r
4704 counter_size = "32";\r
4705 mult = "0.0010";\r
4706 ticks_per_sec = "100";\r
4707 }\r
4708 HDL_INFO \r
4709 {\r
4710 Precompiled_Simulation_Library_Files = "";\r
4711 Simulation_HDL_Files = "";\r
4712 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sys_clk_timer.v";\r
4713 Synthesis_Only_Files = "";\r
4714 }\r
4715 PORT_WIRING \r
4716 {\r
4717 }\r
4718 }\r
4719 MODULE high_res_timer\r
4720 {\r
4721 SLAVE s1\r
4722 {\r
4723 PORT_WIRING \r
4724 {\r
4725 PORT clk\r
4726 {\r
4727 type = "clk";\r
4728 width = "1";\r
4729 direction = "input";\r
4730 Is_Enabled = "1";\r
4731 }\r
4732 PORT reset_n\r
4733 {\r
4734 type = "reset_n";\r
4735 width = "1";\r
4736 direction = "input";\r
4737 Is_Enabled = "1";\r
4738 }\r
4739 PORT irq\r
4740 {\r
4741 type = "irq";\r
4742 width = "1";\r
4743 direction = "output";\r
4744 Is_Enabled = "1";\r
4745 }\r
4746 PORT address\r
4747 {\r
4748 type = "address";\r
4749 width = "3";\r
4750 direction = "input";\r
4751 Is_Enabled = "1";\r
4752 }\r
4753 PORT writedata\r
4754 {\r
4755 type = "writedata";\r
4756 width = "16";\r
4757 direction = "input";\r
4758 Is_Enabled = "1";\r
4759 }\r
4760 PORT readdata\r
4761 {\r
4762 type = "readdata";\r
4763 width = "16";\r
4764 direction = "output";\r
4765 Is_Enabled = "1";\r
4766 }\r
4767 PORT chipselect\r
4768 {\r
4769 type = "chipselect";\r
4770 width = "1";\r
4771 direction = "input";\r
4772 Is_Enabled = "1";\r
4773 }\r
4774 PORT write_n\r
4775 {\r
4776 type = "write_n";\r
4777 width = "1";\r
4778 direction = "input";\r
4779 Is_Enabled = "1";\r
4780 }\r
4781 }\r
4782 SYSTEM_BUILDER_INFO \r
4783 {\r
4784 Has_IRQ = "1";\r
4785 Bus_Type = "avalon";\r
4786 Write_Wait_States = "0cycles";\r
4787 Read_Wait_States = "1cycles";\r
4788 Hold_Time = "0cycles";\r
4789 Setup_Time = "0cycles";\r
4790 Is_Printable_Device = "0";\r
4791 Address_Alignment = "native";\r
4792 Well_Behaved_Waitrequest = "0";\r
4793 Is_Nonvolatile_Storage = "0";\r
4794 Read_Latency = "0";\r
4795 Is_Memory_Device = "0";\r
4796 Maximum_Pending_Read_Transactions = "0";\r
4797 Minimum_Uninterrupted_Run_Length = "1";\r
4798 Accepts_Internal_Connections = "1";\r
4799 Write_Latency = "0";\r
4800 Is_Flash = "0";\r
4801 Data_Width = "16";\r
4802 Address_Width = "3";\r
4803 Maximum_Burst_Size = "1";\r
4804 Register_Incoming_Signals = "0";\r
4805 Register_Outgoing_Signals = "0";\r
4806 Interleave_Bursts = "0";\r
4807 Linewrap_Bursts = "0";\r
4808 Burst_On_Burst_Boundaries_Only = "0";\r
4809 Always_Burst_Max_Burst = "0";\r
4810 Is_Big_Endian = "0";\r
4811 Is_Enabled = "1";\r
4812 IRQ_MASTER cpu/data_master\r
4813 {\r
4814 IRQ_Number = "20";\r
4815 }\r
4816 MASTERED_BY slow_peripheral_bridge/m1\r
4817 {\r
4818 priority = "1";\r
4819 Offset_Address = "0x00001100";\r
4820 }\r
4821 Base_Address = "0x08001100";\r
4822 Address_Group = "0";\r
4823 }\r
4824 }\r
4825 class = "altera_avalon_timer";\r
4826 class_version = "7.08";\r
4827 iss_model_name = "altera_avalon_timer";\r
4828 SYSTEM_BUILDER_INFO \r
4829 {\r
4830 Instantiate_In_System_Module = "1";\r
4831 Is_Enabled = "1";\r
4832 Top_Level_Ports_Are_Enumerated = "1";\r
4833 View \r
4834 {\r
4835 Settings_Summary = "Timer with 10 ms timeout period.";\r
4836 Is_Collapsed = "1";\r
4837 MESSAGES \r
4838 {\r
4839 }\r
4840 }\r
4841 Clock_Source = "pll_c2_out";\r
4842 Has_Clock = "1";\r
4843 }\r
4844 WIZARD_SCRIPT_ARGUMENTS \r
4845 {\r
4846 always_run = "0";\r
4847 fixed_period = "0";\r
4848 snapshot = "1";\r
4849 period = "10";\r
4850 period_units = "ms";\r
4851 reset_output = "0";\r
4852 timeout_pulse_output = "0";\r
4853 load_value = "599999";\r
4854 counter_size = "32";\r
4855 mult = "0.0010";\r
4856 ticks_per_sec = "100";\r
4857 }\r
4858 HDL_INFO \r
4859 {\r
4860 Precompiled_Simulation_Library_Files = "";\r
4861 Simulation_HDL_Files = "";\r
4862 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/high_res_timer.v";\r
4863 Synthesis_Only_Files = "";\r
4864 }\r
4865 PORT_WIRING \r
4866 {\r
4867 }\r
4868 }\r
4869 MODULE sysid\r
4870 {\r
4871 SLAVE control_slave\r
4872 {\r
4873 PORT_WIRING \r
4874 {\r
4875 PORT clock\r
4876 {\r
4877 type = "clk";\r
4878 width = "1";\r
4879 direction = "input";\r
4880 Is_Enabled = "0";\r
4881 }\r
4882 PORT reset_n\r
4883 {\r
4884 type = "reset_n";\r
4885 width = "1";\r
4886 direction = "input";\r
4887 Is_Enabled = "0";\r
4888 }\r
4889 PORT address\r
4890 {\r
4891 type = "address";\r
4892 width = "1";\r
4893 direction = "input";\r
4894 Is_Enabled = "1";\r
4895 }\r
4896 PORT readdata\r
4897 {\r
4898 type = "readdata";\r
4899 width = "32";\r
4900 direction = "output";\r
4901 Is_Enabled = "1";\r
4902 }\r
4903 }\r
4904 SYSTEM_BUILDER_INFO \r
4905 {\r
4906 Bus_Type = "avalon";\r
4907 Write_Wait_States = "0cycles";\r
4908 Read_Wait_States = "1cycles";\r
4909 Hold_Time = "0cycles";\r
4910 Setup_Time = "0cycles";\r
4911 Is_Printable_Device = "0";\r
4912 Address_Alignment = "native";\r
4913 Well_Behaved_Waitrequest = "0";\r
4914 Is_Nonvolatile_Storage = "0";\r
4915 Read_Latency = "0";\r
4916 Is_Memory_Device = "0";\r
4917 Maximum_Pending_Read_Transactions = "0";\r
4918 Minimum_Uninterrupted_Run_Length = "1";\r
4919 Accepts_Internal_Connections = "1";\r
4920 Write_Latency = "0";\r
4921 Is_Flash = "0";\r
4922 Data_Width = "32";\r
4923 Address_Width = "1";\r
4924 Maximum_Burst_Size = "1";\r
4925 Register_Incoming_Signals = "0";\r
4926 Register_Outgoing_Signals = "0";\r
4927 Interleave_Bursts = "0";\r
4928 Linewrap_Bursts = "0";\r
4929 Burst_On_Burst_Boundaries_Only = "0";\r
4930 Always_Burst_Max_Burst = "0";\r
4931 Is_Big_Endian = "0";\r
4932 Is_Enabled = "1";\r
4933 MASTERED_BY slow_peripheral_bridge/m1\r
4934 {\r
4935 priority = "1";\r
4936 Offset_Address = "0x000011a8";\r
4937 }\r
4938 Base_Address = "0x080011a8";\r
4939 Has_IRQ = "0";\r
4940 Address_Group = "0";\r
4941 }\r
4942 }\r
4943 class = "altera_avalon_sysid";\r
4944 class_version = "7.08";\r
4945 SYSTEM_BUILDER_INFO \r
4946 {\r
4947 Date_Modified = "";\r
4948 Is_Enabled = "1";\r
4949 Instantiate_In_System_Module = "1";\r
4950 Fixed_Module_Name = "sysid";\r
4951 Top_Level_Ports_Are_Enumerated = "1";\r
4952 Clock_Source = "pll_c2_out";\r
4953 Has_Clock = "1";\r
4954 View \r
4955 {\r
4956 Settings_Summary = "System ID (at last Generate):<br> <b>53AF24E0</b> (unique ID tag) <br> <b>49362E4D</b> (timestamp: Wed Dec 3, 2008 @7:59 AM)";\r
4957 MESSAGES \r
4958 {\r
4959 }\r
4960 }\r
4961 }\r
4962 WIZARD_SCRIPT_ARGUMENTS \r
4963 {\r
4964 id = "1403987168u";\r
4965 timestamp = "1228287565u";\r
4966 regenerate_values = "0";\r
4967 MAKE \r
4968 {\r
4969 TARGET verifysysid\r
4970 {\r
4971 verifysysid \r
4972 {\r
4973 All_Depends_On = "0";\r
4974 Command = "nios2-download $(JTAG_CABLE) --sidp=0x080011a8 --id=1403987168 --timestamp=1228287565";\r
4975 Is_Phony = "1";\r
4976 Target_File = "dummy_verifysysid_file";\r
4977 }\r
4978 }\r
4979 }\r
4980 }\r
4981 HDL_INFO \r
4982 {\r
4983 Precompiled_Simulation_Library_Files = "";\r
4984 Simulation_HDL_Files = "";\r
4985 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.v";\r
4986 Synthesis_Only_Files = "";\r
4987 }\r
4988 PORT_WIRING \r
4989 {\r
4990 }\r
4991 }\r
4992 MODULE performance_counter\r
4993 {\r
4994 SLAVE control_slave\r
4995 {\r
4996 PORT_WIRING \r
4997 {\r
4998 PORT clk\r
4999 {\r
5000 type = "clk";\r
5001 width = "1";\r
5002 direction = "input";\r
5003 Is_Enabled = "1";\r
5004 }\r
5005 PORT reset_n\r
5006 {\r
5007 type = "reset_n";\r
5008 width = "1";\r
5009 direction = "input";\r
5010 Is_Enabled = "1";\r
5011 }\r
5012 PORT address\r
5013 {\r
5014 type = "address";\r
5015 width = "3";\r
5016 direction = "input";\r
5017 Is_Enabled = "1";\r
5018 }\r
5019 PORT begintransfer\r
5020 {\r
5021 type = "begintransfer";\r
5022 width = "1";\r
5023 direction = "input";\r
5024 Is_Enabled = "1";\r
5025 }\r
5026 PORT readdata\r
5027 {\r
5028 type = "readdata";\r
5029 width = "32";\r
5030 direction = "output";\r
5031 Is_Enabled = "1";\r
5032 }\r
5033 PORT write\r
5034 {\r
5035 type = "write";\r
5036 width = "1";\r
5037 direction = "input";\r
5038 Is_Enabled = "1";\r
5039 }\r
5040 PORT writedata\r
5041 {\r
5042 type = "writedata";\r
5043 width = "32";\r
5044 direction = "input";\r
5045 Is_Enabled = "1";\r
5046 }\r
5047 }\r
5048 SYSTEM_BUILDER_INFO \r
5049 {\r
5050 Bus_Type = "avalon";\r
5051 Write_Wait_States = "0cycles";\r
5052 Read_Wait_States = "0cycles";\r
5053 Hold_Time = "0cycles";\r
5054 Setup_Time = "0cycles";\r
5055 Is_Printable_Device = "0";\r
5056 Address_Alignment = "native";\r
5057 Well_Behaved_Waitrequest = "0";\r
5058 Is_Nonvolatile_Storage = "0";\r
5059 Read_Latency = "1";\r
5060 Is_Memory_Device = "0";\r
5061 Maximum_Pending_Read_Transactions = "0";\r
5062 Minimum_Uninterrupted_Run_Length = "1";\r
5063 Accepts_Internal_Connections = "1";\r
5064 Write_Latency = "0";\r
5065 Is_Flash = "0";\r
5066 Data_Width = "32";\r
5067 Address_Width = "3";\r
5068 Maximum_Burst_Size = "1";\r
5069 Register_Incoming_Signals = "0";\r
5070 Register_Outgoing_Signals = "0";\r
5071 Interleave_Bursts = "0";\r
5072 Linewrap_Bursts = "0";\r
5073 Burst_On_Burst_Boundaries_Only = "0";\r
5074 Always_Burst_Max_Burst = "0";\r
5075 Is_Big_Endian = "0";\r
5076 Is_Enabled = "1";\r
5077 MASTERED_BY slow_peripheral_bridge/m1\r
5078 {\r
5079 priority = "1";\r
5080 Offset_Address = "0x00001120";\r
5081 }\r
5082 Base_Address = "0x08001120";\r
5083 Has_IRQ = "0";\r
5084 Address_Group = "0";\r
5085 }\r
5086 }\r
5087 WIZARD_SCRIPT_ARGUMENTS \r
5088 {\r
5089 how_many_sections = "1";\r
5090 }\r
5091 class = "altera_avalon_performance_counter";\r
5092 class_version = "7.08";\r
5093 SYSTEM_BUILDER_INFO \r
5094 {\r
5095 Is_Enabled = "1";\r
5096 Clock_Source = "pll_c2_out";\r
5097 Has_Clock = "1";\r
5098 Date_Modified = "";\r
5099 Instantiate_In_System_Module = "1";\r
5100 Top_Level_Ports_Are_Enumerated = "1";\r
5101 View \r
5102 {\r
5103 MESSAGES \r
5104 {\r
5105 }\r
5106 }\r
5107 }\r
5108 HDL_INFO \r
5109 {\r
5110 Precompiled_Simulation_Library_Files = "";\r
5111 Simulation_HDL_Files = "";\r
5112 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/performance_counter.v";\r
5113 Synthesis_Only_Files = "";\r
5114 }\r
5115 PORT_WIRING \r
5116 {\r
5117 }\r
5118 }\r
5119 MODULE jtag_uart\r
5120 {\r
5121 SLAVE avalon_jtag_slave\r
5122 {\r
5123 PORT_WIRING \r
5124 {\r
5125 PORT clk\r
5126 {\r
5127 type = "clk";\r
5128 width = "1";\r
5129 direction = "input";\r
5130 Is_Enabled = "1";\r
5131 }\r
5132 PORT reset_n\r
5133 {\r
5134 type = "reset_n";\r
5135 width = "1";\r
5136 direction = "input";\r
5137 Is_Enabled = "0";\r
5138 }\r
5139 PORT av_irq\r
5140 {\r
5141 type = "irq";\r
5142 width = "1";\r
5143 direction = "output";\r
5144 Is_Enabled = "1";\r
5145 }\r
5146 PORT av_chipselect\r
5147 {\r
5148 type = "chipselect";\r
5149 width = "1";\r
5150 direction = "input";\r
5151 Is_Enabled = "1";\r
5152 }\r
5153 PORT av_address\r
5154 {\r
5155 type = "address";\r
5156 width = "1";\r
5157 direction = "input";\r
5158 Is_Enabled = "1";\r
5159 }\r
5160 PORT av_read_n\r
5161 {\r
5162 type = "read_n";\r
5163 width = "1";\r
5164 direction = "input";\r
5165 Is_Enabled = "1";\r
5166 }\r
5167 PORT av_readdata\r
5168 {\r
5169 type = "readdata";\r
5170 width = "32";\r
5171 direction = "output";\r
5172 Is_Enabled = "1";\r
5173 }\r
5174 PORT av_write_n\r
5175 {\r
5176 type = "write_n";\r
5177 width = "1";\r
5178 direction = "input";\r
5179 Is_Enabled = "1";\r
5180 }\r
5181 PORT av_writedata\r
5182 {\r
5183 type = "writedata";\r
5184 width = "32";\r
5185 direction = "input";\r
5186 Is_Enabled = "1";\r
5187 }\r
5188 PORT av_waitrequest\r
5189 {\r
5190 type = "waitrequest";\r
5191 width = "1";\r
5192 direction = "output";\r
5193 Is_Enabled = "1";\r
5194 }\r
5195 PORT dataavailable\r
5196 {\r
5197 type = "dataavailable";\r
5198 width = "1";\r
5199 direction = "output";\r
5200 Is_Enabled = "1";\r
5201 }\r
5202 PORT readyfordata\r
5203 {\r
5204 type = "readyfordata";\r
5205 width = "1";\r
5206 direction = "output";\r
5207 Is_Enabled = "1";\r
5208 }\r
5209 PORT rst_n\r
5210 {\r
5211 type = "reset_n";\r
5212 direction = "input";\r
5213 width = "1";\r
5214 Is_Enabled = "1";\r
5215 }\r
5216 }\r
5217 SYSTEM_BUILDER_INFO \r
5218 {\r
5219 Has_IRQ = "1";\r
5220 Bus_Type = "avalon";\r
5221 Read_Wait_States = "peripheral_controlled";\r
5222 Write_Wait_States = "peripheral_controlled";\r
5223 Hold_Time = "0cycles";\r
5224 Setup_Time = "0cycles";\r
5225 Is_Printable_Device = "1";\r
5226 Address_Alignment = "native";\r
5227 Well_Behaved_Waitrequest = "0";\r
5228 Is_Nonvolatile_Storage = "0";\r
5229 Read_Latency = "0";\r
5230 Is_Memory_Device = "0";\r
5231 Maximum_Pending_Read_Transactions = "0";\r
5232 Minimum_Uninterrupted_Run_Length = "1";\r
5233 Accepts_Internal_Connections = "1";\r
5234 Write_Latency = "0";\r
5235 Is_Flash = "0";\r
5236 Data_Width = "32";\r
5237 Address_Width = "1";\r
5238 Maximum_Burst_Size = "1";\r
5239 Register_Incoming_Signals = "0";\r
5240 Register_Outgoing_Signals = "0";\r
5241 Interleave_Bursts = "0";\r
5242 Linewrap_Bursts = "0";\r
5243 Burst_On_Burst_Boundaries_Only = "0";\r
5244 Always_Burst_Max_Burst = "0";\r
5245 Is_Big_Endian = "0";\r
5246 Is_Enabled = "1";\r
5247 JTAG_Hub_Base_Id = "262254";\r
5248 JTAG_Hub_Instance_Id = "0";\r
5249 Connection_Limit = "1";\r
5250 IRQ_MASTER cpu/data_master\r
5251 {\r
5252 IRQ_Number = "10";\r
5253 }\r
5254 MASTERED_BY slow_peripheral_bridge/m1\r
5255 {\r
5256 priority = "1";\r
5257 Offset_Address = "0x000011a0";\r
5258 }\r
5259 Base_Address = "0x080011a0";\r
5260 Address_Group = "0";\r
5261 }\r
5262 }\r
5263 class = "altera_avalon_jtag_uart";\r
5264 class_version = "7.08";\r
5265 iss_model_name = "altera_avalon_jtag_uart";\r
5266 WIZARD_SCRIPT_ARGUMENTS \r
5267 {\r
5268 write_depth = "8";\r
5269 read_depth = "8";\r
5270 write_threshold = "4";\r
5271 read_threshold = "4";\r
5272 read_char_stream = "";\r
5273 showascii = "1";\r
5274 read_le = "1";\r
5275 write_le = "1";\r
5276 altera_show_unreleased_jtag_uart_features = "0";\r
5277 }\r
5278 SIMULATION \r
5279 {\r
5280 DISPLAY \r
5281 {\r
5282 SIGNAL av_chipselect\r
5283 {\r
5284 name = "av_chipselect";\r
5285 }\r
5286 SIGNAL av_address\r
5287 {\r
5288 name = "av_address";\r
5289 radix = "hexadecimal";\r
5290 }\r
5291 SIGNAL av_read_n\r
5292 {\r
5293 name = "av_read_n";\r
5294 }\r
5295 SIGNAL av_readdata\r
5296 {\r
5297 name = "av_readdata";\r
5298 radix = "hexadecimal";\r
5299 }\r
5300 SIGNAL av_write_n\r
5301 {\r
5302 name = "av_write_n";\r
5303 }\r
5304 SIGNAL av_writedata\r
5305 {\r
5306 name = "av_writedata";\r
5307 radix = "hexadecimal";\r
5308 }\r
5309 SIGNAL av_waitrequest\r
5310 {\r
5311 name = "av_waitrequest";\r
5312 }\r
5313 SIGNAL dataavailable\r
5314 {\r
5315 name = "dataavailable";\r
5316 }\r
5317 SIGNAL readyfordata\r
5318 {\r
5319 name = "readyfordata";\r
5320 }\r
5321 SIGNAL av_irq\r
5322 {\r
5323 name = "av_irq";\r
5324 }\r
5325 }\r
5326 INTERACTIVE_IN drive\r
5327 {\r
5328 enable = "0";\r
5329 file = "_input_data_stream.dat";\r
5330 mutex = "_input_data_mutex.dat";\r
5331 log = "_in.log";\r
5332 rate = "100";\r
5333 signals = "temp,list";\r
5334 exe = "nios2-terminal";\r
5335 }\r
5336 INTERACTIVE_OUT log\r
5337 {\r
5338 enable = "1";\r
5339 exe = "perl -- atail-f.pl";\r
5340 file = "_output_stream.dat";\r
5341 radix = "ascii";\r
5342 signals = "temp,list";\r
5343 }\r
5344 Fix_Me_Up = "";\r
5345 }\r
5346 SYSTEM_BUILDER_INFO \r
5347 {\r
5348 Is_Enabled = "1";\r
5349 Clock_Source = "pll_c2_out";\r
5350 Has_Clock = "1";\r
5351 Instantiate_In_System_Module = "1";\r
5352 Iss_Launch_Telnet = "0";\r
5353 Top_Level_Ports_Are_Enumerated = "1";\r
5354 View \r
5355 {\r
5356 MESSAGES \r
5357 {\r
5358 }\r
5359 Settings_Summary = "<br>Write Depth: 8; Write IRQ Threshold: 4
5360 <br>Read Depth: 8; Read IRQ Threshold: 4";\r
5361 }\r
5362 }\r
5363 HDL_INFO \r
5364 {\r
5365 Precompiled_Simulation_Library_Files = "";\r
5366 Simulation_HDL_Files = "";\r
5367 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart.v";\r
5368 Synthesis_Only_Files = "";\r
5369 }\r
5370 PORT_WIRING \r
5371 {\r
5372 }\r
5373 }\r
5374 MODULE button_pio\r
5375 {\r
5376 SLAVE s1\r
5377 {\r
5378 PORT_WIRING \r
5379 {\r
5380 PORT clk\r
5381 {\r
5382 type = "clk";\r
5383 width = "1";\r
5384 direction = "input";\r
5385 Is_Enabled = "1";\r
5386 }\r
5387 PORT reset_n\r
5388 {\r
5389 type = "reset_n";\r
5390 width = "1";\r
5391 direction = "input";\r
5392 Is_Enabled = "1";\r
5393 }\r
5394 PORT irq\r
5395 {\r
5396 type = "irq";\r
5397 width = "1";\r
5398 direction = "output";\r
5399 Is_Enabled = "1";\r
5400 }\r
5401 PORT address\r
5402 {\r
5403 type = "address";\r
5404 width = "2";\r
5405 direction = "input";\r
5406 Is_Enabled = "1";\r
5407 }\r
5408 PORT write_n\r
5409 {\r
5410 type = "write_n";\r
5411 width = "1";\r
5412 direction = "input";\r
5413 Is_Enabled = "1";\r
5414 }\r
5415 PORT writedata\r
5416 {\r
5417 type = "writedata";\r
5418 width = "4";\r
5419 direction = "input";\r
5420 Is_Enabled = "1";\r
5421 }\r
5422 PORT chipselect\r
5423 {\r
5424 type = "chipselect";\r
5425 width = "1";\r
5426 direction = "input";\r
5427 Is_Enabled = "1";\r
5428 }\r
5429 PORT readdata\r
5430 {\r
5431 type = "readdata";\r
5432 width = "4";\r
5433 direction = "output";\r
5434 Is_Enabled = "1";\r
5435 }\r
5436 }\r
5437 SYSTEM_BUILDER_INFO \r
5438 {\r
5439 Has_IRQ = "1";\r
5440 Bus_Type = "avalon";\r
5441 Write_Wait_States = "0cycles";\r
5442 Read_Wait_States = "1cycles";\r
5443 Hold_Time = "0cycles";\r
5444 Setup_Time = "0cycles";\r
5445 Is_Printable_Device = "0";\r
5446 Address_Alignment = "native";\r
5447 Well_Behaved_Waitrequest = "0";\r
5448 Is_Nonvolatile_Storage = "0";\r
5449 Read_Latency = "0";\r
5450 Is_Memory_Device = "0";\r
5451 Maximum_Pending_Read_Transactions = "0";\r
5452 Minimum_Uninterrupted_Run_Length = "1";\r
5453 Accepts_Internal_Connections = "1";\r
5454 Write_Latency = "0";\r
5455 Is_Flash = "0";\r
5456 Data_Width = "4";\r
5457 Address_Width = "2";\r
5458 Maximum_Burst_Size = "1";\r
5459 Register_Incoming_Signals = "0";\r
5460 Register_Outgoing_Signals = "0";\r
5461 Interleave_Bursts = "0";\r
5462 Linewrap_Bursts = "0";\r
5463 Burst_On_Burst_Boundaries_Only = "0";\r
5464 Always_Burst_Max_Burst = "0";\r
5465 Is_Big_Endian = "0";\r
5466 Is_Enabled = "1";\r
5467 IRQ_MASTER cpu/data_master\r
5468 {\r
5469 IRQ_Number = "12";\r
5470 }\r
5471 MASTERED_BY slow_peripheral_bridge/m1\r
5472 {\r
5473 priority = "1";\r
5474 Offset_Address = "0x00001180";\r
5475 }\r
5476 Base_Address = "0x08001180";\r
5477 Address_Group = "0";\r
5478 Is_Readable = "1";\r
5479 Is_Writable = "1";\r
5480 }\r
5481 }\r
5482 PORT_WIRING \r
5483 {\r
5484 PORT in_port\r
5485 {\r
5486 type = "export";\r
5487 width = "4";\r
5488 direction = "input";\r
5489 Is_Enabled = "1";\r
5490 test_bench_value = "15";\r
5491 }\r
5492 PORT out_port\r
5493 {\r
5494 direction = "output";\r
5495 Is_Enabled = "0";\r
5496 width = "4";\r
5497 }\r
5498 PORT bidir_port\r
5499 {\r
5500 direction = "inout";\r
5501 Is_Enabled = "0";\r
5502 width = "4";\r
5503 }\r
5504 }\r
5505 class = "altera_avalon_pio";\r
5506 class_version = "7.08";\r
5507 SYSTEM_BUILDER_INFO \r
5508 {\r
5509 Is_Enabled = "1";\r
5510 Instantiate_In_System_Module = "1";\r
5511 Wire_Test_Bench_Values = "1";\r
5512 Top_Level_Ports_Are_Enumerated = "1";\r
5513 Clock_Source = "pll_c2_out";\r
5514 Has_Clock = "1";\r
5515 Date_Modified = "";\r
5516 View \r
5517 {\r
5518 MESSAGES \r
5519 {\r
5520 }\r
5521 Settings_Summary = " 4-bit PIO using <br>
5523 input pins with edge type RISING and interrupt source EDGE
5524 ";\r
5525 }\r
5526 }\r
5527 WIZARD_SCRIPT_ARGUMENTS \r
5528 {\r
5529 Do_Test_Bench_Wiring = "1";\r
5530 Driven_Sim_Value = "15";\r
5531 has_tri = "0";\r
5532 has_out = "0";\r
5533 has_in = "1";\r
5534 capture = "1";\r
5535 Data_Width = "4";\r
5536 reset_value = "0";\r
5537 edge_type = "RISING";\r
5538 irq_type = "EDGE";\r
5539 bit_clearing_edge_register = "0";\r
5540 }\r
5541 HDL_INFO \r
5542 {\r
5543 Precompiled_Simulation_Library_Files = "";\r
5544 Simulation_HDL_Files = "";\r
5545 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/button_pio.v";\r
5546 Synthesis_Only_Files = "";\r
5547 }\r
5548 }\r
5549 MODULE led_pio\r
5550 {\r
5551 SLAVE s1\r
5552 {\r
5553 PORT_WIRING \r
5554 {\r
5555 PORT clk\r
5556 {\r
5557 type = "clk";\r
5558 width = "1";\r
5559 direction = "input";\r
5560 Is_Enabled = "1";\r
5561 }\r
5562 PORT reset_n\r
5563 {\r
5564 type = "reset_n";\r
5565 width = "1";\r
5566 direction = "input";\r
5567 Is_Enabled = "1";\r
5568 }\r
5569 PORT address\r
5570 {\r
5571 type = "address";\r
5572 width = "2";\r
5573 direction = "input";\r
5574 Is_Enabled = "1";\r
5575 }\r
5576 PORT write_n\r
5577 {\r
5578 type = "write_n";\r
5579 width = "1";\r
5580 direction = "input";\r
5581 Is_Enabled = "1";\r
5582 }\r
5583 PORT writedata\r
5584 {\r
5585 type = "writedata";\r
5586 width = "2";\r
5587 direction = "input";\r
5588 Is_Enabled = "1";\r
5589 }\r
5590 PORT chipselect\r
5591 {\r
5592 type = "chipselect";\r
5593 width = "1";\r
5594 direction = "input";\r
5595 Is_Enabled = "1";\r
5596 }\r
5597 }\r
5598 SYSTEM_BUILDER_INFO \r
5599 {\r
5600 Bus_Type = "avalon";\r
5601 Write_Wait_States = "0cycles";\r
5602 Read_Wait_States = "1cycles";\r
5603 Hold_Time = "0cycles";\r
5604 Setup_Time = "0cycles";\r
5605 Is_Printable_Device = "0";\r
5606 Address_Alignment = "native";\r
5607 Well_Behaved_Waitrequest = "0";\r
5608 Is_Nonvolatile_Storage = "0";\r
5609 Read_Latency = "0";\r
5610 Is_Memory_Device = "0";\r
5611 Maximum_Pending_Read_Transactions = "0";\r
5612 Minimum_Uninterrupted_Run_Length = "1";\r
5613 Accepts_Internal_Connections = "1";\r
5614 Write_Latency = "0";\r
5615 Is_Flash = "0";\r
5616 Data_Width = "2";\r
5617 Address_Width = "2";\r
5618 Maximum_Burst_Size = "1";\r
5619 Register_Incoming_Signals = "0";\r
5620 Register_Outgoing_Signals = "0";\r
5621 Interleave_Bursts = "0";\r
5622 Linewrap_Bursts = "0";\r
5623 Burst_On_Burst_Boundaries_Only = "0";\r
5624 Always_Burst_Max_Burst = "0";\r
5625 Is_Big_Endian = "0";\r
5626 Is_Enabled = "1";\r
5627 MASTERED_BY slow_peripheral_bridge/m1\r
5628 {\r
5629 priority = "1";\r
5630 Offset_Address = "0x00001190";\r
5631 }\r
5632 Base_Address = "0x08001190";\r
5633 Has_IRQ = "0";\r
5634 Address_Group = "0";\r
5635 Is_Readable = "0";\r
5636 Is_Writable = "1";\r
5637 }\r
5638 }\r
5639 PORT_WIRING \r
5640 {\r
5641 PORT out_port\r
5642 {\r
5643 type = "export";\r
5644 width = "2";\r
5645 direction = "output";\r
5646 Is_Enabled = "1";\r
5647 }\r
5648 PORT in_port\r
5649 {\r
5650 direction = "input";\r
5651 Is_Enabled = "0";\r
5652 width = "2";\r
5653 }\r
5654 PORT bidir_port\r
5655 {\r
5656 direction = "inout";\r
5657 Is_Enabled = "0";\r
5658 width = "2";\r
5659 }\r
5660 }\r
5661 class = "altera_avalon_pio";\r
5662 class_version = "7.08";\r
5663 SYSTEM_BUILDER_INFO \r
5664 {\r
5665 Is_Enabled = "1";\r
5666 Instantiate_In_System_Module = "1";\r
5667 Wire_Test_Bench_Values = "1";\r
5668 Top_Level_Ports_Are_Enumerated = "1";\r
5669 Clock_Source = "pll_c2_out";\r
5670 Has_Clock = "1";\r
5671 Date_Modified = "";\r
5672 View \r
5673 {\r
5674 MESSAGES \r
5675 {\r
5676 }\r
5677 Settings_Summary = " 2-bit PIO using <br>
5680 output pins";\r
5681 }\r
5682 }\r
5683 WIZARD_SCRIPT_ARGUMENTS \r
5684 {\r
5685 Do_Test_Bench_Wiring = "0";\r
5686 Driven_Sim_Value = "0";\r
5687 has_tri = "0";\r
5688 has_out = "1";\r
5689 has_in = "0";\r
5690 capture = "0";\r
5691 Data_Width = "2";\r
5692 reset_value = "0";\r
5693 edge_type = "NONE";\r
5694 irq_type = "NONE";\r
5695 bit_clearing_edge_register = "0";\r
5696 }\r
5697 HDL_INFO \r
5698 {\r
5699 Precompiled_Simulation_Library_Files = "";\r
5700 Simulation_HDL_Files = "";\r
5701 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/led_pio.v";\r
5702 Synthesis_Only_Files = "";\r
5703 }\r
5704 }\r
5705 MODULE remote_update\r
5706 {\r
5707 SLAVE s1\r
5708 {\r
5709 PORT_WIRING \r
5710 {\r
5711 PORT clk\r
5712 {\r
5713 type = "clk";\r
5714 width = "1";\r
5715 direction = "input";\r
5716 Is_Enabled = "1";\r
5717 }\r
5718 PORT reset\r
5719 {\r
5720 type = "reset";\r
5721 width = "1";\r
5722 direction = "input";\r
5723 Is_Enabled = "1";\r
5724 }\r
5725 PORT writedata\r
5726 {\r
5727 type = "writedata";\r
5728 width = "32";\r
5729 direction = "input";\r
5730 Is_Enabled = "1";\r
5731 }\r
5732 PORT readdata\r
5733 {\r
5734 type = "readdata";\r
5735 width = "32";\r
5736 direction = "output";\r
5737 Is_Enabled = "1";\r
5738 }\r
5739 PORT address\r
5740 {\r
5741 type = "address";\r
5742 width = "6";\r
5743 direction = "input";\r
5744 Is_Enabled = "1";\r
5745 }\r
5746 PORT chipselect\r
5747 {\r
5748 type = "chipselect";\r
5749 width = "1";\r
5750 direction = "input";\r
5751 Is_Enabled = "1";\r
5752 }\r
5753 PORT write\r
5754 {\r
5755 type = "write";\r
5756 width = "1";\r
5757 direction = "input";\r
5758 Is_Enabled = "1";\r
5759 }\r
5760 PORT read\r
5761 {\r
5762 type = "read";\r
5763 width = "1";\r
5764 direction = "input";\r
5765 Is_Enabled = "1";\r
5766 }\r
5767 PORT waitrequest\r
5768 {\r
5769 type = "waitrequest";\r
5770 width = "1";\r
5771 direction = "output";\r
5772 Is_Enabled = "1";\r
5773 }\r
5774 }\r
5775 SYSTEM_BUILDER_INFO \r
5776 {\r
5777 Bus_Type = "avalon";\r
5778 Read_Wait_States = "peripheral_controlled";\r
5779 Write_Wait_States = "peripheral_controlled";\r
5780 Hold_Time = "0cycles";\r
5781 Setup_Time = "0cycles";\r
5782 Is_Printable_Device = "0";\r
5783 Address_Alignment = "native";\r
5784 Well_Behaved_Waitrequest = "0";\r
5785 Is_Nonvolatile_Storage = "0";\r
5786 Read_Latency = "2";\r
5787 Is_Memory_Device = "0";\r
5788 Maximum_Pending_Read_Transactions = "0";\r
5789 Minimum_Uninterrupted_Run_Length = "1";\r
5790 Accepts_Internal_Connections = "1";\r
5791 Write_Latency = "0";\r
5792 Is_Flash = "0";\r
5793 Data_Width = "32";\r
5794 Address_Width = "6";\r
5795 Maximum_Burst_Size = "1";\r
5796 Register_Incoming_Signals = "0";\r
5797 Register_Outgoing_Signals = "0";\r
5798 Interleave_Bursts = "0";\r
5799 Linewrap_Bursts = "0";\r
5800 Burst_On_Burst_Boundaries_Only = "0";\r
5801 Always_Burst_Max_Burst = "0";\r
5802 Is_Big_Endian = "0";\r
5803 Is_Enabled = "1";\r
5804 MASTERED_BY slow_peripheral_bridge/m1\r
5805 {\r
5806 priority = "1";\r
5807 Offset_Address = "0x00001000";\r
5808 }\r
5809 Base_Address = "0x08001000";\r
5810 Address_Group = "0";\r
5811 }\r
5812 }\r
5813 class = "no_legacy_module";\r
5814 class_version = "7.08";\r
5815 gtf_class_name = "altera_avalon_remote_update_cycloneiii";\r
5816 gtf_class_version = "8.0";\r
5817 SYSTEM_BUILDER_INFO \r
5818 {\r
5819 Do_Not_Generate = "1";\r
5820 Instantiate_In_System_Module = "1";\r
5821 Is_Enabled = "1";\r
5822 Clock_Source = "pll_c3_out";\r
5823 Has_Clock = "1";\r
5824 View \r
5825 {\r
5826 MESSAGES \r
5827 {\r
5828 }\r
5829 }\r
5830 }\r
5831 HDL_INFO \r
5832 {\r
5833 Simulation_HDL_Files = "__PROJECT_DIRECTORY__/remote_update.v,__PROJECT_DIRECTORY__/remote_update.vo";\r
5834 }\r
5835 WIZARD_SCRIPT_ARGUMENTS \r
5836 {\r
5837 terminated_ports \r
5838 {\r
5839 }\r
5840 }\r
5841 }\r
5842 MODULE ocm\r
5843 {\r
5844 SLAVE control_port\r
5845 {\r
5846 PORT_WIRING \r
5847 {\r
5848 PORT av_clk\r
5849 {\r
5850 type = "clk";\r
5851 width = "1";\r
5852 direction = "input";\r
5853 Is_Enabled = "1";\r
5854 }\r
5855 PORT av_reset\r
5856 {\r
5857 type = "reset";\r
5858 width = "1";\r
5859 direction = "input";\r
5860 Is_Enabled = "1";\r
5861 }\r
5862 PORT av_irq\r
5863 {\r
5864 type = "irq";\r
5865 width = "1";\r
5866 direction = "output";\r
5867 Is_Enabled = "1";\r
5868 }\r
5869 PORT av_address\r
5870 {\r
5871 type = "address";\r
5872 width = "10";\r
5873 direction = "input";\r
5874 Is_Enabled = "1";\r
5875 }\r
5876 PORT av_chipselect\r
5877 {\r
5878 type = "chipselect";\r
5879 width = "1";\r
5880 direction = "input";\r
5881 Is_Enabled = "1";\r
5882 }\r
5883 PORT av_write\r
5884 {\r
5885 type = "write";\r
5886 width = "1";\r
5887 direction = "input";\r
5888 Is_Enabled = "1";\r
5889 }\r
5890 PORT av_read\r
5891 {\r
5892 type = "read";\r
5893 width = "1";\r
5894 direction = "input";\r
5895 Is_Enabled = "1";\r
5896 }\r
5897 PORT av_writedata\r
5898 {\r
5899 type = "writedata";\r
5900 width = "32";\r
5901 direction = "input";\r
5902 Is_Enabled = "1";\r
5903 }\r
5904 PORT av_readdata\r
5905 {\r
5906 type = "readdata";\r
5907 width = "32";\r
5908 direction = "output";\r
5909 Is_Enabled = "1";\r
5910 }\r
5911 PORT av_waitrequest_n\r
5912 {\r
5913 type = "waitrequest_n";\r
5914 width = "1";\r
5915 direction = "output";\r
5916 Is_Enabled = "1";\r
5917 }\r
5918 }\r
5919 SYSTEM_BUILDER_INFO \r
5920 {\r
5921 Has_IRQ = "1";\r
5922 Bus_Type = "avalon";\r
5923 Read_Wait_States = "peripheral_controlled";\r
5924 Write_Wait_States = "peripheral_controlled";\r
5925 Hold_Time = "0cycles";\r
5926 Setup_Time = "0cycles";\r
5927 Is_Printable_Device = "0";\r
5928 Address_Alignment = "dynamic";\r
5929 Well_Behaved_Waitrequest = "0";\r
5930 Is_Nonvolatile_Storage = "0";\r
5931 Address_Span = "4096";\r
5932 Read_Latency = "0";\r
5933 Is_Memory_Device = "0";\r
5934 Maximum_Pending_Read_Transactions = "0";\r
5935 Minimum_Uninterrupted_Run_Length = "1";\r
5936 Accepts_Internal_Connections = "1";\r
5937 Write_Latency = "0";\r
5938 Is_Flash = "0";\r
5939 Data_Width = "32";\r
5940 Address_Width = "10";\r
5941 Maximum_Burst_Size = "1";\r
5942 Register_Incoming_Signals = "0";\r
5943 Register_Outgoing_Signals = "0";\r
5944 Interleave_Bursts = "0";\r
5945 Linewrap_Bursts = "0";\r
5946 Burst_On_Burst_Boundaries_Only = "0";\r
5947 Always_Burst_Max_Burst = "0";\r
5948 Is_Big_Endian = "0";\r
5949 Is_Enabled = "1";\r
5950 IRQ_MASTER cpu/data_master\r
5951 {\r
5952 IRQ_Number = "15";\r
5953 }\r
5954 MASTERED_BY slow_peripheral_bridge/m1\r
5955 {\r
5956 priority = "1";\r
5957 Offset_Address = "0x00002000";\r
5958 }\r
5959 Base_Address = "0x08002000";\r
5960 Address_Group = "0";\r
5961 }\r
5962 }\r
5963 PORT_WIRING \r
5964 {\r
5965 PORT mtx_clk_pad_i\r
5966 {\r
5967 type = "export";\r
5968 width = "1";\r
5969 direction = "input";\r
5970 Is_Enabled = "1";\r
5971 }\r
5972 PORT mtxd_pad_o\r
5973 {\r
5974 type = "export";\r
5975 width = "4";\r
5976 direction = "output";\r
5977 Is_Enabled = "1";\r
5978 }\r
5979 PORT mtxen_pad_o\r
5980 {\r
5981 type = "export";\r
5982 width = "1";\r
5983 direction = "output";\r
5984 Is_Enabled = "1";\r
5985 }\r
5986 PORT mtxerr_pad_o\r
5987 {\r
5988 type = "export";\r
5989 width = "1";\r
5990 direction = "output";\r
5991 Is_Enabled = "1";\r
5992 }\r
5993 PORT mrx_clk_pad_i\r
5994 {\r
5995 type = "export";\r
5996 width = "1";\r
5997 direction = "input";\r
5998 Is_Enabled = "1";\r
5999 }\r
6000 PORT mrxd_pad_i\r
6001 {\r
6002 type = "export";\r
6003 width = "4";\r
6004 direction = "input";\r
6005 Is_Enabled = "1";\r
6006 }\r
6007 PORT mrxdv_pad_i\r
6008 {\r
6009 type = "export";\r
6010 width = "1";\r
6011 direction = "input";\r
6012 Is_Enabled = "1";\r
6013 }\r
6014 PORT mrxerr_pad_i\r
6015 {\r
6016 type = "export";\r
6017 width = "1";\r
6018 direction = "input";\r
6019 Is_Enabled = "1";\r
6020 }\r
6021 PORT mcoll_pad_i\r
6022 {\r
6023 type = "export";\r
6024 width = "1";\r
6025 direction = "input";\r
6026 Is_Enabled = "1";\r
6027 }\r
6028 PORT mcrs_pad_i\r
6029 {\r
6030 type = "export";\r
6031 width = "1";\r
6032 direction = "input";\r
6033 Is_Enabled = "1";\r
6034 }\r
6035 PORT mdc_pad_o\r
6036 {\r
6037 type = "export";\r
6038 width = "1";\r
6039 direction = "output";\r
6040 Is_Enabled = "1";\r
6041 }\r
6042 PORT md_pad_i\r
6043 {\r
6044 type = "export";\r
6045 width = "1";\r
6046 direction = "input";\r
6047 Is_Enabled = "1";\r
6048 }\r
6049 PORT md_pad_o\r
6050 {\r
6051 type = "export";\r
6052 width = "1";\r
6053 direction = "output";\r
6054 Is_Enabled = "1";\r
6055 }\r
6056 PORT md_padoe_o\r
6057 {\r
6058 type = "export";\r
6059 width = "1";\r
6060 direction = "output";\r
6061 Is_Enabled = "1";\r
6062 }\r
6063 }\r
6064 MASTER rx_master\r
6065 {\r
6066 SYSTEM_BUILDER_INFO \r
6067 {\r
6068 Bus_Type = "avalon";\r
6069 Is_Asynchronous = "0";\r
6070 DBS_Big_Endian = "0";\r
6071 Adapts_To = "";\r
6072 Do_Stream_Reads = "0";\r
6073 Do_Stream_Writes = "0";\r
6074 Max_Address_Width = "32";\r
6075 Data_Width = "32";\r
6076 Address_Width = "32";\r
6077 Maximum_Burst_Size = "1";\r
6078 Register_Incoming_Signals = "0";\r
6079 Register_Outgoing_Signals = "0";\r
6080 Interleave_Bursts = "0";\r
6081 Linewrap_Bursts = "0";\r
6082 Burst_On_Burst_Boundaries_Only = "0";\r
6083 Always_Burst_Max_Burst = "0";\r
6084 Is_Big_Endian = "0";\r
6085 Is_Enabled = "1";\r
6086 }\r
6087 PORT_WIRING \r
6088 {\r
6089 PORT av_rx_waitrequest\r
6090 {\r
6091 type = "waitrequest";\r
6092 width = "1";\r
6093 direction = "input";\r
6094 Is_Enabled = "1";\r
6095 }\r
6096 PORT av_rx_address\r
6097 {\r
6098 type = "address";\r
6099 width = "32";\r
6100 direction = "output";\r
6101 Is_Enabled = "1";\r
6102 }\r
6103 PORT av_rx_write\r
6104 {\r
6105 type = "write";\r
6106 width = "1";\r
6107 direction = "output";\r
6108 Is_Enabled = "1";\r
6109 }\r
6110 PORT av_rx_writedata\r
6111 {\r
6112 type = "writedata";\r
6113 width = "32";\r
6114 direction = "output";\r
6115 Is_Enabled = "1";\r
6116 }\r
6117 PORT av_rx_byteenable\r
6118 {\r
6119 type = "byteenable";\r
6120 width = "4";\r
6121 direction = "output";\r
6122 Is_Enabled = "1";\r
6123 }\r
6124 }\r
6125 MEMORY_MAP \r
6126 {\r
6127 Entry slow_ddr_clock_bridge/s1\r
6128 {\r
6129 address = "0x00000000";\r
6130 span = "0x02000000";\r
6131 is_bridge = "1";\r
6132 }\r
6133 Entry ddr_sdram/s1\r
6134 {\r
6135 address = "0x00000000";\r
6136 span = "0x02000000";\r
6137 is_bridge = "0";\r
6138 }\r
6139 }\r
6140 }\r
6141 MASTER tx_master\r
6142 {\r
6143 SYSTEM_BUILDER_INFO \r
6144 {\r
6145 Bus_Type = "avalon";\r
6146 Is_Asynchronous = "0";\r
6147 DBS_Big_Endian = "0";\r
6148 Adapts_To = "";\r
6149 Do_Stream_Reads = "0";\r
6150 Do_Stream_Writes = "0";\r
6151 Max_Address_Width = "32";\r
6152 Data_Width = "32";\r
6153 Address_Width = "32";\r
6154 Maximum_Burst_Size = "1";\r
6155 Register_Incoming_Signals = "0";\r
6156 Register_Outgoing_Signals = "0";\r
6157 Interleave_Bursts = "0";\r
6158 Linewrap_Bursts = "0";\r
6159 Burst_On_Burst_Boundaries_Only = "0";\r
6160 Always_Burst_Max_Burst = "0";\r
6161 Is_Big_Endian = "0";\r
6162 Is_Enabled = "1";\r
6163 }\r
6164 PORT_WIRING \r
6165 {\r
6166 PORT av_tx_readdata\r
6167 {\r
6168 type = "readdata";\r
6169 width = "32";\r
6170 direction = "input";\r
6171 Is_Enabled = "1";\r
6172 }\r
6173 PORT av_tx_waitrequest\r
6174 {\r
6175 type = "waitrequest";\r
6176 width = "1";\r
6177 direction = "input";\r
6178 Is_Enabled = "1";\r
6179 }\r
6180 PORT av_tx_readdatavalid\r
6181 {\r
6182 type = "readdatavalid";\r
6183 width = "1";\r
6184 direction = "input";\r
6185 Is_Enabled = "1";\r
6186 }\r
6187 PORT av_tx_address\r
6188 {\r
6189 type = "address";\r
6190 width = "32";\r
6191 direction = "output";\r
6192 Is_Enabled = "1";\r
6193 }\r
6194 PORT av_tx_read\r
6195 {\r
6196 type = "read";\r
6197 width = "1";\r
6198 direction = "output";\r
6199 Is_Enabled = "1";\r
6200 }\r
6201 }\r
6202 MEMORY_MAP \r
6203 {\r
6204 Entry slow_ddr_clock_bridge/s1\r
6205 {\r
6206 address = "0x00000000";\r
6207 span = "0x02000000";\r
6208 is_bridge = "1";\r
6209 }\r
6210 Entry ddr_sdram/s1\r
6211 {\r
6212 address = "0x00000000";\r
6213 span = "0x02000000";\r
6214 is_bridge = "0";\r
6215 }\r
6216 }\r
6217 }\r
6218 class = "no_legacy_module";\r
6219 class_version = "7.08";\r
6220 gtf_class_name = "eth_ocm";\r
6221 gtf_class_version = "8.0.2";\r
6222 SYSTEM_BUILDER_INFO \r
6223 {\r
6224 Do_Not_Generate = "1";\r
6225 Instantiate_In_System_Module = "1";\r
6226 Is_Enabled = "1";\r
6227 Clock_Source = "pll_c2_out";\r
6228 Has_Clock = "1";\r
6229 View \r
6230 {\r
6231 MESSAGES \r
6232 {\r
6233 }\r
6234 }\r
6235 }\r
6236 HDL_INFO \r
6237 {\r
6238 Simulation_HDL_Files = "__PROJECT_DIRECTORY__/ocm.v,__PROJECT_DIRECTORY__/eth_ocm_80_2/eth_ocm.v";\r
6239 }\r
6240 WIZARD_SCRIPT_ARGUMENTS \r
6241 {\r
6242 terminated_ports \r
6243 {\r
6244 }\r
6245 }\r
6246 }\r
6247 MODULE slow_ddr_clock_bridge\r
6248 {\r
6249 SLAVE s1\r
6250 {\r
6251 PORT_WIRING \r
6252 {\r
6253 PORT slave_clk\r
6254 {\r
6255 type = "clk";\r
6256 width = "1";\r
6257 direction = "input";\r
6258 Is_Enabled = "1";\r
6259 }\r
6260 PORT slave_reset_n\r
6261 {\r
6262 type = "reset_n";\r
6263 width = "1";\r
6264 direction = "input";\r
6265 Is_Enabled = "1";\r
6266 }\r
6267 PORT slave_address\r
6268 {\r
6269 type = "address";\r
6270 width = "23";\r
6271 direction = "input";\r
6272 Is_Enabled = "1";\r
6273 }\r
6274 PORT slave_nativeaddress\r
6275 {\r
6276 type = "nativeaddress";\r
6277 width = "23";\r
6278 direction = "input";\r
6279 Is_Enabled = "1";\r
6280 }\r
6281 PORT slave_read\r
6282 {\r
6283 type = "read";\r
6284 width = "1";\r
6285 direction = "input";\r
6286 Is_Enabled = "1";\r
6287 }\r
6288 PORT slave_write\r
6289 {\r
6290 type = "write";\r
6291 width = "1";\r
6292 direction = "input";\r
6293 Is_Enabled = "1";\r
6294 }\r
6295 PORT slave_writedata\r
6296 {\r
6297 type = "writedata";\r
6298 width = "32";\r
6299 direction = "input";\r
6300 Is_Enabled = "1";\r
6301 }\r
6302 PORT slave_readdata\r
6303 {\r
6304 type = "readdata";\r
6305 width = "32";\r
6306 direction = "output";\r
6307 Is_Enabled = "1";\r
6308 }\r
6309 PORT slave_readdatavalid\r
6310 {\r
6311 type = "readdatavalid";\r
6312 width = "1";\r
6313 direction = "output";\r
6314 Is_Enabled = "1";\r
6315 }\r
6316 PORT slave_waitrequest\r
6317 {\r
6318 type = "waitrequest";\r
6319 width = "1";\r
6320 direction = "output";\r
6321 Is_Enabled = "1";\r
6322 }\r
6323 PORT slave_byteenable\r
6324 {\r
6325 type = "byteenable";\r
6326 width = "4";\r
6327 direction = "input";\r
6328 Is_Enabled = "1";\r
6329 }\r
6330 PORT slave_endofpacket\r
6331 {\r
6332 Is_Enabled = "1";\r
6333 direction = "output";\r
6334 type = "endofpacket";\r
6335 width = "1";\r
6336 }\r
6337 }\r
6338 SYSTEM_BUILDER_INFO \r
6339 {\r
6340 Bus_Type = "avalon";\r
6341 Read_Wait_States = "peripheral_controlled";\r
6342 Write_Wait_States = "peripheral_controlled";\r
6343 Hold_Time = "0cycles";\r
6344 Setup_Time = "0cycles";\r
6345 Is_Printable_Device = "0";\r
6346 Address_Alignment = "dynamic";\r
6347 Well_Behaved_Waitrequest = "0";\r
6348 Is_Nonvolatile_Storage = "0";\r
6349 Address_Span = "33554432";\r
6350 Read_Latency = "0";\r
6351 Is_Memory_Device = "0";\r
6352 Maximum_Pending_Read_Transactions = "64";\r
6353 Minimum_Uninterrupted_Run_Length = "1";\r
6354 Accepts_Internal_Connections = "1";\r
6355 Write_Latency = "0";\r
6356 Is_Flash = "0";\r
6357 Data_Width = "32";\r
6358 Address_Width = "23";\r
6359 Opaque_Bridges_To = "m1";\r
6360 Maximum_Burst_Size = "1";\r
6361 Register_Incoming_Signals = "0";\r
6362 Register_Outgoing_Signals = "0";\r
6363 Interleave_Bursts = "0";\r
6364 Linewrap_Bursts = "0";\r
6365 Burst_On_Burst_Boundaries_Only = "0";\r
6366 Always_Burst_Max_Burst = "0";\r
6367 Is_Big_Endian = "0";\r
6368 Is_Enabled = "1";\r
6369 Clock_Source = "pll_c2_out";\r
6370 Has_Clock = "1";\r
6371 MASTERED_BY ocm/rx_master\r
6372 {\r
6373 priority = "1";\r
6374 Offset_Address = "0x00000000";\r
6375 }\r
6376 MASTERED_BY ocm/tx_master\r
6377 {\r
6378 priority = "2";\r
6379 Offset_Address = "0x00000000";\r
6380 }\r
6381 Base_Address = "0x00000000";\r
6382 Address_Group = "0";\r
6383 }\r
6384 }\r
6385 MASTER m1\r
6386 {\r
6387 PORT_WIRING \r
6388 {\r
6389 PORT master_clk\r
6390 {\r
6391 type = "clk";\r
6392 width = "1";\r
6393 direction = "input";\r
6394 Is_Enabled = "1";\r
6395 }\r
6396 PORT master_reset_n\r
6397 {\r
6398 type = "reset_n";\r
6399 width = "1";\r
6400 direction = "input";\r
6401 Is_Enabled = "1";\r
6402 }\r
6403 PORT master_address\r
6404 {\r
6405 type = "address";\r
6406 width = "25";\r
6407 direction = "output";\r
6408 Is_Enabled = "1";\r
6409 }\r
6410 PORT master_nativeaddress\r
6411 {\r
6412 type = "nativeaddress";\r
6413 width = "23";\r
6414 direction = "output";\r
6415 Is_Enabled = "1";\r
6416 }\r
6417 PORT master_read\r
6418 {\r
6419 type = "read";\r
6420 width = "1";\r
6421 direction = "output";\r
6422 Is_Enabled = "1";\r
6423 }\r
6424 PORT master_write\r
6425 {\r
6426 type = "write";\r
6427 width = "1";\r
6428 direction = "output";\r
6429 Is_Enabled = "1";\r
6430 }\r
6431 PORT master_writedata\r
6432 {\r
6433 type = "writedata";\r
6434 width = "32";\r
6435 direction = "output";\r
6436 Is_Enabled = "1";\r
6437 }\r
6438 PORT master_readdata\r
6439 {\r
6440 type = "readdata";\r
6441 width = "32";\r
6442 direction = "input";\r
6443 Is_Enabled = "1";\r
6444 }\r
6445 PORT master_readdatavalid\r
6446 {\r
6447 type = "readdatavalid";\r
6448 width = "1";\r
6449 direction = "input";\r
6450 Is_Enabled = "1";\r
6451 }\r
6452 PORT master_waitrequest\r
6453 {\r
6454 type = "waitrequest";\r
6455 width = "1";\r
6456 direction = "input";\r
6457 Is_Enabled = "1";\r
6458 }\r
6459 PORT master_byteenable\r
6460 {\r
6461 type = "byteenable";\r
6462 width = "4";\r
6463 direction = "output";\r
6464 Is_Enabled = "1";\r
6465 }\r
6466 PORT master_endofpacket\r
6467 {\r
6468 Is_Enabled = "1";\r
6469 direction = "input";\r
6470 type = "endofpacket";\r
6471 width = "1";\r
6472 }\r
6473 }\r
6474 SYSTEM_BUILDER_INFO \r
6475 {\r
6476 Bus_Type = "avalon";\r
6477 Is_Asynchronous = "0";\r
6478 DBS_Big_Endian = "0";\r
6479 Adapts_To = "";\r
6480 Do_Stream_Reads = "0";\r
6481 Do_Stream_Writes = "0";\r
6482 Max_Address_Width = "32";\r
6483 Data_Width = "32";\r
6484 Address_Width = "25";\r
6485 Opaque_Bridges_To = "s1";\r
6486 Maximum_Burst_Size = "1";\r
6487 Register_Incoming_Signals = "0";\r
6488 Register_Outgoing_Signals = "0";\r
6489 Interleave_Bursts = "0";\r
6490 Linewrap_Bursts = "0";\r
6491 Burst_On_Burst_Boundaries_Only = "0";\r
6492 Always_Burst_Max_Burst = "0";\r
6493 Is_Big_Endian = "0";\r
6494 Is_Enabled = "1";\r
6495 Clock_Source = "ddr_sdram_phy_clk_out";\r
6496 Has_Clock = "1";\r
6497 }\r
6498 MEMORY_MAP \r
6499 {\r
6500 Entry ddr_sdram/s1\r
6501 {\r
6502 address = "0x00000000";\r
6503 span = "0x02000000";\r
6504 is_bridge = "0";\r
6505 }\r
6506 }\r
6507 }\r
6508 class = "altera_avalon_clock_crossing";\r
6509 class_version = "7.08";\r
6510 iss_model_name = "altera_avalon_clock_crossing";\r
6511 WIZARD_SCRIPT_ARGUMENTS \r
6512 {\r
6513 Upstream_FIFO_Depth = "64";\r
6514 Downstream_FIFO_Depth = "16";\r
6515 Data_Width = "32";\r
6516 Native_Address_Width = "23";\r
6517 Use_Byte_Enable = "1";\r
6518 Use_Burst_Count = "0";\r
6519 Maximum_Burst_Size = "8";\r
6520 Upstream_Use_Register = "0";\r
6521 Downstream_Use_Register = "0";\r
6522 Device_Family = "CYCLONEIII";\r
6523 }\r
6524 SYSTEM_BUILDER_INFO \r
6525 {\r
6526 Instantiate_In_System_Module = "1";\r
6527 Is_Enabled = "1";\r
6528 Top_Level_Ports_Are_Enumerated = "1";\r
6529 Has_Clock = "0";\r
6530 Is_Bridge = "1";\r
6531 Clock_Source = "clk";\r
6532 View \r
6533 {\r
6534 MESSAGES \r
6535 {\r
6536 }\r
6537 }\r
6538 }\r
6539 HDL_INFO \r
6540 {\r
6541 Precompiled_Simulation_Library_Files = "";\r
6542 Simulation_HDL_Files = "";\r
6543 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/slow_ddr_clock_bridge.v";\r
6544 Synthesis_Only_Files = "";\r
6545 }\r
6546 PORT_WIRING \r
6547 {\r
6548 }\r
6549 }\r
6550 }\r