| blob | d5fa035f7b96efa26a163aebd4b6574018334bb2 |
1 SYSTEM my_sopc\r
2 {\r
3 System_Wizard_Version = "9.00";\r
4 System_Wizard_Build = "235";\r
5 Builder_Application = "sopc_builder_ca";\r
6 WIZARD_SCRIPT_ARGUMENTS \r
7 {\r
8 hdl_language = "verilog";\r
9 device_family = "CYCLONEIII";\r
10 device_family_id = "CYCLONEIII";\r
11 generate_sdk = "0";\r
12 do_build_sim = "0";\r
13 hardcopy_compatible = "0";\r
14 CLOCKS \r
15 {\r
16 CLOCK ext_clk\r
17 {\r
18 frequency = "16000000";\r
19 source = "External";\r
20 Is_Clock_Source = "0";\r
21 display_name = "ext_clk";\r
22 pipeline = "0";\r
23 clock_module_connection_point_for_c2h = "ext_clk.clk";\r
24 }\r
25 CLOCK main_pll_c0\r
26 {\r
27 frequency = "32000000";\r
28 source = "";\r
29 Is_Clock_Source = "1";\r
30 display_name = "c0 from main_pll";\r
31 pipeline = "0";\r
32 clock_module_connection_point_for_c2h = "main_pll.c0";\r
33 }\r
34 CLOCK sys_clk\r
35 {\r
36 frequency = "32000000";\r
37 source = "main_pll_c0";\r
38 Is_Clock_Source = "0";\r
39 display_name = "sys_clk";\r
40 }\r
41 }\r
42 clock_freq = "16000000";\r
43 clock_freq = "16000000";\r
44 board_class = "";\r
45 view_master_columns = "1";\r
46 view_master_priorities = "0";\r
47 generate_hdl = "";\r
48 bustype_column_width = "0";\r
49 clock_column_width = "80";\r
50 name_column_width = "75";\r
51 desc_column_width = "75";\r
52 base_column_width = "75";\r
53 end_column_width = "75";\r
54 do_log_history = "0";\r
55 }\r
56 MODULE cpu\r
57 {\r
58 MASTER instruction_master\r
59 {\r
60 PORT_WIRING \r
61 {\r
62 PORT clk\r
63 {\r
64 type = "clk";\r
65 width = "1";\r
66 direction = "input";\r
67 Is_Enabled = "0";\r
68 }\r
69 PORT reset_n\r
70 {\r
71 type = "reset_n";\r
72 width = "1";\r
73 direction = "input";\r
74 Is_Enabled = "0";\r
75 }\r
76 PORT i_address\r
77 {\r
78 type = "address";\r
79 width = "21";\r
80 direction = "output";\r
81 Is_Enabled = "1";\r
82 }\r
83 PORT i_read\r
84 {\r
85 type = "read";\r
86 width = "1";\r
87 direction = "output";\r
88 Is_Enabled = "1";\r
89 }\r
90 PORT i_readdata\r
91 {\r
92 type = "readdata";\r
93 width = "32";\r
94 direction = "input";\r
95 Is_Enabled = "1";\r
96 }\r
97 PORT i_readdatavalid\r
98 {\r
99 type = "readdatavalid";\r
100 width = "1";\r
101 direction = "input";\r
102 Is_Enabled = "1";\r
103 }\r
104 PORT i_waitrequest\r
105 {\r
106 type = "waitrequest";\r
107 width = "1";\r
108 direction = "input";\r
109 Is_Enabled = "1";\r
110 }\r
111 }\r
112 SYSTEM_BUILDER_INFO \r
113 {\r
114 Bus_Type = "avalon";\r
115 Is_Asynchronous = "0";\r
116 DBS_Big_Endian = "0";\r
117 Adapts_To = "";\r
118 Do_Stream_Reads = "0";\r
119 Do_Stream_Writes = "0";\r
120 Max_Address_Width = "32";\r
121 Data_Width = "32";\r
122 Address_Width = "21";\r
123 Maximum_Burst_Size = "1";\r
124 Register_Incoming_Signals = "0";\r
125 Register_Outgoing_Signals = "0";\r
126 Interleave_Bursts = "";\r
127 Linewrap_Bursts = "";\r
128 Burst_On_Burst_Boundaries_Only = "";\r
129 Always_Burst_Max_Burst = "";\r
130 Is_Big_Endian = "0";\r
131 Is_Enabled = "1";\r
132 Is_Instruction_Master = "1";\r
133 Is_Readable = "1";\r
134 Is_Writeable = "0";\r
135 Address_Group = "0";\r
136 Has_IRQ = "0";\r
137 Irq_Scheme = "individual_requests";\r
138 Interrupt_Range = "0-0";\r
139 }\r
140 MEMORY_MAP \r
141 {\r
142 Entry cpu/jtag_debug_module\r
143 {\r
144 address = "0x00108800";\r
145 span = "0x00000800";\r
146 is_bridge = "0";\r
147 }\r
148 Entry onchip_ram/s1\r
149 {\r
150 address = "0x00104000";\r
151 span = "0x00004000";\r
152 is_bridge = "0";\r
153 }\r
154 Entry ext_ram/avalon_tristate_slave_0\r
155 {\r
156 address = "0x00080000";\r
157 span = "0x00080000";\r
158 is_bridge = "0";\r
159 }\r
160 }\r
161 }\r
162 MASTER custom_instruction_master\r
163 {\r
164 SYSTEM_BUILDER_INFO \r
165 {\r
166 Bus_Type = "nios_custom_instruction";\r
167 Data_Width = "32";\r
168 Address_Width = "8";\r
169 Is_Custom_Instruction = "1";\r
170 Is_Enabled = "0";\r
171 Max_Address_Width = "8";\r
172 Base_Address = "N/A";\r
173 Is_Visible = "0";\r
174 }\r
175 PORT_WIRING \r
176 {\r
177 PORT dataa\r
178 {\r
179 type = "dataa";\r
180 width = "32";\r
181 direction = "output";\r
182 }\r
183 PORT datab\r
184 {\r
185 type = "datab";\r
186 width = "32";\r
187 direction = "output";\r
188 }\r
189 PORT result\r
190 {\r
191 type = "result";\r
192 width = "32";\r
193 direction = "input";\r
194 }\r
195 PORT clk_en\r
196 {\r
197 type = "clk_en";\r
198 width = "1";\r
199 direction = "output";\r
200 }\r
201 PORT reset\r
202 {\r
203 type = "reset";\r
204 width = "1";\r
205 direction = "output";\r
206 }\r
207 PORT start\r
208 {\r
209 type = "start";\r
210 width = "1";\r
211 direction = "output";\r
212 }\r
213 PORT done\r
214 {\r
215 type = "done";\r
216 width = "1";\r
217 direction = "input";\r
218 }\r
219 PORT n\r
220 {\r
221 type = "n";\r
222 width = "8";\r
223 direction = "output";\r
224 }\r
225 PORT a\r
226 {\r
227 type = "a";\r
228 width = "5";\r
229 direction = "output";\r
230 }\r
231 PORT b\r
232 {\r
233 type = "b";\r
234 width = "5";\r
235 direction = "output";\r
236 }\r
237 PORT c\r
238 {\r
239 type = "c";\r
240 width = "5";\r
241 direction = "output";\r
242 }\r
243 PORT readra\r
244 {\r
245 type = "readra";\r
246 width = "1";\r
247 direction = "output";\r
248 }\r
249 PORT readrb\r
250 {\r
251 type = "readrb";\r
252 width = "1";\r
253 direction = "output";\r
254 }\r
255 PORT writerc\r
256 {\r
257 type = "writerc";\r
258 width = "1";\r
259 direction = "output";\r
260 }\r
261 }\r
262 }\r
263 SLAVE jtag_debug_module\r
264 {\r
265 SYSTEM_BUILDER_INFO \r
266 {\r
267 Bus_Type = "avalon";\r
268 Write_Wait_States = "0cycles";\r
269 Read_Wait_States = "1cycles";\r
270 Hold_Time = "0cycles";\r
271 Setup_Time = "0cycles";\r
272 Is_Printable_Device = "0";\r
273 Address_Alignment = "dynamic";\r
274 Well_Behaved_Waitrequest = "0";\r
275 Is_Nonvolatile_Storage = "0";\r
276 Address_Span = "2048";\r
277 Read_Latency = "0";\r
278 Is_Memory_Device = "1";\r
279 Maximum_Pending_Read_Transactions = "0";\r
280 Minimum_Uninterrupted_Run_Length = "1";\r
281 Accepts_Internal_Connections = "1";\r
282 Write_Latency = "0";\r
283 Is_Flash = "0";\r
284 Data_Width = "32";\r
285 Address_Width = "9";\r
286 Maximum_Burst_Size = "1";\r
287 Register_Incoming_Signals = "0";\r
288 Register_Outgoing_Signals = "0";\r
289 Interleave_Bursts = "0";\r
290 Linewrap_Bursts = "0";\r
291 Burst_On_Burst_Boundaries_Only = "0";\r
292 Always_Burst_Max_Burst = "0";\r
293 Is_Big_Endian = "0";\r
294 Is_Enabled = "1";\r
295 Accepts_External_Connections = "1";\r
296 Requires_Internal_Connections = "";\r
297 MASTERED_BY cpu/instruction_master\r
298 {\r
299 priority = "1";\r
300 Offset_Address = "0x00108800";\r
301 }\r
302 MASTERED_BY cpu/data_master\r
303 {\r
304 priority = "1";\r
305 Offset_Address = "0x00108800";\r
306 }\r
307 Base_Address = "0x00108800";\r
308 Is_Readable = "1";\r
309 Is_Writeable = "1";\r
310 Uses_Tri_State_Data_Bus = "0";\r
311 Has_IRQ = "0";\r
312 JTAG_Hub_Base_Id = "1118278";\r
313 JTAG_Hub_Instance_Id = "0";\r
314 Address_Group = "0";\r
315 IRQ_MASTER cpu/data_master\r
316 {\r
317 IRQ_Number = "NC";\r
318 }\r
319 }\r
320 PORT_WIRING \r
321 {\r
322 PORT jtag_debug_module_address\r
323 {\r
324 type = "address";\r
325 width = "9";\r
326 direction = "input";\r
327 Is_Enabled = "1";\r
328 }\r
329 PORT jtag_debug_module_begintransfer\r
330 {\r
331 type = "begintransfer";\r
332 width = "1";\r
333 direction = "input";\r
334 Is_Enabled = "1";\r
335 }\r
336 PORT jtag_debug_module_byteenable\r
337 {\r
338 type = "byteenable";\r
339 width = "4";\r
340 direction = "input";\r
341 Is_Enabled = "1";\r
342 }\r
343 PORT jtag_debug_module_debugaccess\r
344 {\r
345 type = "debugaccess";\r
346 width = "1";\r
347 direction = "input";\r
348 Is_Enabled = "1";\r
349 }\r
350 PORT jtag_debug_module_readdata\r
351 {\r
352 type = "readdata";\r
353 width = "32";\r
354 direction = "output";\r
355 Is_Enabled = "1";\r
356 }\r
357 PORT jtag_debug_module_resetrequest\r
358 {\r
359 type = "resetrequest";\r
360 width = "1";\r
361 direction = "output";\r
362 Is_Enabled = "1";\r
363 }\r
364 PORT jtag_debug_module_select\r
365 {\r
366 type = "chipselect";\r
367 width = "1";\r
368 direction = "input";\r
369 Is_Enabled = "1";\r
370 }\r
371 PORT jtag_debug_module_write\r
372 {\r
373 type = "write";\r
374 width = "1";\r
375 direction = "input";\r
376 Is_Enabled = "1";\r
377 }\r
378 PORT jtag_debug_module_writedata\r
379 {\r
380 type = "writedata";\r
381 width = "32";\r
382 direction = "input";\r
383 Is_Enabled = "1";\r
384 }\r
385 PORT jtag_debug_module_clk\r
386 {\r
387 Is_Enabled = "1";\r
388 direction = "input";\r
389 type = "clk";\r
390 width = "1";\r
391 }\r
392 PORT jtag_debug_module_reset\r
393 {\r
394 Is_Enabled = "1";\r
395 direction = "input";\r
396 type = "reset";\r
397 width = "1";\r
398 }\r
399 PORT reset_n\r
400 {\r
401 Is_Enabled = "1";\r
402 direction = "input";\r
403 type = "reset_n";\r
404 width = "1";\r
405 }\r
406 }\r
407 }\r
408 MASTER data_master\r
409 {\r
410 SYSTEM_BUILDER_INFO \r
411 {\r
412 Has_IRQ = "1";\r
413 Irq_Scheme = "individual_requests";\r
414 Bus_Type = "avalon";\r
415 Is_Asynchronous = "0";\r
416 DBS_Big_Endian = "0";\r
417 Adapts_To = "";\r
418 Do_Stream_Reads = "0";\r
419 Do_Stream_Writes = "0";\r
420 Max_Address_Width = "32";\r
421 Data_Width = "32";\r
422 Address_Width = "21";\r
423 Maximum_Burst_Size = "1";\r
424 Register_Incoming_Signals = "1";\r
425 Register_Outgoing_Signals = "0";\r
426 Interleave_Bursts = "0";\r
427 Linewrap_Bursts = "0";\r
428 Burst_On_Burst_Boundaries_Only = "";\r
429 Always_Burst_Max_Burst = "0";\r
430 Is_Big_Endian = "0";\r
431 Is_Enabled = "1";\r
432 Is_Data_Master = "1";\r
433 Address_Group = "0";\r
434 Is_Readable = "1";\r
435 Is_Writeable = "1";\r
436 Interrupt_Range = "0-31";\r
437 }\r
438 PORT_WIRING \r
439 {\r
440 PORT d_irq\r
441 {\r
442 type = "irq";\r
443 width = "32";\r
444 direction = "input";\r
445 Is_Enabled = "1";\r
446 }\r
447 PORT d_address\r
448 {\r
449 type = "address";\r
450 width = "21";\r
451 direction = "output";\r
452 Is_Enabled = "1";\r
453 }\r
454 PORT d_byteenable\r
455 {\r
456 type = "byteenable";\r
457 width = "4";\r
458 direction = "output";\r
459 Is_Enabled = "1";\r
460 }\r
461 PORT d_read\r
462 {\r
463 type = "read";\r
464 width = "1";\r
465 direction = "output";\r
466 Is_Enabled = "1";\r
467 }\r
468 PORT d_readdata\r
469 {\r
470 type = "readdata";\r
471 width = "32";\r
472 direction = "input";\r
473 Is_Enabled = "1";\r
474 }\r
475 PORT d_readdatavalid\r
476 {\r
477 type = "readdatavalid";\r
478 width = "1";\r
479 direction = "input";\r
480 Is_Enabled = "0";\r
481 }\r
482 PORT d_waitrequest\r
483 {\r
484 type = "waitrequest";\r
485 width = "1";\r
486 direction = "input";\r
487 Is_Enabled = "1";\r
488 }\r
489 PORT d_write\r
490 {\r
491 type = "write";\r
492 width = "1";\r
493 direction = "output";\r
494 Is_Enabled = "1";\r
495 }\r
496 PORT d_writedata\r
497 {\r
498 type = "writedata";\r
499 width = "32";\r
500 direction = "output";\r
501 Is_Enabled = "1";\r
502 }\r
503 PORT jtag_debug_module_debugaccess_to_roms\r
504 {\r
505 type = "debugaccess";\r
506 width = "1";\r
507 direction = "output";\r
508 Is_Enabled = "1";\r
509 }\r
510 PORT clk\r
511 {\r
512 Is_Enabled = "1";\r
513 direction = "input";\r
514 type = "clk";\r
515 width = "1";\r
516 }\r
517 }\r
518 MEMORY_MAP \r
519 {\r
520 Entry cpu/jtag_debug_module\r
521 {\r
522 address = "0x00108800";\r
523 span = "0x00000800";\r
524 is_bridge = "0";\r
525 }\r
526 Entry jtag_uart/avalon_jtag_slave\r
527 {\r
528 address = "0x00109030";\r
529 span = "0x00000008";\r
530 is_bridge = "0";\r
531 }\r
532 Entry onchip_ram/s1\r
533 {\r
534 address = "0x00104000";\r
535 span = "0x00004000";\r
536 is_bridge = "0";\r
537 }\r
538 Entry led/s1\r
539 {\r
540 address = "0x00109020";\r
541 span = "0x00000010";\r
542 is_bridge = "0";\r
543 }\r
544 Entry ext_ram/avalon_tristate_slave_0\r
545 {\r
546 address = "0x00080000";\r
547 span = "0x00080000";\r
548 is_bridge = "0";\r
549 }\r
550 Entry main_pll/s1\r
551 {\r
552 address = "0x00109000";\r
553 span = "0x00000020";\r
554 is_bridge = "0";\r
555 }\r
556 Entry sys_clk_timer/s1\r
557 {\r
558 address = "0x00000000";\r
559 span = "0x00000020";\r
560 is_bridge = "0";\r
561 }\r
562 }\r
563 }\r
564 WIZARD_SCRIPT_ARGUMENTS \r
565 {\r
566 cache_has_dcache = "0";\r
567 cache_dcache_size = "0";\r
568 cache_dcache_line_size = "0";\r
569 cache_dcache_bursts = "0";\r
570 cache_dcache_ram_block_type = "AUTO";\r
571 num_tightly_coupled_data_masters = "0";\r
572 gui_num_tightly_coupled_data_masters = "0";\r
573 gui_include_tightly_coupled_data_masters = "0";\r
574 gui_omit_avalon_data_master = "0";\r
575 cache_has_icache = "1";\r
576 cache_icache_size = "4096";\r
577 cache_icache_line_size = "32";\r
578 cache_icache_ram_block_type = "AUTO";\r
579 cache_icache_bursts = "0";\r
580 num_tightly_coupled_instruction_masters = "0";\r
581 gui_num_tightly_coupled_instruction_masters = "0";\r
582 gui_include_tightly_coupled_instruction_masters = "0";\r
583 debug_level = "2";\r
584 include_oci = "1";\r
585 oci_num_xbrk = "0";\r
586 oci_num_dbrk = "0";\r
587 oci_dbrk_trace = "0";\r
588 oci_dbrk_pairs = "0";\r
589 oci_onchip_trace = "0";\r
590 oci_offchip_trace = "0";\r
591 oci_data_trace = "0";\r
592 include_third_party_debug_port = "0";\r
593 oci_trace_addr_width = "7";\r
594 oci_debugreq_signals = "0";\r
595 oci_trigger_arming = "1";\r
596 oci_embedded_pll = "0";\r
597 oci_assign_jtag_instance_id = "0";\r
598 oci_jtag_instance_id = "0";\r
599 oci_num_pm = "0";\r
600 oci_pm_width = "32";\r
601 performance_counters_present = "0";\r
602 performance_counters_width = "32";\r
603 always_encrypt = "1";\r
604 debug_simgen = "0";\r
605 activate_model_checker = "0";\r
606 activate_test_end_checker = "0";\r
607 activate_trace = "1";\r
608 activate_monitors = "1";\r
609 clear_x_bits_ld_non_bypass = "1";\r
610 bit_31_bypass_dcache = "1";\r
611 hdl_sim_caches_cleared = "1";\r
612 hbreak_test = "0";\r
613 allow_full_address_range = "0";\r
614 extra_exc_info = "0";\r
615 branch_prediction_type = "Static";\r
616 bht_ptr_sz = "8";\r
617 bht_index_pc_only = "0";\r
618 gui_branch_prediction_type = "Automatic";\r
619 full_waveform_signals = "0";\r
620 export_pcb = "0";\r
621 avalon_debug_port_present = "0";\r
622 illegal_instructions_trap = "0";\r
623 illegal_memory_access_detection = "0";\r
624 illegal_mem_exc = "0";\r
625 slave_access_error_exc = "0";\r
626 division_error_exc = "0";\r
627 eic_present = "0";\r
628 num_shadow_reg_sets = "0";\r
629 gui_mmu_present = "0";\r
630 mmu_present = "0";\r
631 process_id_num_bits = "8";\r
632 tlb_ptr_sz = "7";\r
633 tlb_num_ways = "16";\r
634 udtlb_num_entries = "6";\r
635 uitlb_num_entries = "4";\r
636 fast_tlb_miss_exc_slave = "";\r
637 fast_tlb_miss_exc_offset = "0x00000000";\r
638 mpu_present = "0";\r
639 mpu_num_data_regions = "8";\r
640 mpu_num_inst_regions = "8";\r
641 mpu_min_data_region_size_log2 = "12";\r
642 mpu_min_inst_region_size_log2 = "12";\r
643 mpu_use_limit = "0";\r
644 hardware_divide_present = "0";\r
645 gui_hardware_divide_setting = "0";\r
646 hardware_multiply_present = "1";\r
647 hardware_multiply_impl = "embedded_mul";\r
648 shift_rot_impl = "fast_le_shift";\r
649 gui_hardware_multiply_setting = "embedded_mul_fast_le_shift";\r
650 reset_slave = "ext_ram/avalon_tristate_slave_0";\r
651 break_slave = "cpu/jtag_debug_module";\r
652 exc_slave = "ext_ram/avalon_tristate_slave_0";\r
653 reset_offset = "0x00000000";\r
654 break_offset = "0x00000020";\r
655 exc_offset = "0x00000020";\r
656 cpu_reset = "0";\r
657 CPU_Implementation = "small";\r
658 cpu_selection = "s";\r
659 device_family_id = "CYCLONEIII";\r
660 address_stall_present = "1";\r
661 dsp_block_supports_shift = "0";\r
662 mrams_present = "0";\r
663 cpuid_value = "0";\r
664 dont_overwrite_cpuid = "1";\r
665 allow_legacy_sdk = "1";\r
666 legacy_sdk_support = "1";\r
667 inst_addr_width = "21";\r
668 data_addr_width = "21";\r
669 CPU_Architecture = "nios2";\r
670 cache_icache_burst_type = "none";\r
671 oci_sync_depth = "2";\r
672 hardware_multiply_omits_msw = "1";\r
673 big_endian = "0";\r
674 break_slave_override = "";\r
675 break_offset_override = "0x20";\r
676 altera_show_unreleased_features = "0";\r
677 altera_show_unpublished_features = "0";\r
678 altera_internal_test = "0";\r
679 alt_log_port_base = "";\r
680 alt_log_port_type = "";\r
681 cpuid_sz = "1";\r
682 gui_illegal_instructions_trap = "0";\r
683 advanced_exc = "0";\r
684 gui_illegal_memory_access_detection = "0";\r
685 cache_omit_dcache = "0";\r
686 cache_omit_icache = "0";\r
687 omit_instruction_master = "0";\r
688 omit_data_master = "0";\r
689 ras_ptr_sz = "4";\r
690 jtb_ptr_sz = "5";\r
691 ibuf_ptr_sz = "4";\r
692 always_bypass_dcache = "0";\r
693 iss_trace_on = "0";\r
694 iss_trace_warning = "1";\r
695 iss_trace_info = "1";\r
696 iss_trace_disassembly = "0";\r
697 iss_trace_registers = "0";\r
698 iss_trace_instr_count = "0";\r
699 iss_software_debug = "0";\r
700 iss_software_debug_port = "9996";\r
701 iss_memory_dump_start = "";\r
702 iss_memory_dump_end = "";\r
703 Boot_Copier = "boot_loader_cfi.srec";\r
704 Boot_Copier_EPCS = "boot_loader_epcs.srec";\r
705 Boot_Copier_EPCS_SII_SIII_CIII = "boot_loader_epcs_sii_siii_ciii.srec";\r
706 Boot_Copier_BE = "boot_loader_cfi_be.srec";\r
707 Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec";\r
708 Boot_Copier_EPCS_SII_SIII_CIII_BE = "boot_loader_epcs_sii_siii_ciii_be.srec";\r
709 CONSTANTS \r
710 {\r
711 CONSTANT __nios_catch_irqs__\r
712 {\r
713 value = "1";\r
714 comment = "Include panic handler for all irqs (needs uart)";\r
715 }\r
716 CONSTANT __nios_use_constructors__\r
717 {\r
718 value = "1";\r
719 comment = "Call c++ static constructors";\r
720 }\r
721 CONSTANT __nios_use_small_printf__\r
722 {\r
723 value = "1";\r
724 comment = "Smaller non-ANSI printf, with no floating point";\r
725 }\r
726 CONSTANT nasys_has_icache\r
727 {\r
728 value = "1";\r
729 comment = "True if instruction cache present";\r
730 }\r
731 CONSTANT nasys_icache_size\r
732 {\r
733 value = "4096";\r
734 comment = "Size in bytes of instruction cache";\r
735 }\r
736 CONSTANT nasys_icache_line_size\r
737 {\r
738 value = "32";\r
739 comment = "Size in bytes of each icache line";\r
740 }\r
741 CONSTANT nasys_icache_line_size_log2\r
742 {\r
743 value = "5";\r
744 comment = "Log2 size in bytes of each icache line";\r
745 }\r
746 CONSTANT nasys_has_dcache\r
747 {\r
748 value = "0";\r
749 comment = "True if instruction cache present";\r
750 }\r
751 CONSTANT nasys_dcache_size\r
752 {\r
753 value = "0";\r
754 comment = "Size in bytes of data cache";\r
755 }\r
756 CONSTANT nasys_dcache_line_size\r
757 {\r
758 value = "0";\r
759 comment = "Size in bytes of each dcache line";\r
760 }\r
761 CONSTANT nasys_dcache_line_size_log2\r
762 {\r
763 value = "-Infinity";\r
764 comment = "Log2 size in bytes of each dcache line";\r
765 }\r
766 }\r
767 license_status = "encrypted";\r
768 mainmem_slave = "ext_ram/avalon_tristate_slave_0";\r
769 datamem_slave = "ext_ram/avalon_tristate_slave_0";\r
770 maincomm_slave = "ext_ram/avalon_tristate_slave_0";\r
771 germs_monitor_id = "";\r
772 }\r
773 class = "altera_nios2";\r
774 class_version = "7.080902";\r
775 SYSTEM_BUILDER_INFO \r
776 {\r
777 Is_Enabled = "1";\r
778 Clock_Source = "sys_clk";\r
779 Has_Clock = "1";\r
780 Parameters_Signature = "";\r
781 Is_CPU = "1";\r
782 Instantiate_In_System_Module = "1";\r
783 Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIIGXLITE,STRATIXIII,STRATIXIV,CYCLONE,CYCLONEII,CYCLONEIII,HARDCOPYIII,ARRIAII,TARPON,HARDCOPYIV";\r
784 Default_Module_Name = "cpu";\r
785 Top_Level_Ports_Are_Enumerated = "1";\r
786 View \r
787 {\r
788 Settings_Summary = "Nios II/s
789 <br> 4-Kbyte Instruction Cache
791 <br> JTAG Debug Module
792 ";\r
793 MESSAGES \r
794 {\r
795 }\r
796 }\r
797 }\r
798 iss_model_name = "altera_nios2";\r
799 HDL_INFO \r
800 {\r
801 PLI_Files = "";\r
802 Precompiled_Simulation_Library_Files = "";\r
803 Simulation_HDL_Files = "";\r
804 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_test_bench.v, __PROJECT_DIRECTORY__/cpu_mult_cell.v, __PROJECT_DIRECTORY__/cpu_oci_test_bench.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_tck.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_sysclk.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/cpu.v";\r
805 Synthesis_Only_Files = "";\r
806 }\r
807 MASTER tightly_coupled_instruction_master_0\r
808 {\r
809 PORT_WIRING \r
810 {\r
811 }\r
812 SYSTEM_BUILDER_INFO \r
813 {\r
814 Register_Incoming_Signals = "0";\r
815 Bus_Type = "avalon";\r
816 Data_Width = "32";\r
817 Max_Address_Width = "31";\r
818 Address_Width = "8";\r
819 Is_Instruction_Master = "1";\r
820 Has_IRQ = "0";\r
821 Is_Enabled = "0";\r
822 Is_Big_Endian = "0";\r
823 Connection_Limit = "1";\r
824 Is_Channel = "1";\r
825 }\r
826 }\r
827 MASTER tightly_coupled_instruction_master_1\r
828 {\r
829 PORT_WIRING \r
830 {\r
831 }\r
832 SYSTEM_BUILDER_INFO \r
833 {\r
834 Register_Incoming_Signals = "0";\r
835 Bus_Type = "avalon";\r
836 Data_Width = "32";\r
837 Max_Address_Width = "31";\r
838 Address_Width = "8";\r
839 Address_Group = "0";\r
840 Is_Instruction_Master = "1";\r
841 Is_Readable = "1";\r
842 Is_Writeable = "0";\r
843 Has_IRQ = "0";\r
844 Is_Enabled = "0";\r
845 Is_Big_Endian = "0";\r
846 Connection_Limit = "1";\r
847 Is_Channel = "1";\r
848 }\r
849 }\r
850 MASTER tightly_coupled_instruction_master_2\r
851 {\r
852 PORT_WIRING \r
853 {\r
854 }\r
855 SYSTEM_BUILDER_INFO \r
856 {\r
857 Register_Incoming_Signals = "0";\r
858 Bus_Type = "avalon";\r
859 Data_Width = "32";\r
860 Max_Address_Width = "31";\r
861 Address_Width = "8";\r
862 Address_Group = "0";\r
863 Is_Instruction_Master = "1";\r
864 Is_Readable = "1";\r
865 Is_Writeable = "0";\r
866 Has_IRQ = "0";\r
867 Is_Enabled = "0";\r
868 Is_Big_Endian = "0";\r
869 Connection_Limit = "1";\r
870 Is_Channel = "1";\r
871 }\r
872 }\r
873 MASTER tightly_coupled_instruction_master_3\r
874 {\r
875 PORT_WIRING \r
876 {\r
877 }\r
878 SYSTEM_BUILDER_INFO \r
879 {\r
880 Register_Incoming_Signals = "0";\r
881 Bus_Type = "avalon";\r
882 Data_Width = "32";\r
883 Max_Address_Width = "31";\r
884 Address_Width = "8";\r
885 Address_Group = "0";\r
886 Is_Instruction_Master = "1";\r
887 Is_Readable = "1";\r
888 Is_Writeable = "0";\r
889 Has_IRQ = "0";\r
890 Is_Enabled = "0";\r
891 Is_Big_Endian = "0";\r
892 Connection_Limit = "1";\r
893 Is_Channel = "1";\r
894 }\r
895 }\r
896 MASTER data_master2\r
897 {\r
898 PORT_WIRING \r
899 {\r
900 }\r
901 SYSTEM_BUILDER_INFO \r
902 {\r
903 Register_Incoming_Signals = "1";\r
904 Bus_Type = "avalon";\r
905 Data_Width = "32";\r
906 Max_Address_Width = "31";\r
907 Address_Width = "8";\r
908 Address_Group = "0";\r
909 Is_Data_Master = "1";\r
910 Is_Readable = "1";\r
911 Is_Writeable = "1";\r
912 Has_IRQ = "0";\r
913 Is_Enabled = "0";\r
914 Is_Big_Endian = "0";\r
915 }\r
916 }\r
917 MASTER tightly_coupled_data_master_0\r
918 {\r
919 PORT_WIRING \r
920 {\r
921 }\r
922 SYSTEM_BUILDER_INFO \r
923 {\r
924 Register_Incoming_Signals = "0";\r
925 Bus_Type = "avalon";\r
926 Data_Width = "32";\r
927 Max_Address_Width = "31";\r
928 Address_Width = "8";\r
929 Address_Group = "0";\r
930 Is_Data_Master = "1";\r
931 Is_Readable = "1";\r
932 Is_Writeable = "1";\r
933 Has_IRQ = "0";\r
934 Is_Enabled = "0";\r
935 Is_Big_Endian = "0";\r
936 Connection_Limit = "1";\r
937 Is_Channel = "1";\r
938 }\r
939 }\r
940 MASTER tightly_coupled_data_master_1\r
941 {\r
942 PORT_WIRING \r
943 {\r
944 }\r
945 SYSTEM_BUILDER_INFO \r
946 {\r
947 Register_Incoming_Signals = "0";\r
948 Bus_Type = "avalon";\r
949 Data_Width = "32";\r
950 Max_Address_Width = "31";\r
951 Address_Width = "8";\r
952 Address_Group = "0";\r
953 Is_Data_Master = "1";\r
954 Is_Readable = "1";\r
955 Is_Writeable = "1";\r
956 Has_IRQ = "0";\r
957 Is_Enabled = "0";\r
958 Is_Big_Endian = "0";\r
959 Connection_Limit = "1";\r
960 Is_Channel = "1";\r
961 }\r
962 }\r
963 MASTER tightly_coupled_data_master_2\r
964 {\r
965 PORT_WIRING \r
966 {\r
967 }\r
968 SYSTEM_BUILDER_INFO \r
969 {\r
970 Register_Incoming_Signals = "0";\r
971 Bus_Type = "avalon";\r
972 Data_Width = "32";\r
973 Max_Address_Width = "31";\r
974 Address_Width = "8";\r
975 Address_Group = "0";\r
976 Is_Data_Master = "1";\r
977 Is_Readable = "1";\r
978 Is_Writeable = "1";\r
979 Has_IRQ = "0";\r
980 Is_Enabled = "0";\r
981 Is_Big_Endian = "0";\r
982 Connection_Limit = "1";\r
983 Is_Channel = "1";\r
984 }\r
985 }\r
986 MASTER tightly_coupled_data_master_3\r
987 {\r
988 PORT_WIRING \r
989 {\r
990 }\r
991 SYSTEM_BUILDER_INFO \r
992 {\r
993 Register_Incoming_Signals = "0";\r
994 Bus_Type = "avalon";\r
995 Data_Width = "32";\r
996 Max_Address_Width = "31";\r
997 Address_Width = "8";\r
998 Address_Group = "0";\r
999 Is_Data_Master = "1";\r
1000 Is_Readable = "1";\r
1001 Is_Writeable = "1";\r
1002 Has_IRQ = "0";\r
1003 Is_Enabled = "0";\r
1004 Is_Big_Endian = "0";\r
1005 Connection_Limit = "1";\r
1006 Is_Channel = "1";\r
1007 }\r
1008 }\r
1009 PORT_WIRING \r
1010 {\r
1011 PORT jtag_debug_trigout\r
1012 {\r
1013 width = "1";\r
1014 direction = "output";\r
1015 Is_Enabled = "0";\r
1016 }\r
1017 PORT jtag_debug_offchip_trace_clk\r
1018 {\r
1019 width = "1";\r
1020 direction = "output";\r
1021 Is_Enabled = "0";\r
1022 }\r
1023 PORT jtag_debug_offchip_trace_data\r
1024 {\r
1025 width = "18";\r
1026 direction = "output";\r
1027 Is_Enabled = "0";\r
1028 }\r
1029 PORT clkx2\r
1030 {\r
1031 width = "1";\r
1032 direction = "input";\r
1033 Is_Enabled = "0";\r
1034 visible = "0";\r
1035 }\r
1036 }\r
1037 SIMULATION \r
1038 {\r
1039 DISPLAY \r
1040 {\r
1041 SIGNAL aaa\r
1042 {\r
1043 format = "Logic";\r
1044 name = "i_readdata";\r
1045 radix = "hexadecimal";\r
1046 }\r
1047 SIGNAL aab\r
1048 {\r
1049 format = "Logic";\r
1050 name = "i_readdatavalid";\r
1051 radix = "hexadecimal";\r
1052 }\r
1053 SIGNAL aac\r
1054 {\r
1055 format = "Logic";\r
1056 name = "i_waitrequest";\r
1057 radix = "hexadecimal";\r
1058 }\r
1059 SIGNAL aad\r
1060 {\r
1061 format = "Logic";\r
1062 name = "i_address";\r
1063 radix = "hexadecimal";\r
1064 }\r
1065 SIGNAL aae\r
1066 {\r
1067 format = "Logic";\r
1068 name = "i_read";\r
1069 radix = "hexadecimal";\r
1070 }\r
1071 SIGNAL aaf\r
1072 {\r
1073 format = "Logic";\r
1074 name = "clk";\r
1075 radix = "hexadecimal";\r
1076 }\r
1077 SIGNAL aag\r
1078 {\r
1079 format = "Logic";\r
1080 name = "reset_n";\r
1081 radix = "hexadecimal";\r
1082 }\r
1083 SIGNAL aah\r
1084 {\r
1085 format = "Logic";\r
1086 name = "d_readdata";\r
1087 radix = "hexadecimal";\r
1088 }\r
1089 SIGNAL aai\r
1090 {\r
1091 format = "Logic";\r
1092 name = "d_waitrequest";\r
1093 radix = "hexadecimal";\r
1094 }\r
1095 SIGNAL aaj\r
1096 {\r
1097 format = "Logic";\r
1098 name = "d_irq";\r
1099 radix = "hexadecimal";\r
1100 }\r
1101 SIGNAL aak\r
1102 {\r
1103 format = "Logic";\r
1104 name = "d_address";\r
1105 radix = "hexadecimal";\r
1106 }\r
1107 SIGNAL aal\r
1108 {\r
1109 format = "Logic";\r
1110 name = "d_byteenable";\r
1111 radix = "hexadecimal";\r
1112 }\r
1113 SIGNAL aam\r
1114 {\r
1115 format = "Logic";\r
1116 name = "d_read";\r
1117 radix = "hexadecimal";\r
1118 }\r
1119 SIGNAL aan\r
1120 {\r
1121 format = "Logic";\r
1122 name = "d_write";\r
1123 radix = "hexadecimal";\r
1124 }\r
1125 SIGNAL aao\r
1126 {\r
1127 format = "Logic";\r
1128 name = "d_writedata";\r
1129 radix = "hexadecimal";\r
1130 }\r
1131 SIGNAL aap\r
1132 {\r
1133 format = "Divider";\r
1134 name = "base pipeline";\r
1135 radix = "";\r
1136 }\r
1137 SIGNAL aaq\r
1138 {\r
1139 format = "Logic";\r
1140 name = "clk";\r
1141 radix = "hexadecimal";\r
1142 }\r
1143 SIGNAL aar\r
1144 {\r
1145 format = "Logic";\r
1146 name = "reset_n";\r
1147 radix = "hexadecimal";\r
1148 }\r
1149 SIGNAL aas\r
1150 {\r
1151 format = "Logic";\r
1152 name = "M_stall";\r
1153 radix = "hexadecimal";\r
1154 }\r
1155 SIGNAL aat\r
1156 {\r
1157 format = "Logic";\r
1158 name = "F_pcb_nxt";\r
1159 radix = "hexadecimal";\r
1160 }\r
1161 SIGNAL aau\r
1162 {\r
1163 format = "Logic";\r
1164 name = "F_pcb";\r
1165 radix = "hexadecimal";\r
1166 }\r
1167 SIGNAL aav\r
1168 {\r
1169 format = "Logic";\r
1170 name = "D_pcb";\r
1171 radix = "hexadecimal";\r
1172 }\r
1173 SIGNAL aaw\r
1174 {\r
1175 format = "Logic";\r
1176 name = "E_pcb";\r
1177 radix = "hexadecimal";\r
1178 }\r
1179 SIGNAL aax\r
1180 {\r
1181 format = "Logic";\r
1182 name = "M_pcb";\r
1183 radix = "hexadecimal";\r
1184 }\r
1185 SIGNAL aay\r
1186 {\r
1187 format = "Logic";\r
1188 name = "W_pcb";\r
1189 radix = "hexadecimal";\r
1190 }\r
1191 SIGNAL aaz\r
1192 {\r
1193 format = "Logic";\r
1194 name = "F_vinst";\r
1195 radix = "ascii";\r
1196 }\r
1197 SIGNAL aba\r
1198 {\r
1199 format = "Logic";\r
1200 name = "D_vinst";\r
1201 radix = "ascii";\r
1202 }\r
1203 SIGNAL abb\r
1204 {\r
1205 format = "Logic";\r
1206 name = "E_vinst";\r
1207 radix = "ascii";\r
1208 }\r
1209 SIGNAL abc\r
1210 {\r
1211 format = "Logic";\r
1212 name = "M_vinst";\r
1213 radix = "ascii";\r
1214 }\r
1215 SIGNAL abd\r
1216 {\r
1217 format = "Logic";\r
1218 name = "W_vinst";\r
1219 radix = "ascii";\r
1220 }\r
1221 SIGNAL abe\r
1222 {\r
1223 format = "Logic";\r
1224 name = "F_inst_ram_hit";\r
1225 radix = "hexadecimal";\r
1226 }\r
1227 SIGNAL abf\r
1228 {\r
1229 format = "Logic";\r
1230 name = "F_issue";\r
1231 radix = "hexadecimal";\r
1232 }\r
1233 SIGNAL abg\r
1234 {\r
1235 format = "Logic";\r
1236 name = "F_kill";\r
1237 radix = "hexadecimal";\r
1238 }\r
1239 SIGNAL abh\r
1240 {\r
1241 format = "Logic";\r
1242 name = "D_kill";\r
1243 radix = "hexadecimal";\r
1244 }\r
1245 SIGNAL abi\r
1246 {\r
1247 format = "Logic";\r
1248 name = "D_refetch";\r
1249 radix = "hexadecimal";\r
1250 }\r
1251 SIGNAL abj\r
1252 {\r
1253 format = "Logic";\r
1254 name = "D_issue";\r
1255 radix = "hexadecimal";\r
1256 }\r
1257 SIGNAL abk\r
1258 {\r
1259 format = "Logic";\r
1260 name = "D_valid";\r
1261 radix = "hexadecimal";\r
1262 }\r
1263 SIGNAL abl\r
1264 {\r
1265 format = "Logic";\r
1266 name = "E_valid";\r
1267 radix = "hexadecimal";\r
1268 }\r
1269 SIGNAL abm\r
1270 {\r
1271 format = "Logic";\r
1272 name = "M_valid";\r
1273 radix = "hexadecimal";\r
1274 }\r
1275 SIGNAL abn\r
1276 {\r
1277 format = "Logic";\r
1278 name = "W_valid";\r
1279 radix = "hexadecimal";\r
1280 }\r
1281 SIGNAL abo\r
1282 {\r
1283 format = "Logic";\r
1284 name = "W_wr_dst_reg";\r
1285 radix = "hexadecimal";\r
1286 }\r
1287 SIGNAL abp\r
1288 {\r
1289 format = "Logic";\r
1290 name = "W_dst_regnum";\r
1291 radix = "hexadecimal";\r
1292 }\r
1293 SIGNAL abq\r
1294 {\r
1295 format = "Logic";\r
1296 name = "W_wr_data";\r
1297 radix = "hexadecimal";\r
1298 }\r
1299 SIGNAL abr\r
1300 {\r
1301 format = "Logic";\r
1302 name = "F_en";\r
1303 radix = "hexadecimal";\r
1304 }\r
1305 SIGNAL abs\r
1306 {\r
1307 format = "Logic";\r
1308 name = "D_en";\r
1309 radix = "hexadecimal";\r
1310 }\r
1311 SIGNAL abt\r
1312 {\r
1313 format = "Logic";\r
1314 name = "E_en";\r
1315 radix = "hexadecimal";\r
1316 }\r
1317 SIGNAL abu\r
1318 {\r
1319 format = "Logic";\r
1320 name = "M_en";\r
1321 radix = "hexadecimal";\r
1322 }\r
1323 SIGNAL abv\r
1324 {\r
1325 format = "Logic";\r
1326 name = "F_iw";\r
1327 radix = "hexadecimal";\r
1328 }\r
1329 SIGNAL abw\r
1330 {\r
1331 format = "Logic";\r
1332 name = "D_iw";\r
1333 radix = "hexadecimal";\r
1334 }\r
1335 SIGNAL abx\r
1336 {\r
1337 format = "Logic";\r
1338 name = "E_iw";\r
1339 radix = "hexadecimal";\r
1340 }\r
1341 SIGNAL aby\r
1342 {\r
1343 format = "Logic";\r
1344 name = "E_valid_prior_to_hbreak";\r
1345 radix = "hexadecimal";\r
1346 }\r
1347 SIGNAL abz\r
1348 {\r
1349 format = "Logic";\r
1350 name = "M_pipe_flush_nxt";\r
1351 radix = "hexadecimal";\r
1352 }\r
1353 SIGNAL aca\r
1354 {\r
1355 format = "Logic";\r
1356 name = "M_pipe_flush_baddr_nxt";\r
1357 radix = "hexadecimal";\r
1358 }\r
1359 SIGNAL acb\r
1360 {\r
1361 format = "Logic";\r
1362 name = "M_status_reg_pie";\r
1363 radix = "hexadecimal";\r
1364 }\r
1365 SIGNAL acc\r
1366 {\r
1367 format = "Logic";\r
1368 name = "M_ienable_reg";\r
1369 radix = "hexadecimal";\r
1370 }\r
1371 SIGNAL acd\r
1372 {\r
1373 format = "Logic";\r
1374 name = "intr_req";\r
1375 radix = "hexadecimal";\r
1376 }\r
1377 }\r
1378 }\r
1379 }\r
1380 MODULE jtag_uart\r
1381 {\r
1382 SLAVE avalon_jtag_slave\r
1383 {\r
1384 PORT_WIRING \r
1385 {\r
1386 PORT clk\r
1387 {\r
1388 type = "clk";\r
1389 width = "1";\r
1390 direction = "input";\r
1391 Is_Enabled = "1";\r
1392 }\r
1393 PORT reset_n\r
1394 {\r
1395 type = "reset_n";\r
1396 width = "1";\r
1397 direction = "input";\r
1398 Is_Enabled = "0";\r
1399 }\r
1400 PORT av_irq\r
1401 {\r
1402 type = "irq";\r
1403 width = "1";\r
1404 direction = "output";\r
1405 Is_Enabled = "1";\r
1406 }\r
1407 PORT av_chipselect\r
1408 {\r
1409 type = "chipselect";\r
1410 width = "1";\r
1411 direction = "input";\r
1412 Is_Enabled = "1";\r
1413 }\r
1414 PORT av_address\r
1415 {\r
1416 type = "address";\r
1417 width = "1";\r
1418 direction = "input";\r
1419 Is_Enabled = "1";\r
1420 }\r
1421 PORT av_read_n\r
1422 {\r
1423 type = "read_n";\r
1424 width = "1";\r
1425 direction = "input";\r
1426 Is_Enabled = "1";\r
1427 }\r
1428 PORT av_readdata\r
1429 {\r
1430 type = "readdata";\r
1431 width = "32";\r
1432 direction = "output";\r
1433 Is_Enabled = "1";\r
1434 }\r
1435 PORT av_write_n\r
1436 {\r
1437 type = "write_n";\r
1438 width = "1";\r
1439 direction = "input";\r
1440 Is_Enabled = "1";\r
1441 }\r
1442 PORT av_writedata\r
1443 {\r
1444 type = "writedata";\r
1445 width = "32";\r
1446 direction = "input";\r
1447 Is_Enabled = "1";\r
1448 }\r
1449 PORT av_waitrequest\r
1450 {\r
1451 type = "waitrequest";\r
1452 width = "1";\r
1453 direction = "output";\r
1454 Is_Enabled = "1";\r
1455 }\r
1456 PORT dataavailable\r
1457 {\r
1458 type = "dataavailable";\r
1459 width = "1";\r
1460 direction = "output";\r
1461 Is_Enabled = "1";\r
1462 }\r
1463 PORT readyfordata\r
1464 {\r
1465 type = "readyfordata";\r
1466 width = "1";\r
1467 direction = "output";\r
1468 Is_Enabled = "1";\r
1469 }\r
1470 PORT rst_n\r
1471 {\r
1472 type = "reset_n";\r
1473 direction = "input";\r
1474 width = "1";\r
1475 Is_Enabled = "1";\r
1476 }\r
1477 }\r
1478 SYSTEM_BUILDER_INFO \r
1479 {\r
1480 Has_IRQ = "1";\r
1481 Bus_Type = "avalon";\r
1482 Read_Wait_States = "peripheral_controlled";\r
1483 Write_Wait_States = "peripheral_controlled";\r
1484 Hold_Time = "0cycles";\r
1485 Setup_Time = "0cycles";\r
1486 Is_Printable_Device = "1";\r
1487 Address_Alignment = "native";\r
1488 Well_Behaved_Waitrequest = "0";\r
1489 Is_Nonvolatile_Storage = "0";\r
1490 Read_Latency = "0";\r
1491 Is_Memory_Device = "0";\r
1492 Maximum_Pending_Read_Transactions = "0";\r
1493 Minimum_Uninterrupted_Run_Length = "1";\r
1494 Accepts_Internal_Connections = "1";\r
1495 Write_Latency = "0";\r
1496 Is_Flash = "0";\r
1497 Data_Width = "32";\r
1498 Address_Width = "1";\r
1499 Maximum_Burst_Size = "1";\r
1500 Register_Incoming_Signals = "0";\r
1501 Register_Outgoing_Signals = "0";\r
1502 Interleave_Bursts = "0";\r
1503 Linewrap_Bursts = "0";\r
1504 Burst_On_Burst_Boundaries_Only = "0";\r
1505 Always_Burst_Max_Burst = "0";\r
1506 Is_Big_Endian = "0";\r
1507 Is_Enabled = "1";\r
1508 JTAG_Hub_Base_Id = "262254";\r
1509 JTAG_Hub_Instance_Id = "0";\r
1510 Connection_Limit = "1";\r
1511 MASTERED_BY cpu/data_master\r
1512 {\r
1513 priority = "1";\r
1514 Offset_Address = "0x00109030";\r
1515 }\r
1516 IRQ_MASTER cpu/data_master\r
1517 {\r
1518 IRQ_Number = "2";\r
1519 }\r
1520 Base_Address = "0x00109030";\r
1521 Address_Group = "0";\r
1522 }\r
1523 }\r
1524 class = "altera_avalon_jtag_uart";\r
1525 class_version = "7.080902";\r
1526 iss_model_name = "altera_avalon_jtag_uart";\r
1527 WIZARD_SCRIPT_ARGUMENTS \r
1528 {\r
1529 write_depth = "64";\r
1530 read_depth = "64";\r
1531 write_threshold = "8";\r
1532 read_threshold = "8";\r
1533 read_char_stream = "";\r
1534 showascii = "1";\r
1535 read_le = "0";\r
1536 write_le = "0";\r
1537 altera_show_unreleased_jtag_uart_features = "0";\r
1538 }\r
1539 SIMULATION \r
1540 {\r
1541 DISPLAY \r
1542 {\r
1543 SIGNAL av_chipselect\r
1544 {\r
1545 name = "av_chipselect";\r
1546 }\r
1547 SIGNAL av_address\r
1548 {\r
1549 name = "av_address";\r
1550 radix = "hexadecimal";\r
1551 }\r
1552 SIGNAL av_read_n\r
1553 {\r
1554 name = "av_read_n";\r
1555 }\r
1556 SIGNAL av_readdata\r
1557 {\r
1558 name = "av_readdata";\r
1559 radix = "hexadecimal";\r
1560 }\r
1561 SIGNAL av_write_n\r
1562 {\r
1563 name = "av_write_n";\r
1564 }\r
1565 SIGNAL av_writedata\r
1566 {\r
1567 name = "av_writedata";\r
1568 radix = "hexadecimal";\r
1569 }\r
1570 SIGNAL av_waitrequest\r
1571 {\r
1572 name = "av_waitrequest";\r
1573 }\r
1574 SIGNAL dataavailable\r
1575 {\r
1576 name = "dataavailable";\r
1577 }\r
1578 SIGNAL readyfordata\r
1579 {\r
1580 name = "readyfordata";\r
1581 }\r
1582 SIGNAL av_irq\r
1583 {\r
1584 name = "av_irq";\r
1585 }\r
1586 }\r
1587 INTERACTIVE_IN drive\r
1588 {\r
1589 enable = "0";\r
1590 file = "_input_data_stream.dat";\r
1591 mutex = "_input_data_mutex.dat";\r
1592 log = "_in.log";\r
1593 rate = "100";\r
1594 signals = "temp,list";\r
1595 exe = "nios2-terminal";\r
1596 }\r
1597 INTERACTIVE_OUT log\r
1598 {\r
1599 enable = "1";\r
1600 exe = "perl -- atail-f.pl";\r
1601 file = "_output_stream.dat";\r
1602 radix = "ascii";\r
1603 signals = "temp,list";\r
1604 }\r
1605 Fix_Me_Up = "";\r
1606 }\r
1607 SYSTEM_BUILDER_INFO \r
1608 {\r
1609 Is_Enabled = "1";\r
1610 Clock_Source = "sys_clk";\r
1611 Has_Clock = "1";\r
1612 Instantiate_In_System_Module = "1";\r
1613 Iss_Launch_Telnet = "0";\r
1614 Top_Level_Ports_Are_Enumerated = "1";\r
1615 View \r
1616 {\r
1617 MESSAGES \r
1618 {\r
1619 }\r
1620 Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
1621 <br>Read Depth: 64; Read IRQ Threshold: 8";\r
1622 }\r
1623 }\r
1624 HDL_INFO \r
1625 {\r
1626 Precompiled_Simulation_Library_Files = "";\r
1627 Simulation_HDL_Files = "";\r
1628 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart.v";\r
1629 Synthesis_Only_Files = "";\r
1630 }\r
1631 PORT_WIRING \r
1632 {\r
1633 }\r
1634 }\r
1635 MODULE onchip_ram\r
1636 {\r
1637 SLAVE s1\r
1638 {\r
1639 PORT_WIRING \r
1640 {\r
1641 PORT clk\r
1642 {\r
1643 type = "clk";\r
1644 width = "1";\r
1645 direction = "input";\r
1646 Is_Enabled = "1";\r
1647 }\r
1648 PORT reset_n\r
1649 {\r
1650 type = "reset_n";\r
1651 width = "1";\r
1652 direction = "input";\r
1653 Is_Enabled = "0";\r
1654 }\r
1655 PORT address\r
1656 {\r
1657 type = "address";\r
1658 width = "12";\r
1659 direction = "input";\r
1660 Is_Enabled = "1";\r
1661 }\r
1662 PORT chipselect\r
1663 {\r
1664 type = "chipselect";\r
1665 width = "1";\r
1666 direction = "input";\r
1667 Is_Enabled = "1";\r
1668 }\r
1669 PORT clken\r
1670 {\r
1671 type = "clken";\r
1672 width = "1";\r
1673 direction = "input";\r
1674 Is_Enabled = "1";\r
1675 default_value = "1'b1";\r
1676 }\r
1677 PORT read\r
1678 {\r
1679 type = "read";\r
1680 width = "1";\r
1681 direction = "input";\r
1682 Is_Enabled = "0";\r
1683 }\r
1684 PORT readdata\r
1685 {\r
1686 type = "readdata";\r
1687 width = "32";\r
1688 direction = "output";\r
1689 Is_Enabled = "1";\r
1690 }\r
1691 PORT write\r
1692 {\r
1693 type = "write";\r
1694 width = "1";\r
1695 direction = "input";\r
1696 Is_Enabled = "1";\r
1697 }\r
1698 PORT writedata\r
1699 {\r
1700 type = "writedata";\r
1701 width = "32";\r
1702 direction = "input";\r
1703 Is_Enabled = "1";\r
1704 }\r
1705 PORT debugaccess\r
1706 {\r
1707 type = "debugaccess";\r
1708 width = "1";\r
1709 direction = "input";\r
1710 Is_Enabled = "0";\r
1711 }\r
1712 PORT byteenable\r
1713 {\r
1714 type = "byteenable";\r
1715 width = "4";\r
1716 direction = "input";\r
1717 Is_Enabled = "1";\r
1718 }\r
1719 }\r
1720 SYSTEM_BUILDER_INFO \r
1721 {\r
1722 Bus_Type = "avalon";\r
1723 Write_Wait_States = "0cycles";\r
1724 Read_Wait_States = "0cycles";\r
1725 Hold_Time = "0cycles";\r
1726 Setup_Time = "0cycles";\r
1727 Is_Printable_Device = "0";\r
1728 Address_Alignment = "dynamic";\r
1729 Well_Behaved_Waitrequest = "0";\r
1730 Is_Nonvolatile_Storage = "0";\r
1731 Address_Span = "16384";\r
1732 Read_Latency = "1";\r
1733 Is_Memory_Device = "1";\r
1734 Maximum_Pending_Read_Transactions = "0";\r
1735 Minimum_Uninterrupted_Run_Length = "1";\r
1736 Accepts_Internal_Connections = "1";\r
1737 Write_Latency = "0";\r
1738 Is_Flash = "0";\r
1739 Data_Width = "32";\r
1740 Address_Width = "12";\r
1741 Maximum_Burst_Size = "1";\r
1742 Register_Incoming_Signals = "0";\r
1743 Register_Outgoing_Signals = "0";\r
1744 Interleave_Bursts = "0";\r
1745 Linewrap_Bursts = "0";\r
1746 Burst_On_Burst_Boundaries_Only = "0";\r
1747 Always_Burst_Max_Burst = "0";\r
1748 Is_Big_Endian = "0";\r
1749 Is_Enabled = "1";\r
1750 MASTERED_BY cpu/instruction_master\r
1751 {\r
1752 priority = "1";\r
1753 Offset_Address = "0x00104000";\r
1754 }\r
1755 MASTERED_BY cpu/data_master\r
1756 {\r
1757 priority = "1";\r
1758 Offset_Address = "0x00104000";\r
1759 }\r
1760 Base_Address = "0x00104000";\r
1761 Address_Group = "0";\r
1762 Has_IRQ = "0";\r
1763 Is_Channel = "1";\r
1764 Is_Writable = "1";\r
1765 IRQ_MASTER cpu/data_master\r
1766 {\r
1767 IRQ_Number = "NC";\r
1768 }\r
1769 }\r
1770 }\r
1771 iss_model_name = "altera_memory";\r
1772 WIZARD_SCRIPT_ARGUMENTS \r
1773 {\r
1774 allow_mram_sim_contents_only_file = "0";\r
1775 ram_block_type = "AUTO";\r
1776 init_contents_file = "onchip_ram";\r
1777 non_default_init_file_enabled = "0";\r
1778 gui_ram_block_type = "Automatic";\r
1779 Writeable = "1";\r
1780 dual_port = "0";\r
1781 Size_Value = "16384";\r
1782 Size_Multiple = "1";\r
1783 use_shallow_mem_blocks = "0";\r
1784 init_mem_content = "1";\r
1785 allow_in_system_memory_content_editor = "0";\r
1786 instance_id = "NONE";\r
1787 read_during_write_mode = "DONT_CARE";\r
1788 ignore_auto_block_type_assignment = "1";\r
1789 MAKE \r
1790 {\r
1791 TARGET delete_placeholder_warning\r
1792 {\r
1793 onchip_ram \r
1794 {\r
1795 Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";\r
1796 Is_Phony = "1";\r
1797 Target_File = "do_delete_placeholder_warning";\r
1798 }\r
1799 }\r
1800 TARGET hex\r
1801 {\r
1802 onchip_ram \r
1803 {\r
1804 Command1 = "@echo Post-processing to create $(notdir $@)";\r
1805 Command2 = "elf2hex $(ELF) 0x00104000 0x107FFF --width=32 $(QUARTUS_PROJECT_DIR)/onchip_ram.hex --create-lanes=0 ";\r
1806 Dependency = "$(ELF)";\r
1807 Target_File = "$(QUARTUS_PROJECT_DIR)/onchip_ram.hex";\r
1808 }\r
1809 }\r
1810 TARGET sim\r
1811 {\r
1812 onchip_ram \r
1813 {\r
1814 Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";\r
1815 Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";\r
1816 Command3 = "touch $(SIMDIR)/dummy_file";\r
1817 Dependency = "$(ELF)";\r
1818 Target_File = "$(SIMDIR)/dummy_file";\r
1819 }\r
1820 }\r
1821 }\r
1822 contents_info = "";\r
1823 }\r
1824 SIMULATION \r
1825 {\r
1826 DISPLAY \r
1827 {\r
1828 SIGNAL a\r
1829 {\r
1830 name = "chipselect";\r
1831 conditional = "1";\r
1832 }\r
1833 SIGNAL c\r
1834 {\r
1835 name = "address";\r
1836 radix = "hexadecimal";\r
1837 }\r
1838 SIGNAL d\r
1839 {\r
1840 name = "byteenable";\r
1841 radix = "binary";\r
1842 conditional = "1";\r
1843 }\r
1844 SIGNAL e\r
1845 {\r
1846 name = "readdata";\r
1847 radix = "hexadecimal";\r
1848 }\r
1849 SIGNAL b\r
1850 {\r
1851 name = "write";\r
1852 conditional = "1";\r
1853 }\r
1854 SIGNAL f\r
1855 {\r
1856 name = "writedata";\r
1857 radix = "hexadecimal";\r
1858 conditional = "1";\r
1859 }\r
1860 }\r
1861 }\r
1862 SYSTEM_BUILDER_INFO \r
1863 {\r
1864 Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";\r
1865 Instantiate_In_System_Module = "1";\r
1866 Is_Enabled = "1";\r
1867 Default_Module_Name = "onchip_memory";\r
1868 Top_Level_Ports_Are_Enumerated = "1";\r
1869 Clock_Source = "sys_clk";\r
1870 Has_Clock = "1";\r
1871 View \r
1872 {\r
1873 MESSAGES \r
1874 {\r
1875 }\r
1876 }\r
1877 }\r
1878 class = "altera_avalon_onchip_memory2";\r
1879 class_version = "7.080902";\r
1880 HDL_INFO \r
1881 {\r
1882 Precompiled_Simulation_Library_Files = "";\r
1883 Simulation_HDL_Files = "";\r
1884 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/onchip_ram.v";\r
1885 Synthesis_Only_Files = "";\r
1886 }\r
1887 SLAVE s2\r
1888 {\r
1889 PORT_WIRING \r
1890 {\r
1891 }\r
1892 SYSTEM_BUILDER_INFO \r
1893 {\r
1894 Bus_Type = "avalon";\r
1895 Is_Memory_Device = "1";\r
1896 Address_Group = "0";\r
1897 Address_Alignment = "dynamic";\r
1898 Address_Width = "12";\r
1899 Data_Width = "32";\r
1900 Has_IRQ = "0";\r
1901 Read_Wait_States = "0";\r
1902 Write_Wait_States = "0";\r
1903 Address_Span = "16384";\r
1904 Read_Latency = "1";\r
1905 Is_Channel = "1";\r
1906 Is_Enabled = "0";\r
1907 Is_Writable = "1";\r
1908 }\r
1909 }\r
1910 PORT_WIRING \r
1911 {\r
1912 }\r
1913 }\r
1914 MODULE led\r
1915 {\r
1916 SLAVE s1\r
1917 {\r
1918 PORT_WIRING \r
1919 {\r
1920 PORT clk\r
1921 {\r
1922 type = "clk";\r
1923 width = "1";\r
1924 direction = "input";\r
1925 Is_Enabled = "1";\r
1926 }\r
1927 PORT reset_n\r
1928 {\r
1929 type = "reset_n";\r
1930 width = "1";\r
1931 direction = "input";\r
1932 Is_Enabled = "1";\r
1933 }\r
1934 PORT address\r
1935 {\r
1936 type = "address";\r
1937 width = "2";\r
1938 direction = "input";\r
1939 Is_Enabled = "1";\r
1940 }\r
1941 PORT write_n\r
1942 {\r
1943 type = "write_n";\r
1944 width = "1";\r
1945 direction = "input";\r
1946 Is_Enabled = "1";\r
1947 }\r
1948 PORT writedata\r
1949 {\r
1950 type = "writedata";\r
1951 width = "8";\r
1952 direction = "input";\r
1953 Is_Enabled = "1";\r
1954 }\r
1955 PORT chipselect\r
1956 {\r
1957 type = "chipselect";\r
1958 width = "1";\r
1959 direction = "input";\r
1960 Is_Enabled = "1";\r
1961 }\r
1962 PORT readdata\r
1963 {\r
1964 Is_Enabled = "1";\r
1965 direction = "output";\r
1966 type = "readdata";\r
1967 width = "8";\r
1968 }\r
1969 }\r
1970 SYSTEM_BUILDER_INFO \r
1971 {\r
1972 Bus_Type = "avalon";\r
1973 Write_Wait_States = "0cycles";\r
1974 Read_Wait_States = "1cycles";\r
1975 Hold_Time = "0cycles";\r
1976 Setup_Time = "0cycles";\r
1977 Is_Printable_Device = "0";\r
1978 Address_Alignment = "native";\r
1979 Well_Behaved_Waitrequest = "0";\r
1980 Is_Nonvolatile_Storage = "0";\r
1981 Read_Latency = "0";\r
1982 Is_Memory_Device = "0";\r
1983 Maximum_Pending_Read_Transactions = "0";\r
1984 Minimum_Uninterrupted_Run_Length = "1";\r
1985 Accepts_Internal_Connections = "1";\r
1986 Write_Latency = "0";\r
1987 Is_Flash = "0";\r
1988 Data_Width = "8";\r
1989 Address_Width = "2";\r
1990 Maximum_Burst_Size = "1";\r
1991 Register_Incoming_Signals = "0";\r
1992 Register_Outgoing_Signals = "0";\r
1993 Interleave_Bursts = "0";\r
1994 Linewrap_Bursts = "0";\r
1995 Burst_On_Burst_Boundaries_Only = "0";\r
1996 Always_Burst_Max_Burst = "0";\r
1997 Is_Big_Endian = "0";\r
1998 Is_Enabled = "1";\r
1999 MASTERED_BY cpu/data_master\r
2000 {\r
2001 priority = "1";\r
2002 Offset_Address = "0x00109020";\r
2003 }\r
2004 Base_Address = "0x00109020";\r
2005 Has_IRQ = "0";\r
2006 Address_Group = "0";\r
2007 IRQ_MASTER cpu/data_master\r
2008 {\r
2009 IRQ_Number = "NC";\r
2010 }\r
2011 Is_Readable = "0";\r
2012 Is_Writable = "1";\r
2013 }\r
2014 }\r
2015 PORT_WIRING \r
2016 {\r
2017 PORT out_port\r
2018 {\r
2019 type = "export";\r
2020 width = "8";\r
2021 direction = "output";\r
2022 Is_Enabled = "1";\r
2023 }\r
2024 PORT in_port\r
2025 {\r
2026 direction = "input";\r
2027 Is_Enabled = "0";\r
2028 width = "8";\r
2029 }\r
2030 PORT bidir_port\r
2031 {\r
2032 direction = "inout";\r
2033 Is_Enabled = "0";\r
2034 width = "8";\r
2035 }\r
2036 }\r
2037 class = "altera_avalon_pio";\r
2038 class_version = "7.080902";\r
2039 SYSTEM_BUILDER_INFO \r
2040 {\r
2041 Is_Enabled = "1";\r
2042 Instantiate_In_System_Module = "1";\r
2043 Wire_Test_Bench_Values = "1";\r
2044 Top_Level_Ports_Are_Enumerated = "1";\r
2045 Clock_Source = "sys_clk";\r
2046 Has_Clock = "1";\r
2047 Date_Modified = "";\r
2048 View \r
2049 {\r
2050 MESSAGES \r
2051 {\r
2052 }\r
2053 Settings_Summary = " 8-bit PIO using <br>
2056 output pins";\r
2057 }\r
2058 }\r
2059 WIZARD_SCRIPT_ARGUMENTS \r
2060 {\r
2061 Do_Test_Bench_Wiring = "0";\r
2062 Driven_Sim_Value = "0";\r
2063 has_tri = "0";\r
2064 has_out = "1";\r
2065 has_in = "0";\r
2066 capture = "0";\r
2067 Data_Width = "8";\r
2068 reset_value = "0";\r
2069 edge_type = "NONE";\r
2070 irq_type = "NONE";\r
2071 bit_clearing_edge_register = "0";\r
2072 bit_modifying_output_register = "0";\r
2073 }\r
2074 HDL_INFO \r
2075 {\r
2076 Precompiled_Simulation_Library_Files = "";\r
2077 Simulation_HDL_Files = "";\r
2078 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/led.v";\r
2079 Synthesis_Only_Files = "";\r
2080 }\r
2081 }\r
2082 MODULE ext_bus_unit\r
2083 {\r
2084 SLAVE avalon_slave\r
2085 {\r
2086 PORT_WIRING \r
2087 {\r
2088 }\r
2089 SYSTEM_BUILDER_INFO \r
2090 {\r
2091 Bus_Type = "avalon";\r
2092 Write_Wait_States = "0cycles";\r
2093 Read_Wait_States = "1cycles";\r
2094 Hold_Time = "0cycles";\r
2095 Setup_Time = "0cycles";\r
2096 Is_Printable_Device = "0";\r
2097 Address_Alignment = "dynamic";\r
2098 Well_Behaved_Waitrequest = "0";\r
2099 Is_Nonvolatile_Storage = "0";\r
2100 Address_Span = "1";\r
2101 Read_Latency = "0";\r
2102 Is_Memory_Device = "0";\r
2103 Maximum_Pending_Read_Transactions = "0";\r
2104 Minimum_Uninterrupted_Run_Length = "1";\r
2105 Accepts_Internal_Connections = "1";\r
2106 Write_Latency = "0";\r
2107 Is_Flash = "0";\r
2108 Maximum_Burst_Size = "1";\r
2109 Register_Incoming_Signals = "0";\r
2110 Register_Outgoing_Signals = "1";\r
2111 Interleave_Bursts = "0";\r
2112 Linewrap_Bursts = "0";\r
2113 Burst_On_Burst_Boundaries_Only = "0";\r
2114 Always_Burst_Max_Burst = "0";\r
2115 Is_Big_Endian = "0";\r
2116 Is_Enabled = "1";\r
2117 MASTERED_BY cpu/instruction_master\r
2118 {\r
2119 priority = "1";\r
2120 Offset_Address = "N/A";\r
2121 Base_Address = "N/A";\r
2122 }\r
2123 MASTERED_BY cpu/data_master\r
2124 {\r
2125 priority = "1";\r
2126 Offset_Address = "N/A";\r
2127 Base_Address = "N/A";\r
2128 }\r
2129 Bridges_To = "tristate_master";\r
2130 Base_Address = "N/A";\r
2131 Has_IRQ = "0";\r
2132 IRQ = "N/A";\r
2133 Address_Group = "0";\r
2134 IRQ_MASTER cpu/data_master\r
2135 {\r
2136 IRQ_Number = "NC";\r
2137 }\r
2138 }\r
2139 }\r
2140 MASTER tristate_master\r
2141 {\r
2142 SYSTEM_BUILDER_INFO \r
2143 {\r
2144 Bus_Type = "avalon_tristate";\r
2145 Is_Asynchronous = "0";\r
2146 DBS_Big_Endian = "0";\r
2147 Adapts_To = "";\r
2148 Maximum_Burst_Size = "1";\r
2149 Register_Incoming_Signals = "0";\r
2150 Register_Outgoing_Signals = "0";\r
2151 Interleave_Bursts = "0";\r
2152 Linewrap_Bursts = "0";\r
2153 Burst_On_Burst_Boundaries_Only = "0";\r
2154 Always_Burst_Max_Burst = "0";\r
2155 Is_Big_Endian = "0";\r
2156 Is_Enabled = "1";\r
2157 Bridges_To = "avalon_slave";\r
2158 }\r
2159 PORT_WIRING \r
2160 {\r
2161 }\r
2162 MEMORY_MAP \r
2163 {\r
2164 Entry ext_ram/avalon_tristate_slave_0\r
2165 {\r
2166 address = "0x00080000";\r
2167 span = "0x00080000";\r
2168 is_bridge = "0";\r
2169 }\r
2170 }\r
2171 }\r
2172 WIZARD_SCRIPT_ARGUMENTS \r
2173 {\r
2174 }\r
2175 class = "altera_avalon_tri_state_bridge";\r
2176 class_version = "7.080902";\r
2177 SYSTEM_BUILDER_INFO \r
2178 {\r
2179 Is_Enabled = "1";\r
2180 Clock_Source = "sys_clk";\r
2181 Has_Clock = "1";\r
2182 Instantiate_In_System_Module = "1";\r
2183 Is_Bridge = "1";\r
2184 Top_Level_Ports_Are_Enumerated = "1";\r
2185 View \r
2186 {\r
2187 MESSAGES \r
2188 {\r
2189 }\r
2190 }\r
2191 }\r
2192 }\r
2193 MODULE main_pll\r
2194 {\r
2195 SLAVE s1\r
2196 {\r
2197 PORT_WIRING \r
2198 {\r
2199 PORT inclk0\r
2200 {\r
2201 type = "clk";\r
2202 width = "1";\r
2203 direction = "input";\r
2204 Is_Enabled = "0";\r
2205 }\r
2206 PORT reset_n\r
2207 {\r
2208 type = "reset_n";\r
2209 width = "1";\r
2210 direction = "input";\r
2211 Is_Enabled = "1";\r
2212 }\r
2213 PORT resetrequest\r
2214 {\r
2215 type = "resetrequest";\r
2216 width = "1";\r
2217 direction = "output";\r
2218 Is_Enabled = "1";\r
2219 }\r
2220 PORT address\r
2221 {\r
2222 type = "address";\r
2223 width = "3";\r
2224 direction = "input";\r
2225 Is_Enabled = "1";\r
2226 }\r
2227 PORT chipselect\r
2228 {\r
2229 type = "chipselect";\r
2230 width = "1";\r
2231 direction = "input";\r
2232 Is_Enabled = "1";\r
2233 }\r
2234 PORT read\r
2235 {\r
2236 type = "read";\r
2237 width = "1";\r
2238 direction = "input";\r
2239 Is_Enabled = "1";\r
2240 }\r
2241 PORT readdata\r
2242 {\r
2243 type = "readdata";\r
2244 width = "16";\r
2245 direction = "output";\r
2246 Is_Enabled = "1";\r
2247 }\r
2248 PORT write\r
2249 {\r
2250 type = "write";\r
2251 width = "1";\r
2252 direction = "input";\r
2253 Is_Enabled = "1";\r
2254 }\r
2255 PORT writedata\r
2256 {\r
2257 type = "writedata";\r
2258 width = "16";\r
2259 direction = "input";\r
2260 Is_Enabled = "1";\r
2261 }\r
2262 PORT clk\r
2263 {\r
2264 direction = "input";\r
2265 type = "clk";\r
2266 width = "1";\r
2267 Is_Enabled = "1";\r
2268 }\r
2269 PORT c0\r
2270 {\r
2271 Is_Enabled = "1";\r
2272 direction = "output";\r
2273 type = "out_clk";\r
2274 width = "1";\r
2275 }\r
2276 }\r
2277 SYSTEM_BUILDER_INFO \r
2278 {\r
2279 Bus_Type = "avalon";\r
2280 Write_Wait_States = "0cycles";\r
2281 Read_Wait_States = "1cycles";\r
2282 Hold_Time = "0cycles";\r
2283 Setup_Time = "0cycles";\r
2284 Is_Printable_Device = "0";\r
2285 Address_Alignment = "native";\r
2286 Well_Behaved_Waitrequest = "0";\r
2287 Is_Nonvolatile_Storage = "0";\r
2288 Read_Latency = "0";\r
2289 Is_Memory_Device = "0";\r
2290 Maximum_Pending_Read_Transactions = "0";\r
2291 Minimum_Uninterrupted_Run_Length = "1";\r
2292 Accepts_Internal_Connections = "1";\r
2293 Write_Latency = "0";\r
2294 Is_Flash = "0";\r
2295 Data_Width = "16";\r
2296 Address_Width = "3";\r
2297 Maximum_Burst_Size = "1";\r
2298 Register_Incoming_Signals = "0";\r
2299 Register_Outgoing_Signals = "0";\r
2300 Interleave_Bursts = "0";\r
2301 Linewrap_Bursts = "0";\r
2302 Burst_On_Burst_Boundaries_Only = "0";\r
2303 Always_Burst_Max_Burst = "0";\r
2304 Is_Big_Endian = "0";\r
2305 Is_Enabled = "1";\r
2306 MASTERED_BY cpu/data_master\r
2307 {\r
2308 priority = "1";\r
2309 Offset_Address = "0x00109000";\r
2310 }\r
2311 Clock_Source = "ext_clk";\r
2312 Has_Clock = "1";\r
2313 Base_Address = "0x00109000";\r
2314 Has_IRQ = "0";\r
2315 Date_Modified = "";\r
2316 Instantiate_In_System_Module = "1";\r
2317 Requires_Internal_Clock_Promotion = "Yes";\r
2318 Is_Clock_Source = "1";\r
2319 Address_Group = "0";\r
2320 IRQ_MASTER cpu/data_master\r
2321 {\r
2322 IRQ_Number = "NC";\r
2323 }\r
2324 }\r
2325 }\r
2326 PORT_WIRING \r
2327 {\r
2328 PORT c0\r
2329 {\r
2330 type = "out_clk";\r
2331 width = "1";\r
2332 direction = "output";\r
2333 Is_Enabled = "0";\r
2334 }\r
2335 PORT areset\r
2336 {\r
2337 Is_Enabled = "0";\r
2338 direction = "input";\r
2339 width = "1";\r
2340 }\r
2341 PORT locked\r
2342 {\r
2343 Is_Enabled = "0";\r
2344 direction = "output";\r
2345 width = "1";\r
2346 }\r
2347 PORT pfdena\r
2348 {\r
2349 Is_Enabled = "0";\r
2350 direction = "input";\r
2351 width = "1";\r
2352 }\r
2353 PORT pllena\r
2354 {\r
2355 Is_Enabled = "0";\r
2356 direction = "input";\r
2357 width = "1";\r
2358 }\r
2359 }\r
2360 WIZARD_SCRIPT_ARGUMENTS \r
2361 {\r
2362 areset = "None";\r
2363 pfdena = "None";\r
2364 locked = "None";\r
2365 pllena = "None";\r
2366 scanclk = "None";\r
2367 scandata = "None";\r
2368 scanread = "None";\r
2369 scanwrite = "None";\r
2370 scanclkena = "None";\r
2371 scanaclr = "None";\r
2372 scandataout = "None";\r
2373 scandone = "None";\r
2374 configupdate = "None";\r
2375 phasecounterselect = "None";\r
2376 phasedone = "None";\r
2377 phaseupdown = "None";\r
2378 phasestep = "None";\r
2379 UI_CONTROL \r
2380 {\r
2381 pllena_port_exist = "0";\r
2382 areset_port_exist = "0";\r
2383 pfdena_port_exist = "0";\r
2384 locked_port_exist = "0";\r
2385 }\r
2386 ALTPLL_PORTS \r
2387 {\r
2388 PORT inclk0\r
2389 {\r
2390 Is_Enabled = "1";\r
2391 direction = "input";\r
2392 width = "1";\r
2393 }\r
2394 PORT c0\r
2395 {\r
2396 Is_Enabled = "1";\r
2397 direction = "output";\r
2398 type = "out_clk";\r
2399 width = "1";\r
2400 }\r
2401 }\r
2402 CLOCK_SOURCES \r
2403 {\r
2404 CLOCK c0\r
2405 {\r
2406 DIVIDE_BY = "1";\r
2407 DUTY_CYCLE = "50";\r
2408 MULTIPLY_BY = "2";\r
2409 PHASE_SHIFT = "0";\r
2410 clk_index = "0";\r
2411 clock_freq = "32000000";\r
2412 clock_unit = "MHz";\r
2413 type = "out_clk";\r
2414 }\r
2415 }\r
2416 CLOCK_INFO \r
2417 {\r
2418 CLOCK inclk0\r
2419 {\r
2420 clock_freq = "16000000";\r
2421 clock_unit = "MHz";\r
2422 type = "in_clk";\r
2423 }\r
2424 }\r
2425 CNX_INFO \r
2426 {\r
2427 CONSTANT \r
2428 {\r
2429 STRING \r
2430 {\r
2431 BANDWIDTH_TYPE = "AUTO";\r
2432 CLK0_PHASE_SHIFT = "0";\r
2433 COMPENSATE_CLOCK = "CLK0";\r
2434 INTENDED_DEVICE_FAMILY = "Cyclone III";\r
2435 LPM_TYPE = "altpll";\r
2436 OPERATION_MODE = "NORMAL";\r
2437 PLL_TYPE = "AUTO";\r
2438 PORT_ACTIVECLOCK = "PORT_UNUSED";\r
2439 PORT_ARESET = "PORT_UNUSED";\r
2440 PORT_CLKBAD0 = "PORT_UNUSED";\r
2441 PORT_CLKBAD1 = "PORT_UNUSED";\r
2442 PORT_CLKLOSS = "PORT_UNUSED";\r
2443 PORT_CLKSWITCH = "PORT_UNUSED";\r
2444 PORT_CONFIGUPDATE = "PORT_UNUSED";\r
2445 PORT_FBIN = "PORT_UNUSED";\r
2446 PORT_INCLK0 = "PORT_USED";\r
2447 PORT_INCLK1 = "PORT_UNUSED";\r
2448 PORT_LOCKED = "PORT_UNUSED";\r
2449 PORT_PFDENA = "PORT_UNUSED";\r
2450 PORT_PHASECOUNTERSELECT = "PORT_UNUSED";\r
2451 PORT_PHASEDONE = "PORT_UNUSED";\r
2452 PORT_PHASESTEP = "PORT_UNUSED";\r
2453 PORT_PHASEUPDOWN = "PORT_UNUSED";\r
2454 PORT_PLLENA = "PORT_UNUSED";\r
2455 PORT_SCANACLR = "PORT_UNUSED";\r
2456 PORT_SCANCLK = "PORT_UNUSED";\r
2457 PORT_SCANCLKENA = "PORT_UNUSED";\r
2458 PORT_SCANDATA = "PORT_UNUSED";\r
2459 PORT_SCANDATAOUT = "PORT_UNUSED";\r
2460 PORT_SCANDONE = "PORT_UNUSED";\r
2461 PORT_SCANREAD = "PORT_UNUSED";\r
2462 PORT_SCANWRITE = "PORT_UNUSED";\r
2463 PORT_clk0 = "PORT_USED";\r
2464 PORT_clk1 = "PORT_UNUSED";\r
2465 PORT_clk2 = "PORT_UNUSED";\r
2466 PORT_clk3 = "PORT_UNUSED";\r
2467 PORT_clk4 = "PORT_UNUSED";\r
2468 PORT_clk5 = "PORT_UNUSED";\r
2469 PORT_clkena0 = "PORT_UNUSED";\r
2470 PORT_clkena1 = "PORT_UNUSED";\r
2471 PORT_clkena2 = "PORT_UNUSED";\r
2472 PORT_clkena3 = "PORT_UNUSED";\r
2473 PORT_clkena4 = "PORT_UNUSED";\r
2474 PORT_clkena5 = "PORT_UNUSED";\r
2475 PORT_extclk0 = "PORT_UNUSED";\r
2476 PORT_extclk1 = "PORT_UNUSED";\r
2477 PORT_extclk2 = "PORT_UNUSED";\r
2478 PORT_extclk3 = "PORT_UNUSED";\r
2479 }\r
2480 NUMERIC \r
2481 {\r
2482 CLK0_DIVIDE_BY = "1";\r
2483 CLK0_DUTY_CYCLE = "50";\r
2484 CLK0_MULTIPLY_BY = "2";\r
2485 INCLK0_INPUT_FREQUENCY = "62500";\r
2486 WIDTH_CLOCK = "5";\r
2487 }\r
2488 }\r
2489 LIBRARY = "altera_mf altera_mf.altera_mf_components.all";\r
2490 PRIVATE \r
2491 {\r
2492 STRING \r
2493 {\r
2494 ACTIVECLK_CHECK = "0";\r
2495 BANDWIDTH = "1.000";\r
2496 BANDWIDTH_FEATURE_ENABLED = "1";\r
2497 BANDWIDTH_FREQ_UNIT = "MHz";\r
2498 BANDWIDTH_PRESET = "Low";\r
2499 BANDWIDTH_USE_AUTO = "1";\r
2500 BANDWIDTH_USE_PRESET = "0";\r
2501 CLKBAD_SWITCHOVER_CHECK = "0";\r
2502 CLKLOSS_CHECK = "0";\r
2503 CLKSWITCH_CHECK = "0";\r
2504 CNX_NO_COMPENSATE_RADIO = "0";\r
2505 CREATE_CLKBAD_CHECK = "0";\r
2506 CREATE_INCLK1_CHECK = "0";\r
2507 CUR_DEDICATED_CLK = "c0";\r
2508 CUR_FBIN_CLK = "e0";\r
2509 DEVICE_SPEED_GRADE = "Any";\r
2510 DUTY_CYCLE0 = "50.00000000";\r
2511 EXPLICIT_SWITCHOVER_COUNTER = "0";\r
2512 EXT_FEEDBACK_RADIO = "0";\r
2513 GLOCKED_COUNTER_EDIT_CHANGED = "1";\r
2514 GLOCKED_FEATURE_ENABLED = "0";\r
2515 GLOCKED_MODE_CHECK = "0";\r
2516 HAS_MANUAL_SWITCHOVER = "1";\r
2517 INCLK0_FREQ_EDIT = "16.0";\r
2518 INCLK0_FREQ_UNIT_COMBO = "MHz";\r
2519 INCLK1_FREQ_EDIT = "100.000";\r
2520 INCLK1_FREQ_EDIT_CHANGED = "1";\r
2521 INCLK1_FREQ_UNIT_CHANGED = "1";\r
2522 INCLK1_FREQ_UNIT_COMBO = "MHz";\r
2523 INTENDED_DEVICE_FAMILY = "Cyclone III";\r
2524 INT_FEEDBACK__MODE_RADIO = "1";\r
2525 LOCKED_OUTPUT_CHECK = "0";\r
2526 LONG_SCAN_RADIO = "1";\r
2527 LVDS_MODE_DATA_RATE = "304.000";\r
2528 LVDS_PHASE_SHIFT_UNIT0 = "ps";\r
2529 MIG_DEVICE_SPEED_GRADE = "Any";\r
2530 MIRROR_CLK0 = "0";\r
2531 NORMAL_MODE_RADIO = "1";\r
2532 OUTPUT_FREQ0 = "32.00000000";\r
2533 OUTPUT_FREQ_MODE0 = "1";\r
2534 OUTPUT_FREQ_UNIT0 = "MHz";\r
2535 PHASE_RECONFIG_FEATURE_ENABLED = "1";\r
2536 PHASE_RECONFIG_INPUTS_CHECK = "0";\r
2537 PHASE_SHIFT0 = "0.00000000";\r
2538 PHASE_SHIFT_STEP_ENABLED_CHECK = "0";\r
2539 PHASE_SHIFT_UNIT0 = "ps";\r
2540 PLL_ADVANCED_PARAM_CHECK = "0";\r
2541 PLL_ARESET_CHECK = "0";\r
2542 PLL_FBMIMIC_CHECK = "0";\r
2543 PLL_PFDENA_CHECK = "0";\r
2544 PRIMARY_CLK_COMBO = "inclk0";\r
2545 RECONFIG_FILE = "altpllpll_0.mif";\r
2546 SACN_INPUTS_CHECK = "0";\r
2547 SCAN_FEATURE_ENABLED = "1";\r
2548 SELF_RESET_LOCK_LOSS = "0";\r
2549 SHORT_SCAN_RADIO = "0";\r
2550 SPREAD_FEATURE_ENABLED = "0";\r
2551 SPREAD_FREQ = "50.000";\r
2552 SPREAD_FREQ_UNIT = "KHz";\r
2553 SPREAD_PERCENT = "0.500";\r
2554 SPREAD_USE = "0";\r
2555 SRC_SYNCH_COMP_RADIO = "0";\r
2556 STICKY_CLK0 = "1";\r
2557 SWITCHOVER_FEATURE_ENABLED = "1";\r
2558 SYNTH_WRAPPER_GEN_POSTFIX = "0";\r
2559 USE_CLK0 = "1";\r
2560 USE_CLKENA0 = "0";\r
2561 ZERO_DELAY_RADIO = "0";\r
2562 }\r
2563 NUMERIC \r
2564 {\r
2565 DIV_FACTOR0 = "1";\r
2566 GLOCK_COUNTER_EDIT = "1048575";\r
2567 LVDS_MODE_DATA_RATE_DIRTY = "0";\r
2568 MULT_FACTOR0 = "1";\r
2569 PLL_AUTOPLL_CHECK = "1";\r
2570 PLL_ENHPLL_CHECK = "0";\r
2571 PLL_FASTPLL_CHECK = "0";\r
2572 PLL_LVDS_PLL_CHECK = "0";\r
2573 PLL_TARGET_HARCOPY_CHECK = "0";\r
2574 SWITCHOVER_COUNT_EDIT = "1";\r
2575 USE_MIL_SPEED_GRADE = "0";\r
2576 }\r
2577 }\r
2578 USED_PORT \r
2579 {\r
2580 c0 \r
2581 {\r
2582 VALUE_1 = "0";\r
2583 VALUE_2 = "0";\r
2584 VALUE_3 = "0";\r
2585 VALUE_4 = "0";\r
2586 VALUE_5 = "OUTPUT_CLK_EXT";\r
2587 VALUE_6 = "VCC";\r
2588 VALUE_7 = "c0";\r
2589 }\r
2590 inclk0 \r
2591 {\r
2592 VALUE_1 = "0";\r
2593 VALUE_2 = "0";\r
2594 VALUE_3 = "0";\r
2595 VALUE_4 = "0";\r
2596 VALUE_5 = "INPUT_CLK_EXT";\r
2597 VALUE_6 = "GND";\r
2598 VALUE_7 = "inclk0";\r
2599 }\r
2600 }\r
2601 }\r
2602 Config_Done = "0";\r
2603 }\r
2604 SYSTEM_BUILDER_INFO \r
2605 {\r
2606 Required_Device_Family = "STRATIX,STRATIXII,STRATIXIII,STRATIXIV,CYCLONE,CYCLONEII,CYCLONEIII,TARPON,STRATIXGX,STRATIXIIGX,STRATIXIIGXLITE,ARRIAGX,ARRIAII,HARDCOPYIII";\r
2607 Instantiate_In_System_Module = "1";\r
2608 Is_Enabled = "1";\r
2609 Default_Module_Name = "pll";\r
2610 Top_Level_Ports_Are_Enumerated = "1";\r
2611 Clock_Source = "ext_clk";\r
2612 View \r
2613 {\r
2614 MESSAGES \r
2615 {\r
2616 }\r
2617 Settings_Summary = " Avalon PLL: <br>
2618 input clock configured: <b>ext_clk</b>
2619 ";\r
2620 }\r
2621 }\r
2622 class = "altera_avalon_pll";\r
2623 class_version = "7.080902";\r
2624 HDL_INFO \r
2625 {\r
2626 Precompiled_Simulation_Library_Files = "";\r
2627 Simulation_HDL_Files = "";\r
2628 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/main_pll.v, __PROJECT_DIRECTORY__/altpllmain_pll.v";\r
2629 Synthesis_Only_Files = "";\r
2630 }\r
2631 }\r
2632 MODULE ext_ram\r
2633 {\r
2634 SLAVE avalon_tristate_slave_0\r
2635 {\r
2636 PORT_WIRING \r
2637 {\r
2638 PORT clk\r
2639 {\r
2640 type = "clk";\r
2641 width = "1";\r
2642 direction = "input";\r
2643 Is_Enabled = "1";\r
2644 }\r
2645 PORT address\r
2646 {\r
2647 type = "address";\r
2648 width = "18";\r
2649 direction = "input";\r
2650 Is_Enabled = "1";\r
2651 is_shared = "0";\r
2652 }\r
2653 PORT data\r
2654 {\r
2655 type = "data";\r
2656 width = "16";\r
2657 direction = "inout";\r
2658 Is_Enabled = "1";\r
2659 is_shared = "0";\r
2660 }\r
2661 PORT read_n\r
2662 {\r
2663 type = "read_n";\r
2664 width = "1";\r
2665 direction = "input";\r
2666 Is_Enabled = "1";\r
2667 is_shared = "0";\r
2668 }\r
2669 PORT write_n\r
2670 {\r
2671 type = "write_n";\r
2672 width = "1";\r
2673 direction = "input";\r
2674 Is_Enabled = "1";\r
2675 is_shared = "0";\r
2676 }\r
2677 PORT select_n\r
2678 {\r
2679 type = "chipselect_n";\r
2680 width = "1";\r
2681 direction = "input";\r
2682 Is_Enabled = "1";\r
2683 is_shared = "0";\r
2684 }\r
2685 PORT be_n\r
2686 {\r
2687 type = "byteenable_n";\r
2688 width = "2";\r
2689 direction = "input";\r
2690 Is_Enabled = "1";\r
2691 is_shared = "0";\r
2692 }\r
2693 }\r
2694 SYSTEM_BUILDER_INFO \r
2695 {\r
2696 Bus_Type = "avalon_tristate";\r
2697 Write_Wait_States = "2cycles";\r
2698 Read_Wait_States = "2cycles";\r
2699 Hold_Time = "2cycles";\r
2700 Setup_Time = "0cycles";\r
2701 Is_Printable_Device = "1";\r
2702 Address_Alignment = "dynamic";\r
2703 Well_Behaved_Waitrequest = "0";\r
2704 Is_Nonvolatile_Storage = "0";\r
2705 Address_Span = "524288";\r
2706 Read_Latency = "0";\r
2707 Is_Memory_Device = "1";\r
2708 Maximum_Pending_Read_Transactions = "0";\r
2709 Minimum_Uninterrupted_Run_Length = "1";\r
2710 Accepts_Internal_Connections = "1";\r
2711 Write_Latency = "0";\r
2712 Is_Flash = "0";\r
2713 Active_CS_Through_Read_Latency = "0";\r
2714 Data_Width = "16";\r
2715 Address_Width = "18";\r
2716 Maximum_Burst_Size = "1";\r
2717 Register_Incoming_Signals = "0";\r
2718 Register_Outgoing_Signals = "0";\r
2719 Interleave_Bursts = "0";\r
2720 Linewrap_Bursts = "0";\r
2721 Burst_On_Burst_Boundaries_Only = "0";\r
2722 Always_Burst_Max_Burst = "0";\r
2723 Is_Big_Endian = "0";\r
2724 Is_Enabled = "1";\r
2725 MASTERED_BY ext_bus_unit/tristate_master\r
2726 {\r
2727 priority = "1";\r
2728 Offset_Address = "0x00080000";\r
2729 }\r
2730 Base_Address = "0x00080000";\r
2731 Address_Group = "0";\r
2732 IRQ_MASTER cpu/data_master\r
2733 {\r
2734 IRQ_Number = "NC";\r
2735 }\r
2736 }\r
2737 }\r
2738 class = "no_legacy_module";\r
2739 class_version = "7.080902";\r
2740 gtf_class_name = "ext_ram2_16";\r
2741 gtf_class_version = "1.0.1";\r
2742 SYSTEM_BUILDER_INFO \r
2743 {\r
2744 Do_Not_Generate = "1";\r
2745 Instantiate_In_System_Module = "0";\r
2746 Is_Bridge = "0";\r
2747 Is_Enabled = "1";\r
2748 Clock_Source = "sys_clk";\r
2749 Has_Clock = "1";\r
2750 View \r
2751 {\r
2752 MESSAGES \r
2753 {\r
2754 }\r
2755 }\r
2756 }\r
2757 WIZARD_SCRIPT_ARGUMENTS \r
2758 {\r
2759 terminated_ports \r
2760 {\r
2761 }\r
2762 }\r
2763 }\r
2764 MODULE sys_clk_timer\r
2765 {\r
2766 SLAVE s1\r
2767 {\r
2768 PORT_WIRING \r
2769 {\r
2770 PORT clk\r
2771 {\r
2772 type = "clk";\r
2773 width = "1";\r
2774 direction = "input";\r
2775 Is_Enabled = "1";\r
2776 }\r
2777 PORT reset_n\r
2778 {\r
2779 type = "reset_n";\r
2780 width = "1";\r
2781 direction = "input";\r
2782 Is_Enabled = "1";\r
2783 }\r
2784 PORT irq\r
2785 {\r
2786 type = "irq";\r
2787 width = "1";\r
2788 direction = "output";\r
2789 Is_Enabled = "1";\r
2790 }\r
2791 PORT address\r
2792 {\r
2793 type = "address";\r
2794 width = "3";\r
2795 direction = "input";\r
2796 Is_Enabled = "1";\r
2797 }\r
2798 PORT writedata\r
2799 {\r
2800 type = "writedata";\r
2801 width = "16";\r
2802 direction = "input";\r
2803 Is_Enabled = "1";\r
2804 }\r
2805 PORT readdata\r
2806 {\r
2807 type = "readdata";\r
2808 width = "16";\r
2809 direction = "output";\r
2810 Is_Enabled = "1";\r
2811 }\r
2812 PORT chipselect\r
2813 {\r
2814 type = "chipselect";\r
2815 width = "1";\r
2816 direction = "input";\r
2817 Is_Enabled = "1";\r
2818 }\r
2819 PORT write_n\r
2820 {\r
2821 type = "write_n";\r
2822 width = "1";\r
2823 direction = "input";\r
2824 Is_Enabled = "1";\r
2825 }\r
2826 }\r
2827 SYSTEM_BUILDER_INFO \r
2828 {\r
2829 Has_IRQ = "1";\r
2830 Bus_Type = "avalon";\r
2831 Write_Wait_States = "0cycles";\r
2832 Read_Wait_States = "1cycles";\r
2833 Hold_Time = "0cycles";\r
2834 Setup_Time = "0cycles";\r
2835 Is_Printable_Device = "0";\r
2836 Address_Alignment = "native";\r
2837 Well_Behaved_Waitrequest = "0";\r
2838 Is_Nonvolatile_Storage = "0";\r
2839 Read_Latency = "0";\r
2840 Is_Memory_Device = "0";\r
2841 Maximum_Pending_Read_Transactions = "0";\r
2842 Minimum_Uninterrupted_Run_Length = "1";\r
2843 Accepts_Internal_Connections = "1";\r
2844 Write_Latency = "0";\r
2845 Is_Flash = "0";\r
2846 Data_Width = "16";\r
2847 Address_Width = "3";\r
2848 Maximum_Burst_Size = "1";\r
2849 Register_Incoming_Signals = "0";\r
2850 Register_Outgoing_Signals = "0";\r
2851 Interleave_Bursts = "0";\r
2852 Linewrap_Bursts = "0";\r
2853 Burst_On_Burst_Boundaries_Only = "0";\r
2854 Always_Burst_Max_Burst = "0";\r
2855 Is_Big_Endian = "0";\r
2856 Is_Enabled = "1";\r
2857 MASTERED_BY cpu/data_master\r
2858 {\r
2859 priority = "1";\r
2860 Offset_Address = "0x00000000";\r
2861 }\r
2862 IRQ_MASTER cpu/data_master\r
2863 {\r
2864 IRQ_Number = "1";\r
2865 }\r
2866 Base_Address = "0x00000000";\r
2867 Address_Group = "0";\r
2868 }\r
2869 }\r
2870 class = "altera_avalon_timer";\r
2871 class_version = "7.080902";\r
2872 iss_model_name = "altera_avalon_timer";\r
2873 SYSTEM_BUILDER_INFO \r
2874 {\r
2875 Instantiate_In_System_Module = "1";\r
2876 Is_Enabled = "1";\r
2877 Top_Level_Ports_Are_Enumerated = "1";\r
2878 View \r
2879 {\r
2880 Settings_Summary = "Timer with 10 ms timeout period.";\r
2881 Is_Collapsed = "1";\r
2882 MESSAGES \r
2883 {\r
2884 }\r
2885 }\r
2886 Clock_Source = "ext_clk";\r
2887 Has_Clock = "1";\r
2888 }\r
2889 WIZARD_SCRIPT_ARGUMENTS \r
2890 {\r
2891 always_run = "0";\r
2892 fixed_period = "0";\r
2893 snapshot = "1";\r
2894 period = "10";\r
2895 period_units = "ms";\r
2896 reset_output = "0";\r
2897 timeout_pulse_output = "0";\r
2898 load_value = "159999";\r
2899 counter_size = "32";\r
2900 mult = "0.0010";\r
2901 ticks_per_sec = "100";\r
2902 }\r
2903 HDL_INFO \r
2904 {\r
2905 Precompiled_Simulation_Library_Files = "";\r
2906 Simulation_HDL_Files = "";\r
2907 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sys_clk_timer.v";\r
2908 Synthesis_Only_Files = "";\r
2909 }\r
2910 PORT_WIRING \r
2911 {\r
2912 }\r
2913 }\r
2914 }\r