eth_ocm/inc/eth_ocm_regs.h

   1 #ifndef __ETH_OCM_REGS_H__
   2 #define __ETH_OCM_REGS_H__
   3
   4 #include <io.h>         //Altera IOWR and IORD
   5 #include "alt_types.h"  //Altera defined types
   6
   7 #define ETH_OCM_MODER       0x00
   8 #define ETH_OCM_INT_SOURCE  0x01
   9 #define ETH_OCM_INT_MASK    0x02
  10 #define ETH_OCM_IPGT        0x03
  11 #define ETH_OCM_IPGR1       0x04
  12 #define ETH_OCM_IPGR2       0x05
  13 #define ETH_OCM_PACKETLEN   0x06
  14 #define ETH_OCM_COLLCONF    0x07
  15 #define ETH_OCM_TX_BD_NUM   0x08
  16 #define ETH_OCM_CTRLMODER   0x09
  17 #define ETH_OCM_MIIMODER    0x0A
  18 #define ETH_OCM_MIICOMMAND  0x0B
  19 #define ETH_OCM_MIIADDRESS  0x0C
  20 #define ETH_OCM_MIITX_DATA  0x0D
  21 #define ETH_OCM_MIIRX_DATA  0x0E
  22 #define ETH_OCM_MIISTATUS   0x0F
  23 #define ETH_OCM_MAC_ADDR0   0x10
  24 #define ETH_OCM_MAC_ADDR1   0x11
  25 #define ETH_OCM_ETH_HASH0   0x12
  26 #define ETH_OCM_ETH_HASH1   0x13
  27 #define ETH_OCM_ETH_CTRL    0x14
  28 #define ETH_OCM_DESC_START  0x100
  29 #define ETH_OCM_DESC_END    0x1FF
  30
  31 //Mode register bit masks
  32 #define IOWR_ETH_OCM_MODER(base, dat)   \
  33     IOWR(base, ETH_OCM_MODER, dat)
  34 #define IORD_ETH_OCM_MODER(base)    \
  35     IORD(base, ETH_OCM_MODER)
  36
  37 #define IOWR_ETH_OCM_INT_SOURCE(base, dat)  \
  38     IOWR(base, ETH_OCM_INT_SOURCE, dat)
  39 #define IORD_ETH_OCM_INT_SOURCE(base)   \
  40     IORD(base, ETH_OCM_INT_SOURCE)
  41
  42 #define IOWR_ETH_OCM_INT_MASK(base, dat)    \
  43     IOWR(base, ETH_OCM_INT_MASK, dat)
  44 #define IORD_ETH_OCM_INT_MASK(base) \
  45     IORD(base, ETH_OCM_INT_MASK)
  46
  47 #define IOWR_ETH_OCM_IPGT(base, dat)    \
  48     IOWR(base, ETH_OCM_IPGT, dat)
  49 #define IORD_ETH_OCM_IPGT(base)         \
  50     IORD(base, ETH_OCM_IPGT)
  51
  52 #define IOWR_ETH_OCM_IPGR1(base, dat)   \
  53     IOWR(base, ETH_OCM_IPGR1, dat)
  54 #define IORD_ETH_OCM_IPGR1(base)    \
  55     IORD(base, ETH_OCM_IPGR1)
  56
  57 #define IOWR_ETH_OCM_IPGR2(base, dat)   \
  58     IOWR(base, ETH_OCM_IPGR2, dat)
  59 #define IORD_ETH_OCM_IPGR2(base)    \
  60     IORD(base, ETH_OCM_IPGR2)
  61
  62 #define IOWR_ETH_OCM_PACKETLEN(base, dat)   \
  63     IOWR(base, ETH_OCM_PACKETLEN, dat)
  64 #define IORD_ETH_OCM_PACKETLEN(base)    \
  65     IORD(base, ETH_OCM_PACKETLEN)
  66
  67 #define IOWR_ETH_OCM_COLLCONF(base, dat)    \
  68     IOWR(base, ETH_OCM_COLLCONF, dat)
  69 #define IORD_ETH_OCM_COLLCONF(base) \
  70     IORD(base, ETH_OCM_COLLCONF)
  71
  72 #define IOWR_ETH_OCM_TX_BD_NUM(base, dat)   \
  73     IOWR(base, ETH_OCM_TX_BD_NUM, dat)
  74 #define IORD_ETH_OCM_TX_BD_NUM(base)    \
  75     IORD(base, ETH_OCM_TX_BD_NUM)
  76
  77 #define IOWR_ETH_OCM_CTRLMODER(base, dat)   \
  78     IOWR(base, ETH_OCM_CTRLMODER, dat)
  79 #define IORD_ETH_OCM_CTRLMODER(base)    \
  80     IORD(base, ETH_OCM_CTRLMODER)
  81
  82 #define IOWR_ETH_OCM_MIIMODER(base, dat) \
  83     IOWR(base, ETH_OCM_MIIMODER, dat)
  84 #define IORD_ETH_OCM_MIIMODER(base)  \
  85     IORD(base, ETH_OCM_MIIMODER)
  86
  87 #define IOWR_ETH_OCM_MIICOMMAND(base, dat)  \
  88     IOWR(base, ETH_OCM_MIICOMMAND, dat)
  89 #define IORD_ETH_OCM_MIICOMMAND(base)   \
  90     IORD(base, ETH_OCM_MIICOMMAND)
  91
  92 #define IOWR_ETH_OCM_MIIADDRESS(base, dat)  \
  93     IOWR(base, ETH_OCM_MIIADDRESS, dat)
  94 #define IORD_ETH_OCM_MIIADDRESS(base)   \
  95     IORD(base, ETH_OCM_MIIADDRESS)
  96
  97 #define IOWR_ETH_OCM_MIITX_DATA(base, dat)  \
  98     IOWR(base, ETH_OCM_MIITX_DATA, dat)
  99 #define IORD_ETH_OCM_MIITX_DATA(base)   \
 100     IORD(base, ETH_OCM_MIITX_DATA)
 101
 102 #define IOWR_ETH_OCM_MIIRX_DATA(base, dat)  \
 103     IOWR(base, ETH_OCM_MIIRX_DATA, dat)
 104 #define IORD_ETH_OCM_MIIRX_DATA(base)   \
 105     IORD(base, ETH_OCM_MIIRX_DATA)
 106
 107 #define IOWR_ETH_OCM_MIISTATUS(base, dat)   \
 108     IOWR(base, ETH_OCM_MIISTATUS, dat)
 109 #define IORD_ETH_OCM_MIISTATUS(base)    \
 110     IORD(base, ETH_OCM_MIISTATUS)
 111
 112 #define IOWR_ETH_OCM_MAC_ADDR0(base, dat)   \
 113     IOWR(base, ETH_OCM_MAC_ADDR0, dat)
 114 #define IORD_ETH_OCM_MAC_ADDR0(base)    \
 115     IORD(base, ETH_OCM_MAC_ADDR0)
 116
 117 #define IOWR_ETH_OCM_MAC_ADDR1(base, dat)   \
 118     IOWR(base, ETH_OCM_MAC_ADDR1, dat)
 119 #define IORD_ETH_OCM_MAC_ADDR1(base)    \
 120     IORD(base, ETH_OCM_MAC_ADDR1)
 121
 122 #define IOWR_ETH_OCM_ETH_HASH0(base, dat)   \
 123     IOWR(base, ETH_OCM_ETH_HASH0, dat)
 124 #define IORD_ETH_OCM_ETH_HASH0(base)    \
 125     IORD(base, ETH_OCM_ETH_HASH0)
 126
 127 #define IOWR_ETH_OCM_ETH_HASH1(base, dat)   \
 128     IOWR(base, ETH_OCM_ETH_HASH1, dat)
 129 #define IORD_ETH_OCM_ETH_HASH1(base)    \
 130     IORD(base, ETH_OCM_ETH_HASH1)
 131
 132 #define IOWR_ETH_OCM_ETH_CTRL(base, dat)    \
 133     IOWR(base, ETH_OCM_ETH_CTRL, dat)
 134 #define IORD_ETH_OCM_ETH_CTRL(base) \
 135     IORD(base, ETH_OCM_ETH_CTRL)
 136
 137 #define ETH_OCM_MODER_RECSMALL_MSK      0x00010000
 138 #define ETH_OCM_MODER_RECSMALL_OFST     16
 139 #define ETH_OCM_MODER_PAD_MSK           0x00008000
 140 #define ETH_OCM_MODER_PAD_OFST          15
 141 #define ETH_OCM_MODER_HUGEN_MSK         0x00004000
 142 #define ETH_OCM_MODER_HUGEN_OFST        14
 143 #define ETH_OCM_MODER_CRCEN_MSK         0x00002000
 144 #define ETH_OCM_MODER_CRCEN_OFST        13
 145 #define ETH_OCM_MODER_DLYCRCEN_MSK      0x00001000
 146 #define ETH_OCM_MODER_DLYCRCEN_OFST     12
 147 #define ETH_OCM_MODER_FULLD_MSK         0x00000400
 148 #define ETH_OCM_MODER_FULLD_OFST        10
 149 #define ETH_OCM_MODER_EXDFREN_MSK       0x00000200
 150 #define ETH_OCM_MODER_EXDFREN_OFST      9
 151 #define ETH_OCM_MODER_NOBKOF_MSK        0x00000100
 152 #define ETH_OCM_MODER_NOBKOF_OFST       8
 153 #define ETH_OCM_MODER_LOOPBCK_MSK       0x00000080
 154 #define ETH_OCM_MODER_LOOPBCK_OFST      7
 155 #define ETH_OCM_MODER_IFG_MSK           0x00000040
 156 #define ETH_OCM_MODER_IFG_OFST          6
 157 #define ETH_OCM_MODER_PRO_MSK           0x00000020
 158 #define ETH_OCM_MODER_PRO_OFST          5
 159 #define ETH_OCM_MODER_IAM_MSK           0x00000010
 160 #define ETH_OCM_MODER_IAM_OFST          4
 161 #define ETH_OCM_MODER_BRO_MSK           0x00000008
 162 #define ETH_OCM_MODER_BRO_OFST          3
 163 #define ETH_OCM_MODER_NOPRE_MSK         0x00000004
 164 #define ETH_OCM_MODER_NOPRE_OFST        2
 165 #define ETH_OCM_MODER_TXEN_MSK          0x00000002
 166 #define ETH_OCM_MODER_TXEN_OFST         1
 167 #define ETH_OCM_MODER_RXEN_MSK          0x00000001
 168 #define ETH_OCM_MODER_RXEN_OFST         0
 169 //End of bit masks for MODE register
 170
 171 //Define bit masks for INT_SOURCE and INT_MASK registers
 172 #define ETH_OCM_INT_MASK_RXC_MSK        0x00000040
 173 #define ETH_OCM_INT_MASK_RXC_OFST       6
 174 #define ETH_OCM_INT_MASK_TXC_MSK        0x00000020
 175 #define ETH_OCM_INT_MASK_TXC_OFST       5
 176 #define ETH_OCM_INT_MASK_BUSY_MSK       0x00000010
 177 #define ETH_OCM_INT_MASK_BUSY_OFST      4
 178 #define ETH_OCM_INT_MASK_RXE_MSK        0x00000008
 179 #define ETH_OCM_INT_MASK_RXE_OFST       3
 180 #define ETH_OCM_INT_MASK_RXB_MSK        0x00000004
 181 #define ETH_OCM_INT_MASK_RXB_OFST       2
 182 #define ETH_OCM_INT_MASK_TXE_MSK        0x00000002
 183 #define ETH_OCM_INT_MASK_TXE_OFST       1
 184 #define ETH_OCM_INT_MASK_TXB_MSK        0x00000001
 185 #define ETH_OCM_INT_MASK_TXB_OFST       0
 186 //End of bit masks for INT_SOURCE register
 187
 188 //Bit masks for the PACKETLEN register
 189 #define ETH_OCM_PACKETLEN_MINFL_MSK     0xFFFF0000
 190 #define ETH_OCM_PACKETLEN_MINFL_OFST    16
 191 #define ETH_OCM_PACKETLEN_MAXFL_MSK     0x0000FFFF
 192 #define ETH_OCM_PACKETLEN_MAXFL_OFST    0
 193 //End bit masks for PACKETLEN register
 194
 195 //Bit masks for COLLCONF register
 196 #define ETH_OCM_COLLCONF_MAXRET_MSK     0x000F0000
 197 #define ETH_OCM_COLLCONF_MAXRET_OFST    16
 198 #define ETH_OCM_COLLCONF_COLLVALID_MSK  0x0000003F
 199 #define ETH_OCM_COLLCONF_COLLVALID_OFST 0
 200 //End bit masks for COLLCONF register
 201
 202 //Bit masks for CTRLMODER register
 203 #define ETH_OCM_CTRLMODER_TXFLOW_MSK    0x00000004
 204 #define ETH_OCM_CTRLMODER_TXFLOW_OFST   2
 205 #define ETH_OCM_CTRLMODER_RXFLOW_MSK    0x00000002
 206 #define ETH_OCM_CTRLMODER_RXFLOW_OFST   1
 207 #define ETH_OCM_CTRLMODER_PASSALL_MSK   0x00000001
 208 #define ETH_OCM_CTRLMODER_PASSALL_OFST  0
 209 //End bit masks for CTRLMODER register
 210
 211 //Bit masks for MIIMODER register
 212 #define ETH_OCM_MIIMODER_MIINOPRE_MSK   0x00000100
 213 #define ETH_OCM_MIIMODER_MIINOPRE_OFST  8
 214 #define ETH_OCM_MIIMODER_CLKDIV_MSK     0x000000FF
 215 #define ETH_OCM_MIIMODER_CLKDIV_OFST    0
 216 //End bit masks for MIIMODER register
 217
 218 //Bit masks for MIICOMMAND register
 219 #define ETH_OCM_MIICOMMAND_WCTRLDATA_MSK    0x00000004
 220 #define ETH_OCM_MIICOMMAND_WCTRLDATA_OFST   2
 221 #define ETH_OCM_MIICOMMAND_RSTAT_MSK        0x00000002
 222 #define ETH_OCM_MIICOMMAND_RSTAT_OFST       1
 223 #define ETH_OCM_MIICOMMAND_SCANSTAT_MSK     0x00000001
 224 #define ETH_OCM_MIICOMMAND_SCANSTAT_OFST    0
 225 //End bit masks for MIICOMMAND register
 226
 227 //Bit masks for MIIADDRESS register
 228 #define ETH_OCM_MIIADDRESS_RGAD_MSK         0x00001F00
 229 #define ETH_OCM_MIIADDRESS_RGAD_OFST        8
 230 #define ETH_OCM_MIIADDRESS_FIAD_MSK         0x0000001F
 231 #define ETH_OCM_MIIADDRESS_FIAD_OFST        0
 232 //End bit masks for MIIADDRESS register
 233
 234 //Bit masks for MIISTATUS register
 235 #define ETH_OCM_MIISTATUS_NVALID_MSK        0x00000004
 236 #define ETH_OCM_MIISTATUS_NVALID_OFST       2
 237 #define ETH_OCM_MIISTATUS_BUSY_MSK          0x00000002
 238 #define ETH_OCM_MIISTATUS_BUSY_OFST         1
 239 #define ETH_OCM_MIISTATUS_LINKFAIL_MSK      0x00000001
 240 #define ETH_OCM_MIISTATUS_LINKFAIL_OFST     0
 241 //End bit masks for MIISTATUS register
 242
 243 //Bit masks for TXCTRL register
 244 #define ETH_OCM_TXCTRL_TXPAUSERA_MSK        0x00010000
 245 #define ETH_OCM_TXCTRL_TXPAUSERA_OFST       16
 246 #define ETH_OCM_TXCTRL_TXPAUSETV_MSK        0x0000FFFF
 247 #define ETH_OCM_TXCTRL_TXPAUSETV_OFST       0
 248 //End bit masks for TXCTRL register
 249
 250 #endif //__ETH_OCM_REGS_H__