eth_ocm/test_fifo.v

   1 // megafunction wizard: %FIFO%
   2 // GENERATION: STANDARD
   3 // VERSION: WM1.0
   4 // MODULE: dcfifo
   5
   6 // ============================================================
   7 // File Name: test_fifo.v
   8 // Megafunction Name(s):
   9 //                      dcfifo
  10 //
  11 // Simulation Library Files(s):
  12 //                      altera_mf
  13 // ============================================================
  14 // ************************************************************
  15 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
  16 //
  17 // 7.2 Build 175 11/20/2007 SP 1 SJ Full Version
  18 // ************************************************************
  19
  20
  21 //Copyright (C) 1991-2007 Altera Corporation
  22 //Your use of Altera Corporation's design tools, logic functions
  23 //and other software and tools, and its AMPP partner logic
  24 //functions, and any output files from any of the foregoing
  25 //(including device programming or simulation files), and any
  26 //associated documentation or information are expressly subject
  27 //to the terms and conditions of the Altera Program License
  28 //Subscription Agreement, Altera MegaCore Function License
  29 //Agreement, or other applicable license agreement, including,
  30 //without limitation, that your use is for the sole purpose of
  31 //programming logic devices manufactured by Altera and sold by
  32 //Altera or its authorized distributors.  Please refer to the
  33 //applicable agreement for further details.
  34
  35
  36 // synopsys translate_off
  37 `timescale 1 ps / 1 ps
  38 // synopsys translate_on
  39 module test_fifo (
  40         aclr,
  41         data,
  42         rdclk,
  43         rdreq,
  44         wrclk,
  45         wrreq,
  46         q,
  47         rdempty,
  48         rdusedw,
  49         wrfull);
  50
  51         input     aclr;
  52         input   [35:0]  data;
  53         input     rdclk;
  54         input     rdreq;
  55         input     wrclk;
  56         input     wrreq;
  57         output  [35:0]  q;
  58         output    rdempty;
  59         output  [9:0]  rdusedw;
  60         output    wrfull;
  61
  62         wire  sub_wire0;
  63         wire  sub_wire1;
  64         wire [35:0] sub_wire2;
  65         wire [9:0] sub_wire3;
  66         wire  rdempty = sub_wire0;
  67         wire  wrfull = sub_wire1;
  68         wire [35:0] q = sub_wire2[35:0];
  69         wire [9:0] rdusedw = sub_wire3[9:0];
  70
  71         dcfifo  dcfifo_component (
  72                                 .wrclk (wrclk),
  73                                 .rdreq (rdreq),
  74                                 .aclr (aclr),
  75                                 .rdclk (rdclk),
  76                                 .wrreq (wrreq),
  77                                 .data (data),
  78                                 .rdempty (sub_wire0),
  79                                 .wrfull (sub_wire1),
  80                                 .q (sub_wire2),
  81                                 .rdusedw (sub_wire3)
  82                                 // synopsys translate_off
  83                                 ,
  84                                 .rdfull (),
  85                                 .wrempty (),
  86                                 .wrusedw ()
  87                                 // synopsys translate_on
  88                                 );
  89         defparam
  90                 dcfifo_component.intended_device_family = "Cyclone II",
  91                 dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=7,",
  92                 dcfifo_component.lpm_numwords = 1024,
  93                 dcfifo_component.lpm_showahead = "ON",
  94                 dcfifo_component.lpm_type = "dcfifo",
  95                 dcfifo_component.lpm_width = 36,
  96                 dcfifo_component.lpm_widthu = 10,
  97                 dcfifo_component.overflow_checking = "OFF",
  98                 dcfifo_component.rdsync_delaypipe = 5,
  99                 dcfifo_component.underflow_checking = "OFF",
 100                 dcfifo_component.use_eab = "ON",
 101                 dcfifo_component.write_aclr_synch = "OFF",
 102                 dcfifo_component.wrsync_delaypipe = 5;
 103
 104
 105 endmodule
 106
 107 // ============================================================
 108 // CNX file retrieval info
 109 // ============================================================
 110 // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
 111 // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
 112 // Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
 113 // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
 114 // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
 115 // Retrieval info: PRIVATE: Clock NUMERIC "4"
 116 // Retrieval info: PRIVATE: Depth NUMERIC "1024"
 117 // Retrieval info: PRIVATE: Empty NUMERIC "1"
 118 // Retrieval info: PRIVATE: Full NUMERIC "1"
 119 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
 120 // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
 121 // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
 122 // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
 123 // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
 124 // Retrieval info: PRIVATE: Optimize NUMERIC "1"
 125 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 126 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 127 // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
 128 // Retrieval info: PRIVATE: UsedW NUMERIC "1"
 129 // Retrieval info: PRIVATE: Width NUMERIC "36"
 130 // Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
 131 // Retrieval info: PRIVATE: diff_widths NUMERIC "0"
 132 // Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
 133 // Retrieval info: PRIVATE: output_width NUMERIC "36"
 134 // Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
 135 // Retrieval info: PRIVATE: rsFull NUMERIC "0"
 136 // Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
 137 // Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
 138 // Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
 139 // Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
 140 // Retrieval info: PRIVATE: wsFull NUMERIC "1"
 141 // Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
 142 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
 143 // Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=7,"
 144 // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
 145 // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
 146 // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
 147 // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "36"
 148 // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
 149 // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
 150 // Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
 151 // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
 152 // Retrieval info: CONSTANT: USE_EAB STRING "ON"
 153 // Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
 154 // Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
 155 // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
 156 // Retrieval info: USED_PORT: data 0 0 36 0 INPUT NODEFVAL data[35..0]
 157 // Retrieval info: USED_PORT: q 0 0 36 0 OUTPUT NODEFVAL q[35..0]
 158 // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
 159 // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
 160 // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
 161 // Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL rdusedw[9..0]
 162 // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
 163 // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
 164 // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
 165 // Retrieval info: CONNECT: @data 0 0 36 0 data 0 0 36 0
 166 // Retrieval info: CONNECT: q 0 0 36 0 @q 0 0 36 0
 167 // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
 168 // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
 169 // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
 170 // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
 171 // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
 172 // Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0
 173 // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
 174 // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
 175 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 176 // Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo.v TRUE
 177 // Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo.inc FALSE
 178 // Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo.cmp FALSE
 179 // Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo.bsf FALSE
 180 // Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo_inst.v FALSE
 181 // Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo_bb.v FALSE
 182 // Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo_waveforms.html FALSE
 183 // Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo_wave*.jpg FALSE
 184 // Retrieval info: LIB_FILE: altera_mf