eth_ocm/eth_avalon_dma_fifo.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  eth_avalon_dma_fifo.v                                       ////
   4 ////                                                              ////
   5 ////  This file is a patch used in conjunction with the           ////
   6 ////  Ethernet IP core project.                                   ////
   7 ////  http://www.opencores.org/projects/ethmac/                   ////
   8 ////                                                              ////
   9 ////  Author(s):                                                  ////
  10 ////      - Jakob Jones (jrjonsie@gmail.com)                      ////
  11 ////                                                              ////
  12 ////  All additional information is available in the Readme.txt   ////
  13 ////  file.                                                       ////
  14 ////                                                              ////
  15 //////////////////////////////////////////////////////////////////////
  16 module eth_avalon_dma_fifo #(   parameter   DEPTH=1024,
  17                                 parameter   WIDTH=36) (
  18     input                   aclr,
  19     input   [WIDTH - 1:0]   data,
  20     input                   rdclk,
  21     input                   rdreq,
  22     input                   wrclk,
  23     input                   wrreq,
  24     output  [WIDTH - 1:0]   q,
  25     output                  rdempty,
  26     output  [(clogb2(DEPTH)-2):0]   rdusedw,
  27     output  [(clogb2(DEPTH)-2):0]   wrusedw,
  28     output                  wrfull
  29 );
  30
  31 `include "eth_avalon_functions.v"
  32
  33 localparam  AWIDTH = clogb2(DEPTH) - 1;
  34
  35 dcfifo  dcfifo_component (
  36     .aclr       (aclr       ),
  37     .wrclk      (wrclk      ),
  38     .rdreq      (rdreq      ),
  39     .rdclk      (rdclk      ),
  40     .wrreq      (wrreq      ),
  41     .data       (data       ),
  42     .rdempty    (rdempty    ),
  43     .wrfull     (wrfull     ),
  44     .q          (q          ),
  45     .rdusedw    (rdusedw    ),
  46     .wrusedw    (wrusedw    )
  47     // synopsys translate_off
  48     ,
  49     .rdfull     (),
  50     .wrempty    (),
  51     // synopsys translate_on
  52     );
  53     defparam
  54 //      dcfifo_component.intended_device_family = "Cyclone II",
  55                 dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=7,",
  56                 dcfifo_component.lpm_numwords = DEPTH,
  57                 dcfifo_component.lpm_showahead = "ON",
  58                 dcfifo_component.lpm_type = "dcfifo",
  59                 dcfifo_component.lpm_width = WIDTH,
  60                 dcfifo_component.lpm_widthu = AWIDTH,
  61                 dcfifo_component.overflow_checking = "OFF",
  62                 dcfifo_component.rdsync_delaypipe = 5,
  63                 dcfifo_component.underflow_checking = "OFF",
  64                 dcfifo_component.use_eab = "ON",
  65                 dcfifo_component.write_aclr_synch = "OFF",
  66                 dcfifo_component.wrsync_delaypipe = 5;
  67 endmodule