eth_ocm/eth_outputcontrol.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  eth_outputcontrol.v                                         ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects/ethmac/                   ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Igor Mohor (igorM@opencores.org)                      ////
  10 ////                                                              ////
  11 ////  All additional information is avaliable in the Readme.txt   ////
  12 ////  file.                                                       ////
  13 ////                                                              ////
  14 //////////////////////////////////////////////////////////////////////
  15 ////                                                              ////
  16 //// Copyright (C) 2001 Authors                                   ////
  17 ////                                                              ////
  18 //// This source file may be used and distributed without         ////
  19 //// restriction provided that this copyright statement is not    ////
  20 //// removed from the file and that any derivative work contains  ////
  21 //// the original copyright notice and the associated disclaimer. ////
  22 ////                                                              ////
  23 //// This source file is free software; you can redistribute it   ////
  24 //// and/or modify it under the terms of the GNU Lesser General   ////
  25 //// Public License as published by the Free Software Foundation; ////
  26 //// either version 2.1 of the License, or (at your option) any   ////
  27 //// later version.                                               ////
  28 ////                                                              ////
  29 //// This source is distributed in the hope that it will be       ////
  30 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  31 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  32 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  33 //// details.                                                     ////
  34 ////                                                              ////
  35 //// You should have received a copy of the GNU Lesser General    ////
  36 //// Public License along with this source; if not, download it   ////
  37 //// from http://www.opencores.org/lgpl.shtml                     ////
  38 ////                                                              ////
  39 //////////////////////////////////////////////////////////////////////
  40 //
  41 // CVS Revision History
  42 //
  43 // $Log: eth_outputcontrol.v,v $
  44 // Revision 1.4  2002/07/09 20:11:59  mohor
  45 // Comment removed.
  46 //
  47 // Revision 1.3  2002/01/23 10:28:16  mohor
  48 // Link in the header changed.
  49 //
  50 // Revision 1.2  2001/10/19 08:43:51  mohor
  51 // eth_timescale.v changed to timescale.v This is done because of the
  52 // simulation of the few cores in a one joined project.
  53 //
  54 // Revision 1.1  2001/08/06 14:44:29  mohor
  55 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
  56 // Include files fixed to contain no path.
  57 // File names and module names changed ta have a eth_ prologue in the name.
  58 // File eth_timescale.v is used to define timescale
  59 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
  60 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
  61 // and Mdo_OE. The bidirectional signal must be created on the top level. This
  62 // is done due to the ASIC tools.
  63 //
  64 // Revision 1.1  2001/07/30 21:23:42  mohor
  65 // Directory structure changed. Files checked and joind together.
  66 //
  67 // Revision 1.3  2001/06/01 22:28:56  mohor
  68 // This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
  69 //
  70 //
  71
  72 `include "timescale.v"
  73
  74 module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
  75
  76 parameter Tp = 1;
  77
  78 input         Clk;                // Host Clock
  79 input         Reset;              // General Reset
  80 input         WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)
  81 input         NoPre;              // No Preamble (no 32-bit preamble)
  82 input         InProgress;         // Operation in progress
  83 input         ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal
  84 input   [6:0] BitCounter;         // Bit Counter
  85 input         MdcEn_n;            // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
  86
  87 output        Mdo;                // MII Management Data Output
  88 output        MdoEn;              // MII Management Data Output Enable
  89
  90 wire          SerialEn;
  91
  92 reg           MdoEn_2d;
  93 reg           MdoEn_d;
  94 reg           MdoEn;
  95
  96 reg           Mdo_2d;
  97 reg           Mdo_d;
  98 reg           Mdo;                // MII Management Data Output
  99
 100
 101
 102 // Generation of the Serial Enable signal (enables the serialization of the data)
 103 assign SerialEn =  WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
 104                 | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
 105
 106
 107 // Generation of the MdoEn signal
 108 always @ (posedge Clk or posedge Reset)
 109 begin
 110   if(Reset)
 111     begin
 112       MdoEn_2d <= #Tp 1'b0;
 113       MdoEn_d <= #Tp 1'b0;
 114       MdoEn <= #Tp 1'b0;
 115     end
 116   else
 117     begin
 118       if(MdcEn_n)
 119         begin
 120           MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32;
 121           MdoEn_d <= #Tp MdoEn_2d;
 122           MdoEn <= #Tp MdoEn_d;
 123         end
 124     end
 125 end
 126
 127
 128 // Generation of the Mdo signal.
 129 always @ (posedge Clk or posedge Reset)
 130 begin
 131   if(Reset)
 132     begin
 133       Mdo_2d <= #Tp 1'b0;
 134       Mdo_d <= #Tp 1'b0;
 135       Mdo <= #Tp 1'b0;
 136     end
 137   else
 138     begin
 139       if(MdcEn_n)
 140         begin
 141           Mdo_2d <= #Tp ~SerialEn & BitCounter<32;
 142           Mdo_d <= #Tp ShiftedBit | Mdo_2d;
 143           Mdo <= #Tp Mdo_d;
 144         end
 145     end
 146 end
 147
 148
 149
 150 endmodule