eth_ocm/eth_registers.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  eth_registers.v                                             ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects/ethmac/                   ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Igor Mohor (igorM@opencores.org)                      ////
  10 ////                                                              ////
  11 ////  *NOTE* This file has been modified from its original        ////
  12 ////  version. The byte enable functionality has been removed.    ////
  13 ////  CS is a single bit signal. Jakob Jones (jrjonsie@gmail.com) ////
  14 ////                                                              ////
  15 ////  All additional information is avaliable in the Readme.txt   ////
  16 ////  file.                                                       ////
  17 ////                                                              ////
  18 //////////////////////////////////////////////////////////////////////
  19 ////                                                              ////
  20 //// Copyright (C) 2001, 2002 Authors                             ////
  21 ////                                                              ////
  22 //// This source file may be used and distributed without         ////
  23 //// restriction provided that this copyright statement is not    ////
  24 //// removed from the file and that any derivative work contains  ////
  25 //// the original copyright notice and the associated disclaimer. ////
  26 ////                                                              ////
  27 //// This source file is free software; you can redistribute it   ////
  28 //// and/or modify it under the terms of the GNU Lesser General   ////
  29 //// Public License as published by the Free Software Foundation; ////
  30 //// either version 2.1 of the License, or (at your option) any   ////
  31 //// later version.                                               ////
  32 ////                                                              ////
  33 //// This source is distributed in the hope that it will be       ////
  34 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  35 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  36 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  37 //// details.                                                     ////
  38 ////                                                              ////
  39 //// You should have received a copy of the GNU Lesser General    ////
  40 //// Public License along with this source; if not, download it   ////
  41 //// from http://www.opencores.org/lgpl.shtml                     ////
  42 ////                                                              ////
  43 //////////////////////////////////////////////////////////////////////
  44 //
  45 // CVS Revision History
  46 //
  47 // $Log: eth_registers.v,v $
  48 // Revision 1.29  2005/03/21 20:07:18  igorm
  49 // Some small fixes + some troubles fixed.
  50 //
  51 // Revision 1.28  2004/04/26 15:26:23  igorm
  52 // - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
  53 //   previous update of the core.
  54 // - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
  55 // - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
  56 //   register. (thanks to Mathias and Torbjorn)
  57 // - Multicast reception was fixed. Thanks to Ulrich Gries
  58 //
  59 // Revision 1.27  2004/04/26 11:42:17  igorm
  60 // TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.
  61 //
  62 // Revision 1.26  2003/11/12 18:24:59  tadejm
  63 // WISHBONE slave changed and tested from only 32-bit accesss to byte access.
  64 //
  65 // Revision 1.25  2003/04/18 16:26:25  mohor
  66 // RxBDAddress was updated also when value to r_TxBDNum was written with
  67 // greater value than allowed.
  68 //
  69 // Revision 1.24  2002/11/22 01:57:06  mohor
  70 // Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
  71 // synchronized.
  72 //
  73 // Revision 1.23  2002/11/19 18:13:49  mohor
  74 // r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
  75 //
  76 // Revision 1.22  2002/11/14 18:37:20  mohor
  77 // r_Rst signal does not reset any module any more and is removed from the design.
  78 //
  79 // Revision 1.21  2002/09/10 10:35:23  mohor
  80 // Ethernet debug registers removed.
  81 //
  82 // Revision 1.20  2002/09/04 18:40:25  mohor
  83 // ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
  84 // the control frames connected.
  85 //
  86 // Revision 1.19  2002/08/19 16:01:40  mohor
  87 // Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
  88 // r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
  89 //
  90 // Revision 1.18  2002/08/16 22:28:23  mohor
  91 // Syntax error fixed.
  92 //
  93 // Revision 1.17  2002/08/16 22:23:03  mohor
  94 // Syntax error fixed.
  95 //
  96 // Revision 1.16  2002/08/16 22:14:22  mohor
  97 // Synchronous reset added to all registers. Defines used for width. r_MiiMRst
  98 // changed from bit position 10 to 9.
  99 //
 100 // Revision 1.15  2002/08/14 18:26:37  mohor
 101 // LinkFailRegister is reflecting the status of the PHY's link fail status bit.
 102 //
 103 // Revision 1.14  2002/04/22 14:03:44  mohor
 104 // Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
 105 // or not.
 106 //
 107 // Revision 1.13  2002/02/26 16:18:09  mohor
 108 // Reset values are passed to registers through parameters
 109 //
 110 // Revision 1.12  2002/02/17 13:23:42  mohor
 111 // Define missmatch fixed.
 112 //
 113 // Revision 1.11  2002/02/16 14:03:44  mohor
 114 // Registered trimmed. Unused registers removed.
 115 //
 116 // Revision 1.10  2002/02/15 11:08:25  mohor
 117 // File format fixed a bit.
 118 //
 119 // Revision 1.9  2002/02/14 20:19:41  billditt
 120 // Modified for Address Checking,
 121 // addition of eth_addrcheck.v
 122 //
 123 // Revision 1.8  2002/02/12 17:01:19  mohor
 124 // HASH0 and HASH1 registers added.
 125
 126 // Revision 1.7  2002/01/23 10:28:16  mohor
 127 // Link in the header changed.
 128 //
 129 // Revision 1.6  2001/12/05 15:00:16  mohor
 130 // RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
 131 // instead of the number of RX descriptors).
 132 //
 133 // Revision 1.5  2001/12/05 10:22:19  mohor
 134 // ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
 135 //
 136 // Revision 1.4  2001/10/19 08:43:51  mohor
 137 // eth_timescale.v changed to timescale.v This is done because of the
 138 // simulation of the few cores in a one joined project.
 139 //
 140 // Revision 1.3  2001/10/18 12:07:11  mohor
 141 // Status signals changed, Adress decoding changed, interrupt controller
 142 // added.
 143 //
 144 // Revision 1.2  2001/09/24 15:02:56  mohor
 145 // Defines changed (All precede with ETH_). Small changes because some
 146 // tools generate warnings when two operands are together. Synchronization
 147 // between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
 148 // demands).
 149 //
 150 // Revision 1.1  2001/08/06 14:44:29  mohor
 151 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
 152 // Include files fixed to contain no path.
 153 // File names and module names changed ta have a eth_ prologue in the name.
 154 // File eth_timescale.v is used to define timescale
 155 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
 156 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
 157 // and Mdo_OE. The bidirectional signal must be created on the top level. This
 158 // is done due to the ASIC tools.
 159 //
 160 // Revision 1.2  2001/08/02 09:25:31  mohor
 161 // Unconnected signals are now connected.
 162 //
 163 // Revision 1.1  2001/07/30 21:23:42  mohor
 164 // Directory structure changed. Files checked and joind together.
 165 //
 166 //
 167 //
 168 //
 169 //
 170 //
 171
 172 `include "eth_defines.v"
 173 `include "timescale.v"
 174
 175
 176 module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
 177                       r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
 178                       r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
 179                       r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
 180                       TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
 181                       r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
 182                       r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
 183                       r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
 184                       r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
 185                       LinkFail, r_MAC, WCtrlDataStart, RStatStart,
 186                       UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
 187                       r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
 188                       StartTxDone, TxClk, RxClk, SetPauseTimer
 189                     );
 190
 191 parameter Tp = 1;
 192
 193 input [31:0] DataIn;
 194 input [7:0] Address;
 195
 196 input Rw;
 197 input Cs;
 198 input Clk;
 199 input Reset;
 200
 201 input WCtrlDataStart;
 202 input RStatStart;
 203
 204 input UpdateMIIRX_DATAReg;
 205 input [15:0] Prsd;
 206
 207 output [31:0] DataOut;
 208 reg    [31:0] DataOut;
 209
 210 output r_RecSmall;
 211 output r_Pad;
 212 output r_HugEn;
 213 output r_CrcEn;
 214 output r_DlyCrcEn;
 215 output r_FullD;
 216 output r_ExDfrEn;
 217 output r_NoBckof;
 218 output r_LoopBck;
 219 output r_IFG;
 220 output r_Pro;
 221 output r_Iam;
 222 output r_Bro;
 223 output r_NoPre;
 224 output r_TxEn;
 225 output r_RxEn;
 226 output [31:0] r_HASH0;
 227 output [31:0] r_HASH1;
 228
 229 input TxB_IRQ;
 230 input TxE_IRQ;
 231 input RxB_IRQ;
 232 input RxE_IRQ;
 233 input Busy_IRQ;
 234
 235 output [6:0] r_IPGT;
 236
 237 output [6:0] r_IPGR1;
 238
 239 output [6:0] r_IPGR2;
 240
 241 output [15:0] r_MinFL;
 242 output [15:0] r_MaxFL;
 243
 244 output [3:0] r_MaxRet;
 245 output [5:0] r_CollValid;
 246
 247 output r_TxFlow;
 248 output r_RxFlow;
 249 output r_PassAll;
 250
 251 output r_MiiNoPre;
 252 output [7:0] r_ClkDiv;
 253
 254 output r_WCtrlData;
 255 output r_RStat;
 256 output r_ScanStat;
 257
 258 output [4:0] r_RGAD;
 259 output [4:0] r_FIAD;
 260
 261 output [15:0]r_CtrlData;
 262
 263
 264 input NValid_stat;
 265 input Busy_stat;
 266 input LinkFail;
 267
 268 output [47:0]r_MAC;
 269 output [7:0] r_TxBDNum;
 270 output       int_o;
 271 output [15:0]r_TxPauseTV;
 272 output       r_TxPauseRq;
 273 input        RstTxPauseRq;
 274 input        TxCtrlEndFrm;
 275 input        StartTxDone;
 276 input        TxClk;
 277 input        RxClk;
 278 input        SetPauseTimer;
 279
 280 reg          irq_txb;
 281 reg          irq_txe;
 282 reg          irq_rxb;
 283 reg          irq_rxe;
 284 reg          irq_busy;
 285 reg          irq_txc;
 286 reg          irq_rxc;
 287
 288 reg SetTxCIrq_txclk;
 289 reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
 290 reg SetTxCIrq;
 291 reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
 292
 293 reg SetRxCIrq_rxclk;
 294 reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
 295 reg SetRxCIrq;
 296 reg ResetRxCIrq_sync1;
 297 reg ResetRxCIrq_sync2;
 298 reg ResetRxCIrq_sync3;
 299
 300 wire Write = Cs & Rw;
 301 wire Read  = Cs & ~Rw;
 302
 303 wire MODER_Sel      = (Address == `ETH_MODER_ADR       );
 304 wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR  );
 305 wire INT_MASK_Sel   = (Address == `ETH_INT_MASK_ADR    );
 306 wire IPGT_Sel       = (Address == `ETH_IPGT_ADR        );
 307 wire IPGR1_Sel      = (Address == `ETH_IPGR1_ADR       );
 308 wire IPGR2_Sel      = (Address == `ETH_IPGR2_ADR       );
 309 wire PACKETLEN_Sel  = (Address == `ETH_PACKETLEN_ADR   );
 310 wire COLLCONF_Sel   = (Address == `ETH_COLLCONF_ADR    );
 311
 312 wire CTRLMODER_Sel  = (Address == `ETH_CTRLMODER_ADR   );
 313 wire MIIMODER_Sel   = (Address == `ETH_MIIMODER_ADR    );
 314 wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR  );
 315 wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR  );
 316 wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR  );
 317 wire MAC_ADDR0_Sel  = (Address == `ETH_MAC_ADDR0_ADR   );
 318 wire MAC_ADDR1_Sel  = (Address == `ETH_MAC_ADDR1_ADR   );
 319 wire HASH0_Sel      = (Address == `ETH_HASH0_ADR       );
 320 wire HASH1_Sel      = (Address == `ETH_HASH1_ADR       );
 321 wire TXCTRL_Sel     = (Address == `ETH_TX_CTRL_ADR     );
 322 wire RXCTRL_Sel     = (Address == `ETH_RX_CTRL_ADR     );
 323 wire TX_BD_NUM_Sel  = (Address == `ETH_TX_BD_NUM_ADR   );
 324
 325
 326 wire [2:0] MODER_Wr;
 327 wire [0:0] INT_SOURCE_Wr;
 328 wire [0:0] INT_MASK_Wr;
 329 wire [0:0] IPGT_Wr;
 330 wire [0:0] IPGR1_Wr;
 331 wire [0:0] IPGR2_Wr;
 332 wire [3:0] PACKETLEN_Wr;
 333 wire [2:0] COLLCONF_Wr;
 334 wire [0:0] CTRLMODER_Wr;
 335 wire [1:0] MIIMODER_Wr;
 336 wire [0:0] MIICOMMAND_Wr;
 337 wire [1:0] MIIADDRESS_Wr;
 338 wire [1:0] MIITX_DATA_Wr;
 339 wire       MIIRX_DATA_Wr;
 340 wire [3:0] MAC_ADDR0_Wr;
 341 wire [1:0] MAC_ADDR1_Wr;
 342 wire [3:0] HASH0_Wr;
 343 wire [3:0] HASH1_Wr;
 344 wire [2:0] TXCTRL_Wr;
 345 wire [0:0] TX_BD_NUM_Wr;
 346
 347 assign MODER_Wr[0]       = Write     & MODER_Sel;
 348 assign MODER_Wr[1]       = Write     & MODER_Sel;
 349 assign MODER_Wr[2]       = Write     & MODER_Sel;
 350 assign INT_SOURCE_Wr[0]  = Write     & INT_SOURCE_Sel;
 351 assign INT_MASK_Wr[0]    = Write     & INT_MASK_Sel;
 352 assign IPGT_Wr[0]        = Write     & IPGT_Sel;
 353 assign IPGR1_Wr[0]       = Write     & IPGR1_Sel;
 354 assign IPGR2_Wr[0]       = Write     & IPGR2_Sel;
 355 assign PACKETLEN_Wr[0]   = Write     & PACKETLEN_Sel;
 356 assign PACKETLEN_Wr[1]   = Write     & PACKETLEN_Sel;
 357 assign PACKETLEN_Wr[2]   = Write     & PACKETLEN_Sel;
 358 assign PACKETLEN_Wr[3]   = Write     & PACKETLEN_Sel;
 359 assign COLLCONF_Wr[0]    = Write     & COLLCONF_Sel;
 360 assign COLLCONF_Wr[1]    = 1'b0;  // Not used
 361 assign COLLCONF_Wr[2]    = Write     & COLLCONF_Sel;
 362
 363 assign CTRLMODER_Wr[0]   = Write     & CTRLMODER_Sel;
 364 assign MIIMODER_Wr[0]    = Write     & MIIMODER_Sel;
 365 assign MIIMODER_Wr[1]    = Write     & MIIMODER_Sel;
 366 assign MIICOMMAND_Wr[0]  = Write     & MIICOMMAND_Sel;
 367 assign MIIADDRESS_Wr[0]  = Write     & MIIADDRESS_Sel;
 368 assign MIIADDRESS_Wr[1]  = Write     & MIIADDRESS_Sel;
 369 assign MIITX_DATA_Wr[0]  = Write     & MIITX_DATA_Sel;
 370 assign MIITX_DATA_Wr[1]  = Write     & MIITX_DATA_Sel;
 371 assign MIIRX_DATA_Wr     = UpdateMIIRX_DATAReg;
 372 assign MAC_ADDR0_Wr[0]   = Write     & MAC_ADDR0_Sel;
 373 assign MAC_ADDR0_Wr[1]   = Write     & MAC_ADDR0_Sel;
 374 assign MAC_ADDR0_Wr[2]   = Write     & MAC_ADDR0_Sel;
 375 assign MAC_ADDR0_Wr[3]   = Write     & MAC_ADDR0_Sel;
 376 assign MAC_ADDR1_Wr[0]   = Write     & MAC_ADDR1_Sel;
 377 assign MAC_ADDR1_Wr[1]   = Write     & MAC_ADDR1_Sel;
 378 assign HASH0_Wr[0]       = Write     & HASH0_Sel;
 379 assign HASH0_Wr[1]       = Write     & HASH0_Sel;
 380 assign HASH0_Wr[2]       = Write     & HASH0_Sel;
 381 assign HASH0_Wr[3]       = Write     & HASH0_Sel;
 382 assign HASH1_Wr[0]       = Write     & HASH1_Sel;
 383 assign HASH1_Wr[1]       = Write     & HASH1_Sel;
 384 assign HASH1_Wr[2]       = Write     & HASH1_Sel;
 385 assign HASH1_Wr[3]       = Write     & HASH1_Sel;
 386 assign TXCTRL_Wr[0]      = Write     & TXCTRL_Sel;
 387 assign TXCTRL_Wr[1]      = Write     & TXCTRL_Sel;
 388 assign TXCTRL_Wr[2]      = Write     & TXCTRL_Sel;
 389 assign TX_BD_NUM_Wr[0]   = Write     & TX_BD_NUM_Sel & (DataIn<='h80);
 390
 391
 392
 393 wire [31:0] MODEROut;
 394 wire [31:0] INT_SOURCEOut;
 395 wire [31:0] INT_MASKOut;
 396 wire [31:0] IPGTOut;
 397 wire [31:0] IPGR1Out;
 398 wire [31:0] IPGR2Out;
 399 wire [31:0] PACKETLENOut;
 400 wire [31:0] COLLCONFOut;
 401 wire [31:0] CTRLMODEROut;
 402 wire [31:0] MIIMODEROut;
 403 wire [31:0] MIICOMMANDOut;
 404 wire [31:0] MIIADDRESSOut;
 405 wire [31:0] MIITX_DATAOut;
 406 wire [31:0] MIIRX_DATAOut;
 407 wire [31:0] MIISTATUSOut;
 408 wire [31:0] MAC_ADDR0Out;
 409 wire [31:0] MAC_ADDR1Out;
 410 wire [31:0] TX_BD_NUMOut;
 411 wire [31:0] HASH0Out;
 412 wire [31:0] HASH1Out;
 413 wire [31:0] TXCTRLOut;
 414
 415 // MODER Register
 416 eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0)        MODER_0
 417   (
 418    .DataIn    (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
 419    .DataOut   (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]),
 420    .Write     (MODER_Wr[0]),
 421    .Clk       (Clk),
 422    .Reset     (Reset),
 423    .SyncReset (1'b0)
 424   );
 425 eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1)        MODER_1
 426   (
 427    .DataIn    (DataIn[`ETH_MODER_WIDTH_1 + 7:8]),
 428    .DataOut   (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]),
 429    .Write     (MODER_Wr[1]),
 430    .Clk       (Clk),
 431    .Reset     (Reset),
 432    .SyncReset (1'b0)
 433   );
 434 eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2)        MODER_2
 435   (
 436    .DataIn    (DataIn[`ETH_MODER_WIDTH_2 + 15:16]),
 437    .DataOut   (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]),
 438    .Write     (MODER_Wr[2]),
 439    .Clk       (Clk),
 440    .Reset     (Reset),
 441    .SyncReset (1'b0)
 442   );
 443 assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0;
 444
 445 // INT_MASK Register
 446 eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0)  INT_MASK_0
 447   (
 448    .DataIn    (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]),
 449    .DataOut   (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]),
 450    .Write     (INT_MASK_Wr[0]),
 451    .Clk       (Clk),
 452    .Reset     (Reset),
 453    .SyncReset (1'b0)
 454   );
 455 assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0;
 456
 457 // IPGT Register
 458 eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0)          IPGT_0
 459   (
 460    .DataIn    (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]),
 461    .DataOut   (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]),
 462    .Write     (IPGT_Wr[0]),
 463    .Clk       (Clk),
 464    .Reset     (Reset),
 465    .SyncReset (1'b0)
 466   );
 467 assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0;
 468
 469 // IPGR1 Register
 470 eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0)        IPGR1_0
 471   (
 472    .DataIn    (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]),
 473    .DataOut   (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]),
 474    .Write     (IPGR1_Wr[0]),
 475    .Clk       (Clk),
 476    .Reset     (Reset),
 477    .SyncReset (1'b0)
 478   );
 479 assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0;
 480
 481 // IPGR2 Register
 482 eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0)        IPGR2_0
 483   (
 484    .DataIn    (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]),
 485    .DataOut   (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]),
 486    .Write     (IPGR2_Wr[0]),
 487    .Clk       (Clk),
 488    .Reset     (Reset),
 489    .SyncReset (1'b0)
 490   );
 491 assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0;
 492
 493 // PACKETLEN Register
 494 eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
 495   (
 496    .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
 497    .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
 498    .Write     (PACKETLEN_Wr[0]),
 499    .Clk       (Clk),
 500    .Reset     (Reset),
 501    .SyncReset (1'b0)
 502   );
 503 eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1
 504   (
 505    .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
 506    .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
 507    .Write     (PACKETLEN_Wr[1]),
 508    .Clk       (Clk),
 509    .Reset     (Reset),
 510    .SyncReset (1'b0)
 511   );
 512 eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2
 513   (
 514    .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
 515    .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
 516    .Write     (PACKETLEN_Wr[2]),
 517    .Clk       (Clk),
 518    .Reset     (Reset),
 519    .SyncReset (1'b0)
 520   );
 521 eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3
 522   (
 523    .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
 524    .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
 525    .Write     (PACKETLEN_Wr[3]),
 526    .Clk       (Clk),
 527    .Reset     (Reset),
 528    .SyncReset (1'b0)
 529   );
 530
 531 // COLLCONF Register
 532 eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0)   COLLCONF_0
 533   (
 534    .DataIn    (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]),
 535    .DataOut   (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]),
 536    .Write     (COLLCONF_Wr[0]),
 537    .Clk       (Clk),
 538    .Reset     (Reset),
 539    .SyncReset (1'b0)
 540   );
 541 eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2)   COLLCONF_2
 542   (
 543    .DataIn    (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]),
 544    .DataOut   (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]),
 545    .Write     (COLLCONF_Wr[2]),
 546    .Clk       (Clk),
 547    .Reset     (Reset),
 548    .SyncReset (1'b0)
 549   );
 550 assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0;
 551 assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0;
 552
 553 // TX_BD_NUM Register
 554 eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0
 555   (
 556    .DataIn    (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
 557    .DataOut   (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
 558    .Write     (TX_BD_NUM_Wr[0]),
 559    .Clk       (Clk),
 560    .Reset     (Reset),
 561    .SyncReset (1'b0)
 562   );
 563 assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0;
 564
 565 // CTRLMODER Register
 566 eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0)  CTRLMODER_0
 567   (
 568    .DataIn    (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
 569    .DataOut   (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
 570    .Write     (CTRLMODER_Wr[0]),
 571    .Clk       (Clk),
 572    .Reset     (Reset),
 573    .SyncReset (1'b0)
 574   );
 575 assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0;
 576
 577 // MIIMODER Register
 578 eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0)    MIIMODER_0
 579   (
 580    .DataIn    (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]),
 581    .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]),
 582    .Write     (MIIMODER_Wr[0]),
 583    .Clk       (Clk),
 584    .Reset     (Reset),
 585    .SyncReset (1'b0)
 586   );
 587 eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1)    MIIMODER_1
 588   (
 589    .DataIn    (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]),
 590    .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]),
 591    .Write     (MIIMODER_Wr[1]),
 592    .Clk       (Clk),
 593    .Reset     (Reset),
 594    .SyncReset (1'b0)
 595   );
 596 assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0;
 597
 598 // MIICOMMAND Register
 599 eth_register #(1, 0)                                      MIICOMMAND0
 600   (
 601    .DataIn    (DataIn[0]),
 602    .DataOut   (MIICOMMANDOut[0]),
 603    .Write     (MIICOMMAND_Wr[0]),
 604    .Clk       (Clk),
 605    .Reset     (Reset),
 606    .SyncReset (1'b0)
 607   );
 608 eth_register #(1, 0)                                      MIICOMMAND1
 609   (
 610    .DataIn    (DataIn[1]),
 611    .DataOut   (MIICOMMANDOut[1]),
 612    .Write     (MIICOMMAND_Wr[0]),
 613    .Clk       (Clk),
 614    .Reset     (Reset),
 615    .SyncReset (RStatStart)
 616   );
 617 eth_register #(1, 0)                                      MIICOMMAND2
 618   (
 619    .DataIn    (DataIn[2]),
 620    .DataOut   (MIICOMMANDOut[2]),
 621    .Write     (MIICOMMAND_Wr[0]),
 622    .Clk       (Clk),
 623    .Reset     (Reset),
 624    .SyncReset (WCtrlDataStart)
 625   );
 626 assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0;
 627
 628 // MIIADDRESSRegister
 629 eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0
 630   (
 631    .DataIn    (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
 632    .DataOut   (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
 633    .Write     (MIIADDRESS_Wr[0]),
 634    .Clk       (Clk),
 635    .Reset     (Reset),
 636    .SyncReset (1'b0)
 637   );
 638 eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1
 639   (
 640    .DataIn    (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
 641    .DataOut   (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
 642    .Write     (MIIADDRESS_Wr[1]),
 643    .Clk       (Clk),
 644    .Reset     (Reset),
 645    .SyncReset (1'b0)
 646   );
 647 assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0;
 648 assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0;
 649
 650 // MIITX_DATA Register
 651 eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0
 652   (
 653    .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
 654    .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
 655    .Write     (MIITX_DATA_Wr[0]),
 656    .Clk       (Clk),
 657    .Reset     (Reset),
 658    .SyncReset (1'b0)
 659   );
 660 eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1
 661   (
 662    .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
 663    .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
 664    .Write     (MIITX_DATA_Wr[1]),
 665    .Clk       (Clk),
 666    .Reset     (Reset),
 667    .SyncReset (1'b0)
 668   );
 669 assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0;
 670
 671 // MIIRX_DATA Register
 672 eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
 673   (
 674    .DataIn    (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
 675    .DataOut   (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
 676    .Write     (MIIRX_DATA_Wr), // not written from WB
 677    .Clk       (Clk),
 678    .Reset     (Reset),
 679    .SyncReset (1'b0)
 680   );
 681 assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
 682
 683 // MAC_ADDR0 Register
 684 eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0)  MAC_ADDR0_0
 685   (
 686    .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
 687    .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
 688    .Write     (MAC_ADDR0_Wr[0]),
 689    .Clk       (Clk),
 690    .Reset     (Reset),
 691    .SyncReset (1'b0)
 692   );
 693 eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1)  MAC_ADDR0_1
 694   (
 695    .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
 696    .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
 697    .Write     (MAC_ADDR0_Wr[1]),
 698    .Clk       (Clk),
 699    .Reset     (Reset),
 700    .SyncReset (1'b0)
 701   );
 702 eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2)  MAC_ADDR0_2
 703   (
 704    .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
 705    .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
 706    .Write     (MAC_ADDR0_Wr[2]),
 707    .Clk       (Clk),
 708    .Reset     (Reset),
 709    .SyncReset (1'b0)
 710   );
 711 eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3)  MAC_ADDR0_3
 712   (
 713    .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
 714    .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
 715    .Write     (MAC_ADDR0_Wr[3]),
 716    .Clk       (Clk),
 717    .Reset     (Reset),
 718    .SyncReset (1'b0)
 719   );
 720
 721 // MAC_ADDR1 Register
 722 eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0)  MAC_ADDR1_0
 723   (
 724    .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
 725    .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
 726    .Write     (MAC_ADDR1_Wr[0]),
 727    .Clk       (Clk),
 728    .Reset     (Reset),
 729    .SyncReset (1'b0)
 730   );
 731 eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1)  MAC_ADDR1_1
 732   (
 733    .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
 734    .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
 735    .Write     (MAC_ADDR1_Wr[1]),
 736    .Clk       (Clk),
 737    .Reset     (Reset),
 738    .SyncReset (1'b0)
 739   );
 740 assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
 741
 742 // RXHASH0 Register
 743 eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0)          RXHASH0_0
 744   (
 745    .DataIn    (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]),
 746    .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]),
 747    .Write     (HASH0_Wr[0]),
 748    .Clk       (Clk),
 749    .Reset     (Reset),
 750    .SyncReset (1'b0)
 751   );
 752 eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1)          RXHASH0_1
 753   (
 754    .DataIn    (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]),
 755    .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]),
 756    .Write     (HASH0_Wr[1]),
 757    .Clk       (Clk),
 758    .Reset     (Reset),
 759    .SyncReset (1'b0)
 760   );
 761 eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2)          RXHASH0_2
 762   (
 763    .DataIn    (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]),
 764    .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]),
 765    .Write     (HASH0_Wr[2]),
 766    .Clk       (Clk),
 767    .Reset     (Reset),
 768    .SyncReset (1'b0)
 769   );
 770 eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3)          RXHASH0_3
 771   (
 772    .DataIn    (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]),
 773    .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]),
 774    .Write     (HASH0_Wr[3]),
 775    .Clk       (Clk),
 776    .Reset     (Reset),
 777    .SyncReset (1'b0)
 778   );
 779
 780 // RXHASH1 Register
 781 eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0)          RXHASH1_0
 782   (
 783    .DataIn    (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]),
 784    .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]),
 785    .Write     (HASH1_Wr[0]),
 786    .Clk       (Clk),
 787    .Reset     (Reset),
 788    .SyncReset (1'b0)
 789   );
 790 eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1)          RXHASH1_1
 791   (
 792    .DataIn    (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]),
 793    .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]),
 794    .Write     (HASH1_Wr[1]),
 795    .Clk       (Clk),
 796    .Reset     (Reset),
 797    .SyncReset (1'b0)
 798   );
 799 eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2)          RXHASH1_2
 800   (
 801    .DataIn    (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),
 802    .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),
 803    .Write     (HASH1_Wr[2]),
 804    .Clk       (Clk),
 805    .Reset     (Reset),
 806    .SyncReset (1'b0)
 807   );
 808 eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3)          RXHASH1_3
 809   (
 810    .DataIn    (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),
 811    .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),
 812    .Write     (HASH1_Wr[3]),
 813    .Clk       (Clk),
 814    .Reset     (Reset),
 815    .SyncReset (1'b0)
 816   );
 817
 818 // TXCTRL Register
 819 eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0)  TXCTRL_0
 820   (
 821    .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
 822    .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
 823    .Write     (TXCTRL_Wr[0]),
 824    .Clk       (Clk),
 825    .Reset     (Reset),
 826    .SyncReset (1'b0)
 827   );
 828 eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1)  TXCTRL_1
 829   (
 830    .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
 831    .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
 832    .Write     (TXCTRL_Wr[1]),
 833    .Clk       (Clk),
 834    .Reset     (Reset),
 835    .SyncReset (1'b0)
 836   );
 837 eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2)  TXCTRL_2 // Request bit is synchronously reset
 838   (
 839    .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
 840    .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
 841    .Write     (TXCTRL_Wr[2]),
 842    .Clk       (Clk),
 843    .Reset     (Reset),
 844    .SyncReset (RstTxPauseRq)
 845   );
 846 assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
 847
 848
 849
 850 // Reading data from registers
 851 always @ (Address       or Read           or MODEROut       or INT_SOURCEOut  or
 852           INT_MASKOut   or IPGTOut        or IPGR1Out       or IPGR2Out       or
 853           PACKETLENOut  or COLLCONFOut    or CTRLMODEROut   or MIIMODEROut    or
 854           MIICOMMANDOut or MIIADDRESSOut  or MIITX_DATAOut  or MIIRX_DATAOut  or
 855           MIISTATUSOut  or MAC_ADDR0Out   or MAC_ADDR1Out   or TX_BD_NUMOut   or
 856           HASH0Out      or HASH1Out       or TXCTRLOut
 857          )
 858 begin
 859   if(Read)  // read
 860     begin
 861       case(Address)
 862         `ETH_MODER_ADR        :  DataOut<=MODEROut;
 863         `ETH_INT_SOURCE_ADR   :  DataOut<=INT_SOURCEOut;
 864         `ETH_INT_MASK_ADR     :  DataOut<=INT_MASKOut;
 865         `ETH_IPGT_ADR         :  DataOut<=IPGTOut;
 866         `ETH_IPGR1_ADR        :  DataOut<=IPGR1Out;
 867         `ETH_IPGR2_ADR        :  DataOut<=IPGR2Out;
 868         `ETH_PACKETLEN_ADR    :  DataOut<=PACKETLENOut;
 869         `ETH_COLLCONF_ADR     :  DataOut<=COLLCONFOut;
 870         `ETH_CTRLMODER_ADR    :  DataOut<=CTRLMODEROut;
 871         `ETH_MIIMODER_ADR     :  DataOut<=MIIMODEROut;
 872         `ETH_MIICOMMAND_ADR   :  DataOut<=MIICOMMANDOut;
 873         `ETH_MIIADDRESS_ADR   :  DataOut<=MIIADDRESSOut;
 874         `ETH_MIITX_DATA_ADR   :  DataOut<=MIITX_DATAOut;
 875         `ETH_MIIRX_DATA_ADR   :  DataOut<=MIIRX_DATAOut;
 876         `ETH_MIISTATUS_ADR    :  DataOut<=MIISTATUSOut;
 877         `ETH_MAC_ADDR0_ADR    :  DataOut<=MAC_ADDR0Out;
 878         `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
 879         `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
 880         `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
 881         `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
 882         `ETH_TX_CTRL_ADR      :  DataOut<=TXCTRLOut;
 883
 884         default:             DataOut<=32'h0;
 885       endcase
 886     end
 887   else
 888     DataOut<=32'h0;
 889 end
 890
 891
 892 assign r_RecSmall         = MODEROut[16];
 893 assign r_Pad              = MODEROut[15];
 894 assign r_HugEn            = MODEROut[14];
 895 assign r_CrcEn            = MODEROut[13];
 896 assign r_DlyCrcEn         = MODEROut[12];
 897 // assign r_Rst           = MODEROut[11];   This signal is not used any more
 898 assign r_FullD            = MODEROut[10];
 899 assign r_ExDfrEn          = MODEROut[9];
 900 assign r_NoBckof          = MODEROut[8];
 901 assign r_LoopBck          = MODEROut[7];
 902 assign r_IFG              = MODEROut[6];
 903 assign r_Pro              = MODEROut[5];
 904 assign r_Iam              = MODEROut[4];
 905 assign r_Bro              = MODEROut[3];
 906 assign r_NoPre            = MODEROut[2];
 907 assign r_TxEn             = MODEROut[1] & (TX_BD_NUMOut>0);     // Transmission is enabled when there is at least one TxBD.
 908 assign r_RxEn             = MODEROut[0] & (TX_BD_NUMOut<'h80);  // Reception is enabled when there is  at least one RxBD.
 909
 910 assign r_IPGT[6:0]        = IPGTOut[6:0];
 911
 912 assign r_IPGR1[6:0]       = IPGR1Out[6:0];
 913
 914 assign r_IPGR2[6:0]       = IPGR2Out[6:0];
 915
 916 assign r_MinFL[15:0]      = PACKETLENOut[31:16];
 917 assign r_MaxFL[15:0]      = PACKETLENOut[15:0];
 918
 919 assign r_MaxRet[3:0]      = COLLCONFOut[19:16];
 920 assign r_CollValid[5:0]   = COLLCONFOut[5:0];
 921
 922 assign r_TxFlow           = CTRLMODEROut[2];
 923 assign r_RxFlow           = CTRLMODEROut[1];
 924 assign r_PassAll          = CTRLMODEROut[0];
 925
 926 assign r_MiiNoPre         = MIIMODEROut[8];
 927 assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];
 928
 929 assign r_WCtrlData        = MIICOMMANDOut[2];
 930 assign r_RStat            = MIICOMMANDOut[1];
 931 assign r_ScanStat         = MIICOMMANDOut[0];
 932
 933 assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];
 934 assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];
 935
 936 assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];
 937
 938 assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
 939 assign MIISTATUSOut[2]    = NValid_stat         ;
 940 assign MIISTATUSOut[1]    = Busy_stat           ;
 941 assign MIISTATUSOut[0]    = LinkFail            ;
 942
 943 assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];
 944 assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];
 945 assign r_HASH1[31:0]      = HASH1Out;
 946 assign r_HASH0[31:0]      = HASH0Out;
 947
 948 assign r_TxBDNum[7:0]     = TX_BD_NUMOut[7:0];
 949
 950 assign r_TxPauseTV[15:0]  = TXCTRLOut[15:0];
 951 assign r_TxPauseRq        = TXCTRLOut[16];
 952
 953
 954 // Synchronizing TxC Interrupt
 955 always @ (posedge TxClk or posedge Reset)
 956 begin
 957   if(Reset)
 958     SetTxCIrq_txclk <=#Tp 1'b0;
 959   else
 960   if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
 961     SetTxCIrq_txclk <=#Tp 1'b1;
 962   else
 963   if(ResetTxCIrq_sync2)
 964     SetTxCIrq_txclk <=#Tp 1'b0;
 965 end
 966
 967
 968 always @ (posedge Clk or posedge Reset)
 969 begin
 970   if(Reset)
 971     SetTxCIrq_sync1 <=#Tp 1'b0;
 972   else
 973     SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk;
 974 end
 975
 976 always @ (posedge Clk or posedge Reset)
 977 begin
 978   if(Reset)
 979     SetTxCIrq_sync2 <=#Tp 1'b0;
 980   else
 981     SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
 982 end
 983
 984 always @ (posedge Clk or posedge Reset)
 985 begin
 986   if(Reset)
 987     SetTxCIrq_sync3 <=#Tp 1'b0;
 988   else
 989     SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2;
 990 end
 991
 992 always @ (posedge Clk or posedge Reset)
 993 begin
 994   if(Reset)
 995     SetTxCIrq <=#Tp 1'b0;
 996   else
 997     SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
 998 end
 999
1000 always @ (posedge TxClk or posedge Reset)
1001 begin
1002   if(Reset)
1003     ResetTxCIrq_sync1 <=#Tp 1'b0;
1004   else
1005     ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2;
1006 end
1007
1008 always @ (posedge TxClk or posedge Reset)
1009 begin
1010   if(Reset)
1011     ResetTxCIrq_sync2 <=#Tp 1'b0;
1012   else
1013     ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
1014 end
1015
1016
1017 // Synchronizing RxC Interrupt
1018 always @ (posedge RxClk or posedge Reset)
1019 begin
1020   if(Reset)
1021     SetRxCIrq_rxclk <=#Tp 1'b0;
1022   else
1023   if(SetPauseTimer & r_RxFlow)
1024     SetRxCIrq_rxclk <=#Tp 1'b1;
1025   else
1026   if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
1027     SetRxCIrq_rxclk <=#Tp 1'b0;
1028 end
1029
1030
1031 always @ (posedge Clk or posedge Reset)
1032 begin
1033   if(Reset)
1034     SetRxCIrq_sync1 <=#Tp 1'b0;
1035   else
1036     SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk;
1037 end
1038
1039 always @ (posedge Clk or posedge Reset)
1040 begin
1041   if(Reset)
1042     SetRxCIrq_sync2 <=#Tp 1'b0;
1043   else
1044     SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
1045 end
1046
1047 always @ (posedge Clk or posedge Reset)
1048 begin
1049   if(Reset)
1050     SetRxCIrq_sync3 <=#Tp 1'b0;
1051   else
1052     SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2;
1053 end
1054
1055 always @ (posedge Clk or posedge Reset)
1056 begin
1057   if(Reset)
1058     SetRxCIrq <=#Tp 1'b0;
1059   else
1060     SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
1061 end
1062
1063 always @ (posedge RxClk or posedge Reset)
1064 begin
1065   if(Reset)
1066     ResetRxCIrq_sync1 <=#Tp 1'b0;
1067   else
1068     ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
1069 end
1070
1071 always @ (posedge RxClk or posedge Reset)
1072 begin
1073   if(Reset)
1074     ResetRxCIrq_sync2 <=#Tp 1'b0;
1075   else
1076     ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;
1077 end
1078
1079 always @ (posedge RxClk or posedge Reset)
1080 begin
1081   if(Reset)
1082     ResetRxCIrq_sync3 <=#Tp 1'b0;
1083   else
1084     ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;
1085 end
1086
1087
1088
1089 // Interrupt generation
1090 always @ (posedge Clk or posedge Reset)
1091 begin
1092   if(Reset)
1093     irq_txb <= 1'b0;
1094   else
1095   if(TxB_IRQ)
1096     irq_txb <= #Tp 1'b1;
1097   else
1098   if(INT_SOURCE_Wr[0] & DataIn[0])
1099     irq_txb <= #Tp 1'b0;
1100 end
1101
1102 always @ (posedge Clk or posedge Reset)
1103 begin
1104   if(Reset)
1105     irq_txe <= 1'b0;
1106   else
1107   if(TxE_IRQ)
1108     irq_txe <= #Tp 1'b1;
1109   else
1110   if(INT_SOURCE_Wr[0] & DataIn[1])
1111     irq_txe <= #Tp 1'b0;
1112 end
1113
1114 always @ (posedge Clk or posedge Reset)
1115 begin
1116   if(Reset)
1117     irq_rxb <= 1'b0;
1118   else
1119   if(RxB_IRQ)
1120     irq_rxb <= #Tp 1'b1;
1121   else
1122   if(INT_SOURCE_Wr[0] & DataIn[2])
1123     irq_rxb <= #Tp 1'b0;
1124 end
1125
1126 always @ (posedge Clk or posedge Reset)
1127 begin
1128   if(Reset)
1129     irq_rxe <= 1'b0;
1130   else
1131   if(RxE_IRQ)
1132     irq_rxe <= #Tp 1'b1;
1133   else
1134   if(INT_SOURCE_Wr[0] & DataIn[3])
1135     irq_rxe <= #Tp 1'b0;
1136 end
1137
1138 always @ (posedge Clk or posedge Reset)
1139 begin
1140   if(Reset)
1141     irq_busy <= 1'b0;
1142   else
1143   if(Busy_IRQ)
1144     irq_busy <= #Tp 1'b1;
1145   else
1146   if(INT_SOURCE_Wr[0] & DataIn[4])
1147     irq_busy <= #Tp 1'b0;
1148 end
1149
1150 always @ (posedge Clk or posedge Reset)
1151 begin
1152   if(Reset)
1153     irq_txc <= 1'b0;
1154   else
1155   if(SetTxCIrq)
1156     irq_txc <= #Tp 1'b1;
1157   else
1158   if(INT_SOURCE_Wr[0] & DataIn[5])
1159     irq_txc <= #Tp 1'b0;
1160 end
1161
1162 always @ (posedge Clk or posedge Reset)
1163 begin
1164   if(Reset)
1165     irq_rxc <= 1'b0;
1166   else
1167   if(SetRxCIrq)
1168     irq_rxc <= #Tp 1'b1;
1169   else
1170   if(INT_SOURCE_Wr[0] & DataIn[6])
1171     irq_rxc <= #Tp 1'b0;
1172 end
1173
1174 // Generating interrupt signal
1175 assign int_o = irq_txb  & INT_MASKOut[0] |
1176                irq_txe  & INT_MASKOut[1] |
1177                irq_rxb  & INT_MASKOut[2] |
1178                irq_rxe  & INT_MASKOut[3] |
1179                irq_busy & INT_MASKOut[4] |
1180                irq_txc  & INT_MASKOut[5] |
1181                irq_rxc  & INT_MASKOut[6] ;
1182
1183 // For reading interrupt status
1184 assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
1185
1186
1187
1188 endmodule