eth_ocm/eth_transmitcontrol.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  eth_transmitcontrol.v                                       ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects/ethmac/                   ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Igor Mohor (igorM@opencores.org)                      ////
  10 ////                                                              ////
  11 ////  All additional information is avaliable in the Readme.txt   ////
  12 ////  file.                                                       ////
  13 ////                                                              ////
  14 //////////////////////////////////////////////////////////////////////
  15 ////                                                              ////
  16 //// Copyright (C) 2001 Authors                                   ////
  17 ////                                                              ////
  18 //// This source file may be used and distributed without         ////
  19 //// restriction provided that this copyright statement is not    ////
  20 //// removed from the file and that any derivative work contains  ////
  21 //// the original copyright notice and the associated disclaimer. ////
  22 ////                                                              ////
  23 //// This source file is free software; you can redistribute it   ////
  24 //// and/or modify it under the terms of the GNU Lesser General   ////
  25 //// Public License as published by the Free Software Foundation; ////
  26 //// either version 2.1 of the License, or (at your option) any   ////
  27 //// later version.                                               ////
  28 ////                                                              ////
  29 //// This source is distributed in the hope that it will be       ////
  30 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  31 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  32 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  33 //// details.                                                     ////
  34 ////                                                              ////
  35 //// You should have received a copy of the GNU Lesser General    ////
  36 //// Public License along with this source; if not, download it   ////
  37 //// from http://www.opencores.org/lgpl.shtml                     ////
  38 ////                                                              ////
  39 //////////////////////////////////////////////////////////////////////
  40 //
  41 // CVS Revision History
  42 //
  43 // $Log: eth_transmitcontrol.v,v $
  44 // Revision 1.6  2002/11/21 00:16:14  mohor
  45 // When TxUsedData and CtrlMux occur at the same time, byte counter needs
  46 // to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
  47 //
  48 // Revision 1.5  2002/11/19 17:37:32  mohor
  49 // When control frame (PAUSE) was sent, status was written in the
  50 // eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
  51 // Only TXC interrupt is set.
  52 //
  53 // Revision 1.4  2002/01/23 10:28:16  mohor
  54 // Link in the header changed.
  55 //
  56 // Revision 1.3  2001/10/19 08:43:51  mohor
  57 // eth_timescale.v changed to timescale.v This is done because of the
  58 // simulation of the few cores in a one joined project.
  59 //
  60 // Revision 1.2  2001/09/11 14:17:00  mohor
  61 // Few little NCSIM warnings fixed.
  62 //
  63 // Revision 1.1  2001/08/06 14:44:29  mohor
  64 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
  65 // Include files fixed to contain no path.
  66 // File names and module names changed ta have a eth_ prologue in the name.
  67 // File eth_timescale.v is used to define timescale
  68 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
  69 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
  70 // and Mdo_OE. The bidirectional signal must be created on the top level. This
  71 // is done due to the ASIC tools.
  72 //
  73 // Revision 1.1  2001/07/30 21:23:42  mohor
  74 // Directory structure changed. Files checked and joind together.
  75 //
  76 // Revision 1.1  2001/07/03 12:51:54  mohor
  77 // Initial release of the MAC Control module.
  78 //
  79 //
  80 //
  81 //
  82 //
  83 //
  84
  85
  86 `include "timescale.v"
  87
  88
  89 module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
  90                             TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
  91                             TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
  92                             ControlData, WillSendControlFrame, BlockTxDone
  93                            );
  94
  95 parameter Tp = 1;
  96
  97
  98 input         MTxClk;
  99 input         TxReset;
 100 input         TxUsedDataIn;
 101 input         TxUsedDataOut;
 102 input         TxDoneIn;
 103 input         TxAbortIn;
 104 input         TxStartFrmIn;
 105 input         TPauseRq;
 106 input         TxUsedDataOutDetected;
 107 input         TxFlow;
 108 input         DlyCrcEn;
 109 input  [15:0] TxPauseTV;
 110 input  [47:0] MAC;
 111
 112 output        TxCtrlStartFrm;
 113 output        TxCtrlEndFrm;
 114 output        SendingCtrlFrm;
 115 output        CtrlMux;
 116 output [7:0]  ControlData;
 117 output        WillSendControlFrame;
 118 output        BlockTxDone;
 119
 120 reg           SendingCtrlFrm;
 121 reg           CtrlMux;
 122 reg           WillSendControlFrame;
 123 reg    [3:0]  DlyCrcCnt;
 124 reg    [5:0]  ByteCnt;
 125 reg           ControlEnd_q;
 126 reg    [7:0]  MuxedCtrlData;
 127 reg           TxCtrlStartFrm;
 128 reg           TxCtrlStartFrm_q;
 129 reg           TxCtrlEndFrm;
 130 reg    [7:0]  ControlData;
 131 reg           TxUsedDataIn_q;
 132 reg           BlockTxDone;
 133
 134 wire          IncrementDlyCrcCnt;
 135 wire          ResetByteCnt;
 136 wire          IncrementByteCnt;
 137 wire          ControlEnd;
 138 wire          IncrementByteCntBy2;
 139 wire          EnableCnt;
 140
 141
 142 // A command for Sending the control frame is active (latched)
 143 always @ (posedge MTxClk or posedge TxReset)
 144 begin
 145   if(TxReset)
 146     WillSendControlFrame <= #Tp 1'b0;
 147   else
 148   if(TxCtrlEndFrm & CtrlMux)
 149     WillSendControlFrame <= #Tp 1'b0;
 150   else
 151   if(TPauseRq & TxFlow)
 152     WillSendControlFrame <= #Tp 1'b1;
 153 end
 154
 155
 156 // Generation of the transmit control packet start frame
 157 always @ (posedge MTxClk or posedge TxReset)
 158 begin
 159   if(TxReset)
 160     TxCtrlStartFrm <= #Tp 1'b0;
 161   else
 162   if(TxUsedDataIn_q & CtrlMux)
 163     TxCtrlStartFrm <= #Tp 1'b0;
 164   else
 165   if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
 166     TxCtrlStartFrm <= #Tp 1'b1;
 167 end
 168
 169
 170
 171 // Generation of the transmit control packet end frame
 172 always @ (posedge MTxClk or posedge TxReset)
 173 begin
 174   if(TxReset)
 175     TxCtrlEndFrm <= #Tp 1'b0;
 176   else
 177   if(ControlEnd | ControlEnd_q)
 178     TxCtrlEndFrm <= #Tp 1'b1;
 179   else
 180     TxCtrlEndFrm <= #Tp 1'b0;
 181 end
 182
 183
 184 // Generation of the multiplexer signal (controls muxes for switching between
 185 // normal and control packets)
 186 always @ (posedge MTxClk or posedge TxReset)
 187 begin
 188   if(TxReset)
 189     CtrlMux <= #Tp 1'b0;
 190   else
 191   if(WillSendControlFrame & ~TxUsedDataOut)
 192     CtrlMux <= #Tp 1'b1;
 193   else
 194   if(TxDoneIn)
 195     CtrlMux <= #Tp 1'b0;
 196 end
 197
 198
 199
 200 // Generation of the Sending Control Frame signal (enables padding and CRC)
 201 always @ (posedge MTxClk or posedge TxReset)
 202 begin
 203   if(TxReset)
 204     SendingCtrlFrm <= #Tp 1'b0;
 205   else
 206   if(WillSendControlFrame & TxCtrlStartFrm)
 207     SendingCtrlFrm <= #Tp 1'b1;
 208   else
 209   if(TxDoneIn)
 210     SendingCtrlFrm <= #Tp 1'b0;
 211 end
 212
 213
 214 always @ (posedge MTxClk or posedge TxReset)
 215 begin
 216   if(TxReset)
 217     TxUsedDataIn_q <= #Tp 1'b0;
 218   else
 219     TxUsedDataIn_q <= #Tp TxUsedDataIn;
 220 end
 221
 222
 223
 224 // Generation of the signal that will block sending the Done signal to the eth_wishbone module
 225 // While sending the control frame
 226 always @ (posedge MTxClk or posedge TxReset)
 227 begin
 228   if(TxReset)
 229     BlockTxDone <= #Tp 1'b0;
 230   else
 231   if(TxCtrlStartFrm)
 232     BlockTxDone <= #Tp 1'b1;
 233   else
 234   if(TxStartFrmIn)
 235     BlockTxDone <= #Tp 1'b0;
 236 end
 237
 238
 239 always @ (posedge MTxClk)
 240 begin
 241   ControlEnd_q     <= #Tp ControlEnd;
 242   TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
 243 end
 244
 245
 246 assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn &  ~DlyCrcCnt[2];
 247
 248
 249 // Delayed CRC counter
 250 always @ (posedge MTxClk or posedge TxReset)
 251 begin
 252   if(TxReset)
 253     DlyCrcCnt <= #Tp 4'h0;
 254   else
 255   if(ResetByteCnt)
 256     DlyCrcCnt <= #Tp 4'h0;
 257   else
 258   if(IncrementDlyCrcCnt)
 259     DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
 260 end
 261
 262
 263 assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
 264 assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
 265 assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn;     // When TxUsedDataIn and CtrlMux are set at the same time
 266
 267 assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
 268 // Byte counter
 269 always @ (posedge MTxClk or posedge TxReset)
 270 begin
 271   if(TxReset)
 272     ByteCnt <= #Tp 6'h0;
 273   else
 274   if(ResetByteCnt)
 275     ByteCnt <= #Tp 6'h0;
 276   else
 277   if(IncrementByteCntBy2 & EnableCnt)
 278     ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2;
 279   else
 280   if(IncrementByteCnt & EnableCnt)
 281     ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;
 282 end
 283
 284
 285 assign ControlEnd = ByteCnt[5:0] == 6'h22;
 286
 287
 288 // Control data generation (goes to the TxEthMAC module)
 289 always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
 290 begin
 291   case(ByteCnt)
 292     6'h0:    if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
 293                MuxedCtrlData[7:0] = 8'h01;                   // Reserved Multicast Address
 294              else
 295                                                          MuxedCtrlData[7:0] = 8'h0;
 296     6'h2:      MuxedCtrlData[7:0] = 8'h80;
 297     6'h4:      MuxedCtrlData[7:0] = 8'hC2;
 298     6'h6:      MuxedCtrlData[7:0] = 8'h00;
 299     6'h8:      MuxedCtrlData[7:0] = 8'h00;
 300     6'hA:      MuxedCtrlData[7:0] = 8'h01;
 301     6'hC:      MuxedCtrlData[7:0] = MAC[47:40];
 302     6'hE:      MuxedCtrlData[7:0] = MAC[39:32];
 303     6'h10:     MuxedCtrlData[7:0] = MAC[31:24];
 304     6'h12:     MuxedCtrlData[7:0] = MAC[23:16];
 305     6'h14:     MuxedCtrlData[7:0] = MAC[15:8];
 306     6'h16:     MuxedCtrlData[7:0] = MAC[7:0];
 307     6'h18:     MuxedCtrlData[7:0] = 8'h88;                   // Type/Length
 308     6'h1A:     MuxedCtrlData[7:0] = 8'h08;
 309     6'h1C:     MuxedCtrlData[7:0] = 8'h00;                   // Opcode
 310     6'h1E:     MuxedCtrlData[7:0] = 8'h01;
 311     6'h20:     MuxedCtrlData[7:0] = TxPauseTV[15:8];         // Pause timer value
 312     6'h22:     MuxedCtrlData[7:0] = TxPauseTV[7:0];
 313     default:   MuxedCtrlData[7:0] = 8'h0;
 314   endcase
 315 end
 316
 317
 318 // Latched Control data
 319 always @ (posedge MTxClk or posedge TxReset)
 320 begin
 321   if(TxReset)
 322     ControlData[7:0] <= #Tp 8'h0;
 323   else
 324   if(~ByteCnt[0])
 325     ControlData[7:0] <= #Tp MuxedCtrlData[7:0];
 326 end
 327
 328
 329
 330 endmodule