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Staging: et131x: Properly disable FC in txmac.
[nv-tegra-linux-2.6.git] / drivers / scsi / be2iscsi / be_main.h
blob87ec21280a37424c81a0c5815dcfcebc62bda80f
1 /**
2 * Copyright (C) 2005 - 2010 ServerEngines
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Written by: Jayamohan Kallickal (jayamohank@serverengines.com)
11 *
12 * Contact Information:
13 * linux-drivers@serverengines.com
14 *
15 * ServerEngines
16 * 209 N. Fair Oaks Ave
17 * Sunnyvale, CA 94085
18 *
19 */
20
21 #ifndef _BEISCSI_MAIN_
22 #define _BEISCSI_MAIN_
23
24 #include <linux/kernel.h>
25 #include <linux/pci.h>
26 #include <linux/in.h>
27 #include <scsi/scsi.h>
28 #include <scsi/scsi_cmnd.h>
29 #include <scsi/scsi_device.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/iscsi_proto.h>
32 #include <scsi/libiscsi.h>
33 #include <scsi/scsi_transport_iscsi.h>
34
35 #include "be.h"
36 #define DRV_NAME "be2iscsi"
37 #define BUILD_STR "2.0.527.0"
38 #define BE_NAME "ServerEngines BladeEngine2" \
39 "Linux iSCSI Driver version" BUILD_STR
40 #define DRV_DESC BE_NAME " " "Driver"
41
42 #define BE_VENDOR_ID 0x19A2
43 /* DEVICE ID's for BE2 */
44 #define BE_DEVICE_ID1 0x212
45 #define OC_DEVICE_ID1 0x702
46 #define OC_DEVICE_ID2 0x703
47
48 /* DEVICE ID's for BE3 */
49 #define BE_DEVICE_ID2 0x222
50 #define OC_DEVICE_ID3 0x712
51
52 #define BE2_IO_DEPTH 1024
53 #define BE2_MAX_SESSIONS 256
54 #define BE2_CMDS_PER_CXN 128
55 #define BE2_TMFS 16
56 #define BE2_NOPOUT_REQ 16
57 #define BE2_SGE 32
58 #define BE2_DEFPDU_HDR_SZ 64
59 #define BE2_DEFPDU_DATA_SZ 8192
60
61 #define MAX_CPUS 31
62 #define BEISCSI_SGLIST_ELEMENTS 30
63
64 #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
65 #define BEISCSI_MAX_SECTORS 256 /* scsi_host->max_sectors */
66
67 #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
68 #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
69 #define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
70 #define BEISCSI_MAX_FRAGS_INIT 192
71 #define BE_NUM_MSIX_ENTRIES 1
72 #define MPU_EP_SEMAPHORE 0xac
73
74 #define BE_SENSE_INFO_SIZE 258
75 #define BE_ISCSI_PDU_HEADER_SIZE 64
76 #define BE_MIN_MEM_SIZE 16384
77 #define MAX_CMD_SZ 65536
78 #define IIOC_SCSI_DATA 0x05 /* Write Operation */
79
80 #define DBG_LVL 0x00000001
81 #define DBG_LVL_1 0x00000001
82 #define DBG_LVL_2 0x00000002
83 #define DBG_LVL_3 0x00000004
84 #define DBG_LVL_4 0x00000008
85 #define DBG_LVL_5 0x00000010
86 #define DBG_LVL_6 0x00000020
87 #define DBG_LVL_7 0x00000040
88 #define DBG_LVL_8 0x00000080
89
90 #define SE_DEBUG(debug_mask, fmt, args...) \
91 do { \
92 if (debug_mask & DBG_LVL) { \
93 printk(KERN_ERR "(%s():%d):", __func__, __LINE__);\
94 printk(fmt, ##args); \
95 } \
96 } while (0);
97
98 #define BE_ADAPTER_UP 0x00000000
99 #define BE_ADAPTER_LINK_DOWN 0x00000001
100 /**
101 * hardware needs the async PDU buffers to be posted in multiples of 8
102 * So have atleast 8 of them by default
103 */
104
105 #define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx)
106
107 /********* Memory BAR register ************/
108 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
109 /**
110 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
111 * Disable" may still globally block interrupts in addition to individual
112 * interrupt masks; a mechanism for the device driver to block all interrupts
113 * atomically without having to arbitrate for the PCI Interrupt Disable bit
114 * with the OS.
115 */
116 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
117
118 /********* ISR0 Register offset **********/
119 #define CEV_ISR0_OFFSET 0xC18
120 #define CEV_ISR_SIZE 4
121
122 /**
123 * Macros for reading/writing a protection domain or CSR registers
124 * in BladeEngine.
125 */
126
127 #define DB_TXULP0_OFFSET 0x40
128 #define DB_RXULP0_OFFSET 0xA0
129 /********* Event Q door bell *************/
130 #define DB_EQ_OFFSET DB_CQ_OFFSET
131 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
132 /* Clear the interrupt for this eq */
133 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
134 /* Must be 1 */
135 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
136 /* Number of event entries processed */
137 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
138 /* Rearm bit */
139 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
140
141 /********* Compl Q door bell *************/
142 #define DB_CQ_OFFSET 0x120
143 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
144 /* Number of event entries processed */
145 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
146 /* Rearm bit */
147 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
148
149 #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
150 #define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
151 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
152 #define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
153 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
154
155 #define PAGES_REQUIRED(x) \
156 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
157
158 enum be_mem_enum {
159 HWI_MEM_ADDN_CONTEXT,
160 HWI_MEM_WRB,
161 HWI_MEM_WRBH,
162 HWI_MEM_SGLH,
163 HWI_MEM_SGE,
164 HWI_MEM_ASYNC_HEADER_BUF, /* 5 */
165 HWI_MEM_ASYNC_DATA_BUF,
166 HWI_MEM_ASYNC_HEADER_RING,
167 HWI_MEM_ASYNC_DATA_RING,
168 HWI_MEM_ASYNC_HEADER_HANDLE,
169 HWI_MEM_ASYNC_DATA_HANDLE, /* 10 */
170 HWI_MEM_ASYNC_PDU_CONTEXT,
171 ISCSI_MEM_GLOBAL_HEADER,
172 SE_MEM_MAX
173 };
174
175 struct be_bus_address32 {
176 unsigned int address_lo;
177 unsigned int address_hi;
178 };
179
180 struct be_bus_address64 {
181 unsigned long long address;
182 };
183
184 struct be_bus_address {
185 union {
186 struct be_bus_address32 a32;
187 struct be_bus_address64 a64;
188 } u;
189 };
190
191 struct mem_array {
192 struct be_bus_address bus_address; /* Bus address of location */
193 void *virtual_address; /* virtual address to the location */
194 unsigned int size; /* Size required by memory block */
195 };
196
197 struct be_mem_descriptor {
198 unsigned int index; /* Index of this memory parameter */
199 unsigned int category; /* type indicates cached/non-cached */
200 unsigned int num_elements; /* number of elements in this
201 * descriptor
202 */
203 unsigned int alignment_mask; /* Alignment mask for this block */
204 unsigned int size_in_bytes; /* Size required by memory block */
205 struct mem_array *mem_array;
206 };
207
208 struct sgl_handle {
209 unsigned int sgl_index;
210 unsigned int type;
211 unsigned int cid;
212 struct iscsi_task *task;
213 struct iscsi_sge *pfrag;
214 };
215
216 struct hba_parameters {
217 unsigned int ios_per_ctrl;
218 unsigned int cxns_per_ctrl;
219 unsigned int asyncpdus_per_ctrl;
220 unsigned int icds_per_ctrl;
221 unsigned int num_sge_per_io;
222 unsigned int defpdu_hdr_sz;
223 unsigned int defpdu_data_sz;
224 unsigned int num_cq_entries;
225 unsigned int num_eq_entries;
226 unsigned int wrbs_per_cxn;
227 unsigned int crashmode;
228 unsigned int hba_num;
229
230 unsigned int mgmt_ws_sz;
231 unsigned int hwi_ws_sz;
232
233 unsigned int eto;
234 unsigned int ldto;
235
236 unsigned int dbg_flags;
237 unsigned int num_cxn;
238
239 unsigned int eq_timer;
240 /**
241 * These are calculated from other params. They're here
242 * for debug purposes
243 */
244 unsigned int num_mcc_pages;
245 unsigned int num_mcc_cq_pages;
246 unsigned int num_cq_pages;
247 unsigned int num_eq_pages;
248
249 unsigned int num_async_pdu_buf_pages;
250 unsigned int num_async_pdu_buf_sgl_pages;
251 unsigned int num_async_pdu_buf_cq_pages;
252
253 unsigned int num_async_pdu_hdr_pages;
254 unsigned int num_async_pdu_hdr_sgl_pages;
255 unsigned int num_async_pdu_hdr_cq_pages;
256
257 unsigned int num_sge;
258 };
259
260 struct invalidate_command_table {
261 unsigned short icd;
262 unsigned short cid;
263 } __packed;
264
265 struct beiscsi_hba {
266 struct hba_parameters params;
267 struct hwi_controller *phwi_ctrlr;
268 unsigned int mem_req[SE_MEM_MAX];
269 /* PCI BAR mapped addresses */
270 u8 __iomem *csr_va; /* CSR */
271 u8 __iomem *db_va; /* Door Bell */
272 u8 __iomem *pci_va; /* PCI Config */
273 struct be_bus_address csr_pa; /* CSR */
274 struct be_bus_address db_pa; /* CSR */
275 struct be_bus_address pci_pa; /* CSR */
276 /* PCI representation of our HBA */
277 struct pci_dev *pcidev;
278 unsigned int state;
279 unsigned short asic_revision;
280 unsigned int num_cpus;
281 unsigned int nxt_cqid;
282 struct msix_entry msix_entries[MAX_CPUS + 1];
283 bool msix_enabled;
284 struct be_mem_descriptor *init_mem;
285
286 unsigned short io_sgl_alloc_index;
287 unsigned short io_sgl_free_index;
288 unsigned short io_sgl_hndl_avbl;
289 struct sgl_handle **io_sgl_hndl_base;
290 struct sgl_handle **sgl_hndl_array;
291
292 unsigned short eh_sgl_alloc_index;
293 unsigned short eh_sgl_free_index;
294 unsigned short eh_sgl_hndl_avbl;
295 struct sgl_handle **eh_sgl_hndl_base;
296 spinlock_t io_sgl_lock;
297 spinlock_t mgmt_sgl_lock;
298 spinlock_t isr_lock;
299 unsigned int age;
300 unsigned short avlbl_cids;
301 unsigned short cid_alloc;
302 unsigned short cid_free;
303 struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2];
304 struct list_head hba_queue;
305 unsigned short *cid_array;
306 struct iscsi_endpoint **ep_array;
307 struct Scsi_Host *shost;
308 struct {
309 /**
310 * group together since they are used most frequently
311 * for cid to cri conversion
312 */
313 unsigned int iscsi_cid_start;
314 unsigned int phys_port;
315
316 unsigned int isr_offset;
317 unsigned int iscsi_icd_start;
318 unsigned int iscsi_cid_count;
319 unsigned int iscsi_icd_count;
320 unsigned int pci_function;
321
322 unsigned short cid_alloc;
323 unsigned short cid_free;
324 unsigned short avlbl_cids;
325 unsigned short iscsi_features;
326 spinlock_t cid_lock;
327 } fw_config;
328
329 u8 mac_address[ETH_ALEN];
330 unsigned short todo_cq;
331 unsigned short todo_mcc_cq;
332 char wq_name[20];
333 struct workqueue_struct *wq; /* The actuak work queue */
334 struct work_struct work_cqs; /* The work being queued */
335 struct be_ctrl_info ctrl;
336 unsigned int generation;
337 struct invalidate_command_table inv_tbl[128];
338
339 };
340
341 struct beiscsi_session {
342 struct pci_pool *bhs_pool;
343 };
344
345 /**
346 * struct beiscsi_conn - iscsi connection structure
347 */
348 struct beiscsi_conn {
349 struct iscsi_conn *conn;
350 struct beiscsi_hba *phba;
351 u32 exp_statsn;
352 u32 beiscsi_conn_cid;
353 struct beiscsi_endpoint *ep;
354 unsigned short login_in_progress;
355 struct sgl_handle *plogin_sgl_handle;
356 struct beiscsi_session *beiscsi_sess;
357 struct iscsi_task *task;
358 };
359
360 /* This structure is used by the chip */
361 struct pdu_data_out {
362 u32 dw[12];
363 };
364 /**
365 * Pseudo amap definition in which each bit of the actual structure is defined
366 * as a byte: used to calculate offset/shift/mask of each field
367 */
368 struct amap_pdu_data_out {
369 u8 opcode[6]; /* opcode */
370 u8 rsvd0[2]; /* should be 0 */
371 u8 rsvd1[7];
372 u8 final_bit; /* F bit */
373 u8 rsvd2[16];
374 u8 ahs_length[8]; /* no AHS */
375 u8 data_len_hi[8];
376 u8 data_len_lo[16]; /* DataSegmentLength */
377 u8 lun[64];
378 u8 itt[32]; /* ITT; initiator task tag */
379 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
380 u8 rsvd3[32];
381 u8 exp_stat_sn[32];
382 u8 rsvd4[32];
383 u8 data_sn[32];
384 u8 buffer_offset[32];
385 u8 rsvd5[32];
386 };
387
388 struct be_cmd_bhs {
389 struct iscsi_cmd iscsi_hdr;
390 unsigned char pad1[16];
391 struct pdu_data_out iscsi_data_pdu;
392 unsigned char pad2[BE_SENSE_INFO_SIZE -
393 sizeof(struct pdu_data_out)];
394 };
395
396 struct beiscsi_io_task {
397 struct wrb_handle *pwrb_handle;
398 struct sgl_handle *psgl_handle;
399 struct beiscsi_conn *conn;
400 struct scsi_cmnd *scsi_cmnd;
401 unsigned int cmd_sn;
402 unsigned int flags;
403 unsigned short cid;
404 unsigned short header_len;
405 itt_t libiscsi_itt;
406 struct be_cmd_bhs *cmd_bhs;
407 struct be_bus_address bhs_pa;
408 unsigned short bhs_len;
409 };
410
411 struct be_nonio_bhs {
412 struct iscsi_hdr iscsi_hdr;
413 unsigned char pad1[16];
414 struct pdu_data_out iscsi_data_pdu;
415 unsigned char pad2[BE_SENSE_INFO_SIZE -
416 sizeof(struct pdu_data_out)];
417 };
418
419 struct be_status_bhs {
420 struct iscsi_cmd iscsi_hdr;
421 unsigned char pad1[16];
422 /**
423 * The plus 2 below is to hold the sense info length that gets
424 * DMA'ed by RxULP
425 */
426 unsigned char sense_info[BE_SENSE_INFO_SIZE];
427 };
428
429 struct iscsi_sge {
430 u32 dw[4];
431 };
432
433 /**
434 * Pseudo amap definition in which each bit of the actual structure is defined
435 * as a byte: used to calculate offset/shift/mask of each field
436 */
437 struct amap_iscsi_sge {
438 u8 addr_hi[32];
439 u8 addr_lo[32];
440 u8 sge_offset[22]; /* DWORD 2 */
441 u8 rsvd0[9]; /* DWORD 2 */
442 u8 last_sge; /* DWORD 2 */
443 u8 len[17]; /* DWORD 3 */
444 u8 rsvd1[15]; /* DWORD 3 */
445 };
446
447 struct beiscsi_offload_params {
448 u32 dw[5];
449 };
450
451 #define OFFLD_PARAMS_ERL 0x00000003
452 #define OFFLD_PARAMS_DDE 0x00000004
453 #define OFFLD_PARAMS_HDE 0x00000008
454 #define OFFLD_PARAMS_IR2T 0x00000010
455 #define OFFLD_PARAMS_IMD 0x00000020
456
457 /**
458 * Pseudo amap definition in which each bit of the actual structure is defined
459 * as a byte: used to calculate offset/shift/mask of each field
460 */
461 struct amap_beiscsi_offload_params {
462 u8 max_burst_length[32];
463 u8 max_send_data_segment_length[32];
464 u8 first_burst_length[32];
465 u8 erl[2];
466 u8 dde[1];
467 u8 hde[1];
468 u8 ir2t[1];
469 u8 imd[1];
470 u8 pad[26];
471 u8 exp_statsn[32];
472 };
473
474 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
475 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
476
477 struct async_pdu_handle {
478 struct list_head link;
479 struct be_bus_address pa;
480 void *pbuffer;
481 unsigned int consumed;
482 unsigned char index;
483 unsigned char is_header;
484 unsigned short cri;
485 unsigned long buffer_len;
486 };
487
488 struct hwi_async_entry {
489 struct {
490 unsigned char hdr_received;
491 unsigned char hdr_len;
492 unsigned short bytes_received;
493 unsigned int bytes_needed;
494 struct list_head list;
495 } wait_queue;
496
497 struct list_head header_busy_list;
498 struct list_head data_busy_list;
499 };
500
501 struct hwi_async_pdu_context {
502 struct {
503 struct be_bus_address pa_base;
504 void *va_base;
505 void *ring_base;
506 struct async_pdu_handle *handle_base;
507
508 unsigned int host_write_ptr;
509 unsigned int ep_read_ptr;
510 unsigned int writables;
511
512 unsigned int free_entries;
513 unsigned int busy_entries;
514 unsigned int buffer_size;
515 unsigned int num_entries;
516
517 struct list_head free_list;
518 } async_header;
519
520 struct {
521 struct be_bus_address pa_base;
522 void *va_base;
523 void *ring_base;
524 struct async_pdu_handle *handle_base;
525
526 unsigned int host_write_ptr;
527 unsigned int ep_read_ptr;
528 unsigned int writables;
529
530 unsigned int free_entries;
531 unsigned int busy_entries;
532 unsigned int buffer_size;
533 struct list_head free_list;
534 unsigned int num_entries;
535 } async_data;
536
537 /**
538 * This is a varying size list! Do not add anything
539 * after this entry!!
540 */
541 struct hwi_async_entry async_entry[BE2_MAX_SESSIONS * 2];
542 };
543
544 #define PDUCQE_CODE_MASK 0x0000003F
545 #define PDUCQE_DPL_MASK 0xFFFF0000
546 #define PDUCQE_INDEX_MASK 0x0000FFFF
547
548 struct i_t_dpdu_cqe {
549 u32 dw[4];
550 } __packed;
551
552 /**
553 * Pseudo amap definition in which each bit of the actual structure is defined
554 * as a byte: used to calculate offset/shift/mask of each field
555 */
556 struct amap_i_t_dpdu_cqe {
557 u8 db_addr_hi[32];
558 u8 db_addr_lo[32];
559 u8 code[6];
560 u8 cid[10];
561 u8 dpl[16];
562 u8 index[16];
563 u8 num_cons[10];
564 u8 rsvd0[4];
565 u8 final;
566 u8 valid;
567 } __packed;
568
569 #define CQE_VALID_MASK 0x80000000
570 #define CQE_CODE_MASK 0x0000003F
571 #define CQE_CID_MASK 0x0000FFC0
572
573 #define EQE_VALID_MASK 0x00000001
574 #define EQE_MAJORCODE_MASK 0x0000000E
575 #define EQE_RESID_MASK 0xFFFF0000
576
577 struct be_eq_entry {
578 u32 dw[1];
579 } __packed;
580
581 /**
582 * Pseudo amap definition in which each bit of the actual structure is defined
583 * as a byte: used to calculate offset/shift/mask of each field
584 */
585 struct amap_eq_entry {
586 u8 valid; /* DWORD 0 */
587 u8 major_code[3]; /* DWORD 0 */
588 u8 minor_code[12]; /* DWORD 0 */
589 u8 resource_id[16]; /* DWORD 0 */
590
591 } __packed;
592
593 struct cq_db {
594 u32 dw[1];
595 } __packed;
596
597 /**
598 * Pseudo amap definition in which each bit of the actual structure is defined
599 * as a byte: used to calculate offset/shift/mask of each field
600 */
601 struct amap_cq_db {
602 u8 qid[10];
603 u8 event[1];
604 u8 rsvd0[5];
605 u8 num_popped[13];
606 u8 rearm[1];
607 u8 rsvd1[2];
608 } __packed;
609
610 void beiscsi_process_eq(struct beiscsi_hba *phba);
611
612 struct iscsi_wrb {
613 u32 dw[16];
614 } __packed;
615
616 #define WRB_TYPE_MASK 0xF0000000
617
618 /**
619 * Pseudo amap definition in which each bit of the actual structure is defined
620 * as a byte: used to calculate offset/shift/mask of each field
621 */
622 struct amap_iscsi_wrb {
623 u8 lun[14]; /* DWORD 0 */
624 u8 lt; /* DWORD 0 */
625 u8 invld; /* DWORD 0 */
626 u8 wrb_idx[8]; /* DWORD 0 */
627 u8 dsp; /* DWORD 0 */
628 u8 dmsg; /* DWORD 0 */
629 u8 undr_run; /* DWORD 0 */
630 u8 over_run; /* DWORD 0 */
631 u8 type[4]; /* DWORD 0 */
632 u8 ptr2nextwrb[8]; /* DWORD 1 */
633 u8 r2t_exp_dtl[24]; /* DWORD 1 */
634 u8 sgl_icd_idx[12]; /* DWORD 2 */
635 u8 rsvd0[20]; /* DWORD 2 */
636 u8 exp_data_sn[32]; /* DWORD 3 */
637 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
638 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
639 u8 cmdsn_itt[32]; /* DWORD 6 */
640 u8 dif_ref_tag[32]; /* DWORD 7 */
641 u8 sge0_addr_hi[32]; /* DWORD 8 */
642 u8 sge0_addr_lo[32]; /* DWORD 9 */
643 u8 sge0_offset[22]; /* DWORD 10 */
644 u8 pbs; /* DWORD 10 */
645 u8 dif_mode[2]; /* DWORD 10 */
646 u8 rsvd1[6]; /* DWORD 10 */
647 u8 sge0_last; /* DWORD 10 */
648 u8 sge0_len[17]; /* DWORD 11 */
649 u8 dif_meta_tag[14]; /* DWORD 11 */
650 u8 sge0_in_ddr; /* DWORD 11 */
651 u8 sge1_addr_hi[32]; /* DWORD 12 */
652 u8 sge1_addr_lo[32]; /* DWORD 13 */
653 u8 sge1_r2t_offset[22]; /* DWORD 14 */
654 u8 rsvd2[9]; /* DWORD 14 */
655 u8 sge1_last; /* DWORD 14 */
656 u8 sge1_len[17]; /* DWORD 15 */
657 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
658 u8 rsvd3[2]; /* DWORD 15 */
659 u8 sge1_in_ddr; /* DWORD 15 */
660
661 } __packed;
662
663 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
664 void
665 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
666
667 void beiscsi_process_all_cqs(struct work_struct *work);
668
669 struct pdu_nop_out {
670 u32 dw[12];
671 };
672
673 /**
674 * Pseudo amap definition in which each bit of the actual structure is defined
675 * as a byte: used to calculate offset/shift/mask of each field
676 */
677 struct amap_pdu_nop_out {
678 u8 opcode[6]; /* opcode 0x00 */
679 u8 i_bit; /* I Bit */
680 u8 x_bit; /* reserved; should be 0 */
681 u8 fp_bit_filler1[7];
682 u8 f_bit; /* always 1 */
683 u8 reserved1[16];
684 u8 ahs_length[8]; /* no AHS */
685 u8 data_len_hi[8];
686 u8 data_len_lo[16]; /* DataSegmentLength */
687 u8 lun[64];
688 u8 itt[32]; /* initiator id for ping or 0xffffffff */
689 u8 ttt[32]; /* target id for ping or 0xffffffff */
690 u8 cmd_sn[32];
691 u8 exp_stat_sn[32];
692 u8 reserved5[128];
693 };
694
695 #define PDUBASE_OPCODE_MASK 0x0000003F
696 #define PDUBASE_DATALENHI_MASK 0x0000FF00
697 #define PDUBASE_DATALENLO_MASK 0xFFFF0000
698
699 struct pdu_base {
700 u32 dw[16];
701 } __packed;
702
703 /**
704 * Pseudo amap definition in which each bit of the actual structure is defined
705 * as a byte: used to calculate offset/shift/mask of each field
706 */
707 struct amap_pdu_base {
708 u8 opcode[6];
709 u8 i_bit; /* immediate bit */
710 u8 x_bit; /* reserved, always 0 */
711 u8 reserved1[24]; /* opcode-specific fields */
712 u8 ahs_length[8]; /* length units is 4 byte words */
713 u8 data_len_hi[8];
714 u8 data_len_lo[16]; /* DatasegmentLength */
715 u8 lun[64]; /* lun or opcode-specific fields */
716 u8 itt[32]; /* initiator task tag */
717 u8 reserved4[224];
718 };
719
720 struct iscsi_target_context_update_wrb {
721 u32 dw[16];
722 } __packed;
723
724 /**
725 * Pseudo amap definition in which each bit of the actual structure is defined
726 * as a byte: used to calculate offset/shift/mask of each field
727 */
728 struct amap_iscsi_target_context_update_wrb {
729 u8 lun[14]; /* DWORD 0 */
730 u8 lt; /* DWORD 0 */
731 u8 invld; /* DWORD 0 */
732 u8 wrb_idx[8]; /* DWORD 0 */
733 u8 dsp; /* DWORD 0 */
734 u8 dmsg; /* DWORD 0 */
735 u8 undr_run; /* DWORD 0 */
736 u8 over_run; /* DWORD 0 */
737 u8 type[4]; /* DWORD 0 */
738 u8 ptr2nextwrb[8]; /* DWORD 1 */
739 u8 max_burst_length[19]; /* DWORD 1 */
740 u8 rsvd0[5]; /* DWORD 1 */
741 u8 rsvd1[15]; /* DWORD 2 */
742 u8 max_send_data_segment_length[17]; /* DWORD 2 */
743 u8 first_burst_length[14]; /* DWORD 3 */
744 u8 rsvd2[2]; /* DWORD 3 */
745 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
746 u8 rsvd3[5]; /* DWORD 3 */
747 u8 session_state[3]; /* DWORD 3 */
748 u8 rsvd4[16]; /* DWORD 4 */
749 u8 tx_jumbo; /* DWORD 4 */
750 u8 hde; /* DWORD 4 */
751 u8 dde; /* DWORD 4 */
752 u8 erl[2]; /* DWORD 4 */
753 u8 domain_id[5]; /* DWORD 4 */
754 u8 mode; /* DWORD 4 */
755 u8 imd; /* DWORD 4 */
756 u8 ir2t; /* DWORD 4 */
757 u8 notpredblq[2]; /* DWORD 4 */
758 u8 compltonack; /* DWORD 4 */
759 u8 stat_sn[32]; /* DWORD 5 */
760 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
761 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
762 u8 pad_addr_hi[32]; /* DWORD 8 */
763 u8 pad_addr_lo[32]; /* DWORD 9 */
764 u8 rsvd5[32]; /* DWORD 10 */
765 u8 rsvd6[32]; /* DWORD 11 */
766 u8 rsvd7[32]; /* DWORD 12 */
767 u8 rsvd8[32]; /* DWORD 13 */
768 u8 rsvd9[32]; /* DWORD 14 */
769 u8 rsvd10[32]; /* DWORD 15 */
770
771 } __packed;
772
773 struct be_ring {
774 u32 pages; /* queue size in pages */
775 u32 id; /* queue id assigned by beklib */
776 u32 num; /* number of elements in queue */
777 u32 cidx; /* consumer index */
778 u32 pidx; /* producer index -- not used by most rings */
779 u32 item_size; /* size in bytes of one object */
780
781 void *va; /* The virtual address of the ring. This
782 * should be last to allow 32 & 64 bit debugger
783 * extensions to work.
784 */
785 };
786
787 struct hwi_wrb_context {
788 struct list_head wrb_handle_list;
789 struct list_head wrb_handle_drvr_list;
790 struct wrb_handle **pwrb_handle_base;
791 struct wrb_handle **pwrb_handle_basestd;
792 struct iscsi_wrb *plast_wrb;
793 unsigned short alloc_index;
794 unsigned short free_index;
795 unsigned short wrb_handles_available;
796 unsigned short cid;
797 };
798
799 struct hwi_controller {
800 struct list_head io_sgl_list;
801 struct list_head eh_sgl_list;
802 struct sgl_handle *psgl_handle_base;
803 unsigned int wrb_mem_index;
804
805 struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2];
806 struct mcc_wrb *pmcc_wrb_base;
807 struct be_ring default_pdu_hdr;
808 struct be_ring default_pdu_data;
809 struct hwi_context_memory *phwi_ctxt;
810 };
811
812 enum hwh_type_enum {
813 HWH_TYPE_IO = 1,
814 HWH_TYPE_LOGOUT = 2,
815 HWH_TYPE_TMF = 3,
816 HWH_TYPE_NOP = 4,
817 HWH_TYPE_IO_RD = 5,
818 HWH_TYPE_LOGIN = 11,
819 HWH_TYPE_INVALID = 0xFFFFFFFF
820 };
821
822 struct wrb_handle {
823 enum hwh_type_enum type;
824 unsigned short wrb_index;
825 unsigned short nxt_wrb_index;
826
827 struct iscsi_task *pio_handle;
828 struct iscsi_wrb *pwrb;
829 };
830
831 struct hwi_context_memory {
832 /* Adaptive interrupt coalescing (AIC) info */
833 u16 min_eqd; /* in usecs */
834 u16 max_eqd; /* in usecs */
835 u16 cur_eqd; /* in usecs */
836 struct be_eq_obj be_eq[MAX_CPUS];
837 struct be_queue_info be_cq[MAX_CPUS];
838
839 struct be_queue_info be_def_hdrq;
840 struct be_queue_info be_def_dataq;
841
842 struct be_queue_info be_wrbq[BE2_MAX_SESSIONS];
843 struct be_mcc_wrb_context *pbe_mcc_context;
844
845 struct hwi_async_pdu_context *pasync_ctx;
846 };
847
848 #endif
Mirror of NV Tegra kernel