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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
[nv-tegra-linux-2.6.git] / sound / soc / imx / imx-ssi.c
blob56f46a75d2972515f19e3bb89c8bf6f50960375d
1 /*
2 * imx-ssi.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * This code is based on code copyrighted by Freescale,
7 * Liam Girdwood, Javier Martin and probably others.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 *
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developped with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
25 * rate.
26 * Reading and writing AC97 registers is another challange. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
31 *
32 */
33
34 #include <linux/clk.h>
35 #include <linux/delay.h>
36 #include <linux/device.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/init.h>
39 #include <linux/interrupt.h>
40 #include <linux/module.h>
41 #include <linux/platform_device.h>
42
43 #include <sound/core.h>
44 #include <sound/initval.h>
45 #include <sound/pcm.h>
46 #include <sound/pcm_params.h>
47 #include <sound/soc.h>
48
49 #include <mach/ssi.h>
50 #include <mach/hardware.h>
51
52 #include "imx-ssi.h"
53
54 #define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN | SSI_SACNT_FV)
55
56 /*
57 * SSI Network Mode or TDM slots configuration.
58 * Should only be called when port is inactive (i.e. SSIEN = 0).
59 */
60 static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
61 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
62 {
63 struct imx_ssi *ssi = cpu_dai->private_data;
64 u32 sccr;
65
66 sccr = readl(ssi->base + SSI_STCCR);
67 sccr &= ~SSI_STCCR_DC_MASK;
68 sccr |= SSI_STCCR_DC(slots - 1);
69 writel(sccr, ssi->base + SSI_STCCR);
70
71 sccr = readl(ssi->base + SSI_SRCCR);
72 sccr &= ~SSI_STCCR_DC_MASK;
73 sccr |= SSI_STCCR_DC(slots - 1);
74 writel(sccr, ssi->base + SSI_SRCCR);
75
76 writel(tx_mask, ssi->base + SSI_STMSK);
77 writel(rx_mask, ssi->base + SSI_SRMSK);
78
79 return 0;
80 }
81
82 /*
83 * SSI DAI format configuration.
84 * Should only be called when port is inactive (i.e. SSIEN = 0).
85 * Note: We don't use the I2S modes but instead manually configure the
86 * SSI for I2S because the I2S mode is only a register preset.
87 */
88 static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
89 {
90 struct imx_ssi *ssi = cpu_dai->private_data;
91 u32 strcr = 0, scr;
92
93 scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET);
94
95 /* DAI mode */
96 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
97 case SND_SOC_DAIFMT_I2S:
98 /* data on rising edge of bclk, frame low 1clk before data */
99 strcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
100 scr |= SSI_SCR_NET;
101 break;
102 case SND_SOC_DAIFMT_LEFT_J:
103 /* data on rising edge of bclk, frame high with data */
104 strcr |= SSI_STCR_TXBIT0;
105 break;
106 case SND_SOC_DAIFMT_DSP_B:
107 /* data on rising edge of bclk, frame high with data */
108 strcr |= SSI_STCR_TFSL;
109 break;
110 case SND_SOC_DAIFMT_DSP_A:
111 /* data on rising edge of bclk, frame high 1clk before data */
112 strcr |= SSI_STCR_TFSL | SSI_STCR_TEFS;
113 break;
114 }
115
116 /* DAI clock inversion */
117 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
118 case SND_SOC_DAIFMT_IB_IF:
119 strcr |= SSI_STCR_TFSI;
120 strcr &= ~SSI_STCR_TSCKP;
121 break;
122 case SND_SOC_DAIFMT_IB_NF:
123 strcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI);
124 break;
125 case SND_SOC_DAIFMT_NB_IF:
126 strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP;
127 break;
128 case SND_SOC_DAIFMT_NB_NF:
129 strcr &= ~SSI_STCR_TFSI;
130 strcr |= SSI_STCR_TSCKP;
131 break;
132 }
133
134 /* DAI clock master masks */
135 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
136 case SND_SOC_DAIFMT_CBM_CFM:
137 break;
138 default:
139 /* Master mode not implemented, needs handling of clocks. */
140 return -EINVAL;
141 }
142
143 strcr |= SSI_STCR_TFEN0;
144
145 writel(strcr, ssi->base + SSI_STCR);
146 writel(strcr, ssi->base + SSI_SRCR);
147 writel(scr, ssi->base + SSI_SCR);
148
149 return 0;
150 }
151
152 /*
153 * SSI system clock configuration.
154 * Should only be called when port is inactive (i.e. SSIEN = 0).
155 */
156 static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
157 int clk_id, unsigned int freq, int dir)
158 {
159 struct imx_ssi *ssi = cpu_dai->private_data;
160 u32 scr;
161
162 scr = readl(ssi->base + SSI_SCR);
163
164 switch (clk_id) {
165 case IMX_SSP_SYS_CLK:
166 if (dir == SND_SOC_CLOCK_OUT)
167 scr |= SSI_SCR_SYS_CLK_EN;
168 else
169 scr &= ~SSI_SCR_SYS_CLK_EN;
170 break;
171 default:
172 return -EINVAL;
173 }
174
175 writel(scr, ssi->base + SSI_SCR);
176
177 return 0;
178 }
179
180 /*
181 * SSI Clock dividers
182 * Should only be called when port is inactive (i.e. SSIEN = 0).
183 */
184 static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
185 int div_id, int div)
186 {
187 struct imx_ssi *ssi = cpu_dai->private_data;
188 u32 stccr, srccr;
189
190 stccr = readl(ssi->base + SSI_STCCR);
191 srccr = readl(ssi->base + SSI_SRCCR);
192
193 switch (div_id) {
194 case IMX_SSI_TX_DIV_2:
195 stccr &= ~SSI_STCCR_DIV2;
196 stccr |= div;
197 break;
198 case IMX_SSI_TX_DIV_PSR:
199 stccr &= ~SSI_STCCR_PSR;
200 stccr |= div;
201 break;
202 case IMX_SSI_TX_DIV_PM:
203 stccr &= ~0xff;
204 stccr |= SSI_STCCR_PM(div);
205 break;
206 case IMX_SSI_RX_DIV_2:
207 stccr &= ~SSI_STCCR_DIV2;
208 stccr |= div;
209 break;
210 case IMX_SSI_RX_DIV_PSR:
211 stccr &= ~SSI_STCCR_PSR;
212 stccr |= div;
213 break;
214 case IMX_SSI_RX_DIV_PM:
215 stccr &= ~0xff;
216 stccr |= SSI_STCCR_PM(div);
217 break;
218 default:
219 return -EINVAL;
220 }
221
222 writel(stccr, ssi->base + SSI_STCCR);
223 writel(srccr, ssi->base + SSI_SRCCR);
224
225 return 0;
226 }
227
228 /*
229 * Should only be called when port is inactive (i.e. SSIEN = 0),
230 * although can be called multiple times by upper layers.
231 */
232 static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
233 struct snd_pcm_hw_params *params,
234 struct snd_soc_dai *cpu_dai)
235 {
236 struct imx_ssi *ssi = cpu_dai->private_data;
237 u32 reg, sccr;
238
239 /* Tx/Rx config */
240 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
241 reg = SSI_STCCR;
242 cpu_dai->dma_data = &ssi->dma_params_tx;
243 } else {
244 reg = SSI_SRCCR;
245 cpu_dai->dma_data = &ssi->dma_params_rx;
246 }
247
248 sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;
249
250 /* DAI data (word) size */
251 switch (params_format(params)) {
252 case SNDRV_PCM_FORMAT_S16_LE:
253 sccr |= SSI_SRCCR_WL(16);
254 break;
255 case SNDRV_PCM_FORMAT_S20_3LE:
256 sccr |= SSI_SRCCR_WL(20);
257 break;
258 case SNDRV_PCM_FORMAT_S24_LE:
259 sccr |= SSI_SRCCR_WL(24);
260 break;
261 }
262
263 writel(sccr, ssi->base + reg);
264
265 return 0;
266 }
267
268 static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
269 struct snd_soc_dai *dai)
270 {
271 struct snd_soc_pcm_runtime *rtd = substream->private_data;
272 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
273 struct imx_ssi *ssi = cpu_dai->private_data;
274 unsigned int sier_bits, sier;
275 unsigned int scr;
276
277 scr = readl(ssi->base + SSI_SCR);
278 sier = readl(ssi->base + SSI_SIER);
279
280 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
281 if (ssi->flags & IMX_SSI_DMA)
282 sier_bits = SSI_SIER_TDMAE;
283 else
284 sier_bits = SSI_SIER_TIE | SSI_SIER_TFE0_EN;
285 } else {
286 if (ssi->flags & IMX_SSI_DMA)
287 sier_bits = SSI_SIER_RDMAE;
288 else
289 sier_bits = SSI_SIER_RIE | SSI_SIER_RFF0_EN;
290 }
291
292 switch (cmd) {
293 case SNDRV_PCM_TRIGGER_START:
294 case SNDRV_PCM_TRIGGER_RESUME:
295 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
296 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
297 scr |= SSI_SCR_TE;
298 else
299 scr |= SSI_SCR_RE;
300 sier |= sier_bits;
301
302 if (++ssi->enabled == 1)
303 scr |= SSI_SCR_SSIEN;
304
305 break;
306
307 case SNDRV_PCM_TRIGGER_STOP:
308 case SNDRV_PCM_TRIGGER_SUSPEND:
309 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
310 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
311 scr &= ~SSI_SCR_TE;
312 else
313 scr &= ~SSI_SCR_RE;
314 sier &= ~sier_bits;
315
316 if (--ssi->enabled == 0)
317 scr &= ~SSI_SCR_SSIEN;
318
319 break;
320 default:
321 return -EINVAL;
322 }
323
324 if (!(ssi->flags & IMX_SSI_USE_AC97))
325 /* rx/tx are always enabled to access ac97 registers */
326 writel(scr, ssi->base + SSI_SCR);
327
328 writel(sier, ssi->base + SSI_SIER);
329
330 return 0;
331 }
332
333 static struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
334 .hw_params = imx_ssi_hw_params,
335 .set_fmt = imx_ssi_set_dai_fmt,
336 .set_clkdiv = imx_ssi_set_dai_clkdiv,
337 .set_sysclk = imx_ssi_set_dai_sysclk,
338 .set_tdm_slot = imx_ssi_set_dai_tdm_slot,
339 .trigger = imx_ssi_trigger,
340 };
341
342 static struct snd_soc_dai imx_ssi_dai = {
343 .playback = {
344 .channels_min = 2,
345 .channels_max = 2,
346 .rates = SNDRV_PCM_RATE_8000_96000,
347 .formats = SNDRV_PCM_FMTBIT_S16_LE,
348 },
349 .capture = {
350 .channels_min = 2,
351 .channels_max = 2,
352 .rates = SNDRV_PCM_RATE_8000_96000,
353 .formats = SNDRV_PCM_FMTBIT_S16_LE,
354 },
355 .ops = &imx_ssi_pcm_dai_ops,
356 };
357
358 int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
359 struct vm_area_struct *vma)
360 {
361 struct snd_pcm_runtime *runtime = substream->runtime;
362 int ret;
363
364 ret = dma_mmap_coherent(NULL, vma, runtime->dma_area,
365 runtime->dma_addr, runtime->dma_bytes);
366
367 pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret,
368 runtime->dma_area,
369 runtime->dma_addr,
370 runtime->dma_bytes);
371 return ret;
372 }
373
374 static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
375 {
376 struct snd_pcm_substream *substream = pcm->streams[stream].substream;
377 struct snd_dma_buffer *buf = &substream->dma_buffer;
378 size_t size = IMX_SSI_DMABUF_SIZE;
379
380 buf->dev.type = SNDRV_DMA_TYPE_DEV;
381 buf->dev.dev = pcm->card->dev;
382 buf->private_data = NULL;
383 buf->area = dma_alloc_writecombine(pcm->card->dev, size,
384 &buf->addr, GFP_KERNEL);
385 if (!buf->area)
386 return -ENOMEM;
387 buf->bytes = size;
388
389 return 0;
390 }
391
392 static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);
393
394 int imx_pcm_new(struct snd_card *card, struct snd_soc_dai *dai,
395 struct snd_pcm *pcm)
396 {
397
398 int ret = 0;
399
400 if (!card->dev->dma_mask)
401 card->dev->dma_mask = &imx_pcm_dmamask;
402 if (!card->dev->coherent_dma_mask)
403 card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
404 if (dai->playback.channels_min) {
405 ret = imx_pcm_preallocate_dma_buffer(pcm,
406 SNDRV_PCM_STREAM_PLAYBACK);
407 if (ret)
408 goto out;
409 }
410
411 if (dai->capture.channels_min) {
412 ret = imx_pcm_preallocate_dma_buffer(pcm,
413 SNDRV_PCM_STREAM_CAPTURE);
414 if (ret)
415 goto out;
416 }
417
418 out:
419 return ret;
420 }
421
422 void imx_pcm_free(struct snd_pcm *pcm)
423 {
424 struct snd_pcm_substream *substream;
425 struct snd_dma_buffer *buf;
426 int stream;
427
428 for (stream = 0; stream < 2; stream++) {
429 substream = pcm->streams[stream].substream;
430 if (!substream)
431 continue;
432
433 buf = &substream->dma_buffer;
434 if (!buf->area)
435 continue;
436
437 dma_free_writecombine(pcm->card->dev, buf->bytes,
438 buf->area, buf->addr);
439 buf->area = NULL;
440 }
441 }
442
443 struct snd_soc_platform imx_soc_platform = {
444 .name = "imx-audio",
445 };
446 EXPORT_SYMBOL_GPL(imx_soc_platform);
447
448 static struct snd_soc_dai imx_ac97_dai = {
449 .name = "AC97",
450 .ac97_control = 1,
451 .playback = {
452 .stream_name = "AC97 Playback",
453 .channels_min = 2,
454 .channels_max = 2,
455 .rates = SNDRV_PCM_RATE_48000,
456 .formats = SNDRV_PCM_FMTBIT_S16_LE,
457 },
458 .capture = {
459 .stream_name = "AC97 Capture",
460 .channels_min = 2,
461 .channels_max = 2,
462 .rates = SNDRV_PCM_RATE_48000,
463 .formats = SNDRV_PCM_FMTBIT_S16_LE,
464 },
465 .ops = &imx_ssi_pcm_dai_ops,
466 };
467
468 static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
469 {
470 void __iomem *base = imx_ssi->base;
471
472 writel(0x0, base + SSI_SCR);
473 writel(0x0, base + SSI_STCR);
474 writel(0x0, base + SSI_SRCR);
475
476 writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR);
477
478 writel(SSI_SFCSR_RFWM0(8) |
479 SSI_SFCSR_TFWM0(8) |
480 SSI_SFCSR_RFWM1(8) |
481 SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);
482
483 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR);
484 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR);
485
486 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR);
487 writel(SSI_SOR_WAIT(3), base + SSI_SOR);
488
489 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN |
490 SSI_SCR_TE | SSI_SCR_RE,
491 base + SSI_SCR);
492
493 writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
494 writel(0xff, base + SSI_SACCDIS);
495 writel(0x300, base + SSI_SACCEN);
496 }
497
498 static struct imx_ssi *ac97_ssi;
499
500 static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
501 unsigned short val)
502 {
503 struct imx_ssi *imx_ssi = ac97_ssi;
504 void __iomem *base = imx_ssi->base;
505 unsigned int lreg;
506 unsigned int lval;
507
508 if (reg > 0x7f)
509 return;
510
511 pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
512
513 lreg = reg << 12;
514 writel(lreg, base + SSI_SACADD);
515
516 lval = val << 4;
517 writel(lval , base + SSI_SACDAT);
518
519 writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT);
520 udelay(100);
521 }
522
523 static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
524 unsigned short reg)
525 {
526 struct imx_ssi *imx_ssi = ac97_ssi;
527 void __iomem *base = imx_ssi->base;
528
529 unsigned short val = -1;
530 unsigned int lreg;
531
532 lreg = (reg & 0x7f) << 12 ;
533 writel(lreg, base + SSI_SACADD);
534 writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT);
535
536 udelay(100);
537
538 val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;
539
540 pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
541
542 return val;
543 }
544
545 static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
546 {
547 struct imx_ssi *imx_ssi = ac97_ssi;
548
549 if (imx_ssi->ac97_reset)
550 imx_ssi->ac97_reset(ac97);
551 }
552
553 static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
554 {
555 struct imx_ssi *imx_ssi = ac97_ssi;
556
557 if (imx_ssi->ac97_warm_reset)
558 imx_ssi->ac97_warm_reset(ac97);
559 }
560
561 struct snd_ac97_bus_ops soc_ac97_ops = {
562 .read = imx_ssi_ac97_read,
563 .write = imx_ssi_ac97_write,
564 .reset = imx_ssi_ac97_reset,
565 .warm_reset = imx_ssi_ac97_warm_reset
566 };
567 EXPORT_SYMBOL_GPL(soc_ac97_ops);
568
569 struct snd_soc_dai imx_ssi_pcm_dai[2];
570 EXPORT_SYMBOL_GPL(imx_ssi_pcm_dai);
571
572 static int imx_ssi_probe(struct platform_device *pdev)
573 {
574 struct resource *res;
575 struct imx_ssi *ssi;
576 struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
577 struct snd_soc_platform *platform;
578 int ret = 0;
579 unsigned int val;
580 struct snd_soc_dai *dai = &imx_ssi_pcm_dai[pdev->id];
581
582 if (dai->id >= ARRAY_SIZE(imx_ssi_pcm_dai))
583 return -EINVAL;
584
585 ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
586 if (!ssi)
587 return -ENOMEM;
588
589 if (pdata) {
590 ssi->ac97_reset = pdata->ac97_reset;
591 ssi->ac97_warm_reset = pdata->ac97_warm_reset;
592 ssi->flags = pdata->flags;
593 }
594
595 ssi->irq = platform_get_irq(pdev, 0);
596
597 ssi->clk = clk_get(&pdev->dev, NULL);
598 if (IS_ERR(ssi->clk)) {
599 ret = PTR_ERR(ssi->clk);
600 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
601 ret);
602 goto failed_clk;
603 }
604 clk_enable(ssi->clk);
605
606 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
607 if (!res) {
608 ret = -ENODEV;
609 goto failed_get_resource;
610 }
611
612 if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {
613 dev_err(&pdev->dev, "request_mem_region failed\n");
614 ret = -EBUSY;
615 goto failed_get_resource;
616 }
617
618 ssi->base = ioremap(res->start, resource_size(res));
619 if (!ssi->base) {
620 dev_err(&pdev->dev, "ioremap failed\n");
621 ret = -ENODEV;
622 goto failed_ioremap;
623 }
624
625 if (ssi->flags & IMX_SSI_USE_AC97) {
626 if (ac97_ssi) {
627 ret = -EBUSY;
628 goto failed_ac97;
629 }
630 ac97_ssi = ssi;
631 setup_channel_to_ac97(ssi);
632 memcpy(dai, &imx_ac97_dai, sizeof(imx_ac97_dai));
633 } else
634 memcpy(dai, &imx_ssi_dai, sizeof(imx_ssi_dai));
635
636 writel(0x0, ssi->base + SSI_SIER);
637
638 ssi->dma_params_rx.dma_addr = res->start + SSI_SRX0;
639 ssi->dma_params_tx.dma_addr = res->start + SSI_STX0;
640
641 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
642 if (res)
643 ssi->dma_params_tx.dma = res->start;
644
645 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
646 if (res)
647 ssi->dma_params_rx.dma = res->start;
648
649 dai->id = pdev->id;
650 dai->dev = &pdev->dev;
651 dai->name = kasprintf(GFP_KERNEL, "imx-ssi.%d", pdev->id);
652 dai->private_data = ssi;
653
654 if ((cpu_is_mx27() || cpu_is_mx21()) &&
655 !(ssi->flags & IMX_SSI_USE_AC97)) {
656 ssi->flags |= IMX_SSI_DMA;
657 platform = imx_ssi_dma_mx2_init(pdev, ssi);
658 } else
659 platform = imx_ssi_fiq_init(pdev, ssi);
660
661 imx_soc_platform.pcm_ops = platform->pcm_ops;
662 imx_soc_platform.pcm_new = platform->pcm_new;
663 imx_soc_platform.pcm_free = platform->pcm_free;
664
665 val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.burstsize) |
666 SSI_SFCSR_RFWM0(ssi->dma_params_rx.burstsize);
667 writel(val, ssi->base + SSI_SFCSR);
668
669 ret = snd_soc_register_dai(dai);
670 if (ret) {
671 dev_err(&pdev->dev, "register DAI failed\n");
672 goto failed_register;
673 }
674
675 platform_set_drvdata(pdev, ssi);
676
677 return 0;
678
679 failed_register:
680 failed_ac97:
681 iounmap(ssi->base);
682 failed_ioremap:
683 release_mem_region(res->start, resource_size(res));
684 failed_get_resource:
685 clk_disable(ssi->clk);
686 clk_put(ssi->clk);
687 failed_clk:
688 kfree(ssi);
689
690 return ret;
691 }
692
693 static int __devexit imx_ssi_remove(struct platform_device *pdev)
694 {
695 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
696 struct imx_ssi *ssi = platform_get_drvdata(pdev);
697 struct snd_soc_dai *dai = &imx_ssi_pcm_dai[pdev->id];
698
699 snd_soc_unregister_dai(dai);
700
701 if (ssi->flags & IMX_SSI_USE_AC97)
702 ac97_ssi = NULL;
703
704 if (!(ssi->flags & IMX_SSI_DMA))
705 imx_ssi_fiq_exit(pdev, ssi);
706
707 iounmap(ssi->base);
708 release_mem_region(res->start, resource_size(res));
709 clk_disable(ssi->clk);
710 clk_put(ssi->clk);
711 kfree(ssi);
712
713 return 0;
714 }
715
716 static struct platform_driver imx_ssi_driver = {
717 .probe = imx_ssi_probe,
718 .remove = __devexit_p(imx_ssi_remove),
719
720 .driver = {
721 .name = DRV_NAME,
722 .owner = THIS_MODULE,
723 },
724 };
725
726 static int __init imx_ssi_init(void)
727 {
728 int ret;
729
730 ret = snd_soc_register_platform(&imx_soc_platform);
731 if (ret) {
732 pr_err("failed to register soc platform: %d\n", ret);
733 return ret;
734 }
735
736 ret = platform_driver_register(&imx_ssi_driver);
737 if (ret) {
738 snd_soc_unregister_platform(&imx_soc_platform);
739 return ret;
740 }
741
742 return 0;
743 }
744
745 static void __exit imx_ssi_exit(void)
746 {
747 platform_driver_unregister(&imx_ssi_driver);
748 snd_soc_unregister_platform(&imx_soc_platform);
749 }
750
751 module_init(imx_ssi_init);
752 module_exit(imx_ssi_exit);
753
754 /* Module information */
755 MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
756 MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
757 MODULE_LICENSE("GPL");
758
Mirror of NV Tegra kernel