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mm/ksm.c is doing an unneeded _notify in write_protect_page.
[nv-tegra-linux-2.6.git] / drivers / net / ixgbe / ixgbe_82599.c
blobb405a00817c66f248ac671476f214a7aaffe2f3c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
35
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41
42 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
43 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
44 ixgbe_link_speed speed,
45 bool autoneg,
46 bool autoneg_wait_to_complete);
47 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
48 ixgbe_link_speed speed,
49 bool autoneg,
50 bool autoneg_wait_to_complete);
51 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
52 bool autoneg_wait_to_complete);
53 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
54 ixgbe_link_speed speed,
55 bool autoneg,
56 bool autoneg_wait_to_complete);
57 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
58 ixgbe_link_speed *speed,
59 bool *autoneg);
60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
61 ixgbe_link_speed speed,
62 bool autoneg,
63 bool autoneg_wait_to_complete);
64 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
65
66 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
67 {
68 struct ixgbe_mac_info *mac = &hw->mac;
69 if (hw->phy.multispeed_fiber) {
70 /* Set up dual speed SFP+ support */
71 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
72 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
73 } else {
74 mac->ops.flap_tx_laser = NULL;
75 if ((mac->ops.get_media_type(hw) ==
76 ixgbe_media_type_backplane) &&
77 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
78 hw->phy.smart_speed == ixgbe_smart_speed_on))
79 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
80 else
81 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
82 }
83 }
84
85 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
86 {
87 s32 ret_val = 0;
88 u16 list_offset, data_offset, data_value;
89
90 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
91 ixgbe_init_mac_link_ops_82599(hw);
92
93 hw->phy.ops.reset = NULL;
94
95 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
96 &data_offset);
97
98 if (ret_val != 0)
99 goto setup_sfp_out;
100
101 /* PHY config will finish before releasing the semaphore */
102 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
103 if (ret_val != 0) {
104 ret_val = IXGBE_ERR_SWFW_SYNC;
105 goto setup_sfp_out;
106 }
107
108 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
109 while (data_value != 0xffff) {
110 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
111 IXGBE_WRITE_FLUSH(hw);
112 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
113 }
114 /* Now restart DSP by setting Restart_AN */
115 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
116 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
117
118 /* Release the semaphore */
119 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
120 /* Delay obtaining semaphore again to allow FW access */
121 msleep(hw->eeprom.semaphore_delay);
122 }
123
124 setup_sfp_out:
125 return ret_val;
126 }
127
128 /**
129 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
130 * @hw: pointer to hardware structure
131 *
132 * Read PCIe configuration space, and get the MSI-X vector count from
133 * the capabilities table.
134 **/
135 static u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
136 {
137 struct ixgbe_adapter *adapter = hw->back;
138 u16 msix_count;
139 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
140 &msix_count);
141 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
142
143 /* MSI-X count is zero-based in HW, so increment to give proper value */
144 msix_count++;
145
146 return msix_count;
147 }
148
149 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
150 {
151 struct ixgbe_mac_info *mac = &hw->mac;
152
153 ixgbe_init_mac_link_ops_82599(hw);
154
155 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
156 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
157 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
158 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
159 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
160 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
161
162 return 0;
163 }
164
165 /**
166 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
167 * @hw: pointer to hardware structure
168 *
169 * Initialize any function pointers that were not able to be
170 * set during get_invariants because the PHY/SFP type was
171 * not known. Perform the SFP init if necessary.
172 *
173 **/
174 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
175 {
176 struct ixgbe_mac_info *mac = &hw->mac;
177 struct ixgbe_phy_info *phy = &hw->phy;
178 s32 ret_val = 0;
179
180 /* Identify the PHY or SFP module */
181 ret_val = phy->ops.identify(hw);
182
183 /* Setup function pointers based on detected SFP module and speeds */
184 ixgbe_init_mac_link_ops_82599(hw);
185
186 /* If copper media, overwrite with copper function pointers */
187 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
188 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
189 mac->ops.get_link_capabilities =
190 &ixgbe_get_copper_link_capabilities_82599;
191 }
192
193 /* Set necessary function pointers based on phy type */
194 switch (hw->phy.type) {
195 case ixgbe_phy_tn:
196 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
197 phy->ops.get_firmware_version =
198 &ixgbe_get_phy_firmware_version_tnx;
199 break;
200 default:
201 break;
202 }
203
204 return ret_val;
205 }
206
207 /**
208 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
209 * @hw: pointer to hardware structure
210 * @speed: pointer to link speed
211 * @negotiation: true when autoneg or autotry is enabled
212 *
213 * Determines the link capabilities by reading the AUTOC register.
214 **/
215 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
216 ixgbe_link_speed *speed,
217 bool *negotiation)
218 {
219 s32 status = 0;
220 u32 autoc = 0;
221
222 /*
223 * Determine link capabilities based on the stored value of AUTOC,
224 * which represents EEPROM defaults. If AUTOC value has not been
225 * stored, use the current register value.
226 */
227 if (hw->mac.orig_link_settings_stored)
228 autoc = hw->mac.orig_autoc;
229 else
230 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
231
232 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
233 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
234 *speed = IXGBE_LINK_SPEED_1GB_FULL;
235 *negotiation = false;
236 break;
237
238 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
239 *speed = IXGBE_LINK_SPEED_10GB_FULL;
240 *negotiation = false;
241 break;
242
243 case IXGBE_AUTOC_LMS_1G_AN:
244 *speed = IXGBE_LINK_SPEED_1GB_FULL;
245 *negotiation = true;
246 break;
247
248 case IXGBE_AUTOC_LMS_10G_SERIAL:
249 *speed = IXGBE_LINK_SPEED_10GB_FULL;
250 *negotiation = false;
251 break;
252
253 case IXGBE_AUTOC_LMS_KX4_KX_KR:
254 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
255 *speed = IXGBE_LINK_SPEED_UNKNOWN;
256 if (autoc & IXGBE_AUTOC_KR_SUPP)
257 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
258 if (autoc & IXGBE_AUTOC_KX4_SUPP)
259 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
260 if (autoc & IXGBE_AUTOC_KX_SUPP)
261 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
262 *negotiation = true;
263 break;
264
265 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
266 *speed = IXGBE_LINK_SPEED_100_FULL;
267 if (autoc & IXGBE_AUTOC_KR_SUPP)
268 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
269 if (autoc & IXGBE_AUTOC_KX4_SUPP)
270 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
271 if (autoc & IXGBE_AUTOC_KX_SUPP)
272 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
273 *negotiation = true;
274 break;
275
276 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
277 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
278 *negotiation = false;
279 break;
280
281 default:
282 status = IXGBE_ERR_LINK_SETUP;
283 goto out;
284 break;
285 }
286
287 if (hw->phy.multispeed_fiber) {
288 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
289 IXGBE_LINK_SPEED_1GB_FULL;
290 *negotiation = true;
291 }
292
293 out:
294 return status;
295 }
296
297 /**
298 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
299 * @hw: pointer to hardware structure
300 * @speed: pointer to link speed
301 * @autoneg: boolean auto-negotiation value
302 *
303 * Determines the link capabilities by reading the AUTOC register.
304 **/
305 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
306 ixgbe_link_speed *speed,
307 bool *autoneg)
308 {
309 s32 status = IXGBE_ERR_LINK_SETUP;
310 u16 speed_ability;
311
312 *speed = 0;
313 *autoneg = true;
314
315 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
316 &speed_ability);
317
318 if (status == 0) {
319 if (speed_ability & MDIO_SPEED_10G)
320 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
321 if (speed_ability & MDIO_PMA_SPEED_1000)
322 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
323 }
324
325 return status;
326 }
327
328 /**
329 * ixgbe_get_media_type_82599 - Get media type
330 * @hw: pointer to hardware structure
331 *
332 * Returns the media type (fiber, copper, backplane)
333 **/
334 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
335 {
336 enum ixgbe_media_type media_type;
337
338 /* Detect if there is a copper PHY attached. */
339 if (hw->phy.type == ixgbe_phy_cu_unknown ||
340 hw->phy.type == ixgbe_phy_tn) {
341 media_type = ixgbe_media_type_copper;
342 goto out;
343 }
344
345 switch (hw->device_id) {
346 case IXGBE_DEV_ID_82599_KX4:
347 case IXGBE_DEV_ID_82599_KX4_MEZZ:
348 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
349 case IXGBE_DEV_ID_82599_KR:
350 case IXGBE_DEV_ID_82599_XAUI_LOM:
351 /* Default device ID is mezzanine card KX/KX4 */
352 media_type = ixgbe_media_type_backplane;
353 break;
354 case IXGBE_DEV_ID_82599_SFP:
355 case IXGBE_DEV_ID_82599_SFP_EM:
356 media_type = ixgbe_media_type_fiber;
357 break;
358 case IXGBE_DEV_ID_82599_CX4:
359 media_type = ixgbe_media_type_cx4;
360 break;
361 default:
362 media_type = ixgbe_media_type_unknown;
363 break;
364 }
365 out:
366 return media_type;
367 }
368
369 /**
370 * ixgbe_start_mac_link_82599 - Setup MAC link settings
371 * @hw: pointer to hardware structure
372 * @autoneg_wait_to_complete: true when waiting for completion is needed
373 *
374 * Configures link settings based on values in the ixgbe_hw struct.
375 * Restarts the link. Performs autonegotiation if needed.
376 **/
377 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
378 bool autoneg_wait_to_complete)
379 {
380 u32 autoc_reg;
381 u32 links_reg;
382 u32 i;
383 s32 status = 0;
384
385 /* Restart link */
386 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
387 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
388 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
389
390 /* Only poll for autoneg to complete if specified to do so */
391 if (autoneg_wait_to_complete) {
392 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
393 IXGBE_AUTOC_LMS_KX4_KX_KR ||
394 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
395 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
396 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
397 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
398 links_reg = 0; /* Just in case Autoneg time = 0 */
399 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
400 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
401 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
402 break;
403 msleep(100);
404 }
405 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
406 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
407 hw_dbg(hw, "Autoneg did not complete.\n");
408 }
409 }
410 }
411
412 /* Add delay to filter out noises during initial link setup */
413 msleep(50);
414
415 return status;
416 }
417
418 /**
419 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
420 * @hw: pointer to hardware structure
421 *
422 * When the driver changes the link speeds that it can support,
423 * it sets autotry_restart to true to indicate that we need to
424 * initiate a new autotry session with the link partner. To do
425 * so, we set the speed then disable and re-enable the tx laser, to
426 * alert the link partner that it also needs to restart autotry on its
427 * end. This is consistent with true clause 37 autoneg, which also
428 * involves a loss of signal.
429 **/
430 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
431 {
432 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
433
434 hw_dbg(hw, "ixgbe_flap_tx_laser_multispeed_fiber\n");
435
436 if (hw->mac.autotry_restart) {
437 /* Disable tx laser; allow 100us to go dark per spec */
438 esdp_reg |= IXGBE_ESDP_SDP3;
439 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
440 IXGBE_WRITE_FLUSH(hw);
441 udelay(100);
442
443 /* Enable tx laser; allow 100ms to light up */
444 esdp_reg &= ~IXGBE_ESDP_SDP3;
445 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
446 IXGBE_WRITE_FLUSH(hw);
447 msleep(100);
448
449 hw->mac.autotry_restart = false;
450 }
451 }
452
453 /**
454 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
455 * @hw: pointer to hardware structure
456 * @speed: new link speed
457 * @autoneg: true if autonegotiation enabled
458 * @autoneg_wait_to_complete: true when waiting for completion is needed
459 *
460 * Set the link speed in the AUTOC register and restarts link.
461 **/
462 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
463 ixgbe_link_speed speed,
464 bool autoneg,
465 bool autoneg_wait_to_complete)
466 {
467 s32 status = 0;
468 ixgbe_link_speed phy_link_speed;
469 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
470 u32 speedcnt = 0;
471 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
472 bool link_up = false;
473 bool negotiation;
474 int i;
475
476 /* Mask off requested but non-supported speeds */
477 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
478 speed &= phy_link_speed;
479
480 /*
481 * Try each speed one by one, highest priority first. We do this in
482 * software because 10gb fiber doesn't support speed autonegotiation.
483 */
484 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
485 speedcnt++;
486 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
487
488 /* If we already have link at this speed, just jump out */
489 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
490
491 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
492 goto out;
493
494 /* Set the module link speed */
495 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
496 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
497 IXGBE_WRITE_FLUSH(hw);
498
499 /* Allow module to change analog characteristics (1G->10G) */
500 msleep(40);
501
502 status = ixgbe_setup_mac_link_82599(hw,
503 IXGBE_LINK_SPEED_10GB_FULL,
504 autoneg,
505 autoneg_wait_to_complete);
506 if (status != 0)
507 return status;
508
509 /* Flap the tx laser if it has not already been done */
510 hw->mac.ops.flap_tx_laser(hw);
511
512 /*
513 * Wait for the controller to acquire link. Per IEEE 802.3ap,
514 * Section 73.10.2, we may have to wait up to 500ms if KR is
515 * attempted. 82599 uses the same timing for 10g SFI.
516 */
517
518 for (i = 0; i < 5; i++) {
519 /* Wait for the link partner to also set speed */
520 msleep(100);
521
522 /* If we have link, just jump out */
523 hw->mac.ops.check_link(hw, &phy_link_speed,
524 &link_up, false);
525 if (link_up)
526 goto out;
527 }
528 }
529
530 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
531 speedcnt++;
532 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
533 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
534
535 /* If we already have link at this speed, just jump out */
536 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
537
538 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
539 goto out;
540
541 /* Set the module link speed */
542 esdp_reg &= ~IXGBE_ESDP_SDP5;
543 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
544 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
545 IXGBE_WRITE_FLUSH(hw);
546
547 /* Allow module to change analog characteristics (10G->1G) */
548 msleep(40);
549
550 status = ixgbe_setup_mac_link_82599(hw,
551 IXGBE_LINK_SPEED_1GB_FULL,
552 autoneg,
553 autoneg_wait_to_complete);
554 if (status != 0)
555 return status;
556
557 /* Flap the tx laser if it has not already been done */
558 hw->mac.ops.flap_tx_laser(hw);
559
560 /* Wait for the link partner to also set speed */
561 msleep(100);
562
563 /* If we have link, just jump out */
564 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
565 if (link_up)
566 goto out;
567 }
568
569 /*
570 * We didn't get link. Configure back to the highest speed we tried,
571 * (if there was more than one). We call ourselves back with just the
572 * single highest speed that the user requested.
573 */
574 if (speedcnt > 1)
575 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
576 highest_link_speed,
577 autoneg,
578 autoneg_wait_to_complete);
579
580 out:
581 /* Set autoneg_advertised value based on input link speed */
582 hw->phy.autoneg_advertised = 0;
583
584 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
585 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
586
587 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
588 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
589
590 return status;
591 }
592
593 /**
594 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
595 * @hw: pointer to hardware structure
596 * @speed: new link speed
597 * @autoneg: true if autonegotiation enabled
598 * @autoneg_wait_to_complete: true when waiting for completion is needed
599 *
600 * Implements the Intel SmartSpeed algorithm.
601 **/
602 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
603 ixgbe_link_speed speed, bool autoneg,
604 bool autoneg_wait_to_complete)
605 {
606 s32 status = 0;
607 ixgbe_link_speed link_speed;
608 s32 i, j;
609 bool link_up = false;
610 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
611
612 hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n");
613
614 /* Set autoneg_advertised value based on input link speed */
615 hw->phy.autoneg_advertised = 0;
616
617 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
618 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
619
620 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
621 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
622
623 if (speed & IXGBE_LINK_SPEED_100_FULL)
624 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
625
626 /*
627 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
628 * autoneg advertisement if link is unable to be established at the
629 * highest negotiated rate. This can sometimes happen due to integrity
630 * issues with the physical media connection.
631 */
632
633 /* First, try to get link with full advertisement */
634 hw->phy.smart_speed_active = false;
635 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
636 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
637 autoneg_wait_to_complete);
638 if (status)
639 goto out;
640
641 /*
642 * Wait for the controller to acquire link. Per IEEE 802.3ap,
643 * Section 73.10.2, we may have to wait up to 500ms if KR is
644 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
645 * Table 9 in the AN MAS.
646 */
647 for (i = 0; i < 5; i++) {
648 mdelay(100);
649
650 /* If we have link, just jump out */
651 hw->mac.ops.check_link(hw, &link_speed,
652 &link_up, false);
653 if (link_up)
654 goto out;
655 }
656 }
657
658 /*
659 * We didn't get link. If we advertised KR plus one of KX4/KX
660 * (or BX4/BX), then disable KR and try again.
661 */
662 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
663 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
664 goto out;
665
666 /* Turn SmartSpeed on to disable KR support */
667 hw->phy.smart_speed_active = true;
668 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
669 autoneg_wait_to_complete);
670 if (status)
671 goto out;
672
673 /*
674 * Wait for the controller to acquire link. 600ms will allow for
675 * the AN link_fail_inhibit_timer as well for multiple cycles of
676 * parallel detect, both 10g and 1g. This allows for the maximum
677 * connect attempts as defined in the AN MAS table 73-7.
678 */
679 for (i = 0; i < 6; i++) {
680 mdelay(100);
681
682 /* If we have link, just jump out */
683 hw->mac.ops.check_link(hw, &link_speed,
684 &link_up, false);
685 if (link_up)
686 goto out;
687 }
688
689 /* We didn't get link. Turn SmartSpeed back off. */
690 hw->phy.smart_speed_active = false;
691 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
692 autoneg_wait_to_complete);
693
694 out:
695 return status;
696 }
697
698 /**
699 * ixgbe_check_mac_link_82599 - Determine link and speed status
700 * @hw: pointer to hardware structure
701 * @speed: pointer to link speed
702 * @link_up: true when link is up
703 * @link_up_wait_to_complete: bool used to wait for link up or not
704 *
705 * Reads the links register to determine if link is up and the current speed
706 **/
707 static s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
708 ixgbe_link_speed *speed,
709 bool *link_up,
710 bool link_up_wait_to_complete)
711 {
712 u32 links_reg;
713 u32 i;
714
715 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
716 if (link_up_wait_to_complete) {
717 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
718 if (links_reg & IXGBE_LINKS_UP) {
719 *link_up = true;
720 break;
721 } else {
722 *link_up = false;
723 }
724 msleep(100);
725 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
726 }
727 } else {
728 if (links_reg & IXGBE_LINKS_UP)
729 *link_up = true;
730 else
731 *link_up = false;
732 }
733
734 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
735 IXGBE_LINKS_SPEED_10G_82599)
736 *speed = IXGBE_LINK_SPEED_10GB_FULL;
737 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
738 IXGBE_LINKS_SPEED_1G_82599)
739 *speed = IXGBE_LINK_SPEED_1GB_FULL;
740 else
741 *speed = IXGBE_LINK_SPEED_100_FULL;
742
743 /* if link is down, zero out the current_mode */
744 if (*link_up == false) {
745 hw->fc.current_mode = ixgbe_fc_none;
746 hw->fc.fc_was_autonegged = false;
747 }
748
749 return 0;
750 }
751
752 /**
753 * ixgbe_setup_mac_link_82599 - Set MAC link speed
754 * @hw: pointer to hardware structure
755 * @speed: new link speed
756 * @autoneg: true if autonegotiation enabled
757 * @autoneg_wait_to_complete: true when waiting for completion is needed
758 *
759 * Set the link speed in the AUTOC register and restarts link.
760 **/
761 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
762 ixgbe_link_speed speed, bool autoneg,
763 bool autoneg_wait_to_complete)
764 {
765 s32 status = 0;
766 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
767 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
768 u32 start_autoc = autoc;
769 u32 orig_autoc = 0;
770 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
771 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
772 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
773 u32 links_reg;
774 u32 i;
775 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
776
777 /* Check to see if speed passed in is supported. */
778 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
779 speed &= link_capabilities;
780
781 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
782 status = IXGBE_ERR_LINK_SETUP;
783 goto out;
784 }
785
786 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
787 if (hw->mac.orig_link_settings_stored)
788 orig_autoc = hw->mac.orig_autoc;
789 else
790 orig_autoc = autoc;
791
792
793 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
794 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
795 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
796 /* Set KX4/KX/KR support according to speed requested */
797 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
798 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
799 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
800 autoc |= IXGBE_AUTOC_KX4_SUPP;
801 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
802 (hw->phy.smart_speed_active == false))
803 autoc |= IXGBE_AUTOC_KR_SUPP;
804 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
805 autoc |= IXGBE_AUTOC_KX_SUPP;
806 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
807 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
808 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
809 /* Switch from 1G SFI to 10G SFI if requested */
810 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
811 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
812 autoc &= ~IXGBE_AUTOC_LMS_MASK;
813 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
814 }
815 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
816 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
817 /* Switch from 10G SFI to 1G SFI if requested */
818 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
819 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
820 autoc &= ~IXGBE_AUTOC_LMS_MASK;
821 if (autoneg)
822 autoc |= IXGBE_AUTOC_LMS_1G_AN;
823 else
824 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
825 }
826 }
827
828 if (autoc != start_autoc) {
829 /* Restart link */
830 autoc |= IXGBE_AUTOC_AN_RESTART;
831 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
832
833 /* Only poll for autoneg to complete if specified to do so */
834 if (autoneg_wait_to_complete) {
835 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
836 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
837 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
838 links_reg = 0; /*Just in case Autoneg time=0*/
839 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
840 links_reg =
841 IXGBE_READ_REG(hw, IXGBE_LINKS);
842 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
843 break;
844 msleep(100);
845 }
846 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
847 status =
848 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
849 hw_dbg(hw, "Autoneg did not "
850 "complete.\n");
851 }
852 }
853 }
854
855 /* Add delay to filter out noises during initial link setup */
856 msleep(50);
857 }
858
859 out:
860 return status;
861 }
862
863 /**
864 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
865 * @hw: pointer to hardware structure
866 * @speed: new link speed
867 * @autoneg: true if autonegotiation enabled
868 * @autoneg_wait_to_complete: true if waiting is needed to complete
869 *
870 * Restarts link on PHY and MAC based on settings passed in.
871 **/
872 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
873 ixgbe_link_speed speed,
874 bool autoneg,
875 bool autoneg_wait_to_complete)
876 {
877 s32 status;
878
879 /* Setup the PHY according to input speed */
880 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
881 autoneg_wait_to_complete);
882 /* Set up MAC */
883 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
884
885 return status;
886 }
887
888 /**
889 * ixgbe_reset_hw_82599 - Perform hardware reset
890 * @hw: pointer to hardware structure
891 *
892 * Resets the hardware by resetting the transmit and receive units, masks
893 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
894 * reset.
895 **/
896 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
897 {
898 s32 status = 0;
899 u32 ctrl;
900 u32 i;
901 u32 autoc;
902 u32 autoc2;
903
904 /* Call adapter stop to disable tx/rx and clear interrupts */
905 hw->mac.ops.stop_adapter(hw);
906
907 /* PHY ops must be identified and initialized prior to reset */
908
909 /* Init PHY and function pointers, perform SFP setup */
910 status = hw->phy.ops.init(hw);
911
912 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
913 goto reset_hw_out;
914
915 /* Setup SFP module if there is one present. */
916 if (hw->phy.sfp_setup_needed) {
917 status = hw->mac.ops.setup_sfp(hw);
918 hw->phy.sfp_setup_needed = false;
919 }
920
921 /* Reset PHY */
922 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
923 hw->phy.ops.reset(hw);
924
925 /*
926 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
927 * access and verify no pending requests before reset
928 */
929 status = ixgbe_disable_pcie_master(hw);
930 if (status != 0) {
931 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
932 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
933 }
934
935 /*
936 * Issue global reset to the MAC. This needs to be a SW reset.
937 * If link reset is used, it might reset the MAC when mng is using it
938 */
939 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
940 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
941 IXGBE_WRITE_FLUSH(hw);
942
943 /* Poll for reset bit to self-clear indicating reset is complete */
944 for (i = 0; i < 10; i++) {
945 udelay(1);
946 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
947 if (!(ctrl & IXGBE_CTRL_RST))
948 break;
949 }
950 if (ctrl & IXGBE_CTRL_RST) {
951 status = IXGBE_ERR_RESET_FAILED;
952 hw_dbg(hw, "Reset polling failed to complete.\n");
953 }
954
955 msleep(50);
956
957 /*
958 * Store the original AUTOC/AUTOC2 values if they have not been
959 * stored off yet. Otherwise restore the stored original
960 * values since the reset operation sets back to defaults.
961 */
962 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
963 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
964 if (hw->mac.orig_link_settings_stored == false) {
965 hw->mac.orig_autoc = autoc;
966 hw->mac.orig_autoc2 = autoc2;
967 hw->mac.orig_link_settings_stored = true;
968 } else {
969 if (autoc != hw->mac.orig_autoc)
970 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
971 IXGBE_AUTOC_AN_RESTART));
972
973 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
974 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
975 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
976 autoc2 |= (hw->mac.orig_autoc2 &
977 IXGBE_AUTOC2_UPPER_MASK);
978 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
979 }
980 }
981
982 /*
983 * Store MAC address from RAR0, clear receive address registers, and
984 * clear the multicast table. Also reset num_rar_entries to 128,
985 * since we modify this value when programming the SAN MAC address.
986 */
987 hw->mac.num_rar_entries = 128;
988 hw->mac.ops.init_rx_addrs(hw);
989
990 /* Store the permanent mac address */
991 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
992
993 /* Store the permanent SAN mac address */
994 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
995
996 /* Add the SAN MAC address to the RAR only if it's a valid address */
997 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
998 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
999 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1000
1001 /* Reserve the last RAR for the SAN MAC address */
1002 hw->mac.num_rar_entries--;
1003 }
1004
1005 /* Store the alternative WWNN/WWPN prefix */
1006 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1007 &hw->mac.wwpn_prefix);
1008
1009 reset_hw_out:
1010 return status;
1011 }
1012
1013 /**
1014 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
1015 * @hw: pointer to hardware struct
1016 * @rar: receive address register index to disassociate
1017 * @vmdq: VMDq pool index to remove from the rar
1018 **/
1019 static s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
1020 {
1021 u32 mpsar_lo, mpsar_hi;
1022 u32 rar_entries = hw->mac.num_rar_entries;
1023
1024 if (rar < rar_entries) {
1025 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1026 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1027
1028 if (!mpsar_lo && !mpsar_hi)
1029 goto done;
1030
1031 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
1032 if (mpsar_lo) {
1033 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
1034 mpsar_lo = 0;
1035 }
1036 if (mpsar_hi) {
1037 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
1038 mpsar_hi = 0;
1039 }
1040 } else if (vmdq < 32) {
1041 mpsar_lo &= ~(1 << vmdq);
1042 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
1043 } else {
1044 mpsar_hi &= ~(1 << (vmdq - 32));
1045 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
1046 }
1047
1048 /* was that the last pool using this rar? */
1049 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
1050 hw->mac.ops.clear_rar(hw, rar);
1051 } else {
1052 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1053 }
1054
1055 done:
1056 return 0;
1057 }
1058
1059 /**
1060 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
1061 * @hw: pointer to hardware struct
1062 * @rar: receive address register index to associate with a VMDq index
1063 * @vmdq: VMDq pool index
1064 **/
1065 static s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
1066 {
1067 u32 mpsar;
1068 u32 rar_entries = hw->mac.num_rar_entries;
1069
1070 if (rar < rar_entries) {
1071 if (vmdq < 32) {
1072 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1073 mpsar |= 1 << vmdq;
1074 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
1075 } else {
1076 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1077 mpsar |= 1 << (vmdq - 32);
1078 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
1079 }
1080 } else {
1081 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1082 }
1083 return 0;
1084 }
1085
1086 /**
1087 * ixgbe_set_vfta_82599 - Set VLAN filter table
1088 * @hw: pointer to hardware structure
1089 * @vlan: VLAN id to write to VLAN filter
1090 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1091 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1092 *
1093 * Turn on/off specified VLAN in the VLAN filter table.
1094 **/
1095 static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1096 bool vlan_on)
1097 {
1098 u32 regindex;
1099 u32 vlvf_index;
1100 u32 bitindex;
1101 u32 bits;
1102 u32 first_empty_slot;
1103 u32 vt_ctl;
1104
1105 if (vlan > 4095)
1106 return IXGBE_ERR_PARAM;
1107
1108 /*
1109 * this is a 2 part operation - first the VFTA, then the
1110 * VLVF and VLVFB if vind is set
1111 */
1112
1113 /* Part 1
1114 * The VFTA is a bitstring made up of 128 32-bit registers
1115 * that enable the particular VLAN id, much like the MTA:
1116 * bits[11-5]: which register
1117 * bits[4-0]: which bit in the register
1118 */
1119 regindex = (vlan >> 5) & 0x7F;
1120 bitindex = vlan & 0x1F;
1121 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1122 if (vlan_on)
1123 bits |= (1 << bitindex);
1124 else
1125 bits &= ~(1 << bitindex);
1126 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1127
1128
1129 /* Part 2
1130 * If VT mode is set
1131 * Either vlan_on
1132 * make sure the vlan is in VLVF
1133 * set the vind bit in the matching VLVFB
1134 * Or !vlan_on
1135 * clear the pool bit and possibly the vind
1136 */
1137 vt_ctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1138 if (!(vt_ctl & IXGBE_VT_CTL_VT_ENABLE))
1139 goto out;
1140
1141 /* find the vlanid or the first empty slot */
1142 first_empty_slot = 0;
1143
1144 for (vlvf_index = 1; vlvf_index < IXGBE_VLVF_ENTRIES; vlvf_index++) {
1145 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(vlvf_index));
1146 if (!bits && !first_empty_slot)
1147 first_empty_slot = vlvf_index;
1148 else if ((bits & 0x0FFF) == vlan)
1149 break;
1150 }
1151
1152 if (vlvf_index >= IXGBE_VLVF_ENTRIES) {
1153 if (first_empty_slot)
1154 vlvf_index = first_empty_slot;
1155 else {
1156 hw_dbg(hw, "No space in VLVF.\n");
1157 goto out;
1158 }
1159 }
1160
1161 if (vlan_on) {
1162 /* set the pool bit */
1163 if (vind < 32) {
1164 bits = IXGBE_READ_REG(hw,
1165 IXGBE_VLVFB(vlvf_index * 2));
1166 bits |= (1 << vind);
1167 IXGBE_WRITE_REG(hw,
1168 IXGBE_VLVFB(vlvf_index * 2), bits);
1169 } else {
1170 bits = IXGBE_READ_REG(hw,
1171 IXGBE_VLVFB((vlvf_index * 2) + 1));
1172 bits |= (1 << (vind - 32));
1173 IXGBE_WRITE_REG(hw,
1174 IXGBE_VLVFB((vlvf_index * 2) + 1), bits);
1175 }
1176 } else {
1177 /* clear the pool bit */
1178 if (vind < 32) {
1179 bits = IXGBE_READ_REG(hw,
1180 IXGBE_VLVFB(vlvf_index * 2));
1181 bits &= ~(1 << vind);
1182 IXGBE_WRITE_REG(hw,
1183 IXGBE_VLVFB(vlvf_index * 2), bits);
1184 bits |= IXGBE_READ_REG(hw,
1185 IXGBE_VLVFB((vlvf_index * 2) + 1));
1186 } else {
1187 bits = IXGBE_READ_REG(hw,
1188 IXGBE_VLVFB((vlvf_index * 2) + 1));
1189 bits &= ~(1 << (vind - 32));
1190 IXGBE_WRITE_REG(hw,
1191 IXGBE_VLVFB((vlvf_index * 2) + 1), bits);
1192 bits |= IXGBE_READ_REG(hw,
1193 IXGBE_VLVFB(vlvf_index * 2));
1194 }
1195 }
1196
1197 if (bits) {
1198 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
1199 (IXGBE_VLVF_VIEN | vlan));
1200 /* if bits is non-zero then some pools/VFs are still
1201 * using this VLAN ID. Force the VFTA entry to on */
1202 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1203 bits |= (1 << bitindex);
1204 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1205 }
1206 else
1207 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
1208
1209 out:
1210 return 0;
1211 }
1212
1213 /**
1214 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1215 * @hw: pointer to hardware structure
1216 *
1217 * Clears the VLAN filer table, and the VMDq index associated with the filter
1218 **/
1219 static s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1220 {
1221 u32 offset;
1222
1223 for (offset = 0; offset < hw->mac.vft_size; offset++)
1224 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1225
1226 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1227 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1228 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1229 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1230 }
1231
1232 return 0;
1233 }
1234
1235 /**
1236 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1237 * @hw: pointer to hardware structure
1238 **/
1239 static s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1240 {
1241 int i;
1242 hw_dbg(hw, " Clearing UTA\n");
1243
1244 for (i = 0; i < 128; i++)
1245 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1246
1247 return 0;
1248 }
1249
1250 /**
1251 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1252 * @hw: pointer to hardware structure
1253 **/
1254 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1255 {
1256 int i;
1257 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1258 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1259
1260 /*
1261 * Before starting reinitialization process,
1262 * FDIRCMD.CMD must be zero.
1263 */
1264 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1265 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1266 IXGBE_FDIRCMD_CMD_MASK))
1267 break;
1268 udelay(10);
1269 }
1270 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1271 hw_dbg(hw ,"Flow Director previous command isn't complete, "
1272 "aborting table re-initialization. \n");
1273 return IXGBE_ERR_FDIR_REINIT_FAILED;
1274 }
1275
1276 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1277 IXGBE_WRITE_FLUSH(hw);
1278 /*
1279 * 82599 adapters flow director init flow cannot be restarted,
1280 * Workaround 82599 silicon errata by performing the following steps
1281 * before re-writing the FDIRCTRL control register with the same value.
1282 * - write 1 to bit 8 of FDIRCMD register &
1283 * - write 0 to bit 8 of FDIRCMD register
1284 */
1285 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1286 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1287 IXGBE_FDIRCMD_CLEARHT));
1288 IXGBE_WRITE_FLUSH(hw);
1289 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1290 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1291 ~IXGBE_FDIRCMD_CLEARHT));
1292 IXGBE_WRITE_FLUSH(hw);
1293 /*
1294 * Clear FDIR Hash register to clear any leftover hashes
1295 * waiting to be programmed.
1296 */
1297 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1298 IXGBE_WRITE_FLUSH(hw);
1299
1300 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1301 IXGBE_WRITE_FLUSH(hw);
1302
1303 /* Poll init-done after we write FDIRCTRL register */
1304 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1305 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1306 IXGBE_FDIRCTRL_INIT_DONE)
1307 break;
1308 udelay(10);
1309 }
1310 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1311 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1312 return IXGBE_ERR_FDIR_REINIT_FAILED;
1313 }
1314
1315 /* Clear FDIR statistics registers (read to clear) */
1316 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1317 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1318 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1319 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1320 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1321
1322 return 0;
1323 }
1324
1325 /**
1326 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1327 * @hw: pointer to hardware structure
1328 * @pballoc: which mode to allocate filters with
1329 **/
1330 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1331 {
1332 u32 fdirctrl = 0;
1333 u32 pbsize;
1334 int i;
1335
1336 /*
1337 * Before enabling Flow Director, the Rx Packet Buffer size
1338 * must be reduced. The new value is the current size minus
1339 * flow director memory usage size.
1340 */
1341 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1342 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1343 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1344
1345 /*
1346 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1347 * intialized to zero for non DCB mode otherwise actual total RX PB
1348 * would be bigger than programmed and filter space would run into
1349 * the PB 0 region.
1350 */
1351 for (i = 1; i < 8; i++)
1352 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1353
1354 /* Send interrupt when 64 filters are left */
1355 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1356
1357 /* Set the maximum length per hash bucket to 0xA filters */
1358 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1359
1360 switch (pballoc) {
1361 case IXGBE_FDIR_PBALLOC_64K:
1362 /* 8k - 1 signature filters */
1363 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1364 break;
1365 case IXGBE_FDIR_PBALLOC_128K:
1366 /* 16k - 1 signature filters */
1367 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1368 break;
1369 case IXGBE_FDIR_PBALLOC_256K:
1370 /* 32k - 1 signature filters */
1371 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1372 break;
1373 default:
1374 /* bad value */
1375 return IXGBE_ERR_CONFIG;
1376 };
1377
1378 /* Move the flexible bytes to use the ethertype - shift 6 words */
1379 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1380
1381 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1382
1383 /* Prime the keys for hashing */
1384 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1385 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1386 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1387 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1388
1389 /*
1390 * Poll init-done after we write the register. Estimated times:
1391 * 10G: PBALLOC = 11b, timing is 60us
1392 * 1G: PBALLOC = 11b, timing is 600us
1393 * 100M: PBALLOC = 11b, timing is 6ms
1394 *
1395 * Multiple these timings by 4 if under full Rx load
1396 *
1397 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1398 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1399 * this might not finish in our poll time, but we can live with that
1400 * for now.
1401 */
1402 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1403 IXGBE_WRITE_FLUSH(hw);
1404 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1405 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1406 IXGBE_FDIRCTRL_INIT_DONE)
1407 break;
1408 msleep(1);
1409 }
1410 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1411 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1412
1413 return 0;
1414 }
1415
1416 /**
1417 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1418 * @hw: pointer to hardware structure
1419 * @pballoc: which mode to allocate filters with
1420 **/
1421 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1422 {
1423 u32 fdirctrl = 0;
1424 u32 pbsize;
1425 int i;
1426
1427 /*
1428 * Before enabling Flow Director, the Rx Packet Buffer size
1429 * must be reduced. The new value is the current size minus
1430 * flow director memory usage size.
1431 */
1432 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1433 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1434 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1435
1436 /*
1437 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1438 * intialized to zero for non DCB mode otherwise actual total RX PB
1439 * would be bigger than programmed and filter space would run into
1440 * the PB 0 region.
1441 */
1442 for (i = 1; i < 8; i++)
1443 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1444
1445 /* Send interrupt when 64 filters are left */
1446 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1447
1448 /* Initialize the drop queue to Rx queue 127 */
1449 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1450
1451 switch (pballoc) {
1452 case IXGBE_FDIR_PBALLOC_64K:
1453 /* 2k - 1 perfect filters */
1454 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1455 break;
1456 case IXGBE_FDIR_PBALLOC_128K:
1457 /* 4k - 1 perfect filters */
1458 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1459 break;
1460 case IXGBE_FDIR_PBALLOC_256K:
1461 /* 8k - 1 perfect filters */
1462 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1463 break;
1464 default:
1465 /* bad value */
1466 return IXGBE_ERR_CONFIG;
1467 };
1468
1469 /* Turn perfect match filtering on */
1470 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1471 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1472
1473 /* Move the flexible bytes to use the ethertype - shift 6 words */
1474 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1475
1476 /* Prime the keys for hashing */
1477 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1478 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1479 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1480 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1481
1482 /*
1483 * Poll init-done after we write the register. Estimated times:
1484 * 10G: PBALLOC = 11b, timing is 60us
1485 * 1G: PBALLOC = 11b, timing is 600us
1486 * 100M: PBALLOC = 11b, timing is 6ms
1487 *
1488 * Multiple these timings by 4 if under full Rx load
1489 *
1490 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1491 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1492 * this might not finish in our poll time, but we can live with that
1493 * for now.
1494 */
1495
1496 /* Set the maximum length per hash bucket to 0xA filters */
1497 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1498
1499 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1500 IXGBE_WRITE_FLUSH(hw);
1501 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1502 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1503 IXGBE_FDIRCTRL_INIT_DONE)
1504 break;
1505 msleep(1);
1506 }
1507 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1508 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1509
1510 return 0;
1511 }
1512
1513
1514 /**
1515 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1516 * @stream: input bitstream to compute the hash on
1517 * @key: 32-bit hash key
1518 **/
1519 static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1520 u32 key)
1521 {
1522 /*
1523 * The algorithm is as follows:
1524 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1525 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1526 * and A[n] x B[n] is bitwise AND between same length strings
1527 *
1528 * K[n] is 16 bits, defined as:
1529 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1530 * for n modulo 32 < 15, K[n] =
1531 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1532 *
1533 * S[n] is 16 bits, defined as:
1534 * for n >= 15, S[n] = S[n:n - 15]
1535 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1536 *
1537 * To simplify for programming, the algorithm is implemented
1538 * in software this way:
1539 *
1540 * Key[31:0], Stream[335:0]
1541 *
1542 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1543 * int_key[350:0] = tmp_key[351:1]
1544 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1545 *
1546 * hash[15:0] = 0;
1547 * for (i = 0; i < 351; i++) {
1548 * if (int_key[i])
1549 * hash ^= int_stream[(i + 15):i];
1550 * }
1551 */
1552
1553 union {
1554 u64 fill[6];
1555 u32 key[11];
1556 u8 key_stream[44];
1557 } tmp_key;
1558
1559 u8 *stream = (u8 *)atr_input;
1560 u8 int_key[44]; /* upper-most bit unused */
1561 u8 hash_str[46]; /* upper-most 2 bits unused */
1562 u16 hash_result = 0;
1563 int i, j, k, h;
1564
1565 /*
1566 * Initialize the fill member to prevent warnings
1567 * on some compilers
1568 */
1569 tmp_key.fill[0] = 0;
1570
1571 /* First load the temporary key stream */
1572 for (i = 0; i < 6; i++) {
1573 u64 fillkey = ((u64)key << 32) | key;
1574 tmp_key.fill[i] = fillkey;
1575 }
1576
1577 /*
1578 * Set the interim key for the hashing. Bit 352 is unused, so we must
1579 * shift and compensate when building the key.
1580 */
1581
1582 int_key[0] = tmp_key.key_stream[0] >> 1;
1583 for (i = 1, j = 0; i < 44; i++) {
1584 unsigned int this_key = tmp_key.key_stream[j] << 7;
1585 j++;
1586 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1587 }
1588
1589 /*
1590 * Set the interim bit string for the hashing. Bits 368 and 367 are
1591 * unused, so shift and compensate when building the string.
1592 */
1593 hash_str[0] = (stream[40] & 0x7f) >> 1;
1594 for (i = 1, j = 40; i < 46; i++) {
1595 unsigned int this_str = stream[j] << 7;
1596 j++;
1597 if (j > 41)
1598 j = 0;
1599 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1600 }
1601
1602 /*
1603 * Now compute the hash. i is the index into hash_str, j is into our
1604 * key stream, k is counting the number of bits, and h interates within
1605 * each byte.
1606 */
1607 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1608 for (h = 0; h < 8 && k < 351; h++, k++) {
1609 if (int_key[j] & (1 << h)) {
1610 /*
1611 * Key bit is set, XOR in the current 16-bit
1612 * string. Example of processing:
1613 * h = 0,
1614 * tmp = (hash_str[i - 2] & 0 << 16) |
1615 * (hash_str[i - 1] & 0xff << 8) |
1616 * (hash_str[i] & 0xff >> 0)
1617 * So tmp = hash_str[15 + k:k], since the
1618 * i + 2 clause rolls off the 16-bit value
1619 * h = 7,
1620 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1621 * (hash_str[i - 1] & 0xff << 1) |
1622 * (hash_str[i] & 0x80 >> 7)
1623 */
1624 int tmp = (hash_str[i] >> h);
1625 tmp |= (hash_str[i - 1] << (8 - h));
1626 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1627 << (16 - h);
1628 hash_result ^= (u16)tmp;
1629 }
1630 }
1631 }
1632
1633 return hash_result;
1634 }
1635
1636 /**
1637 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1638 * @input: input stream to modify
1639 * @vlan: the VLAN id to load
1640 **/
1641 s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1642 {
1643 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1644 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1645
1646 return 0;
1647 }
1648
1649 /**
1650 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1651 * @input: input stream to modify
1652 * @src_addr: the IP address to load
1653 **/
1654 s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1655 {
1656 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1657 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1658 (src_addr >> 16) & 0xff;
1659 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1660 (src_addr >> 8) & 0xff;
1661 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1662
1663 return 0;
1664 }
1665
1666 /**
1667 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1668 * @input: input stream to modify
1669 * @dst_addr: the IP address to load
1670 **/
1671 s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1672 {
1673 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1674 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1675 (dst_addr >> 16) & 0xff;
1676 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1677 (dst_addr >> 8) & 0xff;
1678 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1679
1680 return 0;
1681 }
1682
1683 /**
1684 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1685 * @input: input stream to modify
1686 * @src_addr_1: the first 4 bytes of the IP address to load
1687 * @src_addr_2: the second 4 bytes of the IP address to load
1688 * @src_addr_3: the third 4 bytes of the IP address to load
1689 * @src_addr_4: the fourth 4 bytes of the IP address to load
1690 **/
1691 s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
1692 u32 src_addr_1, u32 src_addr_2,
1693 u32 src_addr_3, u32 src_addr_4)
1694 {
1695 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1696 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1697 (src_addr_4 >> 8) & 0xff;
1698 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1699 (src_addr_4 >> 16) & 0xff;
1700 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1701
1702 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1703 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1704 (src_addr_3 >> 8) & 0xff;
1705 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1706 (src_addr_3 >> 16) & 0xff;
1707 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1708
1709 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1710 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1711 (src_addr_2 >> 8) & 0xff;
1712 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1713 (src_addr_2 >> 16) & 0xff;
1714 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1715
1716 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1717 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1718 (src_addr_1 >> 8) & 0xff;
1719 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1720 (src_addr_1 >> 16) & 0xff;
1721 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1722
1723 return 0;
1724 }
1725
1726 /**
1727 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1728 * @input: input stream to modify
1729 * @dst_addr_1: the first 4 bytes of the IP address to load
1730 * @dst_addr_2: the second 4 bytes of the IP address to load
1731 * @dst_addr_3: the third 4 bytes of the IP address to load
1732 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1733 **/
1734 s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
1735 u32 dst_addr_1, u32 dst_addr_2,
1736 u32 dst_addr_3, u32 dst_addr_4)
1737 {
1738 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1739 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1740 (dst_addr_4 >> 8) & 0xff;
1741 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1742 (dst_addr_4 >> 16) & 0xff;
1743 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1744
1745 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1746 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1747 (dst_addr_3 >> 8) & 0xff;
1748 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1749 (dst_addr_3 >> 16) & 0xff;
1750 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1751
1752 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1753 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1754 (dst_addr_2 >> 8) & 0xff;
1755 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1756 (dst_addr_2 >> 16) & 0xff;
1757 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1758
1759 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1760 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1761 (dst_addr_1 >> 8) & 0xff;
1762 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1763 (dst_addr_1 >> 16) & 0xff;
1764 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1765
1766 return 0;
1767 }
1768
1769 /**
1770 * ixgbe_atr_set_src_port_82599 - Sets the source port
1771 * @input: input stream to modify
1772 * @src_port: the source port to load
1773 **/
1774 s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1775 {
1776 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1777 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1778
1779 return 0;
1780 }
1781
1782 /**
1783 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1784 * @input: input stream to modify
1785 * @dst_port: the destination port to load
1786 **/
1787 s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1788 {
1789 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1790 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1791
1792 return 0;
1793 }
1794
1795 /**
1796 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1797 * @input: input stream to modify
1798 * @flex_bytes: the flexible bytes to load
1799 **/
1800 s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1801 {
1802 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1803 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1804
1805 return 0;
1806 }
1807
1808 /**
1809 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1810 * @input: input stream to modify
1811 * @vm_pool: the Virtual Machine pool to load
1812 **/
1813 s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
1814 u8 vm_pool)
1815 {
1816 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1817
1818 return 0;
1819 }
1820
1821 /**
1822 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1823 * @input: input stream to modify
1824 * @l4type: the layer 4 type value to load
1825 **/
1826 s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1827 {
1828 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1829
1830 return 0;
1831 }
1832
1833 /**
1834 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1835 * @input: input stream to search
1836 * @vlan: the VLAN id to load
1837 **/
1838 static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
1839 {
1840 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1841 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1842
1843 return 0;
1844 }
1845
1846 /**
1847 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1848 * @input: input stream to search
1849 * @src_addr: the IP address to load
1850 **/
1851 static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1852 u32 *src_addr)
1853 {
1854 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1855 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1856 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1857 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1858
1859 return 0;
1860 }
1861
1862 /**
1863 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1864 * @input: input stream to search
1865 * @dst_addr: the IP address to load
1866 **/
1867 static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1868 u32 *dst_addr)
1869 {
1870 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1871 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1872 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1873 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1874
1875 return 0;
1876 }
1877
1878 /**
1879 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1880 * @input: input stream to search
1881 * @src_addr_1: the first 4 bytes of the IP address to load
1882 * @src_addr_2: the second 4 bytes of the IP address to load
1883 * @src_addr_3: the third 4 bytes of the IP address to load
1884 * @src_addr_4: the fourth 4 bytes of the IP address to load
1885 **/
1886 static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1887 u32 *src_addr_1, u32 *src_addr_2,
1888 u32 *src_addr_3, u32 *src_addr_4)
1889 {
1890 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1891 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1892 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1893 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1894
1895 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1896 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1897 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1898 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1899
1900 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1901 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1902 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1903 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1904
1905 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1906 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1907 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1908 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1909
1910 return 0;
1911 }
1912
1913 /**
1914 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1915 * @input: input stream to search
1916 * @dst_addr_1: the first 4 bytes of the IP address to load
1917 * @dst_addr_2: the second 4 bytes of the IP address to load
1918 * @dst_addr_3: the third 4 bytes of the IP address to load
1919 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1920 **/
1921 s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
1922 u32 *dst_addr_1, u32 *dst_addr_2,
1923 u32 *dst_addr_3, u32 *dst_addr_4)
1924 {
1925 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1926 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1927 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1928 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1929
1930 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1931 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1932 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1933 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1934
1935 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1936 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1937 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1938 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1939
1940 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1941 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1942 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1943 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1944
1945 return 0;
1946 }
1947
1948 /**
1949 * ixgbe_atr_get_src_port_82599 - Gets the source port
1950 * @input: input stream to modify
1951 * @src_port: the source port to load
1952 *
1953 * Even though the input is given in big-endian, the FDIRPORT registers
1954 * expect the ports to be programmed in little-endian. Hence the need to swap
1955 * endianness when retrieving the data. This can be confusing since the
1956 * internal hash engine expects it to be big-endian.
1957 **/
1958 static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1959 u16 *src_port)
1960 {
1961 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1962 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1963
1964 return 0;
1965 }
1966
1967 /**
1968 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1969 * @input: input stream to modify
1970 * @dst_port: the destination port to load
1971 *
1972 * Even though the input is given in big-endian, the FDIRPORT registers
1973 * expect the ports to be programmed in little-endian. Hence the need to swap
1974 * endianness when retrieving the data. This can be confusing since the
1975 * internal hash engine expects it to be big-endian.
1976 **/
1977 static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1978 u16 *dst_port)
1979 {
1980 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1981 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1982
1983 return 0;
1984 }
1985
1986 /**
1987 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1988 * @input: input stream to modify
1989 * @flex_bytes: the flexible bytes to load
1990 **/
1991 static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1992 u16 *flex_byte)
1993 {
1994 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1995 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1996
1997 return 0;
1998 }
1999
2000 /**
2001 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
2002 * @input: input stream to modify
2003 * @vm_pool: the Virtual Machine pool to load
2004 **/
2005 s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
2006 u8 *vm_pool)
2007 {
2008 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
2009
2010 return 0;
2011 }
2012
2013 /**
2014 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
2015 * @input: input stream to modify
2016 * @l4type: the layer 4 type value to load
2017 **/
2018 static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
2019 u8 *l4type)
2020 {
2021 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
2022
2023 return 0;
2024 }
2025
2026 /**
2027 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
2028 * @hw: pointer to hardware structure
2029 * @stream: input bitstream
2030 * @queue: queue index to direct traffic to
2031 **/
2032 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
2033 struct ixgbe_atr_input *input,
2034 u8 queue)
2035 {
2036 u64 fdirhashcmd;
2037 u64 fdircmd;
2038 u32 fdirhash;
2039 u16 bucket_hash, sig_hash;
2040 u8 l4type;
2041
2042 bucket_hash = ixgbe_atr_compute_hash_82599(input,
2043 IXGBE_ATR_BUCKET_HASH_KEY);
2044
2045 /* bucket_hash is only 15 bits */
2046 bucket_hash &= IXGBE_ATR_HASH_MASK;
2047
2048 sig_hash = ixgbe_atr_compute_hash_82599(input,
2049 IXGBE_ATR_SIGNATURE_HASH_KEY);
2050
2051 /* Get the l4type in order to program FDIRCMD properly */
2052 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
2053 ixgbe_atr_get_l4type_82599(input, &l4type);
2054
2055 /*
2056 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
2057 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
2058 */
2059 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2060
2061 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
2062 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
2063
2064 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2065 case IXGBE_ATR_L4TYPE_TCP:
2066 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
2067 break;
2068 case IXGBE_ATR_L4TYPE_UDP:
2069 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
2070 break;
2071 case IXGBE_ATR_L4TYPE_SCTP:
2072 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
2073 break;
2074 default:
2075 hw_dbg(hw, "Error on l4type input\n");
2076 return IXGBE_ERR_CONFIG;
2077 }
2078
2079 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
2080 fdircmd |= IXGBE_FDIRCMD_IPV6;
2081
2082 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
2083 fdirhashcmd = ((fdircmd << 32) | fdirhash);
2084
2085 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
2086
2087 return 0;
2088 }
2089
2090 /**
2091 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
2092 * @hw: pointer to hardware structure
2093 * @input: input bitstream
2094 * @input_masks: bitwise masks for relevant fields
2095 * @soft_id: software index into the silicon hash tables for filter storage
2096 * @queue: queue index to direct traffic to
2097 *
2098 * Note that the caller to this function must lock before calling, since the
2099 * hardware writes must be protected from one another.
2100 **/
2101 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
2102 struct ixgbe_atr_input *input,
2103 struct ixgbe_atr_input_masks *input_masks,
2104 u16 soft_id, u8 queue)
2105 {
2106 u32 fdircmd = 0;
2107 u32 fdirhash;
2108 u32 src_ipv4 = 0, dst_ipv4 = 0;
2109 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
2110 u16 src_port, dst_port, vlan_id, flex_bytes;
2111 u16 bucket_hash;
2112 u8 l4type;
2113 u8 fdirm = 0;
2114
2115 /* Get our input values */
2116 ixgbe_atr_get_l4type_82599(input, &l4type);
2117
2118 /*
2119 * Check l4type formatting, and bail out before we touch the hardware
2120 * if there's a configuration issue
2121 */
2122 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2123 case IXGBE_ATR_L4TYPE_TCP:
2124 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
2125 break;
2126 case IXGBE_ATR_L4TYPE_UDP:
2127 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
2128 break;
2129 case IXGBE_ATR_L4TYPE_SCTP:
2130 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
2131 break;
2132 default:
2133 hw_dbg(hw, "Error on l4type input\n");
2134 return IXGBE_ERR_CONFIG;
2135 }
2136
2137 bucket_hash = ixgbe_atr_compute_hash_82599(input,
2138 IXGBE_ATR_BUCKET_HASH_KEY);
2139
2140 /* bucket_hash is only 15 bits */
2141 bucket_hash &= IXGBE_ATR_HASH_MASK;
2142
2143 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
2144 ixgbe_atr_get_src_port_82599(input, &src_port);
2145 ixgbe_atr_get_dst_port_82599(input, &dst_port);
2146 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
2147
2148 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2149
2150 /* Now figure out if we're IPv4 or IPv6 */
2151 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
2152 /* IPv6 */
2153 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
2154 &src_ipv6_3, &src_ipv6_4);
2155
2156 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
2157 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
2158 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
2159 /* The last 4 bytes is the same register as IPv4 */
2160 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
2161
2162 fdircmd |= IXGBE_FDIRCMD_IPV6;
2163 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
2164 } else {
2165 /* IPv4 */
2166 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
2167 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
2168 }
2169
2170 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
2171 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
2172
2173 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
2174 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
2175 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
2176 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
2177
2178 /*
2179 * Program the relevant mask registers. If src/dst_port or src/dst_addr
2180 * are zero, then assume a full mask for that field. Also assume that
2181 * a VLAN of 0 is unspecified, so mask that out as well. L4type
2182 * cannot be masked out in this implementation.
2183 *
2184 * This also assumes IPv4 only. IPv6 masking isn't supported at this
2185 * point in time.
2186 */
2187 if (src_ipv4 == 0)
2188 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xffffffff);
2189 else
2190 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
2191
2192 if (dst_ipv4 == 0)
2193 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xffffffff);
2194 else
2195 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
2196
2197 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2198 case IXGBE_ATR_L4TYPE_TCP:
2199 if (src_port == 0)
2200 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xffff);
2201 else
2202 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
2203 input_masks->src_port_mask);
2204
2205 if (dst_port == 0)
2206 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
2207 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
2208 (0xffff << 16)));
2209 else
2210 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
2211 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
2212 (input_masks->dst_port_mask << 16)));
2213 break;
2214 case IXGBE_ATR_L4TYPE_UDP:
2215 if (src_port == 0)
2216 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xffff);
2217 else
2218 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
2219 input_masks->src_port_mask);
2220
2221 if (dst_port == 0)
2222 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
2223 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
2224 (0xffff << 16)));
2225 else
2226 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
2227 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
2228 (input_masks->src_port_mask << 16)));
2229 break;
2230 default:
2231 /* this already would have failed above */
2232 break;
2233 }
2234
2235 /* Program the last mask register, FDIRM */
2236 if (input_masks->vlan_id_mask || !vlan_id)
2237 /* Mask both VLAN and VLANP - bits 0 and 1 */
2238 fdirm |= 0x3;
2239
2240 if (input_masks->data_mask || !flex_bytes)
2241 /* Flex bytes need masking, so mask the whole thing - bit 4 */
2242 fdirm |= 0x10;
2243
2244 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
2245 fdirm |= 0x24;
2246
2247 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
2248
2249 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
2250 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
2251 fdircmd |= IXGBE_FDIRCMD_LAST;
2252 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
2253 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
2254
2255 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2256 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
2257
2258 return 0;
2259 }
2260 /**
2261 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2262 * @hw: pointer to hardware structure
2263 * @reg: analog register to read
2264 * @val: read value
2265 *
2266 * Performs read operation to Omer analog register specified.
2267 **/
2268 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2269 {
2270 u32 core_ctl;
2271
2272 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2273 (reg << 8));
2274 IXGBE_WRITE_FLUSH(hw);
2275 udelay(10);
2276 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2277 *val = (u8)core_ctl;
2278
2279 return 0;
2280 }
2281
2282 /**
2283 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2284 * @hw: pointer to hardware structure
2285 * @reg: atlas register to write
2286 * @val: value to write
2287 *
2288 * Performs write operation to Omer analog register specified.
2289 **/
2290 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2291 {
2292 u32 core_ctl;
2293
2294 core_ctl = (reg << 8) | val;
2295 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2296 IXGBE_WRITE_FLUSH(hw);
2297 udelay(10);
2298
2299 return 0;
2300 }
2301
2302 /**
2303 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2304 * @hw: pointer to hardware structure
2305 *
2306 * Starts the hardware using the generic start_hw function.
2307 * Then performs device-specific:
2308 * Clears the rate limiter registers.
2309 **/
2310 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2311 {
2312 u32 q_num;
2313 s32 ret_val;
2314
2315 ret_val = ixgbe_start_hw_generic(hw);
2316
2317 /* Clear the rate limiters */
2318 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2319 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2320 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2321 }
2322 IXGBE_WRITE_FLUSH(hw);
2323
2324 /* We need to run link autotry after the driver loads */
2325 hw->mac.autotry_restart = true;
2326
2327 if (ret_val == 0)
2328 ret_val = ixgbe_verify_fw_version_82599(hw);
2329
2330 return ret_val;
2331 }
2332
2333 /**
2334 * ixgbe_identify_phy_82599 - Get physical layer module
2335 * @hw: pointer to hardware structure
2336 *
2337 * Determines the physical layer module found on the current adapter.
2338 **/
2339 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2340 {
2341 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2342 status = ixgbe_identify_phy_generic(hw);
2343 if (status != 0)
2344 status = ixgbe_identify_sfp_module_generic(hw);
2345 return status;
2346 }
2347
2348 /**
2349 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2350 * @hw: pointer to hardware structure
2351 *
2352 * Determines physical layer capabilities of the current configuration.
2353 **/
2354 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2355 {
2356 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2357 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2358 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2359 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2360 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2361 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2362 u16 ext_ability = 0;
2363 u8 comp_codes_10g = 0;
2364
2365 hw->phy.ops.identify(hw);
2366
2367 if (hw->phy.type == ixgbe_phy_tn ||
2368 hw->phy.type == ixgbe_phy_cu_unknown) {
2369 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2370 &ext_ability);
2371 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
2372 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2373 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
2374 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2375 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
2376 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2377 goto out;
2378 }
2379
2380 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2381 case IXGBE_AUTOC_LMS_1G_AN:
2382 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2383 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2384 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2385 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2386 goto out;
2387 } else
2388 /* SFI mode so read SFP module */
2389 goto sfp_check;
2390 break;
2391 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2392 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2393 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2394 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2395 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2396 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2397 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2398 goto out;
2399 break;
2400 case IXGBE_AUTOC_LMS_10G_SERIAL:
2401 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2402 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2403 goto out;
2404 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2405 goto sfp_check;
2406 break;
2407 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2408 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2409 if (autoc & IXGBE_AUTOC_KX_SUPP)
2410 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2411 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2412 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2413 if (autoc & IXGBE_AUTOC_KR_SUPP)
2414 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2415 goto out;
2416 break;
2417 default:
2418 goto out;
2419 break;
2420 }
2421
2422 sfp_check:
2423 /* SFP check must be done last since DA modules are sometimes used to
2424 * test KR mode - we need to id KR mode correctly before SFP module.
2425 * Call identify_sfp because the pluggable module may have changed */
2426 hw->phy.ops.identify_sfp(hw);
2427 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2428 goto out;
2429
2430 switch (hw->phy.type) {
2431 case ixgbe_phy_tw_tyco:
2432 case ixgbe_phy_tw_unknown:
2433 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2434 break;
2435 case ixgbe_phy_sfp_avago:
2436 case ixgbe_phy_sfp_ftl:
2437 case ixgbe_phy_sfp_intel:
2438 case ixgbe_phy_sfp_unknown:
2439 hw->phy.ops.read_i2c_eeprom(hw,
2440 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2441 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2442 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2443 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2444 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2445 break;
2446 default:
2447 break;
2448 }
2449
2450 out:
2451 return physical_layer;
2452 }
2453
2454 /**
2455 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2456 * @hw: pointer to hardware structure
2457 * @regval: register value to write to RXCTRL
2458 *
2459 * Enables the Rx DMA unit for 82599
2460 **/
2461 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2462 {
2463 #define IXGBE_MAX_SECRX_POLL 30
2464 int i;
2465 int secrxreg;
2466
2467 /*
2468 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2469 * If traffic is incoming before we enable the Rx unit, it could hang
2470 * the Rx DMA unit. Therefore, make sure the security engine is
2471 * completely disabled prior to enabling the Rx unit.
2472 */
2473 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2474 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2475 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2476 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2477 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2478 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2479 break;
2480 else
2481 udelay(10);
2482 }
2483
2484 /* For informational purposes only */
2485 if (i >= IXGBE_MAX_SECRX_POLL)
2486 hw_dbg(hw, "Rx unit being enabled before security "
2487 "path fully disabled. Continuing with init.\n");
2488
2489 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2490 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2491 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2492 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2493 IXGBE_WRITE_FLUSH(hw);
2494
2495 return 0;
2496 }
2497
2498 /**
2499 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2500 * @hw: pointer to hardware structure
2501 * @device_caps: the EEPROM word with the extra device capabilities
2502 *
2503 * This function will read the EEPROM location for the device capabilities,
2504 * and return the word through device_caps.
2505 **/
2506 static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
2507 {
2508 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2509
2510 return 0;
2511 }
2512
2513 /**
2514 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2515 * @hw: pointer to hardware structure
2516 * @san_mac_offset: SAN MAC address offset
2517 *
2518 * This function will read the EEPROM location for the SAN MAC address
2519 * pointer, and returns the value at that location. This is used in both
2520 * get and set mac_addr routines.
2521 **/
2522 static s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
2523 u16 *san_mac_offset)
2524 {
2525 /*
2526 * First read the EEPROM pointer to see if the MAC addresses are
2527 * available.
2528 */
2529 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2530
2531 return 0;
2532 }
2533
2534 /**
2535 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2536 * @hw: pointer to hardware structure
2537 * @san_mac_addr: SAN MAC address
2538 *
2539 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2540 * per-port, so set_lan_id() must be called before reading the addresses.
2541 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2542 * upon for non-SFP connections, so we must call it here.
2543 **/
2544 static s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
2545 {
2546 u16 san_mac_data, san_mac_offset;
2547 u8 i;
2548
2549 /*
2550 * First read the EEPROM pointer to see if the MAC addresses are
2551 * available. If they're not, no point in calling set_lan_id() here.
2552 */
2553 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2554
2555 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2556 /*
2557 * No addresses available in this EEPROM. It's not an
2558 * error though, so just wipe the local address and return.
2559 */
2560 for (i = 0; i < 6; i++)
2561 san_mac_addr[i] = 0xFF;
2562
2563 goto san_mac_addr_out;
2564 }
2565
2566 /* make sure we know which port we need to program */
2567 hw->mac.ops.set_lan_id(hw);
2568 /* apply the port offset to the address offset */
2569 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2570 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2571 for (i = 0; i < 3; i++) {
2572 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2573 san_mac_addr[i * 2] = (u8)(san_mac_data);
2574 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2575 san_mac_offset++;
2576 }
2577
2578 san_mac_addr_out:
2579 return 0;
2580 }
2581
2582 /**
2583 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2584 * @hw: pointer to hardware structure
2585 *
2586 * Verifies that installed the firmware version is 0.6 or higher
2587 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2588 *
2589 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2590 * if the FW version is not supported.
2591 **/
2592 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2593 {
2594 s32 status = IXGBE_ERR_EEPROM_VERSION;
2595 u16 fw_offset, fw_ptp_cfg_offset;
2596 u16 fw_version = 0;
2597
2598 /* firmware check is only necessary for SFI devices */
2599 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2600 status = 0;
2601 goto fw_version_out;
2602 }
2603
2604 /* get the offset to the Firmware Module block */
2605 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2606
2607 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2608 goto fw_version_out;
2609
2610 /* get the offset to the Pass Through Patch Configuration block */
2611 hw->eeprom.ops.read(hw, (fw_offset +
2612 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2613 &fw_ptp_cfg_offset);
2614
2615 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2616 goto fw_version_out;
2617
2618 /* get the firmware version */
2619 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2620 IXGBE_FW_PATCH_VERSION_4),
2621 &fw_version);
2622
2623 if (fw_version > 0x5)
2624 status = 0;
2625
2626 fw_version_out:
2627 return status;
2628 }
2629
2630 /**
2631 * ixgbe_get_wwn_prefix_82599 - Get alternative WWNN/WWPN prefix from
2632 * the EEPROM
2633 * @hw: pointer to hardware structure
2634 * @wwnn_prefix: the alternative WWNN prefix
2635 * @wwpn_prefix: the alternative WWPN prefix
2636 *
2637 * This function will read the EEPROM from the alternative SAN MAC address
2638 * block to check the support for the alternative WWNN/WWPN prefix support.
2639 **/
2640 static s32 ixgbe_get_wwn_prefix_82599(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2641 u16 *wwpn_prefix)
2642 {
2643 u16 offset, caps;
2644 u16 alt_san_mac_blk_offset;
2645
2646 /* clear output first */
2647 *wwnn_prefix = 0xFFFF;
2648 *wwpn_prefix = 0xFFFF;
2649
2650 /* check if alternative SAN MAC is supported */
2651 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2652 &alt_san_mac_blk_offset);
2653
2654 if ((alt_san_mac_blk_offset == 0) ||
2655 (alt_san_mac_blk_offset == 0xFFFF))
2656 goto wwn_prefix_out;
2657
2658 /* check capability in alternative san mac address block */
2659 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2660 hw->eeprom.ops.read(hw, offset, &caps);
2661 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2662 goto wwn_prefix_out;
2663
2664 /* get the corresponding prefix for WWNN/WWPN */
2665 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2666 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2667
2668 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2669 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2670
2671 wwn_prefix_out:
2672 return 0;
2673 }
2674
2675 static struct ixgbe_mac_operations mac_ops_82599 = {
2676 .init_hw = &ixgbe_init_hw_generic,
2677 .reset_hw = &ixgbe_reset_hw_82599,
2678 .start_hw = &ixgbe_start_hw_82599,
2679 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2680 .get_media_type = &ixgbe_get_media_type_82599,
2681 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2682 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2683 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2684 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
2685 .get_device_caps = &ixgbe_get_device_caps_82599,
2686 .get_wwn_prefix = &ixgbe_get_wwn_prefix_82599,
2687 .stop_adapter = &ixgbe_stop_adapter_generic,
2688 .get_bus_info = &ixgbe_get_bus_info_generic,
2689 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2690 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2691 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2692 .setup_link = &ixgbe_setup_mac_link_82599,
2693 .check_link = &ixgbe_check_mac_link_82599,
2694 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2695 .led_on = &ixgbe_led_on_generic,
2696 .led_off = &ixgbe_led_off_generic,
2697 .blink_led_start = &ixgbe_blink_led_start_generic,
2698 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2699 .set_rar = &ixgbe_set_rar_generic,
2700 .clear_rar = &ixgbe_clear_rar_generic,
2701 .set_vmdq = &ixgbe_set_vmdq_82599,
2702 .clear_vmdq = &ixgbe_clear_vmdq_82599,
2703 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2704 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2705 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2706 .enable_mc = &ixgbe_enable_mc_generic,
2707 .disable_mc = &ixgbe_disable_mc_generic,
2708 .clear_vfta = &ixgbe_clear_vfta_82599,
2709 .set_vfta = &ixgbe_set_vfta_82599,
2710 .fc_enable = &ixgbe_fc_enable_generic,
2711 .init_uta_tables = &ixgbe_init_uta_tables_82599,
2712 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2713 };
2714
2715 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2716 .init_params = &ixgbe_init_eeprom_params_generic,
2717 .read = &ixgbe_read_eeprom_generic,
2718 .write = &ixgbe_write_eeprom_generic,
2719 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2720 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2721 };
2722
2723 static struct ixgbe_phy_operations phy_ops_82599 = {
2724 .identify = &ixgbe_identify_phy_82599,
2725 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2726 .init = &ixgbe_init_phy_ops_82599,
2727 .reset = &ixgbe_reset_phy_generic,
2728 .read_reg = &ixgbe_read_phy_reg_generic,
2729 .write_reg = &ixgbe_write_phy_reg_generic,
2730 .setup_link = &ixgbe_setup_phy_link_generic,
2731 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2732 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2733 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2734 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2735 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2736 };
2737
2738 struct ixgbe_info ixgbe_82599_info = {
2739 .mac = ixgbe_mac_82599EB,
2740 .get_invariants = &ixgbe_get_invariants_82599,
2741 .mac_ops = &mac_ops_82599,
2742 .eeprom_ops = &eeprom_ops_82599,
2743 .phy_ops = &phy_ops_82599,
2744 .mbx_ops = &mbx_ops_82599,
2745 };
Mirror of NV Tegra kernel