| blob | 5770491b30ce13ae7d43a39e47fc47f0d4287ffe |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2024 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
23 #define INCLUDE_STRING
24 #define INCLUDE_ALGORITHM
25 #define INCLUDE_MEMORY
26 #define INCLUDE_VECTOR
102 /* This file should be included last. */
105 /* Defined for convenience. */
106 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
108 /* Maximum bytes set for an inline memset expansion. With -Os use 3 STP
109 and 1 MOVI/DUP (same size as a call). */
110 #define MAX_SET_SIZE(speed) (speed ? 256 : 96)
112 /* Flags that describe how a function shares certain architectural state
113 with its callers.
115 - AARCH64_STATE_SHARED indicates that the function does share the state
116 with callers.
118 - AARCH64_STATE_IN indicates that the function reads (or might read) the
119 incoming state. The converse is that the function ignores the incoming
120 state.
122 - AARCH64_STATE_OUT indicates that the function returns new state.
123 The converse is that the state on return is the same as it was on entry.
125 A function that partially modifies the state treats it as both IN
126 and OUT (because the value on return depends to some extent on the
127 value on input). */
132 /* Information about a legitimate vector immediate operand. */
133 struct simd_immediate_info
134 {
146 /* The mode of the elements. */
147 scalar_mode elt_mode;
149 /* The instruction to use to move the immediate into a vector. */
150 insn_type insn;
152 union
153 {
154 /* For MOV and MVN. */
155 struct
156 {
157 /* The value of each element. */
158 rtx value;
160 /* The kind of shift modifier to use, and the number of bits to shift.
161 This is (LSL, 0) if no shift is needed. */
162 modifier_type modifier;
166 /* For INDEX. */
167 struct
168 {
169 /* The value of the first element and the step to be added for each
170 subsequent element. */
174 /* For PTRUE. */
175 aarch64_svpattern pattern;
177 };
179 /* Construct a floating-point immediate in which each element has mode
180 ELT_MODE_IN and value VALUE_IN. */
181 inline simd_immediate_info
184 {
188 }
190 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
191 and value VALUE_IN. The other parameters are as for the structure
192 fields. */
193 inline simd_immediate_info
199 {
203 }
205 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
206 and where element I is equal to BASE_IN + I * STEP_IN. */
207 inline simd_immediate_info
210 {
213 }
215 /* Construct a predicate that controls elements of mode ELT_MODE_IN
216 and has PTRUE pattern PATTERN_IN. */
217 inline simd_immediate_info
219 aarch64_svpattern pattern_in)
221 {
223 }
227 /* Describes types that map to Pure Scalable Types (PSTs) in the AAPCS64. */
228 class pure_scalable_type_info
229 {
231 /* Represents the result of analyzing a type. All values are nonzero,
232 in the possibly forlorn hope that accidental conversions to bool
233 trigger a warning. */
234 enum analysis_result
235 {
236 /* The type does not have an ABI identity; i.e. it doesn't contain
237 at least one object whose type is a Fundamental Data Type. */
240 /* The type is definitely a Pure Scalable Type. */
241 IS_PST,
243 /* The type is definitely not a Pure Scalable Type. */
244 ISNT_PST,
246 /* It doesn't matter for PCS purposes whether the type is a Pure
247 Scalable Type or not, since the type will be handled the same
248 way regardless.
250 Specifically, this means that if the type is a Pure Scalable Type,
251 there aren't enough argument registers to hold it, and so it will
252 need to be passed or returned in memory. If the type isn't a
253 Pure Scalable Type, it's too big to be passed or returned in core
254 or SIMD&FP registers, and so again will need to go in memory. */
255 DOESNT_MATTER
256 };
258 /* Aggregates of 17 bytes or more are normally passed and returned
259 in memory, so aggregates of that size can safely be analyzed as
260 DOESNT_MATTER. We need to be able to collect enough pieces to
261 represent a PST that is smaller than that. Since predicates are
262 2 bytes in size for -msve-vector-bits=128, that means we need to be
263 able to store at least 8 pieces.
265 We also need to be able to store enough pieces to represent
266 a single vector in each vector argument register and a single
267 predicate in each predicate argument register. This means that
268 we need at least 12 pieces. */
272 /* Describes one piece of a PST. Each piece is one of:
274 - a single Scalable Vector Type (SVT)
275 - a single Scalable Predicate Type (SPT)
276 - a PST containing 2, 3 or 4 SVTs, with no padding
278 It either represents a single built-in type or a PST formed from
279 multiple homogeneous built-in types. */
280 struct piece
281 {
284 /* The number of vector and predicate registers that the piece
285 occupies. One of the two is always zero. */
289 /* The mode of the registers described above. */
290 machine_mode mode;
292 /* If this piece is formed from multiple homogeneous built-in types,
293 this is the mode of the built-in types, otherwise it is MODE. */
294 machine_mode orig_mode;
296 /* The offset in bytes of the piece from the start of the type. */
297 poly_uint64 offset;
298 };
300 /* Divides types analyzed as IS_PST into individual pieces. The pieces
301 are in memory order. */
316 };
317 }
319 /* The current code model. */
324 /* The number of 64-bit elements in an SVE vector. */
325 poly_uint16 aarch64_sve_vg;
327 #ifdef HAVE_AS_TLS
328 #undef TARGET_HAVE_TLS
329 #define TARGET_HAVE_TLS 1
330 #endif
335 const_tree,
344 const_tree type,
349 aarch64_addr_query_type);
351 /* The processor for which instructions should be scheduled. */
354 /* Global flag for PC relative loads. */
357 /* Global flag for whether frame pointer is enabled. */
360 /* Support for command line parsing of boolean flags in the tuning
361 structures. */
362 struct aarch64_flag_desc
363 {
366 };
368 #define AARCH64_FUSION_PAIR(name, internal_name) \
369 { name, AARCH64_FUSE_##internal_name },
371 {
376 };
378 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
379 { name, AARCH64_EXTRA_TUNE_##internal_name },
381 {
386 };
388 /* Tuning parameters. */
421 /* Support for fine-grained override of the tuning structures. */
422 struct aarch64_tuning_override_function
423 {
426 };
432 static const struct aarch64_tuning_override_function
433 aarch64_tuning_override_functions[] =
434 {
439 };
441 /* A processor implementing AArch64. */
442 struct processor
443 {
445 aarch64_processor ident;
446 aarch64_processor sched_core;
447 aarch64_arch arch;
448 aarch64_feature_flags flags;
450 };
452 /* Architectures implementing AArch64. */
454 {
455 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, D, E) \
456 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, \
457 feature_deps::ARCH_IDENT ().enable, NULL},
460 };
462 /* Processor cores implementing AArch64. */
464 {
465 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, E, COSTS, G, H, I) \
466 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
467 feature_deps::cpu_##IDENT, &COSTS##_tunings},
470 };
471 /* Internal representation of system registers. */
474 /* Stringified sysreg encoding values, represented as
475 s<sn>_<op1>_c<cn>_c<cm>_<op2>. */
477 /* Flags affecting sysreg usage, such as read/write-only. */
479 /* Architectural features implied by sysreg. */
480 aarch64_feature_flags arch_reqs;
483 /* An aarch64_feature_set initializer for a single feature,
484 AARCH64_FEATURE_<FEAT>. */
485 #define AARCH64_FEATURE(FEAT) AARCH64_FL_##FEAT
487 /* Used by AARCH64_FEATURES. */
488 #define AARCH64_OR_FEATURES_1(X, F1) \
489 AARCH64_FEATURE (F1)
490 #define AARCH64_OR_FEATURES_2(X, F1, F2) \
491 (AARCH64_FEATURE (F1) | AARCH64_OR_FEATURES_1 (X, F2))
492 #define AARCH64_OR_FEATURES_3(X, F1, ...) \
493 (AARCH64_FEATURE (F1) | AARCH64_OR_FEATURES_2 (X, __VA_ARGS__))
495 /* An aarch64_feature_set initializer for the N features listed in "...". */
496 #define AARCH64_FEATURES(N, ...) \
497 AARCH64_OR_FEATURES_##N (0, __VA_ARGS__)
499 #define AARCH64_NO_FEATURES 0
501 /* Flags associated with the properties of system registers. It mainly serves
502 to mark particular registers as read or write only. */
503 #define F_DEPRECATED (1 << 1)
504 #define F_REG_READ (1 << 2)
505 #define F_REG_WRITE (1 << 3)
506 #define F_ARCHEXT (1 << 4)
507 /* Flag indicating register name is alias for another system register. */
508 #define F_REG_ALIAS (1 << 5)
509 /* Flag indicatinig registers which may be implemented with 128-bits. */
510 #define F_REG_128 (1 << 6)
512 /* Database of system registers, their encodings and architectural
513 requirements. */
515 {
517 #define SYSREG(NAME, ENC, FLAGS, ARCH) \
518 { NAME, ENC, FLAGS, ARCH },
520 #undef CPENC
521 };
523 #undef AARCH64_NO_FEATURES
528 /* Map system register names to their hardware metadata: encoding,
529 feature flags and architectural feature requirements, all of which
530 are encoded in a sysreg_t struct. */
531 void
533 {
536 }
538 /* Lazily initialize hash table for system register validation,
539 checking the validity of supplied register name and returning
540 register's associated metadata. */
541 static void
543 {
549 {
552 }
553 }
555 /* No direct access to the sysreg hash-map should be made. Doing so
556 risks trying to acess an unitialized hash-map and dereferencing the
557 returned double pointer without due care risks dereferencing a
558 null-pointer. */
561 {
569 }
571 /* The current tuning set. */
574 /* If NAME is the name of an arm:: attribute that describes shared state,
575 return its associated AARCH64_STATE_* flags, otherwise return 0. */
576 static unsigned int
578 {
588 }
590 /* See whether attribute list ATTRS has any sharing information
591 for state STATE_NAME. Return the associated state flags if so,
592 otherwise return 0. */
593 static unsigned int
595 {
597 {
607 {
612 }
613 }
615 }
617 /* Return true if DECL creates a new scope for state STATE_STRING. */
618 static bool
620 {
623 {
628 }
630 }
632 /* Return true if attribute argument VALUE is a recognized state string,
633 otherwise report an error. NAME is the name of the attribute to which
634 VALUE is being passed. */
635 static bool
637 {
639 {
642 }
647 {
650 }
653 }
655 /* qsort callback to compare two STRING_CSTs. */
656 static int
658 {
661 }
663 /* Canonicalize a list of state strings. ARGS contains the arguments to
664 a new attribute while OLD_ATTR, if nonnull, contains a previous attribute
665 of the same type. If CAN_MERGE_IN_PLACE, it is safe to adjust OLD_ATTR's
666 arguments and drop the new attribute. Otherwise, the new attribute must
667 be kept and ARGS must include the information in OLD_ATTR.
669 In both cases, the new arguments must be a sorted list of state strings
670 with duplicates removed.
672 Return true if new attribute should be kept, false if it should be
673 dropped. */
674 static bool
677 {
678 /* Get a sorted list of all state strings (including duplicates). */
680 {
684 };
691 /* The list can be empty if there was no previous attribute and if all
692 the new arguments are erroneous. Drop the attribute in that case. */
696 /* Destructively modify one of the argument lists, removing duplicates
697 on the fly. */
702 {
708 else
711 }
714 }
716 /* Check whether an 'aarch64_vector_pcs' attribute is valid. */
718 static tree
721 {
722 /* Since we set fn_type_req to true, the caller should have checked
723 this for us. */
726 {
733 name);
740 }
742 }
744 /* Return true if arm::new(ARGS) is compatible with the type of decl DECL,
745 otherwise report an error. */
746 static bool
748 {
751 {
754 {
757 {
759 "cannot create a new %qs scope since %qs is shared"
762 }
763 }
764 }
766 }
768 /* Callback for arm::new attributes. */
769 static tree
771 {
774 {
778 }
780 {
783 }
789 {
792 }
794 /* If there is an old attribute, we should try to update it in-place,
795 so that there is only one (definitive) arm::new attribute on the decl. */
801 }
803 /* Callback for arm::{in,out,inout,preserves} attributes. */
804 static tree
807 {
812 {
815 {
818 state_name);
820 {
824 }
825 }
826 }
828 /* We can't update an old attribute in-place, since types are shared.
829 Instead make sure that this new attribute contains all the
830 information, so that the old attribute becomes redundant. */
832 old_attrs);
837 }
839 /* Mutually-exclusive function type attributes for controlling PSTATE.SM. */
841 {
842 /* Attribute name exclusion applies to:
843 function, type, variable */
847 };
849 /* Table of machine attributes. */
851 {
852 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
853 affects_type_identity, handler, exclude } */
858 NULL },
862 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
865 #endif
866 #ifdef SUBTARGET_ATTRIBUTE_TABLE
867 SUBTARGET_ATTRIBUTE_TABLE
868 #endif
869 };
872 {
874 };
877 {
893 };
896 {
898 };
901 {
903 &aarch64_arm_attribute_table
904 };
907 {
911 }
912 aarch64_cc;
914 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
917 /* The condition codes of the processor, and the inverse function. */
919 {
922 };
924 /* The preferred condition codes for SVE conditions. */
926 {
929 };
931 /* Return the assembly token for svpattern value VALUE. */
935 {
937 {
938 #define CASE(UPPER, LOWER, VALUE) case AARCH64_SV_##UPPER: return #LOWER;
940 #undef CASE
943 }
945 }
947 /* Return the location of a piece that is known to be passed or returned
948 in registers. FIRST_ZR is the first unused vector argument register
949 and FIRST_PR is the first unused predicate argument register. */
951 rtx
954 {
966 }
968 /* Return the total number of vector registers required by the PST. */
970 unsigned int
972 {
977 }
979 /* Return the total number of predicate registers required by the PST. */
981 unsigned int
983 {
988 }
990 /* Return the location of a PST that is known to be passed or returned
991 in registers. FIRST_ZR is the first unused vector argument register
992 and FIRST_PR is the first unused predicate argument register. */
994 rtx
998 {
999 /* Try to return a single REG if possible. This leads to better
1000 code generation; it isn't required for correctness. */
1002 {
1005 }
1007 /* Build up a PARALLEL that contains the individual pieces. */
1010 {
1016 }
1018 }
1020 /* Analyze whether TYPE is a Pure Scalable Type according to the rules
1021 in the AAPCS64. */
1025 {
1026 /* Prevent accidental reuse. */
1029 /* No code will be generated for erroneous types, so we won't establish
1030 an ABI mapping. */
1034 /* Zero-sized types disappear in the language->ABI mapping. */
1038 /* Check for SVTs, SPTs, and built-in tuple types that map to PSTs. */
1039 piece p = {};
1041 {
1049 }
1051 /* Check for user-defined PSTs. */
1058 }
1060 /* Analyze a type that is known not to be passed or returned in memory.
1061 Return true if it has an ABI identity and is a Pure Scalable Type. */
1063 bool
1065 {
1069 }
1071 /* Subroutine of analyze for handling ARRAY_TYPEs. */
1075 {
1076 /* Analyze the element type. */
1077 pure_scalable_type_info element_info;
1082 /* An array of unknown, flexible or variable length will be passed and
1083 returned by reference whatever we do. */
1088 /* Likewise if the array is constant-sized but too big to be interesting.
1089 The double checks against MAX_PIECES are to protect against overflow. */
1097 /* The above checks should have weeded out elements of unknown size. */
1098 poly_uint64 element_bytes;
1102 /* Build up the list of individual vectors and predicates. */
1106 {
1110 }
1112 }
1114 /* Subroutine of analyze for handling RECORD_TYPEs. */
1118 {
1120 {
1124 /* Zero-sized fields disappear in the language->ABI mapping. */
1128 /* All fields with an ABI identity must be PSTs for the record as
1129 a whole to be a PST. If any individual field is too big to be
1130 interesting then the record is too. */
1131 pure_scalable_type_info field_info;
1138 /* Since all previous fields are PSTs, we ought to be able to track
1139 the field offset using poly_ints. */
1143 /* For the same reason, it shouldn't be possible to create a PST field
1144 whose offset isn't byte-aligned. */
1146 BITS_PER_UNIT);
1148 /* Punt if the record is too big to be interesting. */
1149 poly_uint64 bytepos;
1154 /* Add the individual vectors and predicates in the field to the
1155 record's list. */
1158 {
1162 }
1163 }
1164 /* Empty structures disappear in the language->ABI mapping. */
1166 }
1168 /* Add P to the list of pieces in the type. */
1170 void
1172 {
1173 /* Try to fold the new piece into the previous one to form a
1174 single-mode PST. For example, if we see three consecutive vectors
1175 of the same mode, we can represent them using the corresponding
1176 3-tuple mode.
1178 This is purely an optimization. */
1180 {
1193 {
1197 }
1198 }
1200 }
1202 /* Return true if at least one possible value of type TYPE includes at
1203 least one object of Pure Scalable Type, in the sense of the AAPCS64.
1205 This is a relatively expensive test for some types, so it should
1206 generally be made as late as possible. */
1208 static bool
1210 {
1227 }
1229 /* Return the descriptor of the SIMD ABI. */
1233 {
1236 {
1237 HARD_REG_SET full_reg_clobbers
1243 }
1245 }
1247 /* Return the descriptor of the SVE PCS. */
1251 {
1254 {
1255 HARD_REG_SET full_reg_clobbers
1262 }
1264 }
1266 /* If X is an UNSPEC_SALT_ADDR expression, return the address that it
1267 wraps, otherwise return X itself. */
1269 static rtx
1271 {
1278 }
1280 /* Like strip_offset, but also strip any UNSPEC_SALT_ADDR from the
1281 expression. */
1283 static rtx
1285 {
1287 }
1289 /* Generate code to enable conditional branches in functions over 1 MiB. */
1293 {
1310 }
1312 void
1314 {
1319 else
1322 else
1326 else
1329 }
1331 /* Report when we try to do something that requires SVE when SVE is disabled.
1332 This is an error of last resort and isn't very high-quality. It usually
1333 involves attempts to measure the vector length in some way. */
1334 static void
1336 {
1339 /* Avoid reporting a slew of messages for a single oversight. */
1345 " option %<-march%>, or by using the %<target%>"
1348 }
1350 /* Return true if REGNO is P0-P15 or one of the special FFR-related
1351 registers. */
1354 {
1356 }
1358 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
1359 The register allocator chooses POINTER_AND_FP_REGS if FP_REGS and
1360 GENERAL_REGS have the same cost - even if POINTER_AND_FP_REGS has a much
1361 higher cost. POINTER_AND_FP_REGS is also used if the cost of both FP_REGS
1362 and GENERAL_REGS is lower than the memory cost (in this case the best class
1363 is the lowest cost one). Using POINTER_AND_FP_REGS irrespectively of its
1364 cost results in bad allocations with many redundant int<->FP moves which
1365 are expensive on various cores.
1366 To avoid this we don't allow POINTER_AND_FP_REGS as the allocno class, but
1367 force a decision between FP_REGS and GENERAL_REGS. We use the allocno class
1368 if it isn't POINTER_AND_FP_REGS. Similarly, use the best class if it isn't
1369 POINTER_AND_FP_REGS. Otherwise set the allocno class depending on the mode.
1370 The result of this is that it is no longer inefficient to have a higher
1371 memory move cost than the register move cost.
1372 */
1374 static reg_class_t
1376 reg_class_t best_class)
1377 {
1378 machine_mode mode;
1390 }
1392 static unsigned int
1394 {
1398 }
1400 /* Return the reassociation width of treeop OPC with mode MODE. */
1401 static int
1403 {
1408 /* Reassociation reduces the number of FMAs which may result in worse
1409 performance. Use a per-CPU setting for FMA reassociation which allows
1410 narrow CPUs with few FP pipes to switch it off (value of 1), and wider
1411 CPUs with many FP pipes to enable reassociation.
1412 Since the reassociation pass doesn't understand FMA at all, assume
1413 that any FP addition might turn into FMA. */
1418 }
1420 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
1421 unsigned
1423 {
1435 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
1436 equivalent DWARF register. */
1438 }
1440 /* Implement TARGET_DWARF_FRAME_REG_MODE. */
1441 static machine_mode
1443 {
1444 /* Predicate registers are call-clobbered in the EH ABI (which is
1445 ARM_PCS_AAPCS64), so they should not be described by CFI.
1446 Their size changes as VL changes, so any values computed by
1447 __builtin_init_dwarf_reg_size_table might not be valid for
1448 all frames. */
1452 }
1454 /* Implement TARGET_OUTPUT_CFI_DIRECTIVE. */
1455 static bool
1457 {
1460 {
1463 }
1465 }
1467 /* Implement TARGET_DW_CFI_OPRND1_DESC. */
1468 static bool
1471 {
1473 {
1476 }
1478 }
1480 /* If X is a CONST_DOUBLE, return its bit representation as a constant
1481 integer, otherwise return X unmodified. */
1482 static rtx
1484 {
1488 }
1490 /* Return an estimate for the number of quadwords in an SVE vector. This is
1491 equivalent to the number of Advanced SIMD vectors in an SVE vector. */
1492 static unsigned int
1494 {
1496 }
1498 /* Return true if MODE is an SVE predicate mode. */
1499 static bool
1501 {
1507 }
1509 /* Three mutually-exclusive flags describing a vector or predicate type. */
1513 /* Indicates a structure of 2, 3 or 4 vectors or predicates. */
1515 /* Can be used in combination with VEC_SVE_DATA to indicate that the
1516 vector has fewer significant bytes than a full SVE vector. */
1518 /* Useful combinations of the above. */
1522 /* Return a set of flags describing the vector properties of mode MODE.
1523 If ANY_TARGET_P is false (the default), ignore modes that are not supported
1524 by the current target. Otherwise categorize the modes that can be used
1525 with the set of all targets supported by the port. */
1527 static unsigned int
1529 {
1533 /* Make the decision based on the mode's enum value rather than its
1534 properties, so that we keep the correct classification regardless
1535 of -msve-vector-bits. */
1537 {
1538 /* Partial SVE QI vectors. */
1542 /* Partial SVE HI vectors. */
1545 /* Partial SVE SI vector. */
1547 /* Partial SVE HF vectors. */
1550 /* Partial SVE BF vectors. */
1553 /* Partial SVE SF vector. */
1567 /* x2 SVE vectors. */
1576 /* x3 SVE vectors. */
1585 /* x4 SVE vectors. */
1601 /* Structures of 64-bit Advanced SIMD vectors. */
1629 /* Structures of 128-bit Advanced SIMD vectors. */
1656 /* 64-bit Advanced SIMD vectors. */
1665 /* 128-bit Advanced SIMD vectors. */
1681 }
1682 }
1684 /* Return true if MODE is any of the Advanced SIMD structure modes. */
1685 bool
1687 {
1690 }
1692 /* Return true if MODE is an Advanced SIMD D-register structure mode. */
1693 static bool
1695 {
1698 }
1700 /* Return true if MODE is an Advanced SIMD Q-register structure mode. */
1701 static bool
1703 {
1705 }
1707 /* Return true if MODE is any of the data vector modes, including
1708 structure modes. */
1709 static bool
1711 {
1713 }
1715 /* Return true if MODE is any form of SVE mode, including predicates,
1716 vectors and structures. */
1717 bool
1719 {
1721 }
1723 /* Return true if MODE is an SVE data vector mode; either a single vector
1724 or a structure of vectors. */
1725 static bool
1727 {
1729 }
1731 /* Return the number of defined bytes in one constituent vector of
1732 SVE mode MODE, which has vector flags VEC_FLAGS. */
1733 static poly_int64
1735 {
1737 /* A single partial vector. */
1741 /* A single vector or a tuple. */
1744 /* A single predicate. */
1747 }
1749 /* If MODE holds an array of vectors, return the number of vectors
1750 in the array, otherwise return 1. */
1752 static unsigned int
1754 {
1764 }
1766 /* Given an Advanced SIMD vector mode MODE and a tuple size NELEMS, return the
1767 corresponding vector structure mode. */
1768 static opt_machine_mode
1771 {
1776 machine_mode struct_mode;
1784 }
1786 /* Return the SVE vector mode that has NUNITS elements of mode INNER_MODE. */
1788 opt_machine_mode
1790 {
1793 machine_mode mode;
1800 }
1802 /* Implement target hook TARGET_ARRAY_MODE. */
1803 static opt_machine_mode
1805 {
1807 {
1808 /* Use VNx32BI for pairs of predicates, but explicitly reject giving
1809 a mode to other array sizes. Using integer modes requires a round
1810 trip through memory and generates terrible code. */
1816 }
1827 }
1829 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1830 static bool
1833 {
1841 }
1843 /* MODE is some form of SVE vector mode. For data modes, return the number
1844 of vector register bits that each element of MODE occupies, such as 64
1845 for both VNx2DImode and VNx2SImode (where each 32-bit value is stored
1846 in a 64-bit container). For predicate modes, return the number of
1847 data bits controlled by each significant predicate bit. */
1849 static unsigned int
1851 {
1854 ? BITS_PER_SVE_VECTOR
1857 }
1859 /* Return the SVE predicate mode to use for elements that have
1860 ELEM_NBYTES bytes, if such a mode exists. */
1862 opt_machine_mode
1864 {
1866 {
1875 }
1877 }
1879 /* Return the SVE predicate mode that should be used to control
1880 SVE mode MODE. */
1882 machine_mode
1884 {
1887 }
1889 /* Implement TARGET_VECTORIZE_GET_MASK_MODE. */
1891 static opt_machine_mode
1893 {
1899 }
1901 /* Return the integer element mode associated with SVE mode MODE. */
1903 static scalar_int_mode
1905 {
1907 ? BITS_PER_SVE_VECTOR
1912 }
1914 /* Return an integer element mode that contains exactly
1915 aarch64_sve_container_bits (MODE) bits. This is wider than
1916 aarch64_sve_element_int_mode if MODE is a partial vector,
1917 otherwise it's the same. */
1919 static scalar_int_mode
1921 {
1923 }
1925 /* Return the integer vector mode associated with SVE mode MODE.
1926 Unlike related_int_vector_mode, this can handle the case in which
1927 MODE is a predicate (and thus has a different total size). */
1929 machine_mode
1931 {
1934 }
1936 /* Look for a vector mode with the same classification as VEC_MODE,
1937 but with each group of FACTOR elements coalesced into a single element.
1938 In other words, look for a mode in which the elements are FACTOR times
1939 larger and in which the number of elements is FACTOR times smaller.
1941 Return the mode found, if one exists. */
1943 static opt_machine_mode
1945 {
1950 {
1954 }
1956 scalar_mode new_elt_mode;
1961 {
1966 }
1968 {
1969 poly_uint64 new_nunits;
1972 }
1974 }
1976 /* Implement TARGET_VECTORIZE_RELATED_MODE. */
1978 static opt_machine_mode
1980 scalar_mode element_mode,
1981 poly_uint64 nunits)
1982 {
1985 /* If we're operating on SVE vectors, try to return an SVE mode. */
1986 poly_uint64 sve_nunits;
1990 {
1991 machine_mode sve_mode;
1993 {
1994 /* Try to find a full or partial SVE mode with exactly
1995 NUNITS units. */
2000 }
2001 else
2002 {
2003 /* Take the preferred number of units from the number of bytes
2004 that fit in VECTOR_MODE. We always start by "autodetecting"
2005 a full vector mode with preferred_simd_mode, so vectors
2006 chosen here will also be full vector modes. Then
2007 autovectorize_vector_modes tries smaller starting modes
2008 and thus smaller preferred numbers of units. */
2013 }
2014 }
2016 /* Prefer to use 1 128-bit vector instead of 2 64-bit vectors. */
2023 {
2027 }
2030 }
2032 /* Implement TARGET_VECTORIZE_PREFERRED_DIV_AS_SHIFTS_OVER_MULT. */
2034 static bool
2036 {
2043 }
2045 /* Implement TARGET_PREFERRED_ELSE_VALUE. For binary operations,
2046 prefer to use the first arithmetic operand as the else value if
2047 the else value doesn't matter, since that exactly matches the SVE
2048 destructive merging form. For ternary operations we could either
2049 pick the first operand and use FMAD-like instructions or the last
2050 operand and use FMLA-like instructions; the latter seems more
2051 natural. */
2053 static tree
2055 {
2057 }
2059 /* Implement TARGET_HARD_REGNO_NREGS. */
2061 static unsigned int
2063 {
2064 /* ??? Logically we should only need to provide a value when
2065 HARD_REGNO_MODE_OK says that the combination is valid,
2066 but at the moment we need to handle all modes. Just ignore
2067 any runtime parts for registers that can't store them. */
2070 {
2074 {
2082 }
2097 }
2099 }
2101 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2103 static bool
2105 {
2114 /* This must have the same size as _Unwind_Word. */
2130 /* These registers are abstract; their modes don't matter. */
2135 /* The purpose of comparing with ptr_mode is to support the
2136 global register variable associated with the stack pointer
2137 register via the syntax of asm ("wsp") in ILP32. */
2144 {
2151 }
2153 {
2156 else
2158 }
2161 }
2163 /* Return true if a function with type FNTYPE returns its value in
2164 SVE vector or predicate registers. */
2166 static bool
2168 {
2171 pure_scalable_type_info pst_info;
2173 {
2185 }
2187 }
2189 /* Return true if a function with type FNTYPE takes arguments in
2190 SVE vector or predicate registers. */
2192 static bool
2194 {
2195 CUMULATIVE_ARGS args_so_far_v;
2203 {
2210 pure_scalable_type_info pst_info;
2212 {
2217 }
2220 }
2222 }
2224 /* Implement TARGET_FNTYPE_ABI. */
2228 {
2237 }
2239 /* Return the state of PSTATE.SM on entry to functions of type FNTYPE. */
2241 static aarch64_isa_mode
2243 {
2252 }
2254 /* Return state flags that describe whether and how functions of type
2255 FNTYPE share state STATE_NAME with their callers. */
2257 static unsigned int
2259 {
2261 state_name);
2262 }
2264 /* Return the state of PSTATE.ZA on entry to functions of type FNTYPE. */
2266 static aarch64_isa_mode
2268 {
2274 }
2276 /* Return the ISA mode on entry to functions of type FNTYPE. */
2278 static aarch64_isa_mode
2280 {
2283 }
2285 /* Return true if FNDECL uses streaming mode internally, as an
2286 implementation choice. */
2288 static bool
2290 {
2293 }
2295 /* Return the state of PSTATE.SM when compiling the body of
2296 function FNDECL. This might be different from the state of
2297 PSTATE.SM on entry. */
2299 static aarch64_isa_mode
2301 {
2306 }
2308 /* Return true if function FNDECL has state STATE_NAME, either by creating
2309 new state itself or by sharing state with callers. */
2311 static bool
2313 {
2317 }
2319 /* Return the state of PSTATE.ZA when compiling the body of function FNDECL.
2320 This might be different from the state of PSTATE.ZA on entry. */
2322 static aarch64_isa_mode
2324 {
2330 }
2332 /* Return the ISA mode that should be used to compile the body of
2333 function FNDECL. */
2335 static aarch64_isa_mode
2337 {
2340 }
2342 /* Return the state of PSTATE.SM on entry to the current function.
2343 This might be different from the state of PSTATE.SM in the function
2344 body. */
2346 static aarch64_isa_mode
2348 {
2350 }
2352 /* Return the state of PSTATE.ZA on entry to the current function.
2353 This might be different from the state of PSTATE.ZA in the function
2354 body. */
2356 static aarch64_isa_mode
2358 {
2360 }
2362 /* Return state flags that describe whether and how the current function shares
2363 state STATE_NAME with callers. */
2365 static unsigned int
2367 {
2369 }
2371 /* Return true if the current function creates new state of type STATE_NAME
2372 (as opposed to sharing the state with its callers or ignoring the state
2373 altogether). */
2375 static bool
2377 {
2379 }
2381 /* Return true if PSTATE.SM is 1 in the body of the current function,
2382 but is not guaranteed to be 1 on entry. */
2384 static bool
2386 {
2389 }
2391 /* Return true if the current function has state STATE_NAME, either by
2392 creating new state itself or by sharing state with callers. */
2394 static bool
2396 {
2398 }
2400 /* Return true if a call from the current function to a function with
2401 ISA mode CALLEE_MODE would involve a change to PSTATE.SM around
2402 the BL instruction. */
2404 static bool
2406 {
2408 }
2410 /* Implement TARGET_COMPATIBLE_VECTOR_TYPES_P. */
2412 static bool
2414 {
2417 }
2419 /* Return true if we should emit CFI for register REGNO. */
2421 static bool
2423 {
2426 }
2428 /* Return the mode we should use to save and restore register REGNO. */
2430 static machine_mode
2432 {
2438 {
2440 /* Only the low 64 bits are saved by the base PCS. */
2444 /* The vector PCS saves the low 128 bits (which is the full
2445 register on non-SVE targets). */
2449 /* Use vectors of DImode for registers that need frame
2450 information, so that the first 64 bytes of the save slot
2451 are always the equivalent of what storing D<n> would give. */
2455 /* Use vectors of bytes otherwise, so that the layout is
2456 endian-agnostic, and so that we can use LDR and STR for
2457 big-endian targets. */
2463 }
2466 /* Save the full predicate register. */
2470 }
2472 /* Given the ISA mode on entry to a callee and the ABI of the callee,
2473 return the CONST_INT that should be placed in an UNSPEC_CALLEE_ABI rtx. */
2475 rtx
2477 {
2480 DImode);
2481 }
2483 /* COOKIE is a CONST_INT from an UNSPEC_CALLEE_ABI rtx. Return the
2484 callee's ABI. */
2488 {
2490 }
2492 /* COOKIE is a CONST_INT from an UNSPEC_CALLEE_ABI rtx. Return the
2493 required ISA mode on entry to the callee, which is also the ISA
2494 mode on return from the callee. */
2496 static aarch64_isa_mode
2498 {
2500 }
2502 /* INSN is a call instruction. Return the CONST_INT stored in its
2503 UNSPEC_CALLEE_ABI rtx. */
2505 static rtx
2507 {
2514 }
2516 /* Implement TARGET_INSN_CALLEE_ABI. */
2520 {
2522 }
2524 /* INSN is a call instruction. Return the required ISA mode on entry to
2525 the callee, which is also the ISA mode on return from the callee. */
2527 static aarch64_isa_mode
2529 {
2531 }
2533 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
2534 the lower 64 bits of a 128-bit register. Tell the compiler the callee
2535 clobbers the top 64 bits when restoring the bottom 64 bits. */
2537 static bool
2540 machine_mode mode)
2541 {
2543 {
2551 }
2553 }
2555 /* Implement REGMODE_NATURAL_SIZE. */
2556 poly_uint64
2558 {
2559 /* The natural size for SVE data modes is one SVE data vector,
2560 and similarly for predicates. We can't independently modify
2561 anything smaller than that. */
2562 /* ??? For now, only do this for variable-width SVE registers.
2563 Doing it for constant-sized registers breaks lower-subreg.cc. */
2564 /* ??? And once that's fixed, we should probably have similar
2565 code for Advanced SIMD. */
2567 {
2573 }
2575 }
2577 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
2578 machine_mode
2580 machine_mode mode)
2581 {
2582 /* The predicate mode determines which bits are significant and
2583 which are "don't care". Decreasing the number of lanes would
2584 lose data while increasing the number of lanes would make bits
2585 unnecessarily significant. */
2593 }
2595 /* Return true if I's bits are consecutive ones from the MSB. */
2596 bool
2598 {
2600 }
2602 /* Implement TARGET_CONSTANT_ALIGNMENT. Make strings word-aligned so
2603 that strcpy from constants will be faster. */
2605 static HOST_WIDE_INT
2607 {
2611 }
2613 /* Return true if calls to DECL should be treated as
2614 long-calls (ie called via a register). */
2615 static bool
2617 {
2619 }
2621 /* Return true if calls to symbol-ref SYM should be treated as
2622 long-calls (ie called via a register). */
2623 bool
2625 {
2627 }
2629 /* Return true if calls to symbol-ref SYM should not go through
2630 plt stubs. */
2632 bool
2634 {
2638 && decl
2639 && (!flag_plt
2645 }
2647 /* Emit an insn that's a simple single-set. Both the operands must be
2648 known to be valid. */
2651 {
2653 }
2655 /* X and Y are two things to compare using CODE. Emit the compare insn and
2656 return the rtx for register 0 in the proper mode. */
2657 rtx
2659 {
2661 machine_mode cc_mode;
2662 rtx cc_reg;
2665 {
2680 }
2681 else
2682 {
2686 }
2688 }
2690 /* Similarly, but maybe zero-extend Y if Y_MODE < SImode. */
2692 static rtx
2694 machine_mode y_mode)
2695 {
2697 {
2699 {
2702 }
2703 else
2704 {
2706 machine_mode cc_mode;
2714 }
2715 }
2721 }
2723 /* Generate conditional branch to LABEL, comparing X to 0 using CODE.
2724 Return the jump instruction. */
2726 static rtx
2729 {
2731 {
2732 /* Emit an explicit compare instruction, so that we can correctly
2733 track the condition codes. */
2736 }
2737 else
2743 }
2745 /* Return an rtx that branches to LABEL based on the value of bit BITNUM of X.
2746 If CODE is NE, it branches to LABEL when the bit is set; if CODE is EQ,
2747 it branches to LABEL when the bit is clear. */
2749 static rtx
2752 {
2755 {
2761 }
2764 }
2766 /* Consider the operation:
2768 OPERANDS[0] = CODE (OPERANDS[1], OPERANDS[2]) + OPERANDS[3]
2770 where:
2772 - CODE is [SU]MAX or [SU]MIN
2773 - OPERANDS[2] and OPERANDS[3] are constant integers
2774 - OPERANDS[3] is a positive or negative shifted 12-bit immediate
2775 - all operands have mode MODE
2777 Decide whether it is possible to implement the operation using:
2779 SUBS <tmp>, OPERANDS[1], -OPERANDS[3]
2780 or
2781 ADDS <tmp>, OPERANDS[1], OPERANDS[3]
2783 followed by:
2785 <insn> OPERANDS[0], <tmp>, [wx]zr, <cond>
2787 where <insn> is one of CSEL, CSINV or CSINC. Return true if so.
2788 If GENERATE_P is true, also update OPERANDS as follows:
2790 OPERANDS[4] = -OPERANDS[3]
2791 OPERANDS[5] = the rtl condition representing <cond>
2792 OPERANDS[6] = <tmp>
2793 OPERANDS[7] = 0 for CSEL, -1 for CSINV or 1 for CSINC. */
2794 bool
2796 {
2803 /* max (x, y) - z == (x >= y + 1 ? x : y) - z
2804 == (x >= y ? x : y) - z
2805 == (x > y ? x : y) - z
2806 == (x > y - 1 ? x : y) - z
2808 min (x, y) - z == (x <= y - 1 ? x : y) - z
2809 == (x <= y ? x : y) - z
2810 == (x < y ? x : y) - z
2811 == (x < y + 1 ? x : y) - z
2813 Check whether z is in { y - 1, y, y + 1 } and pick the form(s) for
2814 which x is compared with z. Set DIFF to y - z. Thus the supported
2815 combinations are as follows, with DIFF being the value after the ":":
2817 max (x, y) - z == x >= y + 1 ? x - (y + 1) : -1 [z == y + 1]
2818 == x >= y ? x - y : 0 [z == y]
2819 == x > y ? x - y : 0 [z == y]
2820 == x > y - 1 ? x - (y - 1) : 1 [z == y - 1]
2822 min (x, y) - z == x <= y - 1 ? x - (y - 1) : 1 [z == y - 1]
2823 == x <= y ? x - y : 0 [z == y]
2824 == x < y ? x - y : 0 [z == y]
2825 == x < y + 1 ? x - (y + 1) : -1 [z == y + 1]. */
2838 rtx_code cmp;
2840 {
2855 }
2862 else
2867 }
2870 /* Build the SYMBOL_REF for __tls_get_addr. */
2874 rtx
2876 {
2880 }
2882 /* Return the TLS model to use for ADDR. */
2884 static enum tls_model
2886 {
2888 poly_int64 offset;
2894 }
2896 /* We'll allow lo_sum's in addresses in our legitimate addresses
2897 so that combine would take care of combining addresses where
2898 necessary, but for generation purposes, we'll generate the address
2899 as :
2900 RTL Absolute
2901 tmp = hi (symbol_ref); adrp x1, foo
2902 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
2903 nop
2905 PIC TLS
2906 adrp x1, :got:foo adrp tmp, :tlsgd:foo
2907 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
2908 bl __tls_get_addr
2909 nop
2911 Load TLS symbol, depending on TLS mechanism and TLS access model.
2913 Global Dynamic - Traditional TLS:
2914 adrp tmp, :tlsgd:imm
2915 add dest, tmp, #:tlsgd_lo12:imm
2916 bl __tls_get_addr
2918 Global Dynamic - TLS Descriptors:
2919 adrp dest, :tlsdesc:imm
2920 ldr tmp, [dest, #:tlsdesc_lo12:imm]
2921 add dest, dest, #:tlsdesc_lo12:imm
2922 blr tmp
2923 mrs tp, tpidr_el0
2924 add dest, dest, tp
2926 Initial Exec:
2927 mrs tp, tpidr_el0
2928 adrp tmp, :gottprel:imm
2929 ldr dest, [tmp, #:gottprel_lo12:imm]
2930 add dest, dest, tp
2932 Local Exec:
2933 mrs tp, tpidr_el0
2934 add t0, tp, #:tprel_hi12:imm, lsl #12
2935 add t0, t0, #:tprel_lo12_nc:imm
2936 */
2938 static void
2941 {
2942 #if TARGET_PECOFF
2945 {
2948 }
2949 #endif
2952 {
2954 {
2955 /* In ILP32, the mode of dest can be either SImode or DImode. */
2967 }
2974 {
2977 rtx insn;
2978 rtx mem;
2980 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
2981 here before rtl expand. Tree IVOPT will generate rtl pattern to
2982 decide rtx costs, in which case pic_offset_table_rtx is not
2983 initialized. For that case no need to generate the first adrp
2984 instruction as the final cost for global variable access is
2985 one instruction. */
2987 {
2988 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
2989 using the page base as GOT base, the first page may be wasted,
2990 in the worst scenario, there is only 28K space for GOT).
2992 The generate instruction sequence for accessing global variable
2993 is:
2995 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
2997 Only one instruction needed. But we must initialize
2998 pic_offset_table_rtx properly. We generate initialize insn for
2999 every global access, and allow CSE to remove all redundant.
3001 The final instruction sequences will look like the following
3002 for multiply global variables access.
3004 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
3006 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
3007 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
3008 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
3009 ... */
3018 }
3021 {
3024 else
3028 }
3029 else
3030 {
3035 }
3037 /* The operand is expected to be MEM. Whenever the related insn
3038 pattern changed, above code which calculate mem should be
3039 updated. */
3045 }
3052 {
3054 /* The return type of __tls_get_addr is the C pointer type
3055 so use ptr_mode. */
3065 else
3072 /* Convert back to the mode of the dest adding a zero_extend
3073 from SImode (ptr_mode) to DImode (Pmode). */
3077 }
3080 {
3083 rtx tp;
3087 /* In ILP32, the got entry is always of SImode size. Unlike
3088 small GOT, the dest is fixed at reg 0. */
3091 else
3102 }
3105 {
3106 /* In ILP32, the mode of dest can be either SImode or DImode,
3107 while the got entry is always of SImode size. The mode of
3108 dest depends on how dest is used: if dest is assigned to a
3109 pointer (e.g. in the memory), it has SImode; it may have
3110 DImode if dest is dereferenced to access the memeory.
3111 This is why we have to handle three different tlsie_small
3112 patterns here (two patterns for ILP32). */
3118 {
3121 else
3122 {
3125 }
3126 }
3127 else
3128 {
3131 }
3137 }
3143 {
3151 {
3174 }
3179 }
3182 {
3183 rtx insn;
3188 else
3189 {
3192 }
3196 }
3199 {
3204 {
3207 else
3208 {
3211 }
3212 }
3213 else
3214 {
3217 }
3222 }
3226 }
3227 }
3229 /* Emit a move from SRC to DEST. Assume that the move expanders can
3230 handle all moves if !can_create_pseudo_p (). The distinction is
3231 important because, unlike emit_move_insn, the move expanders know
3232 how to force Pmode objects into the constant pool even when the
3233 constant pool address is not itself legitimate. */
3234 static rtx
3236 {
3240 }
3242 /* Apply UNOPTAB to OP and store the result in DEST. */
3244 static void
3246 {
3250 }
3252 /* Apply BINOPTAB to OP0 and OP1 and store the result in DEST. */
3254 static void
3256 {
3258 OPTAB_DIRECT);
3261 }
3263 /* Split a move from SRC to DST into two moves of mode SINGLE_MODE. */
3265 void
3267 {
3277 /* At most one pairing may overlap. */
3279 {
3282 }
3283 else
3284 {
3287 }
3288 }
3290 /* Split a 128-bit move operation into two 64-bit move operations,
3291 taking care to handle partial overlap of register to register
3292 copies. Special cases are needed when moving between GP regs and
3293 FP regs. SRC can be a register, constant or memory; DST a register
3294 or memory. If either operand is memory it must not have any side
3295 effects. */
3296 void
3298 {
3306 {
3310 /* Handle FP <-> GP regs. */
3312 {
3319 }
3321 {
3328 }
3329 }
3332 }
3334 /* Return true if we should split a move from 128-bit value SRC
3335 to 128-bit register DEST. */
3337 bool
3339 {
3342 /* All moves to GPRs need to be split. */
3344 }
3346 /* Split a complex SIMD move. */
3348 void
3350 {
3357 {
3360 }
3361 }
3363 /* Return a register that contains SVE value X reinterpreted as SVE mode MODE.
3364 The semantics of those of svreinterpret rather than those of subregs;
3365 see the comment at the head of aarch64-sve.md for details about the
3366 difference. */
3368 rtx
3370 {
3374 /* can_change_mode_class must only return true if subregs and svreinterprets
3375 have the same semantics. */
3383 }
3385 bool
3388 {
3392 }
3394 /* Return TARGET if it is nonnull and a register of mode MODE.
3395 Otherwise, return a fresh register of mode MODE if we can,
3396 or TARGET reinterpreted as MODE if we can't. */
3398 static rtx
3400 {
3404 {
3407 }
3409 }
3411 /* Return a register that contains the constant in BUILDER, given that
3412 the constant is a legitimate move operand. Use TARGET as the register
3413 if it is nonnull and convenient. */
3415 static rtx
3417 {
3422 }
3424 static rtx
3426 {
3429 else
3430 {
3434 }
3435 }
3437 /* Return true if predicate value X is a constant in which every element
3438 is a CONST_INT. When returning true, describe X in BUILDER as a VNx16BI
3439 value, i.e. as a predicate in which all bits are significant. */
3441 static bool
3443 {
3455 {
3463 }
3466 }
3468 /* BUILDER contains a predicate constant of mode VNx16BI. Return the
3469 widest predicate element size it can have (that is, the largest size
3470 for which each element would still be 0 or 1). */
3472 unsigned int
3474 {
3475 /* Start with the most optimistic assumption: that we only need
3476 one bit per pattern. This is what we will use if only the first
3477 bit in each pattern is ever set. */
3481 /* Look for set bits. */
3485 {
3489 }
3491 }
3493 /* If VNx16BImode rtx X is a canonical PTRUE for a predicate mode,
3494 return that predicate mode, otherwise return opt_machine_mode (). */
3496 opt_machine_mode
3498 {
3512 }
3514 /* BUILDER is a predicate constant of mode VNx16BI. Consider the value
3515 that the constant would have with predicate element size ELT_SIZE
3516 (ignoring the upper bits in each element) and return:
3518 * -1 if all bits are set
3519 * N if the predicate has N leading set bits followed by all clear bits
3520 * 0 if the predicate does not have any of these forms. */
3522 int
3525 {
3526 /* If nelts_per_pattern is 3, we have set bits followed by clear bits
3527 followed by set bits. */
3531 /* Skip over leading set bits. */
3539 /* Check for the all-true case. */
3543 /* If nelts_per_pattern is 1, then either VL is zero, or we have a
3544 repeating pattern of set bits followed by clear bits. */
3548 /* We have a "foreground" value and a duplicated "background" value.
3549 If the background might repeat and the last set bit belongs to it,
3550 we might have set bits followed by clear bits followed by set bits. */
3554 /* Make sure that the rest are all clear. */
3560 }
3562 /* See if there is an svpattern that encodes an SVE predicate of mode
3563 PRED_MODE in which the first VL bits are set and the rest are clear.
3564 Return the pattern if so, otherwise return AARCH64_NUM_SVPATTERNS.
3565 A VL of -1 indicates an all-true vector. */
3567 aarch64_svpattern
3569 {
3584 {
3587 /* These would only trigger for non-power-of-2 lengths. */
3594 }
3596 }
3598 /* Return a VNx16BImode constant in which every sequence of ELT_SIZE
3599 bits has the lowest bit set and the upper bits clear. This is the
3600 VNx16BImode equivalent of a PTRUE for controlling elements of
3601 ELT_SIZE bytes. However, because the constant is VNx16BImode,
3602 all bits are significant, even the upper zeros. */
3604 rtx
3606 {
3612 }
3614 /* Return an all-true predicate register of mode MODE. */
3616 rtx
3618 {
3622 }
3624 /* Return an all-false predicate register of mode MODE. */
3626 rtx
3628 {
3632 }
3634 /* PRED1[0] is a PTEST predicate and PRED1[1] is an aarch64_sve_ptrue_flag
3635 for it. PRED2[0] is the predicate for the instruction whose result
3636 is tested by the PTEST and PRED2[1] is again an aarch64_sve_ptrue_flag
3637 for it. Return true if we can prove that the two predicates are
3638 equivalent for PTEST purposes; that is, if we can replace PRED2[0]
3639 with PRED1[0] without changing behavior. */
3641 bool
3643 {
3655 }
3657 /* Emit a comparison CMP between OP0 and OP1, both of which have mode
3658 DATA_MODE, and return the result in a predicate of mode PRED_MODE.
3659 Use TARGET as the target register if nonnull and convenient. */
3661 static rtx
3664 {
3674 }
3676 /* Use a comparison to convert integer vector SRC into MODE, which is
3677 the corresponding SVE predicate mode. Use TARGET for the result
3678 if it's nonnull and convenient. */
3680 rtx
3682 {
3686 }
3688 /* Return the assembly token for svprfop value PRFOP. */
3692 {
3694 {
3695 #define CASE(UPPER, LOWER, VALUE) case AARCH64_SV_##UPPER: return #LOWER;
3697 #undef CASE
3700 }
3702 }
3704 /* Return the assembly string for an SVE prefetch operation with
3705 mnemonic MNEMONIC, given that PRFOP_RTX is the prefetch operation
3706 and that SUFFIX is the format for the remaining operands. */
3711 {
3718 }
3720 /* Check whether we can calculate the number of elements in PATTERN
3721 at compile time, given that there are NELTS_PER_VQ elements per
3722 128-bit block. Return the value if so, otherwise return -1. */
3724 HOST_WIDE_INT
3726 {
3733 {
3734 /* There are two vector granules per quadword. */
3737 {
3743 }
3744 }
3745 else
3748 /* There are two vector granules per quadword. */
3753 /* Requesting more elements than are available results in a PFALSE. */
3758 }
3760 /* Return true if a single CNT[BHWD] instruction can multiply FACTOR
3761 by the number of 128-bit quadwords in an SVE vector. */
3763 static bool
3765 {
3766 /* The coefficient must be [1, 16] * {2, 4, 8, 16}. */
3770 }
3772 /* Return true if we can move VALUE into a register using a single
3773 CNT[BHWD] instruction. */
3775 static bool
3777 {
3780 }
3782 /* Likewise for rtx X. */
3784 bool
3786 {
3787 poly_int64 value;
3789 }
3791 /* Return the asm string for an instruction with a CNT-like vector size
3792 operand (a vector pattern followed by a multiplier in the range [1, 16]).
3793 PREFIX is the mnemonic without the size suffix and OPERANDS is the
3794 first part of the operands template (the part that comes before the
3795 vector size itself). PATTERN is the pattern to use. FACTOR is the
3796 number of quadwords. NELTS_PER_VQ, if nonzero, is the number of elements
3797 in each quadword. If it is zero, we can use any element size. */
3801 aarch64_svpattern pattern,
3804 {
3808 /* There is some overlap in the ranges of the four CNT instructions.
3809 Here we always use the smallest possible element size, so that the
3810 multiplier is 1 whereever possible. */
3824 else
3827 factor);
3830 }
3832 /* Return the asm string for an instruction with a CNT-like vector size
3833 operand (a vector pattern followed by a multiplier in the range [1, 16]).
3834 PREFIX is the mnemonic without the size suffix and OPERANDS is the
3835 first part of the operands template (the part that comes before the
3836 vector size itself). X is the value of the vector size operand,
3837 as a polynomial integer rtx; we need to convert this into an "all"
3838 pattern with a multiplier. */
3842 rtx x)
3843 {
3848 }
3850 /* Return the asm string for an instruction with a CNT-like vector size
3851 operand (a vector pattern followed by a multiplier in the range [1, 16]).
3852 PREFIX is the mnemonic without the size suffix and OPERANDS is the
3853 first part of the operands template (the part that comes before the
3854 vector size itself). CNT_PAT[0..2] are the operands of the
3855 UNSPEC_SVE_CNT_PAT; see aarch64_sve_cnt_pat for details. */
3860 {
3866 }
3868 /* Return true if we can add X using a single SVE INC or DEC instruction. */
3870 bool
3872 {
3873 poly_int64 value;
3877 }
3879 /* Return the asm string for adding SVE INC/DEC immediate OFFSET to
3880 operand 0. */
3884 {
3890 else
3893 }
3895 /* Return true if a single RDVL instruction can multiply FACTOR by the
3896 number of 128-bit quadwords in an SVE vector. This is also the
3897 range of ADDVL. */
3899 static bool
3901 {
3904 }
3906 /* Return true if ADDPL can be used to add FACTOR multiplied by the number
3907 of quadwords in an SVE vector. */
3909 static bool
3911 {
3914 }
3916 /* Return true if we can move VALUE into a register using a single
3917 RDVL instruction. */
3919 static bool
3921 {
3924 }
3926 /* Likewise for rtx X. */
3928 bool
3930 {
3931 poly_int64 value;
3933 }
3935 /* Return the asm string for moving RDVL immediate OFFSET into register
3936 operand 0. */
3940 {
3948 }
3950 /* Return true if we can add VALUE to a register using a single ADDVL
3951 or ADDPL instruction. */
3953 static bool
3955 {
3961 }
3963 /* Likewise for rtx X. */
3965 bool
3967 {
3968 poly_int64 value;
3971 }
3973 /* Return the asm string for adding ADDVL or ADDPL immediate OFFSET
3974 to operand 1 and storing the result in operand 0. */
3978 {
3986 else
3989 }
3991 /* Return true if X is a valid immediate for an SVE vector INC or DEC
3992 instruction. If it is, store the number of elements in each vector
3993 quadword in *NELTS_PER_VQ_OUT (if nonnull) and store the multiplication
3994 factor in *FACTOR_OUT (if nonnull). */
3996 bool
3999 {
4000 rtx elt;
4001 poly_int64 value;
4009 /* There's no vector INCB. */
4016 /* The coefficient must be [1, 16] * NELTS_PER_VQ. */
4026 }
4028 /* Return true if X is a valid immediate for an SVE vector INC or DEC
4029 instruction. */
4031 bool
4033 {
4035 }
4037 /* Return the asm template for an SVE vector INC or DEC instruction.
4038 OPERANDS gives the operands before the vector count and X is the
4039 value of the vector count operand itself. */
4043 {
4051 else
4054 }
4056 /* Return a constant that represents FACTOR multiplied by the
4057 number of 128-bit quadwords in an SME vector. ISA_MODE is the
4058 ISA mode in which the calculation is being performed. */
4060 rtx
4062 aarch64_isa_mode isa_mode)
4063 {
4066 /* We're in streaming mode, so we can use normal poly-int values. */
4072 }
4074 /* Return true if X is a constant that represents some number X
4075 multiplied by the number of quadwords in an SME vector. Store this X
4076 in *FACTOR if so. */
4078 static bool
4080 {
4096 }
4098 /* Return true if X is a constant that represents some number Y
4099 multiplied by the number of quadwords in an SME vector, and if
4100 that Y is in the range of RDSVL. */
4102 bool
4104 {
4105 HOST_WIDE_INT factor;
4108 }
4110 /* Return the asm string for an RDSVL instruction that calculates X,
4111 which is a constant that satisfies aarch64_rdsvl_immediate_p. */
4115 {
4122 }
4124 /* Return true if X is a constant that can be added using ADDSVL or ADDSPL. */
4126 bool
4128 {
4129 HOST_WIDE_INT factor;
4133 }
4135 /* X is a constant that satisfies aarch64_addsvl_addspl_immediate_p.
4136 Return the asm string for the associated instruction. */
4140 {
4142 HOST_WIDE_INT factor;
4151 else
4154 }
4156 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
4159 {
4165 };
4169 /* Return true if 64-bit VAL is a valid bitmask immediate. */
4170 static bool
4172 {
4176 /* Check for a single sequence of one bits and return quickly if so.
4177 The special cases of all ones and all zeroes returns false. */
4183 /* Invert if the immediate doesn't start with a zero bit - this means we
4184 only need to search for sequences of one bits. */
4188 /* Find the first set bit and set tmp to val with the first sequence of one
4189 bits removed. Return success if there is a single sequence of ones. */
4196 /* Find the next set bit and compute the difference in bit position. */
4201 /* Check the bit position difference is a power of 2, and that the first
4202 sequence of one bits fits within 'bits' bits. */
4206 /* Check the sequence of one bits is repeated 64/bits times. */
4208 }
4211 /* Return true if VAL is a valid bitmask immediate for MODE. */
4212 bool
4214 {
4221 /* Replicate small immediates to fit 64 bits. */
4227 }
4230 /* Return true if the immediate VAL can be a bitfield immediate
4231 by changing the given MASK bits in VAL to zeroes, ones or bits
4232 from the other half of VAL. Return the new immediate in VAL2. */
4237 {
4252 }
4255 /* Return true if VAL is a valid MOVZ immediate. */
4258 {
4260 }
4263 /* Return true if immediate VAL can be created by a 64-bit MOVI/MOVN/MOVZ. */
4264 bool
4266 {
4269 }
4272 /* Return true if VAL is an immediate that can be created by a single
4273 MOV instruction. */
4274 bool
4276 {
4290 }
4293 static int
4295 machine_mode mode)
4296 {
4307 {
4311 }
4314 {
4316 {
4321 else
4324 }
4326 }
4328 /* Remaining cases are all for DImode. */
4336 /* Try a bitmask immediate and a movk to generate the immediate
4337 in 2 instructions. */
4340 {
4342 {
4349 }
4352 {
4354 {
4358 }
4360 }
4362 /* Try 2 bitmask immediates which are xor'd together. */
4364 {
4370 }
4373 {
4375 {
4378 }
4380 }
4381 }
4383 /* Try a bitmask plus 2 movk to generate the immediate in 3 instructions. */
4385 {
4389 {
4391 {
4397 }
4399 }
4401 /* Try shifting and inserting the bottom 32-bits into the top bits. */
4407 {
4409 {
4414 }
4416 }
4418 {
4420 {
4425 dest));
4426 }
4428 }
4429 }
4431 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
4432 are emitted by the initial mov. If one_match > zero_match, skip set bits,
4433 otherwise skip zero bits. */
4445 {
4451 num_insns ++;
4452 }
4455 }
4457 /* Return whether imm is a 128-bit immediate which is simple enough to
4458 expand inline. */
4459 bool
4461 {
4472 }
4475 /* Return true if val can be encoded as a 12-bit unsigned immediate with
4476 a left shift of 0 or 12 bits. */
4477 bool
4479 {
4481 }
4483 /* Returns the nearest value to VAL that will fit as a 12-bit unsigned immediate
4484 that can be created with a left shift of 0 or 12. */
4485 static HOST_WIDE_INT
4487 {
4488 /* Check to see if the value fits in 24 bits, as that is the maximum we can
4489 handle correctly. */
4496 }
4499 /* Test whether:
4501 X = (X & AND_VAL) | IOR_VAL;
4503 can be implemented using:
4505 MOVK X, #(IOR_VAL >> shift), LSL #shift
4507 Return the shift if so, otherwise return -1. */
4508 int
4511 {
4515 {
4519 }
4521 }
4523 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
4524 Assumed precondition: VAL_IN Is not zero. */
4526 unsigned HOST_WIDE_INT
4528 {
4535 }
4537 /* Create constant where bits outside of lowest bit set to highest bit set
4538 are set to 1. */
4540 unsigned HOST_WIDE_INT
4542 {
4544 }
4546 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
4548 bool
4550 {
4551 scalar_int_mode int_mode;
4564 }
4566 /* Return the number of temporary registers that aarch64_add_offset_1
4567 would need to add OFFSET to a register. */
4569 static unsigned int
4571 {
4573 }
4575 /* A subroutine of aarch64_add_offset. Set DEST to SRC + OFFSET for
4576 a non-polynomial OFFSET. MODE is the mode of the addition.
4577 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
4578 be set and CFA adjustments added to the generated instructions.
4580 TEMP1, if nonnull, is a register of mode MODE that can be used as a
4581 temporary if register allocation is already complete. This temporary
4582 register may overlap DEST but must not overlap SRC. If TEMP1 is known
4583 to hold abs (OFFSET), EMIT_MOVE_IMM can be set to false to avoid emitting
4584 the immediate again.
4586 Since this function may be used to adjust the stack pointer, we must
4587 ensure that it cannot cause transient stack deallocation (for example
4588 by first incrementing SP and then decrementing when adjusting by a
4589 large immediate). */
4591 static void
4595 {
4603 {
4605 {
4608 }
4610 }
4612 /* Single instruction adjustment. */
4614 {
4618 }
4620 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits
4621 and either:
4623 a) the offset cannot be loaded by a 16-bit move or
4624 b) there is no spare register into which we can move it. */
4628 {
4637 }
4639 /* Emit a move immediate if required and an addition/subtraction. */
4641 {
4645 }
4650 {
4654 }
4655 }
4657 /* Return the number of temporary registers that aarch64_add_offset
4658 would need to move OFFSET into a register or add OFFSET to a register;
4659 ADD_P is true if we want the latter rather than the former. */
4661 static unsigned int
4663 {
4664 /* This follows the same structure as aarch64_add_offset. */
4673 /* Need one register for the ADDVL/ADDPL result. */
4676 {
4679 /* Need one register for the CNT or RDVL result and one for the
4680 multiplication factor. If necessary, the second temporary
4681 can be reused for the constant part of the offset. */
4683 /* Need one register for the CNT or RDVL result (which might then
4684 be shifted). */
4686 }
4688 }
4690 /* If X can be represented as a poly_int64, return the number
4691 of temporaries that are required to add it to a register.
4692 Return -1 otherwise. */
4694 int
4696 {
4697 poly_int64 offset;
4701 }
4703 /* Set DEST to SRC + OFFSET. MODE is the mode of the addition.
4704 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
4705 be set and CFA adjustments added to the generated instructions.
4707 TEMP1, if nonnull, is a register of mode MODE that can be used as a
4708 temporary if register allocation is already complete. This temporary
4709 register may overlap DEST if !FRAME_RELATED_P but must not overlap SRC.
4710 If TEMP1 is known to hold abs (OFFSET), EMIT_MOVE_IMM can be set to
4711 false to avoid emitting the immediate again.
4713 TEMP2, if nonnull, is a second temporary register that doesn't
4714 overlap either DEST or REG.
4716 FORCE_ISA_MODE is AARCH64_ISA_MODE_SM_ON if any variable component of OFFSET
4717 is measured relative to the SME vector length instead of the current
4718 prevailing vector length. It is 0 otherwise.
4720 Since this function may be used to adjust the stack pointer, we must
4721 ensure that it cannot cause transient stack deallocation (for example
4722 by first incrementing SP and then decrementing when adjusting by a
4723 large immediate). */
4725 static void
4728 aarch64_isa_mode force_isa_mode,
4730 {
4734 || !frame_related_p
4738 /* Try using ADDVL or ADDPL to add the whole value. */
4740 {
4742 rtx offset_rtx;
4745 else
4752 offset)));
4754 }
4756 /* Coefficient 1 is multiplied by the number of 128-bit blocks in an
4757 SVE vector register, over and above the minimum size of 128 bits.
4758 This is equivalent to half the value returned by CNTD with a
4759 vector shape of ALL. */
4763 /* Try using ADDVL or ADDPL to add the VG-based part. */
4767 {
4768 rtx offset_rtx;
4771 else
4774 {
4780 poly_offset)));
4782 }
4783 else
4784 {
4789 }
4790 }
4791 /* Otherwise use a CNT-based sequence. */
4793 {
4794 /* Calculate CNTB * FACTOR / 16 as CNTB * REL_FACTOR * 2**SHIFT,
4795 with negative shifts indicating a shift right. */
4801 /* Set CODE, VAL and SHIFT so that [+-] VAL * 2**SHIFT is
4802 equal to CNTB * FACTOR / 16, with CODE being the [+-].
4804 We can avoid a multiplication if REL_FACTOR is in the range
4805 of RDVL, although there are then various optimizations that
4806 we can try on top. */
4808 rtx val;
4810 {
4812 {
4813 /* Try to use an unshifted RDSVL, otherwise fall back on
4814 a shifted RDSVL #1. */
4817 else
4820 }
4821 /* Try to use an unshifted CNT[BHWD] or RDVL. */
4824 {
4827 }
4828 /* Try to subtract an unshifted CNT[BHWD]. */
4830 {
4834 }
4835 /* If subtraction is free, prefer to load a positive constant.
4836 In the best case this will fit a shifted CNTB. */
4838 {
4841 }
4842 /* Otherwise use a shifted RDVL or CNT[BHWD]. */
4843 else
4845 }
4846 else
4847 {
4848 /* If we can calculate CNTB << SHIFT directly, prefer to do that,
4849 since it should increase the chances of being able to use
4850 a shift and add sequence for the multiplication.
4851 If CNTB << SHIFT is out of range, stick with the current
4852 shift factor. */
4855 {
4858 }
4861 {
4864 }
4865 else
4870 /* Prefer to multiply by a positive factor and subtract rather
4871 than multiply by a negative factor and add, since positive
4872 values are usually easier to move. */
4874 {
4877 }
4880 {
4883 }
4884 else
4885 {
4889 }
4890 }
4892 /* Multiply by 2 ** SHIFT. */
4894 {
4897 }
4899 {
4902 }
4904 /* Add the result to SRC or subtract the result from SRC. */
4906 {
4909 }
4911 {
4914 }
4917 {
4920 {
4924 poly_offset)));
4925 }
4929 }
4930 else
4931 {
4935 }
4938 }
4942 }
4944 /* Like aarch64_add_offset, but the offset is given as an rtx rather
4945 than a poly_int64. */
4947 void
4950 {
4953 }
4955 /* Add DELTA to the stack pointer, marking the instructions frame-related.
4956 TEMP1 is available as a temporary if nonnull. FORCE_ISA_MODE is as
4957 for aarch64_add_offset. EMIT_MOVE_IMM is false if TEMP1 already
4958 contains abs (DELTA). */
4963 {
4966 }
4968 /* Subtract DELTA from the stack pointer, marking the instructions
4969 frame-related if FRAME_RELATED_P. FORCE_ISA_MODE is as for
4970 aarch64_add_offset. TEMP1 is available as a temporary if nonnull. */
4974 aarch64_isa_mode force_isa_mode,
4976 {
4979 emit_move_imm);
4980 }
4982 /* A streaming-compatible function needs to switch temporarily to the known
4983 PSTATE.SM mode described by LOCAL_MODE. The low bit of OLD_SVCR contains
4984 the runtime state of PSTATE.SM in the streaming-compatible code, before
4985 the start of the switch to LOCAL_MODE.
4987 Emit instructions to branch around the mode switch if PSTATE.SM already
4988 matches LOCAL_MODE. Return the label that the branch jumps to. */
4992 {
4998 label);
5002 }
5004 /* Emit code to switch from the PSTATE.SM state in OLD_MODE to the PSTATE.SM
5005 state in NEW_MODE. This is known to involve either an SMSTART SM or
5006 an SMSTOP SM. */
5008 static void
5010 {
5018 else
5020 }
5022 /* As a side-effect, SMSTART SM and SMSTOP SM clobber the contents of all
5023 FP and predicate registers. This class emits code to preserve any
5024 necessary registers around the mode switch.
5026 The class uses four approaches to saving and restoring contents, enumerated
5027 by group_type:
5029 - GPR: save and restore the contents of FP registers using GPRs.
5030 This is used if the FP register contains no more than 64 significant
5031 bits. The registers used are FIRST_GPR onwards.
5033 - MEM_128: save and restore 128-bit SIMD registers using memory.
5035 - MEM_SVE_PRED: save and restore full SVE predicate registers using memory.
5037 - MEM_SVE_DATA: save and restore full SVE vector registers using memory.
5039 The save slots within each memory group are consecutive, with the
5040 MEM_SVE_PRED slots occupying a region below the MEM_SVE_DATA slots.
5042 There will only be two mode switches for each use of SME, so they should
5043 not be particularly performance-sensitive. It's also rare for SIMD, SVE
5044 or predicate registers to be live across mode switches. We therefore
5045 don't preallocate the save slots but instead allocate them locally on
5046 demand. This makes the code emitted by the class self-contained. */
5048 class aarch64_sme_mode_switch_regs
5049 {
5062 /* The number of GPRs needed to save FP registers, starting from
5063 FIRST_GPR. */
5070 /* Information about the save location for one FP, SIMD, SVE data, or
5071 SVE predicate register. */
5073 /* The register to be saved. */
5074 rtx reg;
5076 /* Which group the save location belongs to. */
5077 group_type group;
5079 /* A zero-based index of the register within the group. */
5081 };
5094 /* All save locations, in no particular order. */
5097 /* The number of registers in each group. */
5099 };
5101 /* Record that (reg:MODE REGNO) needs to be preserved around the mode
5102 switch. */
5104 void
5106 {
5114 {
5115 /* Force the mode of SVE saves and restores even for single registers.
5116 This is necessary because big-endian targets only allow LDR Z and
5117 STR Z to be used with byte modes. */
5124 {
5127 else
5129 }
5130 save_location loc;
5133 {
5136 }
5137 else
5138 {
5144 else
5146 }
5149 }
5150 }
5152 /* Record that the arguments to CALL_INSN need to be preserved around
5153 the mode switch. */
5155 void
5157 {
5160 {
5168 }
5169 }
5171 /* Record that the return value from CALL_INSN (if any) needs to be
5172 preserved around the mode switch. */
5174 void
5176 {
5185 {
5190 }
5191 else
5193 }
5195 /* REGNO is a register that is call-preserved under the current function's ABI.
5196 Record that it must be preserved around the mode switch. */
5198 void
5200 {
5203 {
5215 }
5218 }
5220 /* The hard registers in REGS are call-preserved under the current function's
5221 ABI. Record that they must be preserved around the mode switch. */
5223 void
5225 {
5226 bitmap_iterator bi;
5231 else
5233 }
5235 /* Emit code to save registers before the mode switch. */
5237 void
5239 {
5245 }
5247 /* Emit code to restore registers after the mode switch. */
5249 void
5251 {
5257 }
5259 /* The SVE predicate registers are stored below the SVE data registers,
5260 with the predicate save area being padded to a data-register-sized
5261 boundary. Return the size of this padded area as a whole number
5262 of data register slots. */
5264 unsigned int
5266 {
5268 }
5270 /* Return a memory reference of mode MODE to OFFSET bytes from the
5271 stack pointer. */
5273 rtx
5275 poly_int64 offset)
5276 {
5279 }
5281 /* Allocate or deallocate SIZE bytes of stack space: SEQ decides which. */
5283 void
5285 poly_int64 size)
5286 {
5291 }
5293 /* Save or restore the register in LOC, whose slot is OFFSET bytes from
5294 the stack pointer. SEQ chooses between saving and restoring. */
5296 void
5299 poly_int64 offset)
5300 {
5304 else
5306 }
5308 /* Emit instructions to save or restore the GPR group. SEQ chooses between
5309 saving and restoring. */
5311 void
5313 {
5316 {
5321 else
5323 }
5324 }
5326 /* Emit instructions to save or restore the MEM_128 group. SEQ chooses
5327 between saving and restoring. */
5329 void
5331 {
5339 /* Pick a common mode that supports LDR & STR with pre/post-modification
5340 and LDP & STP with pre/post-modification. */
5343 /* An instruction pattern that should be emitted at the end. */
5346 /* A previous MEM_128 location that hasn't been handled yet. */
5349 /* Look for LDP/STPs and record any leftover LDR/STR in PREV_LOC. */
5352 {
5354 {
5357 }
5360 /* The offset of the base of the save area from the current
5361 stack pointer. */
5366 /* Get the two sets in the LDP/STP. */
5367 rtx ops[] = {
5372 };
5377 /* Combine the sets with any stack allocation/deallocation. */
5378 rtx pat;
5380 {
5384 }
5387 else
5390 /* Queue a deallocation to the end, otherwise emit the
5391 instruction now. */
5394 else
5397 }
5399 /* Handle any leftover LDR/STR. */
5401 {
5403 rtx addr;
5407 {
5410 }
5411 else
5412 {
5415 }
5419 else
5421 }
5425 }
5427 /* Allocate or deallocate the stack space needed by the SVE groups.
5428 SEQ chooses between allocating and deallocating. */
5430 void
5432 {
5435 }
5437 /* Save or restore the MEM_SVE_DATA group. SEQ chooses between saving
5438 and restoring. */
5440 void
5442 {
5445 {
5448 }
5449 }
5451 /* Save or restore the MEM_SVE_PRED group. SEQ chooses between saving
5452 and restoring. */
5454 void
5456 {
5460 }
5462 /* Set DEST to (vec_series BASE STEP). */
5464 static void
5466 {
5470 /* Each operand can be a register or an immediate in the range [-16, 15]. */
5477 }
5479 /* Duplicate 128-bit Advanced SIMD vector SRC so that it fills an SVE
5480 register of mode MODE. Use TARGET for the result if it's nonnull
5481 and convenient.
5483 The two vector modes must have the same element mode. The behavior
5484 is to duplicate architectural lane N of SRC into architectural lanes
5485 N + I * STEP of the result. On big-endian targets, architectural
5486 lane 0 of an Advanced SIMD vector is the last element of the vector
5487 in memory layout, so for big-endian targets this operation has the
5488 effect of reversing SRC before duplicating it. Callers need to
5489 account for this. */
5491 rtx
5493 {
5496 insn_code icode = (BYTES_BIG_ENDIAN
5505 {
5506 /* Create a PARALLEL describing the reversal of SRC. */
5511 }
5514 }
5516 /* Try to force 128-bit vector value SRC into memory and use LD1RQ to fetch
5517 the memory image into DEST. Return true on success. */
5519 static bool
5521 {
5526 /* Make sure that the address is legitimate. */
5528 {
5531 }
5538 }
5540 /* SRC is an SVE CONST_VECTOR that contains N "foreground" values followed
5541 by N "background" values. Try to move it into TARGET using:
5543 PTRUE PRED.<T>, VL<N>
5544 MOV TRUE.<T>, #<foreground>
5545 MOV FALSE.<T>, #<background>
5546 SEL TARGET.<T>, PRED.<T>, TRUE.<T>, FALSE.<T>
5548 The PTRUE is always a single instruction but the MOVs might need a
5549 longer sequence. If the background value is zero (as it often is),
5550 the sequence can sometimes collapse to a PTRUE followed by a
5551 zero-predicated move.
5553 Return the target on success, otherwise return null. */
5555 static rtx
5557 {
5560 /* Make sure that the PTRUE is valid. */
5572 {
5575 }
5577 {
5580 }
5588 }
5590 /* Return a register containing CONST_VECTOR SRC, given that SRC has an
5591 SVE data mode and isn't a legitimate constant. Use TARGET for the
5592 result if convenient.
5594 The returned register can have whatever mode seems most natural
5595 given the contents of SRC. */
5597 static rtx
5599 {
5611 {
5612 /* We have a partial vector mode and a constant whose full-vector
5613 equivalent would occupy a repeating 128-bit sequence. Build that
5614 full-vector equivalent instead, so that we have the option of
5615 using LD1RQ and Advanced SIMD operations. */
5624 }
5627 {
5628 /* The constant is a duplicated quadword but can't be narrowed
5629 beyond a quadword. Get the memory image of the first quadword
5630 as a 128-bit vector and try using LD1RQ to load it from memory.
5632 The effect for both endiannesses is to load memory lane N into
5633 architectural lanes N + I * STEP of the result. On big-endian
5634 targets, the layout of the 128-bit vector in an Advanced SIMD
5635 register would be different from its layout in an SVE register,
5636 but this 128-bit vector is a memory value only. */
5641 }
5644 {
5645 /* The vector is a repeating sequence of 64 bits or fewer.
5646 See if we can load them using an Advanced SIMD move and then
5647 duplicate it to fill a vector. This is better than using a GPR
5648 move because it keeps everything in the same register file. */
5652 {
5653 /* We want memory lane N to go into architectural lane N,
5654 so reverse for big-endian targets. The DUP .Q pattern
5655 has a compensating reverse built-in. */
5658 }
5661 {
5664 }
5666 /* Get an integer representation of the repeating part of Advanced
5667 SIMD vector VQ_SRC. This preserves the endianness of VQ_SRC,
5668 which for big-endian targets is lane-swapped wrt a normal
5669 Advanced SIMD vector. This means that for both endiannesses,
5670 memory lane N of SVE vector SRC corresponds to architectural
5671 lane N of a register holding VQ_SRC. This in turn means that
5672 memory lane 0 of SVE vector SRC is in the lsb of VQ_SRC (viewed
5673 as a single 128-bit value) and thus that memory lane 0 of SRC is
5674 in the lsb of the integer. Duplicating the integer therefore
5675 ensures that memory lane N of SRC goes into architectural lane
5676 N + I * INDEX of the SVE register. */
5680 {
5681 /* Pretend that we had a vector of INT_MODE to start with. */
5685 /* If the integer can be moved into a general register by a
5686 single instruction, do that and duplicate the result. */
5690 {
5693 }
5694 }
5696 /* We're duplicating a single value, but can't do better than
5697 force it to memory and load from there. This handles things
5698 like symbolic constants. */
5702 {
5703 /* Load the element from memory if we can, otherwise move it into
5704 a register and use a DUP. */
5709 }
5710 }
5712 /* Try using INDEX. */
5715 {
5718 }
5720 /* From here on, it's better to force the whole constant to memory
5721 if we can. */
5729 /* Expand each pattern individually. */
5731 rtx_vector_builder builder;
5734 {
5739 }
5741 /* Use permutes to interleave the separate vectors. */
5743 {
5746 {
5751 }
5752 }
5755 }
5757 /* Use WHILE to set a predicate register of mode MODE in which the first
5758 VL bits are set and the rest are clear. Use TARGET for the register
5759 if it's nonnull and convenient. */
5761 static rtx
5764 {
5770 }
5772 static rtx
5775 /* BUILDER is a constant predicate in which the index of every set bit
5776 is a multiple of ELT_SIZE (which is <= 8). Try to load the constant
5777 by inverting every element at a multiple of ELT_SIZE and EORing the
5778 result with an ELT_SIZE PTRUE.
5780 Return a register that contains the constant on success, otherwise
5781 return null. Use TARGET as the register if it is nonnull and
5782 convenient. */
5784 static rtx
5787 {
5788 /* Invert every element at a multiple of ELT_SIZE, keeping the
5789 other bits zero. */
5795 else
5799 /* See if we can load the constant cheaply. */
5804 /* EOR the result with an ELT_SIZE PTRUE. */
5811 }
5813 /* BUILDER is a constant predicate in which the index of every set bit
5814 is a multiple of ELT_SIZE (which is <= 8). Try to load the constant
5815 using a TRN1 of size PERMUTE_SIZE, which is >= ELT_SIZE. Return the
5816 register on success, otherwise return null. Use TARGET as the register
5817 if nonnull and convenient. */
5819 static rtx
5823 {
5824 /* We're going to split the constant into two new constants A and B,
5825 with element I of BUILDER going into A if (I & PERMUTE_SIZE) == 0
5826 and into B otherwise. E.g. for PERMUTE_SIZE == 4 && ELT_SIZE == 1:
5828 A: { 0, 1, 2, 3, _, _, _, _, 8, 9, 10, 11, _, _, _, _ }
5829 B: { 4, 5, 6, 7, _, _, _, _, 12, 13, 14, 15, _, _, _, _ }
5831 where _ indicates elements that will be discarded by the permute.
5833 First calculate the ELT_SIZEs for A and B. */
5838 {
5841 else
5843 }
5847 /* Now construct the vectors themselves. */
5855 {
5858 }
5860 {
5861 /* The A and B elements are significant. */
5864 }
5865 else
5866 {
5867 /* The A and B elements are going to be discarded, so pick whatever
5868 is likely to give a nice constant. We are targeting element
5869 sizes A_ELT_SIZE and B_ELT_SIZE for A and B respectively,
5870 with the aim of each being a sequence of ones followed by
5871 a sequence of zeros. So:
5873 * if X_ELT_SIZE <= PERMUTE_SIZE, the best approach is to
5874 duplicate the last X_ELT_SIZE element, to extend the
5875 current sequence of ones or zeros.
5877 * if X_ELT_SIZE > PERMUTE_SIZE, the best approach is to add a
5878 zero, so that the constant really does have X_ELT_SIZE and
5879 not a smaller size. */
5882 else
5886 else
5888 }
5892 /* Try loading A into a register. */
5898 /* Try loading B into a register. */
5901 {
5904 {
5907 }
5908 }
5910 /* Emit the TRN1 itself. We emit a TRN that operates on VNx16BI
5911 operands but permutes them as though they had mode MODE. */
5917 }
5919 /* Subroutine of aarch64_expand_sve_const_pred. Try to load the VNx16BI
5920 constant in BUILDER into an SVE predicate register. Return the register
5921 on success, otherwise return null. Use TARGET for the register if
5922 nonnull and convenient.
5924 ALLOW_RECURSE_P is true if we can use methods that would call this
5925 function recursively. */
5927 static rtx
5930 {
5932 /* A PFALSE or a PTRUE .B ALL. */
5937 {
5938 /* If we can load the constant using PTRUE, use it as-is. */
5943 /* Otherwise use WHILE to set the first VL bits. */
5945 }
5950 /* Try inverting the vector in element size ELT_SIZE and then EORing
5951 the result with an ELT_SIZE PTRUE. */
5954 elt_size))
5957 /* Try using TRN1 to permute two simpler constants. */
5964 }
5966 /* Return an SVE predicate register that contains the VNx16BImode
5967 constant in BUILDER, without going through the move expanders.
5969 The returned register can have whatever mode seems most natural
5970 given the contents of BUILDER. Use TARGET for the result if
5971 convenient. */
5973 static rtx
5975 {
5976 /* Try loading the constant using pure predicate operations. */
5980 /* Try forcing the constant to memory. */
5983 {
5987 }
5989 /* The last resort is to load the constant as an integer and then
5990 compare it against zero. Use -1 for set bits in order to increase
5991 the changes of using SVE DUPM or an Advanced SIMD byte mask. */
5999 }
6001 /* Set DEST to immediate IMM. */
6003 void
6005 {
6008 /* Check on what type of symbol it is. */
6009 scalar_int_mode int_mode;
6015 {
6016 rtx mem;
6017 poly_int64 offset;
6018 HOST_WIDE_INT const_offset;
6021 /* If we have (const (plus symbol offset)), separate out the offset
6022 before we start classifying the symbol. */
6025 /* We must always add an offset involving VL separately, rather than
6026 folding it into the relocation. */
6028 {
6030 {
6033 }
6038 else
6039 {
6040 /* Do arithmetic on 32-bit values if the result is smaller
6041 than that. */
6043 {
6044 /* It is invalid to do symbol calculations in modes
6045 narrower than SImode. */
6049 }
6051 {
6055 }
6056 else
6059 }
6061 }
6064 {
6065 /* We could handle non-constant offsets if they are ever
6066 generated. */
6070 }
6074 {
6081 {
6087 }
6092 /* If we aren't generating PC relative literals, then
6093 we need to expand the literal pool access carefully.
6094 This is something that needs to be done in a number
6095 of places, so could well live as a separate function. */
6097 {
6104 }
6121 {
6127 }
6128 /* FALLTHRU */
6141 }
6142 }
6145 {
6147 {
6148 /* Only the low bit of each .H, .S and .D element is defined,
6149 so we can set the upper bits to whatever we like. If the
6150 predicate is all-true in MODE, prefer to set all the undefined
6151 bits as well, so that we can share a single .B predicate for
6152 all modes. */
6156 /* All methods for constructing predicate modes wider than VNx16BI
6157 will set the upper bits of each element to zero. Expose this
6158 by moving such constants as a VNx16BI, so that all bits are
6159 significant and so that constants for different modes can be
6160 shared. The wider constant will still be available as a
6161 REG_EQUAL note. */
6162 rtx_vector_builder builder;
6164 {
6169 }
6170 }
6174 {
6177 }
6181 {
6185 }
6191 }
6194 }
6196 /* Return the MEM rtx that provides the canary value that should be used
6197 for stack-smashing protection. MODE is the mode of the memory.
6198 For SSP_GLOBAL, DECL_RTL is the MEM rtx for the canary variable
6199 (__stack_chk_guard), otherwise it has no useful value. SALT_TYPE
6200 indicates whether the caller is performing a SET or a TEST operation. */
6202 rtx
6204 aarch64_salt_type salt_type)
6205 {
6206 rtx addr;
6208 {
6211 poly_int64 offset;
6220 }
6221 else
6222 {
6223 /* Calculate the address from the system register. */
6228 else
6229 {
6232 }
6234 }
6236 }
6238 /* Emit an SVE predicated move from SRC to DEST. PRED is a predicate
6239 that is known to contain PTRUE. */
6241 void
6243 {
6251 }
6253 /* Expand a pre-RA SVE data move from SRC to DEST in which at least one
6254 operand is in memory. In this case we need to use the predicated LD1
6255 and ST1 instead of LDR and STR, both for correctness on big-endian
6256 targets and because LD1 and ST1 support a wider range of addressing modes.
6257 PRED_MODE is the mode of the predicate.
6259 See the comment at the head of aarch64-sve.md for details about the
6260 big-endian handling. */
6262 void
6264 {
6269 {
6273 else
6276 }
6278 }
6280 /* Called only on big-endian targets. See whether an SVE vector move
6281 from SRC to DEST is effectively a REV[BHW] instruction, because at
6282 least one operand is a subreg of an SVE vector that has wider or
6283 narrower elements. Return true and emit the instruction if so.
6285 For example:
6287 (set (reg:VNx8HI R1) (subreg:VNx8HI (reg:VNx16QI R2) 0))
6289 represents a VIEW_CONVERT between the following vectors, viewed
6290 in memory order:
6292 R2: { [0].high, [0].low, [1].high, [1].low, ... }
6293 R1: { [0], [1], [2], [3], ... }
6295 The high part of lane X in R2 should therefore correspond to lane X*2
6296 of R1, but the register representations are:
6298 msb lsb
6299 R2: ...... [1].high [1].low [0].high [0].low
6300 R1: ...... [3] [2] [1] [0]
6302 where the low part of lane X in R2 corresponds to lane X*2 in R1.
6303 We therefore need a reverse operation to swap the high and low values
6304 around.
6306 This is purely an optimization. Without it we would spill the
6307 subreg operand to the stack in one mode and reload it in the
6308 other mode, which has the same effect as the REV. */
6310 bool
6312 {
6315 /* Do not try to optimize subregs that LRA has created for matched
6316 reloads. These subregs only exist as a temporary measure to make
6317 the RTL well-formed, but they are exempt from the usual
6318 TARGET_CAN_CHANGE_MODE_CLASS rules.
6320 For example, if we have:
6322 (set (reg:VNx8HI R1) (foo:VNx8HI (reg:VNx4SI R2)))
6324 and the constraints require R1 and R2 to be in the same register,
6325 LRA may need to create RTL such as:
6327 (set (subreg:VNx4SI (reg:VNx8HI TMP) 0) (reg:VNx4SI R2))
6328 (set (reg:VNx8HI TMP) (foo:VNx8HI (subreg:VNx4SI (reg:VNx8HI TMP) 0)))
6329 (set (reg:VNx8HI R1) (reg:VNx8HI TMP))
6331 which forces both the input and output of the original instruction
6332 to use the same hard register. But for this to work, the normal
6333 rules have to be suppressed on the subreg input, otherwise LRA
6334 would need to reload that input too, meaning that the process
6335 would never terminate. To compensate for this, the normal rules
6336 are also suppressed for the subreg output of the first move.
6337 Ignoring the special case and handling the first move normally
6338 would therefore generate wrong code: we would reverse the elements
6339 for the first subreg but not reverse them back for the second subreg. */
6345 /* The optimization handles two single SVE REGs with different element
6346 sizes. */
6355 /* Generate *aarch64_sve_mov<mode>_subreg_be. */
6358 UNSPEC_REV_SUBREG);
6361 }
6363 /* Return a copy of X with mode MODE, without changing its other
6364 attributes. Unlike gen_lowpart, this doesn't care whether the
6365 mode change is valid. */
6367 rtx
6369 {
6376 }
6378 /* Return the SVE REV[BHW] unspec for reversing quantites of mode MODE
6379 stored in wider integer containers. */
6381 static unsigned int
6383 {
6385 {
6389 }
6391 }
6393 /* Split a *aarch64_sve_mov<mode>_subreg_be pattern with the given
6394 operands. */
6396 void
6398 {
6399 /* Decide which REV operation we need. The mode with wider elements
6400 determines the mode of the operands and the mode with the narrower
6401 elements determines the reverse width. */
6411 /* Get the operands in the appropriate modes and emit the instruction. */
6417 }
6419 static bool
6421 {
6433 }
6435 /* Subroutine of aarch64_pass_by_reference for arguments that are not
6436 passed in SVE registers. */
6438 static bool
6441 {
6442 HOST_WIDE_INT size;
6443 machine_mode dummymode;
6446 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
6449 else
6450 /* No frontends can create types with variable-sized modes, so we
6451 shouldn't be asked to pass or return them. */
6454 /* Aggregates are passed by reference based on their size. */
6458 /* Variable sized arguments are always returned by reference. */
6462 /* Can this be a candidate to be passed in fp/simd register(s)? */
6468 /* Arguments which are variable sized or larger than 2 registers are
6469 passed by reference unless they are a homogenous floating point
6470 aggregate. */
6472 }
6474 /* Implement TARGET_PASS_BY_REFERENCE. */
6476 static bool
6479 {
6485 pure_scalable_type_info pst_info;
6487 {
6490 /* We can't gracefully recover at this point, so make this a
6491 fatal error. */
6495 /* Variadic SVE types are passed by reference. Normal non-variadic
6496 arguments are too if we've run out of registers. */
6508 }
6510 }
6512 /* Return TRUE if VALTYPE is padded to its least significant bits. */
6513 static bool
6515 {
6516 machine_mode dummy_mode;
6519 /* Never happens in little-endian mode. */
6523 /* Only composite types smaller than or equal to 16 bytes can
6524 be potentially returned in registers. */
6530 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
6531 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
6532 is always passed/returned in the least significant bits of fp/simd
6533 register(s). */
6539 /* Likewise pure scalable types for SVE vector and predicate registers. */
6540 pure_scalable_type_info pst_info;
6545 }
6547 /* Implement TARGET_FUNCTION_VALUE.
6548 Define how to find the value returned by a function. */
6550 static rtx
6553 {
6554 machine_mode mode;
6561 pure_scalable_type_info pst_info;
6565 /* Generic vectors that map to full SVE modes with -msve-vector-bits=N
6566 are returned in memory, not by value. */
6571 {
6575 {
6578 }
6579 }
6582 machine_mode ag_mode;
6585 {
6588 {
6591 }
6598 else
6599 {
6601 rtx par;
6605 {
6610 }
6612 }
6613 }
6614 else
6615 {
6617 {
6618 /* Vector types can acquire a partial SVE mode using things like
6619 __attribute__((vector_size(N))), and this is potentially useful.
6620 However, the choice of mode doesn't affect the type's ABI
6621 identity, so we should treat the types as though they had
6622 the associated integer mode, just like they did before SVE
6623 was introduced.
6625 We know that the vector must be 128 bits or smaller,
6626 otherwise we'd have returned it in memory instead. */
6635 }
6637 }
6638 }
6640 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
6641 Return true if REGNO is the number of a hard register in which the values
6642 of called function may come back. */
6644 static bool
6646 {
6647 /* Maximum of 16 bytes can be returned in the general registers. Examples
6648 of 16-byte return values are: 128-bit integers and 16-byte small
6649 structures (excluding homogeneous floating-point aggregates). */
6653 /* Up to four fp/simd registers can return a function value, e.g. a
6654 homogeneous floating-point aggregate having four members. */
6662 }
6664 /* Subroutine for aarch64_return_in_memory for types that are not returned
6665 in SVE registers. */
6667 static bool
6669 {
6670 HOST_WIDE_INT size;
6671 machine_mode ag_mode;
6678 /* Simple scalar types always returned in registers. */
6685 /* Types larger than 2 registers returned in memory. */
6688 }
6690 /* Implement TARGET_RETURN_IN_MEMORY.
6692 If the type T of the result of a function is such that
6693 void func (T arg)
6694 would require that arg be passed as a value in a register (or set of
6695 registers) according to the parameter passing rules, then the result
6696 is returned in the same registers as would be used for such an
6697 argument. */
6699 static bool
6701 {
6702 pure_scalable_type_info pst_info;
6704 {
6716 }
6718 }
6720 static bool
6723 {
6728 }
6730 /* Given MODE and TYPE of a function argument, return the alignment in
6731 bits. The idea is to suppress any stronger alignment requested by
6732 the user and opt for the natural alignment (specified in AAPCS64 \S
6733 4.1). ABI_BREAK_GCC_9 is set to the old alignment if the alignment
6734 was incorrectly calculated in versions of GCC prior to GCC 9.
6735 ABI_BREAK_GCC_13 is set to the old alignment if it was incorrectly
6736 calculated in versions between GCC 9 and GCC 13. If the alignment
6737 might have changed between GCC 13 and GCC 14, ABI_BREAK_GCC_14
6738 is the old GCC 13 alignment, otherwise it is zero.
6740 This is a helper function for local use only. */
6742 static unsigned int
6747 {
6760 {
6761 /* The ABI alignment is the natural alignment of the type, without
6762 any attributes applied. Normally this is the alignment of the
6763 TYPE_MAIN_VARIANT, but not always; see PR108910 for a counterexample.
6764 For now we just handle the known exceptions explicitly. */
6767 {
6770 }
6772 {
6775 }
6778 }
6788 {
6789 /* Note that we explicitly consider zero-sized fields here,
6790 even though they don't map to AAPCS64 machine types.
6791 For example, in:
6793 struct __attribute__((aligned(8))) empty {};
6795 struct s {
6796 [[no_unique_address]] empty e;
6797 int x;
6798 };
6800 "s" contains only one Fundamental Data Type (the int field)
6801 but gains 8-byte alignment and size thanks to "e". */
6804 {
6805 /* Take the bit-field type's alignment into account only
6806 if the user didn't reduce this field's alignment with
6807 the packed attribute. */
6809 bitfield_alignment
6813 /* Compute the alignment even if the bit-field is
6814 packed, so that we can emit a warning in case the
6815 alignment changed between GCC versions. */
6816 bitfield_alignment_with_packed
6819 }
6820 }
6822 /* Emit a warning if the alignment is different when taking the
6823 'packed' attribute into account. */
6829 {
6832 }
6835 }
6837 /* Return true if TYPE describes a _BitInt(N) or an angreggate that uses the
6838 _BitInt(N) type. These include ARRAY_TYPE's with an element that is a
6839 _BitInt(N) or an aggregate that uses it, and a RECORD_TYPE or a UNION_TYPE
6840 with a field member that is a _BitInt(N) or an aggregate that uses it.
6841 Return false otherwise. */
6843 static bool
6845 {
6852 /* If ARRAY_TYPE, check it's element type. */
6856 /* If RECORD_TYPE or UNION_TYPE, check the fields' types. */
6859 {
6864 }
6866 }
6868 /* Layout a function argument according to the AAPCS64 rules. The rule
6869 numbers refer to the rule numbers in the AAPCS64. ORIG_MODE is the
6870 mode that was originally given to us by the target hook, whereas the
6871 mode in ARG might be the result of replacing partial SVE modes with
6872 the equivalent integer mode. */
6874 static void
6876 {
6882 HOST_WIDE_INT size;
6887 /* We need to do this once per argument. */
6891 bool warn_pcs_change
6892 = (warn_psabi
6894 && (currently_expanding_function_start
6897 /* HFAs and HVAs can have an alignment greater than 16 bytes. For example:
6899 typedef struct foo {
6900 __Int8x16_t foo[2] __attribute__((aligned(32)));
6901 } foo;
6903 is still a HVA despite its larger-than-normal alignment.
6904 However, such over-aligned HFAs and HVAs are guaranteed to have
6905 no padding.
6907 If we exclude HFAs and HVAs from the discussion below, then there
6908 are several things to note:
6910 - Both the C and AAPCS64 interpretations of a type's alignment should
6911 give a value that is no greater than the type's size.
6913 - Types bigger than 16 bytes are passed indirectly.
6915 - If an argument of type T is passed indirectly, TYPE and MODE describe
6916 a pointer to T rather than T iself.
6918 It follows that the AAPCS64 alignment of TYPE must be no greater
6919 than 16 bytes.
6921 Versions prior to GCC 9.1 ignored a bitfield's underlying type
6922 and so could calculate an alignment that was too small. If this
6923 happened for TYPE then ABI_BREAK_GCC_9 is this older, too-small alignment.
6925 Although GCC 9.1 fixed that bug, it introduced a different one:
6926 it would consider the alignment of a bitfield's underlying type even
6927 if the field was packed (which should have the effect of overriding
6928 the alignment of the underlying type). This was fixed in GCC 13.1.
6930 As a result of this bug, GCC 9 to GCC 12 could calculate an alignment
6931 that was too big. If this happened for TYPE, ABI_BREAK_GCC_13 is
6932 this older, too-big alignment.
6934 Also, the fact that GCC 9 to GCC 12 considered irrelevant
6935 alignments meant they could calculate type alignments that were
6936 bigger than the type's size, contrary to the assumption above.
6937 The handling of register arguments was nevertheless (and justifiably)
6938 written to follow the assumption that the alignment can never be
6939 greater than the size. The same was not true for stack arguments;
6940 their alignment was instead handled by MIN bounds in
6941 aarch64_function_arg_boundary.
6943 The net effect is that, if GCC 9 to GCC 12 incorrectly calculated
6944 an alignment of more than 16 bytes for TYPE then:
6946 - If the argument was passed in registers, these GCC versions
6947 would treat the alignment as though it was *less than* 16 bytes.
6949 - If the argument was passed on the stack, these GCC versions
6950 would treat the alignment as though it was *equal to* 16 bytes.
6952 Both behaviors were wrong, but in different cases. */
6956 pure_scalable_type_info pst_info;
6958 {
6959 /* aarch64_function_arg_alignment has never had an effect on
6960 this case. */
6962 /* The PCS says that it is invalid to pass an SVE value to an
6963 unprototyped function. There is no ABI-defined location we
6964 can return in this case, so we have no real choice but to raise
6965 an error immediately, even though this is only a query function. */
6967 {
6971 /* Avoid repeating the message, and avoid tripping the assert
6972 below. */
6974 }
6976 /* We would have converted the argument into pass-by-reference
6977 form if it didn't fit in registers. */
6987 }
6989 /* Generic vectors that map to full SVE modes with -msve-vector-bits=N
6990 are passed by reference, not by value. */
6994 /* Vector types can acquire a partial SVE mode using things like
6995 __attribute__((vector_size(N))), and this is potentially useful.
6996 However, the choice of mode doesn't affect the type's ABI
6997 identity, so we should treat the types as though they had
6998 the associated integer mode, just like they did before SVE
6999 was introduced.
7001 We know that the vector must be 128 bits or smaller,
7002 otherwise we'd have passed it in memory instead. */
7007 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
7010 else
7011 /* No frontends can create types with variable-sized modes, so we
7012 shouldn't be asked to pass or return them. */
7018 mode,
7019 type,
7023 unsigned int alignment
7031 /* _BitInt(N) was only added in GCC 14. */
7032 bool warn_pcs_change_le_gcc14
7035 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
7036 The following code thus handles passing by SIMD/FP registers first. */
7040 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
7041 and homogenous short-vector aggregates (HVA). */
7043 {
7044 /* aarch64_function_arg_alignment has never had an effect on
7045 this case. */
7050 {
7053 {
7056 }
7063 else
7064 {
7065 rtx par;
7069 {
7072 rtx offset = gen_int_mode
7076 }
7078 }
7080 }
7081 else
7082 {
7083 /* C.3 NSRN is set to 8. */
7086 }
7087 }
7092 /* C6 - C9. though the sign and zero extension semantics are
7093 handled elsewhere. This is the case where the argument fits
7094 entirely general registers. */
7096 {
7099 /* C.8 if the argument has an alignment of 16 then the NGRN is
7100 rounded up to the next even number. */
7103 {
7104 /* Emit a warning if the alignment changed when taking the
7105 'packed' attribute into account. */
7107 && abi_break_gcc_13
7114 && abi_break_gcc_14
7120 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
7121 comparison is there because for > 16 * BITS_PER_UNIT
7122 alignment nregs should be > 2 and therefore it should be
7123 passed by reference rather than value. */
7125 {
7132 }
7133 }
7135 /* If an argument with an SVE mode needs to be shifted up to the
7136 high part of the register, treat it as though it had an integer mode.
7137 Using the normal (parallel [...]) would suppress the shifting. */
7139 && BYTES_BIG_ENDIAN
7142 {
7145 }
7147 /* NREGS can be 0 when e.g. an empty structure is to be passed.
7148 A reg is still generated for it, but the caller should be smart
7149 enough not to use it. */
7154 else
7155 {
7156 rtx par;
7161 {
7169 }
7171 }
7175 }
7177 /* C.11 */
7180 /* The argument is passed on stack; record the needed number of words for
7181 this argument and align the total size if necessary. */
7182 on_stack:
7186 && abi_break_gcc_13
7193 && abi_break_gcc_14
7200 {
7203 {
7209 }
7210 }
7212 }
7214 /* Add the current argument register to the set of those that need
7215 to be saved and restored around a change to PSTATE.SM. */
7217 static void
7219 {
7222 {
7225 {
7229 }
7230 }
7231 }
7233 /* Return a parallel that contains all the registers that need to be
7234 saved around a change to PSTATE.SM. Return const0_rtx if there is
7235 no such mode switch, or if no registers need to be saved. */
7237 static rtx
7239 {
7246 }
7248 /* Implement TARGET_FUNCTION_ARG. */
7250 static rtx
7252 {
7259 {
7266 sme_mode_switch_args,
7267 shared_za_flags,
7268 shared_zt0_flags));
7269 }
7273 }
7275 void
7277 const_tree fntype,
7278 rtx libname ATTRIBUTE_UNUSED,
7279 const_tree fndecl,
7282 {
7290 {
7293 }
7294 else
7295 {
7298 }
7304 pcum->shared_za_flags
7306 pcum->shared_zt0_flags
7311 && !TARGET_FLOAT
7313 {
7320 }
7323 && !TARGET_SVE
7325 {
7326 /* We can't gracefully recover at this point, so make this a
7327 fatal error. */
7330 fndecl);
7331 else
7334 }
7335 }
7337 static void
7340 {
7345 {
7360 }
7361 }
7363 bool
7365 {
7369 }
7371 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
7372 PARM_BOUNDARY bits of alignment, but will be given anything up
7373 to STACK_BOUNDARY bits if the type requires it. This makes sure
7374 that both before and after the layout of each argument, the Next
7375 Stacked Argument Address (NSAA) will have a minimum alignment of
7376 8 bytes. */
7378 static unsigned int
7380 {
7388 /* We rely on aarch64_layout_arg and aarch64_gimplify_va_arg_expr
7389 to emit warnings about ABI incompatibility. */
7392 }
7394 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
7396 static fixed_size_mode
7398 {
7399 /* Don't use any non GP registers for __builtin_apply and
7400 __builtin_return if general registers only mode is requested. */
7404 /* Don't use the SVE part of the register for __builtin_apply and
7405 __builtin_return. The SVE registers aren't used by the normal PCS,
7406 so using them there would be a waste of time. The PCS extensions
7407 for SVE types are fundamentally incompatible with the
7408 __builtin_return/__builtin_apply interface. */
7411 /* For SVE PR regs, indicate that they should be ignored for
7412 __builtin_apply/__builtin_return. */
7415 }
7417 /* Implement TARGET_FUNCTION_ARG_PADDING.
7419 Small aggregate types are placed in the lowest memory address.
7421 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
7423 static pad_direction
7425 {
7426 /* On little-endian targets, the least significant byte of every stack
7427 argument is passed at the lowest byte address of the stack slot. */
7431 /* Otherwise, integral, floating-point and pointer types are padded downward:
7432 the least significant byte of a stack argument is passed at the highest
7433 byte address of the stack slot. */
7440 /* Everything else padded upward, i.e. data in first byte of stack slot. */
7442 }
7444 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7446 It specifies padding for the last (may also be the only)
7447 element of a block move between registers and memory. If
7448 assuming the block is in the memory, padding upward means that
7449 the last element is padded after its highest significant byte,
7450 while in downward padding, the last element is padded at the
7451 its least significant byte side.
7453 Small aggregates and small complex types are always padded
7454 upwards.
7456 We don't need to worry about homogeneous floating-point or
7457 short-vector aggregates; their move is not affected by the
7458 padding direction determined here. Regardless of endianness,
7459 each element of such an aggregate is put in the least
7460 significant bits of a fp/simd register.
7462 Return !BYTES_BIG_ENDIAN if the least significant byte of the
7463 register has useful data, and return the opposite if the most
7464 significant byte does. */
7466 bool
7469 {
7471 /* Aside from pure scalable types, small composite types are always
7472 padded upward. */
7474 {
7475 HOST_WIDE_INT size;
7478 else
7479 /* No frontends can create types with variable-sized modes, so we
7480 shouldn't be asked to pass or return them. */
7483 {
7484 pure_scalable_type_info pst_info;
7488 }
7489 }
7491 /* Otherwise, use the default padding. */
7493 }
7495 static scalar_int_mode
7497 {
7499 }
7501 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
7503 /* We use the 12-bit shifted immediate arithmetic instructions so values
7504 must be multiple of (1 << 12), i.e. 4096. */
7505 #define ARITH_FACTOR 4096
7507 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
7508 #error Cannot use simple address calculation for stack probing
7509 #endif
7511 /* Emit code to probe a range of stack addresses from FIRST to FIRST+POLY_SIZE,
7512 inclusive. These are offsets from the current stack pointer. */
7514 static void
7516 {
7517 HOST_WIDE_INT size;
7519 {
7522 }
7526 /* See the same assertion on PROBE_INTERVAL above. */
7529 /* See if we have a constant small number of probes to generate. If so,
7530 that's the easy case. */
7532 {
7539 }
7541 /* The run-time loop is made up of 8 insns in the generic case while the
7542 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
7544 {
7549 stack_pointer_rtx,
7553 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
7554 it exceeds SIZE. If only two probes are needed, this will not
7555 generate any code. Then probe at FIRST + SIZE. */
7557 {
7561 }
7565 {
7570 }
7571 else
7573 }
7575 /* Otherwise, do the same as above, but in a loop. Note that we must be
7576 extra careful with variables wrapping around because we might be at
7577 the very top (or the very bottom) of the address space and we have
7578 to be able to handle this case properly; in particular, we use an
7579 equality test for the loop condition. */
7580 else
7581 {
7584 /* Step 1: round SIZE to the previous multiple of the interval. */
7589 /* Step 2: compute initial and final value of the loop counter. */
7591 /* TEST_ADDR = SP + FIRST. */
7595 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
7598 {
7602 }
7603 else
7607 /* Step 3: the loop
7609 do
7610 {
7611 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
7612 probe at TEST_ADDR
7613 }
7614 while (TEST_ADDR != LAST_ADDR)
7616 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
7617 until it is equal to ROUNDED_SIZE. */
7622 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
7623 that SIZE is equal to ROUNDED_SIZE. */
7626 {
7630 {
7635 }
7636 else
7638 }
7639 }
7641 /* Make sure nothing is scheduled before we are done. */
7643 }
7645 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
7646 absolute addresses. */
7650 {
7657 /* Loop. */
7660 HOST_WIDE_INT stack_clash_probe_interval
7663 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
7665 HOST_WIDE_INT interval;
7668 else
7676 /* If doing stack clash protection then we probe up by the ABI specified
7677 amount. We do this because we're dropping full pages at a time in the
7678 loop. But if we're doing non-stack clash probing, probe at SP 0. */
7681 else
7684 /* Probe at TEST_ADDR. If we're inside the loop it is always safe to probe
7685 by this amount for each iteration. */
7688 /* Test if TEST_ADDR == LAST_ADDR. */
7692 /* Branch. */
7698 }
7700 /* Emit the probe loop for doing stack clash probes and stack adjustments for
7701 SVE. This emits probes from BASE to BASE - ADJUSTMENT based on a guard size
7702 of GUARD_SIZE. When a probe is emitted it is done at most
7703 MIN_PROBE_THRESHOLD bytes from the current BASE at an interval of
7704 at most MIN_PROBE_THRESHOLD. By the end of this function
7705 BASE = BASE - ADJUSTMENT. */
7710 {
7711 /* This function is not allowed to use any instruction generation function
7712 like gen_ and friends. If you do you'll likely ICE during CFG validation,
7713 so instead emit the code you want using output_asm_insn. */
7718 /* The minimum required allocation before the residual requires probing. */
7721 /* Clamp the value down to the nearest value that can be used with a cmp. */
7736 /* Emit loop start label. */
7739 /* ADJUSTMENT < RESIDUAL_PROBE_GUARD. */
7744 /* Branch to end if not enough adjustment to probe. */
7749 /* BASE = BASE - RESIDUAL_PROBE_GUARD. */
7754 /* Probe at BASE. */
7758 /* ADJUSTMENT = ADJUSTMENT - RESIDUAL_PROBE_GUARD. */
7763 /* Branch to start if still more bytes to allocate. */
7768 /* No probe leave. */
7771 /* BASE = BASE - ADJUSTMENT. */
7776 }
7778 /* Determine whether a frame chain needs to be generated. */
7779 static bool
7781 {
7785 /* A leaf function cannot have calls or write LR. */
7788 /* Don't use a frame chain in leaf functions if leaf frame pointers
7789 are disabled. */
7794 }
7796 /* Return true if the current function should save registers above
7797 the locals area, rather than below it. */
7799 static bool
7801 {
7802 /* When using stack smash protection, make sure that the canary slot
7803 comes between the locals and the saved registers. Otherwise,
7804 it would be possible for a carefully sized smash attack to change
7805 the saved registers (particularly LR and FP) without reaching the
7806 canary. */
7808 }
7810 /* Return true if the current function needs to record the incoming
7811 value of PSTATE.SM. */
7812 static bool
7814 {
7815 /* Exit early if the incoming value of PSTATE.SM is known at
7816 compile time. */
7823 /* Non-local goto receivers are entered with PSTATE.SM equal to 0,
7824 but the function needs to return with PSTATE.SM unchanged. */
7828 /* Likewise for exception handlers. */
7829 eh_landing_pad lp;
7834 /* Non-local gotos need to set PSTATE.SM to zero. It's possible to call
7835 streaming-compatible functions without SME being available, so PSTATE.SM
7836 should only be changed if it is currently set to one. */
7844 {
7845 /* Return true if there is a call to a non-streaming-compatible
7846 function. */
7850 }
7852 }
7854 /* Mark the registers that need to be saved by the callee and calculate
7855 the size of the callee-saved registers area and frame record (both FP
7856 and LR may be omitted). */
7857 static void
7859 {
7874 /* Adjust the outgoing arguments size if required. Keep it in sync with what
7875 the mid-end is doing. */
7878 #define SLOT_NOT_REQUIRED (-2)
7879 #define SLOT_REQUIRED (-1)
7885 /* First mark all the registers that really need to be saved... */
7890 /* ... that includes the eh data registers (if needed)... */
7895 /* ... and any callee saved register that dataflow says is live. */
7907 {
7912 }
7914 /* Big-endian SVE frames need a spare predicate register in order
7915 to save Z8-Z15. Decide which register they should use. Prefer
7916 an unused argument register if possible, so that we don't force P4
7917 to be saved unnecessarily. */
7921 {
7930 }
7943 {
7947 }
7951 /* Now assign stack slots for the registers. Start with the predicate
7952 registers, since predicate LDR and STR have a relatively small
7953 offset range. These saves happen below the hard frame pointer. */
7956 {
7962 }
7966 {
7967 /* If we have any vector registers to save above the predicate registers,
7968 the offset of the vector register save slots need to be a multiple
7969 of the vector size. This lets us use the immediate forms of LDR/STR
7970 (or LD1/ST1 for big-endian).
7972 A vector register is 8 times the size of a predicate register,
7973 and we need to save a maximum of 12 predicate registers, so the
7974 first vector register will be at either #1, MUL VL or #2, MUL VL.
7976 If we don't have any vector registers to save, and we know how
7977 big the predicate save area is, we can just round it up to the
7978 next 16-byte boundary. */
7981 else
7982 {
7987 else
7989 }
7990 }
7992 /* If we need to save any SVE vector registers, add them next. */
7996 {
8002 }
8004 /* OFFSET is now the offset of the hard frame pointer from the bottom
8005 of the callee save area. */
8017 {
8021 };
8024 {
8025 /* FP and LR are placed in the linkage record. */
8028 }
8031 /* Put the LR save slot first, since it makes a good choice of probe
8032 for stack clash purposes. The idea is that the link register usually
8033 has to be saved before a call anyway, and so we lose little by
8034 stopping it from being individually shrink-wrapped. */
8042 {
8045 }
8047 /* If the current function changes the SVE vector length, ensure that the
8048 old value of the DWARF VG register is saved and available in the CFI,
8049 so that outer frames with VL-sized offsets can be processed correctly. */
8052 {
8055 }
8063 {
8065 /* If there is an alignment gap between integer and fp callee-saves,
8066 allocate the last fp register to it if possible. */
8068 && has_align_gap
8071 {
8074 }
8078 }
8088 {
8093 }
8095 /* With stack-clash, a register must be saved in non-leaf functions.
8096 The saving of the bottommost register counts as an implicit probe,
8097 which allows us to maintain the invariant described in the comment
8098 at expand_prologue. */
8102 {
8106 }
8123 /* Shadow call stack only deals with functions where the LR is pushed
8124 onto the stack and without specifying the "no_sanitize" attribute
8125 with the argument "shadow-call-stack". */
8126 frame.is_scs_enabled
8131 /* When shadow call stack is enabled, the scs_pop in the epilogue will
8132 restore x30, and we don't need to pop x30 again in the traditional
8133 way. Pop candidates record the registers that need to be popped
8134 eventually. */
8136 {
8141 }
8143 /* If candidate2 is INVALID_REGNUM, we need to adjust max_push_offset to
8144 256 to ensure that the offset meets the requirements of emit_move_insn.
8145 Similarly, if candidate1 is INVALID_REGNUM, we need to set
8146 max_push_offset to 0, because no registers are popped at this time,
8147 so callee_adjust cannot be adjusted. */
8150 {
8153 else
8155 }
8158 HOST_WIDE_INT const_saved_regs_size;
8164 {
8165 /* Simple, small frame with no data below the saved registers.
8167 stp reg1, reg2, [sp, -frame_size]!
8168 stp reg3, reg4, [sp, 16] */
8170 }
8174 /* We could handle this case even with data below the saved
8175 registers, provided that that data left us with valid offsets
8176 for all predicate and vector save slots. It's such a rare
8177 case that it hardly seems worth the effort though. */
8182 {
8183 /* Frame with small area below the saved registers:
8185 sub sp, sp, frame_size
8186 stp reg1, reg2, [sp, bytes_below_saved_regs]
8187 stp reg3, reg4, [sp, bytes_below_saved_regs + 16] */
8189 }
8192 {
8193 /* Frame in which all saves are SVE saves:
8195 sub sp, sp, frame_size - bytes_below_saved_regs
8196 save SVE registers relative to SP
8197 sub sp, sp, bytes_below_saved_regs */
8200 }
8204 {
8205 /* Frame with large area below the saved registers, or with SVE saves,
8206 but with a small area above:
8208 stp reg1, reg2, [sp, -hard_fp_offset]!
8209 stp reg3, reg4, [sp, 16]
8210 [sub sp, sp, below_hard_fp_saved_regs_size]
8211 [save SVE registers relative to SP]
8212 sub sp, sp, bytes_below_saved_regs */
8216 }
8217 else
8218 {
8219 /* General case:
8221 sub sp, sp, hard_fp_offset
8222 stp x29, x30, [sp, 0]
8223 add x29, sp, 0
8224 stp reg3, reg4, [sp, 16]
8225 [sub sp, sp, below_hard_fp_saved_regs_size]
8226 [save SVE registers relative to SP]
8227 sub sp, sp, bytes_below_saved_regs */
8231 }
8233 /* The frame is allocated in pieces, with each non-final piece
8234 including a register save at offset 0 that acts as a probe for
8235 the following piece. In addition, the save of the bottommost register
8236 acts as a probe for callees and allocas. Roll back any probes that
8237 aren't needed.
8239 A probe isn't needed if it is associated with the final allocation
8240 (including callees and allocas) that happens before the epilogue is
8241 executed. */
8245 {
8248 else
8250 }
8252 /* Make sure the individual adjustments add up to the full frame size. */
8259 {
8260 /* We've decided not to do a "real" push and pop. However,
8261 setting up the frame chain is treated as being essentially
8262 a multi-instruction push. */
8266 }
8269 }
8271 /* Return true if the register REGNO is saved on entry to
8272 the current function. */
8274 static bool
8276 {
8278 }
8280 /* Push the register number REGNO of mode MODE to the stack with write-back
8281 adjusting the stack by ADJUSTMENT. */
8283 static void
8285 HOST_WIDE_INT adjustment)
8286 {
8297 }
8299 /* Generate and return an instruction to store the pair of registers
8300 REG and REG2 of mode MODE to location BASE with write-back adjusting
8301 the stack location BASE by ADJUSTMENT. */
8303 static rtx
8305 HOST_WIDE_INT adjustment)
8306 {
8316 }
8318 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
8319 stack pointer by ADJUSTMENT. */
8321 static void
8323 {
8338 }
8340 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
8341 adjusting it by ADJUSTMENT afterwards. */
8343 static rtx
8345 HOST_WIDE_INT adjustment)
8346 {
8356 }
8358 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
8359 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
8360 into CFI_OPS. */
8362 static void
8365 {
8372 {
8376 }
8377 else
8378 {
8383 }
8384 }
8386 /* Given an ldp/stp register operand mode MODE, return a suitable mode to use
8387 for a mem rtx representing the entire pair. */
8389 static machine_mode
8391 {
8398 else
8400 }
8402 /* Given a base mem MEM with mode and address suitable for a single ldp/stp
8403 operand, return an rtx like MEM which instead represents the entire pair. */
8405 static rtx
8407 {
8412 }
8414 /* Generate and return a store pair instruction to store REG1 and REG2
8415 into memory starting at BASE_MEM. All three rtxes should have modes of the
8416 same size. */
8418 rtx
8420 {
8426 UNSPEC_STP));
8427 }
8429 /* Generate and return a load pair instruction to load a pair of
8430 registers starting at BASE_MEM into REG1 and REG2. If CODE is
8431 UNKNOWN, all three rtxes should have modes of the same size.
8432 Otherwise, CODE is {SIGN,ZERO}_EXTEND, base_mem should be in SImode,
8433 and REG{1,2} should be in DImode. */
8435 rtx
8437 {
8445 else
8451 UNSPEC_LDP_FST),
8454 UNSPEC_LDP_SND)
8455 };
8465 }
8467 /* Return TRUE if return address signing should be enabled for the current
8468 function, otherwise return FALSE. */
8470 bool
8472 {
8473 /* This function should only be called after frame laid out. */
8476 /* If signing scope is AARCH_FUNCTION_NON_LEAF, we only sign a leaf function
8477 if its LR is pushed onto stack. */
8481 }
8483 /* Only used by the arm backend. */
8485 {}
8487 /* Return TRUE if Branch Target Identification Mechanism is enabled. */
8488 bool
8490 {
8492 }
8494 /* Check if INSN is a BTI J insn. */
8495 bool
8497 {
8503 }
8505 /* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction. */
8506 bool
8508 {
8514 {
8517 {
8520 {
8527 }
8529 }
8530 }
8532 }
8535 {
8537 }
8540 {
8542 }
8544 /* The caller is going to use ST1D or LD1D to save or restore an SVE
8545 register in mode MODE at BASE_RTX + OFFSET, where OFFSET is in
8546 the range [1, 16] * GET_MODE_SIZE (MODE). Prepare for this by:
8548 (1) updating BASE_RTX + OFFSET so that it is a legitimate ST1D
8549 or LD1D address
8551 (2) setting PRED to a valid predicate register for the ST1D or LD1D,
8552 if the variable isn't already nonnull
8554 (1) is needed when OFFSET is in the range [8, 16] * GET_MODE_SIZE (MODE).
8555 Handle this case using a temporary base register that is suitable for
8556 all offsets in that range. Use ANCHOR_REG as this base register if it
8557 is nonnull, otherwise create a new register and store it in ANCHOR_REG. */
8563 {
8565 {
8566 /* This is the maximum valid offset of the anchor from the base.
8567 Lower values would be valid too. */
8570 {
8574 }
8577 }
8579 {
8584 }
8585 }
8587 /* Add a REG_CFA_EXPRESSION note to INSN to say that register REG
8588 is saved at BASE + OFFSET. */
8590 static void
8593 {
8597 }
8599 /* Emit code to save the callee-saved registers in REGS. Skip any
8600 write-back candidates if SKIP_WB is true, otherwise consider only
8601 write-back candidates.
8603 The stack pointer is currently BYTES_BELOW_SP bytes above the bottom
8604 of the static frame. HARD_FP_VALID_P is true if the hard frame pointer
8605 has been set up. */
8607 static void
8611 {
8617 {
8626 };
8629 {
8631 poly_int64 offset;
8642 {
8645 }
8649 HOST_WIDE_INT const_offset;
8655 {
8659 else
8660 {
8662 {
8666 }
8668 }
8670 }
8673 stack_pointer_rtx,
8674 sp_offset));
8685 {
8691 rtx cfi_mem2
8694 stack_pointer_rtx,
8698 /* The first part of a frame-related parallel insn is always
8699 assumed to be relevant to the frame calculations;
8700 subsequent parts, are only frame-related if
8701 explicitly marked. */
8705 /* Add a REG_FRAME_RELATED_EXPR note since the unspec
8706 representation of stp cannot be understood directly by
8707 dwarf2cfi. */
8714 }
8715 else
8716 {
8718 {
8722 }
8725 else
8730 }
8734 /* Emit a fake instruction to indicate that the VG save slot has
8735 been initialized. */
8738 }
8739 }
8741 /* Emit code to restore the callee registers in REGS, ignoring pop candidates
8742 and any other registers that are handled separately. Write the appropriate
8743 REG_CFA_RESTORE notes into CFI_OPS.
8745 The stack pointer is currently BYTES_BELOW_SP bytes above the bottom
8746 of the static frame. */
8748 static void
8751 {
8753 poly_int64 offset;
8757 {
8765 /* The shadow call stack code restores LR separately. */
8770 };
8773 {
8794 {
8803 }
8808 else
8812 }
8813 }
8815 /* Return true if OFFSET is a signed 4-bit value multiplied by the size
8816 of MODE. */
8820 {
8821 HOST_WIDE_INT multiple;
8824 }
8826 /* Return true if OFFSET is a signed 6-bit value multiplied by the size
8827 of MODE. */
8831 {
8832 HOST_WIDE_INT multiple;
8835 }
8837 /* Return true if OFFSET is an unsigned 6-bit value multiplied by the size
8838 of MODE. */
8842 {
8843 HOST_WIDE_INT multiple;
8846 }
8848 /* Return true if OFFSET is a signed 7-bit value multiplied by the size
8849 of MODE. */
8851 bool
8853 {
8854 HOST_WIDE_INT multiple;
8857 }
8859 /* Return true if OFFSET is a signed 9-bit value. */
8861 bool
8863 poly_int64 offset)
8864 {
8865 HOST_WIDE_INT const_offset;
8868 }
8870 /* Return true if OFFSET is a signed 9-bit value multiplied by the size
8871 of MODE. */
8875 {
8876 HOST_WIDE_INT multiple;
8879 }
8881 /* Return true if OFFSET is an unsigned 12-bit value multiplied by the size
8882 of MODE. */
8886 {
8887 HOST_WIDE_INT multiple;
8890 }
8892 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
8894 static sbitmap
8896 {
8901 /* The registers we need saved to the frame. */
8905 {
8906 /* Disallow shrink wrapping for registers that will be clobbered
8907 by an SMSTART SM in the prologue. */
8912 /* Punt on saves and restores that use ST1D and LD1D. We could
8913 try to be smarter, but it would involve making sure that the
8914 spare predicate register itself is safe to use at the save
8915 and restore points. Also, when a frame pointer is being used,
8916 the slots are often out of reach of ST1D and LD1D anyway. */
8923 /* Get the offset relative to the register we'll use. */
8927 /* Check that we can access the stack slot of the register with one
8928 direct load with no adjustments needed. */
8933 }
8935 /* Don't mess with the hard frame pointer. */
8939 /* If the spare predicate register used by big-endian SVE code
8940 is call-preserved, it must be saved in the main prologue
8941 before any saves that use it. */
8947 /* If registers have been chosen to be stored/restored with
8948 writeback don't interfere with them to avoid having to output explicit
8949 stack adjustment instructions. */
8958 {
8963 }
8965 /* The VG save sequence needs a temporary GPR. Punt for now on trying
8966 to find one. */
8970 }
8972 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
8974 static sbitmap
8976 {
8984 /* Clobbered registers don't generate values in any meaningful sense,
8985 since nothing after the clobber can rely on their value. And we can't
8986 say that partially-clobbered registers are unconditionally killed,
8987 because whether they're killed or not depends on the mode of the
8988 value they're holding. Thus partially call-clobbered registers
8989 appear in neither the kill set nor the gen set.
8991 Check manually for any calls that clobber more of a register than the
8992 current function can. */
8993 function_abi_aggregator callee_abis;
9000 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
9008 {
9011 /* If there is a callee-save at an adjacent offset, add it too
9012 to increase the use of LDP/STP. */
9017 {
9023 }
9024 }
9027 }
9029 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
9030 Nothing to do for aarch64. */
9032 static void
9034 {
9035 }
9037 /* Return the next set bit in BMP from START onwards. Return the total number
9038 of bits in BMP if no set bit is found at or after START. */
9040 static unsigned int
9042 {
9053 }
9055 /* Do the work for aarch64_emit_prologue_components and
9056 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
9057 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
9058 for these components or the epilogue sequence. That is, it determines
9059 whether we should emit stores or loads and what kind of CFA notes to attach
9060 to the insns. Otherwise the logic for the two sequences is very
9061 similar. */
9063 static void
9065 {
9068 ? HARD_FRAME_POINTER_REGNUM
9076 {
9090 /* No more registers to handle after REGNO.
9091 Emit a single save/restore and exit. */
9093 {
9096 {
9100 else
9102 }
9104 }
9107 /* The next register is not of the same class or its offset is not
9108 mergeable with the current one into a pair. */
9115 {
9118 {
9122 else
9124 }
9128 }
9132 /* REGNO2 can be saved/restored in a pair with REGNO. */
9143 else
9147 {
9150 {
9155 }
9156 else
9157 {
9162 }
9163 }
9166 }
9167 }
9169 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
9171 static void
9173 {
9175 }
9177 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
9179 static void
9181 {
9183 }
9185 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
9187 static void
9189 {
9193 }
9195 /* On AArch64 we have an ABI defined safe buffer. This constant is used to
9196 determining the probe offset for alloca. */
9198 static HOST_WIDE_INT
9200 {
9202 }
9204 /* Emit a stack tie that acts as a scheduling barrier for all previous and
9205 subsequent memory accesses and that requires the stack pointer and REG
9206 to have their current values. REG can be stack_pointer_rtx if no
9207 other register's value needs to be fixed. */
9209 static void
9211 {
9213 }
9215 /* Allocate POLY_SIZE bytes of stack space using TEMP1 and TEMP2 as scratch
9216 registers. If POLY_SIZE is not large enough to require a probe this function
9217 will only adjust the stack. When allocating the stack space
9218 FRAME_RELATED_P is then used to indicate if the allocation is frame related.
9219 FINAL_ADJUSTMENT_P indicates whether we are allocating the area below
9220 the saved registers. If we are then we ensure that any allocation
9221 larger than the ABI defined buffer needs a probe so that the
9222 invariant of having a 1KB buffer is maintained.
9224 We emit barriers after each stack adjustment to prevent optimizations from
9225 breaking the invariant that we never drop the stack more than a page. This
9226 invariant is needed to make it easier to correctly handle asynchronous
9227 events, e.g. if we were to allow the stack to be dropped by more than a page
9228 and then have multiple probes up and we take a signal somewhere in between
9229 then the signal handler doesn't know the state of the stack and can make no
9230 assumptions about which pages have been probed.
9232 FORCE_ISA_MODE is AARCH64_ISA_MODE_SM_ON if any variable component of
9233 POLY_SIZE is measured relative to the SME vector length instead of the
9234 current prevailing vector length. It is 0 otherwise. */
9236 static void
9238 poly_int64 poly_size,
9239 aarch64_isa_mode force_isa_mode,
9242 {
9244 HOST_WIDE_INT guard_size
9249 HOST_WIDE_INT min_probe_threshold
9250 = (final_adjustment_p
9255 /* We should always have a positive probe threshold. */
9259 {
9265 {
9267 }
9271 {
9273 }
9274 }
9276 /* If SIZE is not large enough to require probing, just adjust the stack and
9277 exit. */
9280 {
9282 frame_related_p);
9284 }
9286 HOST_WIDE_INT size;
9287 /* Handle the SVE non-constant case first. */
9289 {
9291 {
9295 }
9297 /* First calculate the amount of bytes we're actually spilling. */
9305 {
9306 /* This is done to provide unwinding information for the stack
9307 adjustments we're about to do, however to prevent the optimizers
9308 from removing the R11 move and leaving the CFA note (which would be
9309 very wrong) we tie the old and new stack pointer together.
9310 The tie will expand to nothing but the optimizers will not touch
9311 the instruction. */
9316 /* We want the CFA independent of the stack pointer for the
9317 duration of the loop. */
9320 }
9329 /* Now reset the CFA register if needed. */
9331 {
9336 }
9339 }
9343 "Stack clash AArch64 prologue: " HOST_WIDE_INT_PRINT_DEC
9346 /* Round size to the nearest multiple of guard_size, and calculate the
9347 residual as the difference between the original size and the rounded
9348 size. */
9352 /* We can handle a small number of allocations/probes inline. Otherwise
9353 punt to a loop. */
9355 {
9357 {
9360 guard_used_by_caller));
9362 }
9364 }
9365 else
9366 {
9367 /* Compute the ending address. */
9372 /* For the initial allocation, we don't have a frame pointer
9373 set up, so we always need CFI notes. If we're doing the
9374 final allocation, then we may have a frame pointer, in which
9375 case it is the CFA, otherwise we need CFI notes.
9377 We can determine which allocation we are doing by looking at
9378 the value of FRAME_RELATED_P since the final allocations are not
9379 frame related. */
9381 {
9382 /* We want the CFA independent of the stack pointer for the
9383 duration of the loop. */
9387 }
9389 /* This allocates and probes the stack. Note that this re-uses some of
9390 the existing Ada stack protection code. However we are guaranteed not
9391 to enter the non loop or residual branches of that code.
9393 The non-loop part won't be entered because if our allocation amount
9394 doesn't require a loop, the case above would handle it.
9396 The residual amount won't be entered because TEMP1 is a mutliple of
9397 the allocation size. The residual will always be 0. As such, the only
9398 part we are actually using from that code is the loop setup. The
9399 actual probing is done in aarch64_output_probe_stack_range. */
9403 /* Now reset the CFA register if needed. */
9405 {
9409 }
9413 }
9415 /* Handle any residuals. Residuals of at least MIN_PROBE_THRESHOLD have to
9416 be probed. This maintains the requirement that each page is probed at
9417 least once. For initial probing we probe only if the allocation is
9418 more than GUARD_SIZE - buffer, and below the saved registers we probe
9419 if the amount is larger than buffer. GUARD_SIZE - buffer + buffer ==
9420 GUARD_SIZE. This works that for any allocation that is large enough to
9421 trigger a probe here, we'll have at least one, and if they're not large
9422 enough for this code to emit anything for them, The page would have been
9423 probed by the saving of FP/LR either by this function or any callees. If
9424 we don't have any callees then we won't have more stack adjustments and so
9425 are still safe. */
9427 {
9430 /* If we're doing final adjustments, and we've done any full page
9431 allocations then any residual needs to be probed. */
9437 {
9440 "Stack clash AArch64 prologue residuals: "
9441 HOST_WIDE_INT_PRINT_DEC " bytes, probing will be required."
9445 guard_used_by_caller));
9447 }
9448 }
9449 }
9451 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9453 void
9455 {
9457 {
9464 /* The only time ZA can't have live contents on entry is when
9465 the function explicitly treats it as a pure output. */
9470 /* Since ZT0 is call-clobbered, it is only live on input if
9471 it is explicitly shared, and is not a pure output. */
9476 }
9477 }
9479 /* Return 1 if the register is used by the epilogue. We need to say the
9480 return register is used, but only after epilogue generation is complete.
9481 Note that in the case of sibcalls, the values "used by the epilogue" are
9482 considered live at the start of the called function. */
9484 int
9486 {
9488 {
9491 }
9498 /* If the function shares SME state with its caller, ensure that that
9499 data is not in the lazy save buffer on exit. */
9507 }
9509 /* Implement TARGET_USE_LATE_PROLOGUE_EPILOGUE. */
9511 static bool
9513 {
9515 }
9517 /* The current function's frame has a save slot for the incoming state
9518 of SVCR. Return a legitimate memory for the slot, based on the hard
9519 frame pointer. */
9521 static rtx
9523 {
9528 /* hard fp -> bottom of frame. */
9530 /* bottom of frame -> save slot. */
9533 }
9535 /* The current function's frame has a save slot for the incoming state
9536 of SVCR. Load the slot into register REGNO and return the register. */
9538 static rtx
9540 {
9544 }
9546 /* Like the rtx version of aarch64_guard_switch_pstate_sm, but first
9547 load the incoming value of SVCR from its save slot into temporary
9548 register REGNO. */
9552 aarch64_isa_mode local_mode)
9553 {
9556 }
9558 /* AArch64 stack frames generated by this compiler look like:
9560 +-------------------------------+
9561 | |
9562 | incoming stack arguments |
9563 | |
9564 +-------------------------------+
9565 | | <-- incoming stack pointer (aligned)
9566 | callee-allocated save area |
9567 | for register varargs |
9568 | |
9569 +-------------------------------+
9570 | local variables (1) | <-- frame_pointer_rtx
9571 | |
9572 +-------------------------------+
9573 | padding (1) |
9574 +-------------------------------+
9575 | callee-saved registers |
9576 +-------------------------------+
9577 | LR' |
9578 +-------------------------------+
9579 | FP' |
9580 +-------------------------------+ <-- hard_frame_pointer_rtx (aligned)
9581 | SVE vector registers |
9582 +-------------------------------+
9583 | SVE predicate registers |
9584 +-------------------------------+
9585 | local variables (2) |
9586 +-------------------------------+
9587 | padding (2) |
9588 +-------------------------------+
9589 | dynamic allocation |
9590 +-------------------------------+
9591 | padding |
9592 +-------------------------------+
9593 | outgoing stack arguments | <-- arg_pointer
9594 | |
9595 +-------------------------------+
9596 | | <-- stack_pointer_rtx (aligned)
9598 The regions marked (1) and (2) are mutually exclusive. (2) is used
9599 when aarch64_save_regs_above_locals_p is true.
9601 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
9602 but leave frame_pointer_rtx and hard_frame_pointer_rtx
9603 unchanged.
9605 By default for stack-clash we assume the guard is at least 64KB, but this
9606 value is configurable to either 4KB or 64KB. We also force the guard size to
9607 be the same as the probing interval and both values are kept in sync.
9609 With those assumptions the callee can allocate up to 63KB (or 3KB depending
9610 on the guard size) of stack space without probing.
9612 When probing is needed, we emit a probe at the start of the prologue
9613 and every PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE bytes thereafter.
9615 We can also use register saves as probes. These are stored in
9616 sve_save_and_probe and hard_fp_save_and_probe.
9618 For outgoing arguments we probe if the size is larger than 1KB, such that
9619 the ABI specified buffer is maintained for the next callee.
9621 The following registers are reserved during frame layout and should not be
9622 used for any other purpose:
9624 - r11: Used by stack clash protection when SVE is enabled, and also
9625 as an anchor register when saving and restoring registers
9626 - r12(EP0) and r13(EP1): Used as temporaries for stack adjustment.
9627 - r14 and r15: Used for speculation tracking.
9628 - r16(IP0), r17(IP1): Used by indirect tailcalls.
9629 - r30(LR), r29(FP): Used by standard frame layout.
9631 These registers must be avoided in frame layout related code unless the
9632 explicit intention is to interact with one of the features listed above. */
9634 /* Generate the prologue instructions for entry into a function.
9635 Establish the stack frame by decreasing the stack pointer with a
9636 properly calculated size and, if necessary, create a frame record
9637 filled with the values of LR and previous frame pointer. The
9638 current FP is also set up if it is in use. */
9640 void
9642 {
9660 {
9661 /* Fold the SVE allocation into the initial allocation.
9662 We don't do this in aarch64_layout_arg to avoid pessimizing
9663 the epilogue code. */
9666 }
9668 /* Sign return address for functions. */
9670 {
9672 {
9681 }
9684 }
9686 /* Push return address to shadow call stack. */
9694 {
9696 {
9700 (frame_size
9702 }
9705 }
9710 /* In theory we should never have both an initial adjustment
9711 and a callee save adjustment. Verify that is the case since the
9712 code below does not handle it for -fstack-clash-protection. */
9715 /* Will only probe if the initial adjustment is larger than the guard
9716 less the amount of the guard reserved for use by the caller's
9717 outgoing args. */
9724 /* The offset of the current SP from the bottom of the static frame. */
9728 {
9729 /* The offset of the frame chain record (if any) from the current SP. */
9738 else
9743 frame_pointer_needed);
9745 {
9746 /* Variable-sized frames need to describe the save slot
9747 address using DW_CFA_expression rather than DW_CFA_offset.
9748 This means that, without taking further action, the
9749 locations of the registers that we've already saved would
9750 remain based on the stack pointer even after we redefine
9751 the CFA based on the frame pointer. We therefore need new
9752 DW_CFA_expressions to re-express the save slots with addresses
9753 based on the frame pointer. */
9757 /* Add an explicit CFA definition if this was previously
9758 implicit. */
9760 {
9764 }
9766 /* Change the save slot expressions for the registers that
9767 we've already saved. */
9772 }
9774 }
9777 emit_frame_chain);
9779 {
9782 emit_frame_chain);
9783 }
9785 {
9788 /* The VG save isn't shrink-wrapped and so serves as
9789 a probe of the initial allocation. */
9792 sve_callee_adjust,
9793 force_isa_mode,
9796 }
9798 emit_frame_chain);
9800 emit_frame_chain);
9802 /* We may need to probe the final adjustment if it is larger than the guard
9803 that is assumed by the called. */
9806 force_isa_mode,
9811 /* Save the incoming value of PSTATE.SM, if required. Code further
9812 down does this for locally-streaming functions. */
9815 {
9819 {
9823 }
9824 else
9825 {
9829 {
9832 }
9834 {
9837 }
9844 }
9845 }
9847 /* Enable PSTATE.SM, if required. */
9849 {
9852 {
9853 /* The current function is streaming-compatible. Save the
9854 original state of PSTATE.SM. */
9859 AARCH64_ISA_MODE);
9860 }
9861 aarch64_sme_mode_switch_regs args_switch;
9864 {
9867 }
9873 }
9874 }
9876 /* Return TRUE if we can use a simple_return insn.
9878 This function checks whether the callee saved stack is empty, which
9879 means no restore actions are need. The pro_and_epilogue will use
9880 this to check whether shrink-wrapping opt is feasible. */
9882 bool
9884 {
9892 }
9894 /* Generate the epilogue instructions for returning from a function.
9895 This is almost exactly the reverse of the prolog sequence, except
9896 that we need to insert barriers to avoid scheduling loads that read
9897 from a deallocated stack, and we optimize the unwind records by
9898 emitting them all together if possible. */
9899 void
9901 {
9912 /* A stack clash protection prologue may not have left EP0_REGNUM or
9913 EP1_REGNUM in a usable state. The same is true for allocations
9914 with an SVE component, since we then need both temporary registers
9915 for each allocation. For stack clash we are in a usable state if
9916 the adjustment is less than GUARD_SIZE - GUARD_USED_BY_CALLER. */
9917 HOST_WIDE_INT guard_size
9924 /* We can re-use the registers when:
9926 (a) the deallocation amount is the same as the corresponding
9927 allocation amount (which is false if we combine the initial
9928 and SVE callee save allocations in the prologue); and
9930 (b) the allocation amount doesn't need a probe (which is false
9931 if the amount is guard_size - guard_used_by_caller or greater).
9933 In such situations the register should remain live with the correct
9934 value. */
9937 && (!flag_stack_clash_protection
9942 /* We need to add memory barrier to prevent read from deallocated stack. */
9943 bool need_barrier_p
9947 /* Reset PSTATE.SM, if required. */
9949 {
9953 AARCH64_ISA_MODE);
9954 aarch64_sme_mode_switch_regs return_switch;
9965 }
9967 /* Emit a barrier to prevent loads from a deallocated stack. */
9971 {
9974 }
9976 /* Restore the stack pointer from the frame pointer if it may not
9977 be the same as the stack pointer. */
9982 /* If writeback is used when restoring callee-saves, the CFA
9983 is restored on the instruction doing the writeback. */
9985 hard_frame_pointer_rtx,
9989 else
9990 /* The case where we need to re-use the register here is very rare, so
9991 avoid the complicated condition and just always emit a move if the
9992 immediate doesn't fit. */
9995 /* Restore the vector registers before the predicate registers,
9996 so that we can use P4 as a temporary for big-endian SVE frames. */
10003 /* When shadow call stack is enabled, the scs_pop in the epilogue will
10004 restore x30, we don't need to restore x30 again in the traditional
10005 way. */
10015 /* If we have no register restore information, the CFA must have been
10016 defined in terms of the stack pointer since the end of the prologue. */
10020 {
10021 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
10027 }
10029 /* Liveness of EP0_REGNUM can not be trusted across function calls either, so
10030 add restriction on emit_move optimization to leaf functions. */
10036 {
10037 /* Emit delayed restores and reset the CFA to be SP. */
10042 }
10044 /* Pop return address from shadow call stack. */
10046 {
10053 }
10055 /* Stack adjustment for exception handler. */
10057 {
10058 /* If the EH_RETURN_TAKEN_RTX flag is set then we need
10059 to unwind the stack and jump to the handler, otherwise
10060 skip this eh_return logic and continue with normal
10061 return after the label. We have already reset the CFA
10062 to be SP; letting the CFA move during this adjustment
10063 is just as correct as retaining the CFA from the body
10064 of the function. Therefore, do nothing special. */
10067 label);
10072 EH_RETURN_STACKADJ_RTX));
10076 }
10078 /* We prefer to emit the combined return/authenticate instruction RETAA,
10079 however there are three cases in which we must instead emit an explicit
10080 authentication instruction.
10082 1) Sibcalls don't return in a normal way, so if we're about to call one
10083 we must authenticate.
10085 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
10086 generating code for !TARGET_ARMV8_3 we can't use it and must
10087 explicitly authenticate.
10088 */
10091 {
10093 {
10102 }
10105 }
10110 }
10112 /* Output code to add DELTA to the first argument, and then jump
10113 to FUNCTION. Used for C++ multiple inheritance. */
10114 static void
10116 HOST_WIDE_INT delta,
10117 HOST_WIDE_INT vcall_offset,
10118 tree function)
10119 {
10120 /* The this pointer is always in x0. Note that this differs from
10121 Arm where the this pointer maybe bumped to r1 if r0 is required
10122 to return a pointer to an aggregate. On AArch64 a result value
10123 pointer will be in x8. */
10142 else
10143 {
10148 {
10152 else
10155 }
10159 else
10166 else
10167 {
10169 Pmode);
10171 }
10175 else
10181 }
10183 /* Generate a tail call to the target function. */
10185 {
10188 }
10206 /* Stop pretending to be a post-reload pass. */
10208 }
10210 static bool
10212 {
10217 {
10221 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
10222 TLS offsets, not real symbol references. */
10225 }
10227 }
10230 static bool
10232 {
10236 /* There's no way to calculate VL-based values using relocations. */
10238 HOST_WIDE_INT factor;
10244 poly_int64 offset;
10247 {
10248 /* We checked for POLY_INT_CST offsets above. */
10252 else
10253 /* Avoid generating a 64-bit relocation in ILP32; leave
10254 to aarch64_expand_mov_immediate to handle it properly. */
10256 }
10259 }
10261 /* Implement TARGET_CASE_VALUES_THRESHOLD.
10262 The expansion for a table switch is quite expensive due to the number
10263 of instructions, the table lookup and hard to predict indirect jump.
10264 When optimizing for speed, and -O3 enabled, use the per-core tuning if
10265 set, otherwise use tables for >= 11 cases as a tradeoff between size and
10266 performance. When optimizing for size, use 8 for smallest codesize. */
10268 static unsigned int
10270 {
10271 /* Use the specified limit for the number of cases before using jump
10272 tables at higher optimization levels. */
10276 else
10278 }
10280 /* Return true if register REGNO is a valid index register.
10281 STRICT_P is true if REG_OK_STRICT is in effect. */
10283 bool
10285 {
10287 {
10295 }
10297 }
10299 /* Return true if register REGNO is a valid base register for mode MODE.
10300 STRICT_P is true if REG_OK_STRICT is in effect. */
10302 bool
10304 {
10306 {
10314 }
10316 /* The fake registers will be eliminated to either the stack or
10317 hard frame pointer, both of which are usually valid base registers.
10318 Reload deals with the cases where the eliminated form isn't valid. */
10323 }
10325 /* Return true if X is a valid base register for mode MODE.
10326 STRICT_P is true if REG_OK_STRICT is in effect. */
10328 static bool
10330 {
10337 }
10339 /* Return true if address offset is a valid index. If it is, fill in INFO
10340 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
10342 static bool
10345 {
10347 rtx index;
10350 /* (reg:P) */
10353 {
10357 }
10358 /* (sign_extend:DI (reg:SI)) */
10363 {
10368 }
10369 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
10376 {
10381 }
10382 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
10389 {
10394 }
10395 /* (and:DI (mult:DI (reg:DI) (const_int scale))
10396 (const_int 0xffffffff<<shift)) */
10403 {
10407 /* Avoid undefined code dealing with shift being -1. */
10411 }
10412 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
10413 (const_int 0xffffffff<<shift)) */
10420 {
10426 }
10427 /* (mult:P (reg:P) (const_int scale)) */
10432 {
10436 }
10437 /* (ashift:P (reg:P) (const_int shift)) */
10442 {
10446 }
10447 else
10456 {
10460 }
10461 else
10462 {
10467 }
10471 {
10476 }
10479 }
10481 /* Return true if MODE is one of the modes for which we
10482 support LDP/STP operations. */
10484 static bool
10486 {
10493 }
10495 /* Return true if REGNO is a virtual pointer register, or an eliminable
10496 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
10497 include stack_pointer or hard_frame_pointer. */
10498 static bool
10500 {
10505 }
10507 /* Return true if X is a valid address of type TYPE for machine mode MODE.
10508 If it is, fill in INFO appropriately. STRICT_P is true if
10509 REG_OK_STRICT is in effect. */
10511 bool
10514 aarch64_addr_query_type type)
10515 {
10518 poly_int64 offset;
10520 HOST_WIDE_INT const_size;
10522 /* Whether a vector mode is partial doesn't affect address legitimacy.
10523 Partial vectors like VNx8QImode allow the same indexed addressing
10524 mode and MUL VL addressing mode as full vectors like VNx16QImode;
10525 in both cases, MUL VL counts multiples of GET_MODE_SIZE. */
10529 /* On BE, we use load/store pair for all large int mode load/stores.
10530 TI/TF/TDmode may also use a load/store pair. */
10539 /* If we are dealing with ADDR_QUERY_LDP_STP_N that means the incoming mode
10540 corresponds to the actual size of the memory being loaded/stored and the
10541 mode of the corresponding addressing mode is half of that. */
10543 {
10550 else
10553 /* This isn't really an Advanced SIMD struct mode, but a mode
10554 used to represent the complete mem in a load/store pair. */
10556 }
10565 /* For SVE, only accept [Rn], [Rn, #offset, MUL VL] and [Rn, Rm, LSL #shift].
10566 The latter is not valid for SVE predicates, and that's rejected through
10567 allow_reg_index_p above. */
10572 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
10573 REG addressing. */
10575 && TARGET_SIMD
10576 && !BYTES_BIG_ENDIAN
10584 {
10601 {
10608 }
10613 {
10619 /* TImode, TFmode and TDmode values are allowed in both pairs of X
10620 registers and individual Q registers. The available
10621 address modes are:
10622 X,X: 7-bit signed scaled offset
10623 Q: 9-bit signed offset
10624 We conservatively require an offset representable in either mode.
10625 When performing the check for pairs of X registers i.e. LDP/STP
10626 pass down DImode since that is the natural size of the LDP/STP
10627 instruction memory accesses. */
10637 /* A 7bit offset check because OImode will emit a ldp/stp
10638 instruction (only !TARGET_SIMD or big endian will get here).
10639 For ldp/stp instructions, the offset is scaled for the size of a
10640 single element of the pair. */
10648 /* Three 9/12 bit offsets checks because CImode will emit three
10649 ldr/str instructions (only !TARGET_SIMD or big endian will
10650 get here). */
10666 /* Two 7bit offsets checks because XImode will emit two ldp/stp
10667 instructions (only big endian will get here). */
10679 /* Make "m" use the LD1 offset range for SVE data modes, so
10680 that pre-RTL optimizers like ivopts will work to that
10681 instead of the wider LDR/STR range. */
10688 {
10689 poly_int64 end_offset = (offset
10696 end_offset)));
10697 }
10703 {
10704 poly_int64 end_offset = (offset
10709 }
10716 else
10719 }
10722 {
10723 /* Look for base + (scaled/extended) index register. */
10726 {
10729 }
10732 {
10735 }
10736 }
10757 {
10761 /* TImode, TFmode and TDmode values are allowed in both pairs of X
10762 registers and individual Q registers. The available
10763 address modes are:
10764 X,X: 7-bit signed scaled offset
10765 Q: 9-bit signed offset
10766 We conservatively require an offset representable in either mode.
10767 */
10777 else
10779 }
10785 /* load literal: pc-relative constant pool entry. Only supported
10786 for SI mode or larger. */
10792 {
10793 poly_int64 offset;
10799 }
10808 {
10809 poly_int64 offset;
10810 HOST_WIDE_INT const_offset;
10816 {
10817 /* The symbol and offset must be aligned to the access size. */
10823 {
10827 }
10833 else
10842 }
10843 }
10848 }
10849 }
10851 /* Return true if the address X is valid for a PRFM instruction.
10852 STRICT_P is true if we should do strict checking with
10853 aarch64_classify_address. */
10855 bool
10857 {
10860 /* PRFM accepts the same addresses as DImode... */
10865 /* ... except writeback forms. */
10867 }
10869 bool
10871 {
10872 poly_int64 offset;
10875 }
10877 /* Classify the base of symbolic expression X. */
10879 enum aarch64_symbol_type
10881 {
10882 rtx offset;
10886 }
10889 /* Return TRUE if X is a legitimate address for accessing memory in
10890 mode MODE. */
10891 static bool
10894 {
10898 }
10900 /* Return TRUE if X is a legitimate address of type TYPE for accessing
10901 memory in mode MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
10902 bool
10904 aarch64_addr_query_type type)
10905 {
10909 }
10911 /* Implement TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT. */
10913 static bool
10915 poly_int64 orig_offset,
10916 machine_mode mode)
10917 {
10918 HOST_WIDE_INT size;
10920 {
10923 /* A general SVE offset is A * VQ + B. Remove the A component from
10924 coefficient 0 in order to get the constant B. */
10927 /* Split an out-of-range address displacement into a base and
10928 offset. Use 4KB range for 1- and 2-byte accesses and a 16KB
10929 range otherwise to increase opportunities for sharing the base
10930 address of different sizes. Unaligned accesses use the signed
10931 9-bit range, TImode/TFmode/TDmode use the intersection of signed
10932 scaled 7-bit and signed 9-bit offset. */
10937 else
10943 /* Split the offset into second_offset and the rest. */
10947 }
10948 else
10949 {
10950 /* Get the mode we should use as the basis of the range. For structure
10951 modes this is the mode of one vector. */
10953 machine_mode step_mode
10956 /* Get the "mul vl" multiplier we'd like to use. */
10960 /* LDR supports a 9-bit range, but the move patterns for
10961 structure modes require all vectors to be in range of the
10962 same base. The simplest way of accomodating that while still
10963 promoting reuse of anchor points between different modes is
10964 to use an 8-bit range unconditionally. */
10966 else
10967 /* Predicates are only handled singly, so we might as well use
10968 the full range. */
10973 /* Convert the "mul vl" multiplier into a byte offset. */
10978 /* Split the offset into second_offset and the rest. */
10982 }
10983 }
10985 /* Return the binary representation of floating point constant VALUE in INTVAL.
10986 If the value cannot be converted, return false without setting INTVAL.
10987 The conversion is done in the given MODE. */
10988 bool
10990 {
10992 /* We make a general exception for 0. */
10994 {
10997 }
10999 scalar_float_mode mode;
11003 /* Only support up to DF mode. */
11015 {
11019 }
11020 else
11025 }
11027 /* Return TRUE if rtx X is an immediate constant that can be moved using a
11028 single MOV(+MOVK) followed by an FMOV. */
11029 bool
11031 {
11036 /* Determine whether it's cheaper to write float constants as
11037 mov/movk pairs over ldr/adrp pairs. */
11043 {
11048 }
11051 }
11053 /* Return TRUE if rtx X is immediate constant 0.0 (but not in Decimal
11054 Floating Point). */
11055 bool
11057 {
11058 /* 0.0 in Decimal Floating Point cannot be represented by #0 or
11059 zr as our callers expect, so no need to check the actual
11060 value if X is of Decimal Floating Point type. */
11067 }
11069 /* Return true if X is any kind of constant zero rtx. */
11071 bool
11073 {
11076 }
11078 /* Return TRUE if rtx X is immediate constant that fits in a single
11079 MOVI immediate operation. */
11080 bool
11082 {
11086 machine_mode vmode;
11087 scalar_int_mode imode;
11092 {
11096 /* We make a general exception for 0. */
11101 }
11105 else
11108 /* use a 64 bit mode for everything except for DI/DF/DD mode, where we use
11109 a 128 bit vector mode. */
11116 }
11119 /* Return the fixed registers used for condition codes. */
11121 static bool
11123 {
11127 }
11129 /* Return a fresh memory reference to the current function's TPIDR2 block,
11130 creating a block if necessary. */
11132 static rtx
11134 {
11136 /* The TPIDR2 block is 16 bytes in size and must be aligned to a 128-bit
11137 boundary. */
11140 }
11142 /* Return a fresh register that points to the current function's
11143 TPIDR2 block, creating a block if necessary. */
11145 static rtx
11147 {
11150 }
11152 /* Emit instructions to allocate a ZA lazy save buffer and initialize the
11153 current function's TPIDR2 block. */
11155 static void
11157 {
11160 /* The ZA save buffer is SVL.B*SVL.B bytes in size. */
11170 /* The first word of the block points to the save buffer and the second
11171 word is the number of ZA slices to save. */
11178 }
11180 /* Restore the contents of ZA from the lazy save buffer, given that
11181 register TPIDR2_BLOCK points to the current function's TPIDR2 block.
11182 PSTATE.ZA is known to be 0 and TPIDR2_EL0 is known to be null. */
11184 void
11186 {
11191 }
11193 /* Return the ZT0 save buffer, creating one if necessary. */
11195 static rtx
11197 {
11201 }
11203 /* Save ZT0 to the current function's save buffer. */
11205 static void
11207 {
11211 }
11213 /* Restore ZT0 from the current function's save buffer. FROM_LAZY_SAVE_P
11214 is true if the load is happening after a call to a private-ZA function,
11215 false if it can be treated as a normal load. */
11217 static void
11219 {
11225 }
11227 /* Implement TARGET_START_CALL_ARGS. */
11229 static void
11231 {
11235 {
11239 " option %<-march%>, or by using the %<target%>"
11241 }
11255 /* If this is a call to a private ZA function, emit a marker to
11256 indicate where any necessary set-up code could be inserted.
11257 The code itself is inserted by the mode-switching pass. */
11261 /* If this is a call to a shared-ZA function that doesn't share ZT0,
11262 save and restore ZT0 around the call. */
11267 }
11269 /* This function is used by the call expanders of the machine description.
11270 RESULT is the register in which the result is returned. It's NULL for
11271 "call" and "sibcall".
11272 MEM is the location of the function call.
11273 COOKIE is either:
11274 - a const_int that gives the argument to the call's UNSPEC_CALLEE_ABI.
11275 - a PARALLEL that contains such a const_int as its first element.
11276 The second element is a PARALLEL that lists all the argument
11277 registers that need to be saved and restored around a change
11278 in PSTATE.SM, or const0_rtx if no such switch is needed.
11279 The third and fourth elements are const_ints that contain the
11280 sharing flags for ZA and ZT0 respectively.
11281 SIBCALL indicates whether this function call is normal call or sibling call.
11282 It will generate different pattern accordingly. */
11284 void
11286 {
11288 rtvec vec;
11289 machine_mode mode;
11296 {
11301 }
11309 {
11314 }
11319 #if TARGET_PECOFF
11323 #endif
11328 /* Decide if we should generate indirect calls by loading the
11329 address of the callee into a register before performing
11330 the branch-and-link. */
11337 /* Accumulate the return values, including state that is shared via
11338 attributes. */
11341 {
11345 else
11347 }
11351 /* When calling private-ZA functions from functions with ZA state,
11352 we want to know whether the call committed a lazy save. */
11358 /* Create the new return value, if necessary. */
11360 {
11363 else
11364 {
11371 }
11372 }
11381 else
11385 UNSPEC_CALLEE_ABI);
11392 /* Check whether the call requires a change to PSTATE.SM. We can't
11393 emit the instructions to change PSTATE.SM yet, since they involve
11394 a change in vector length and a change in instruction set, which
11395 cannot be represented in RTL.
11397 For now, just record which registers will be clobbered and used
11398 by the changes to PSTATE.SM. */
11400 {
11401 aarch64_sme_mode_switch_regs args_switch;
11403 {
11406 {
11409 }
11410 }
11412 aarch64_sme_mode_switch_regs result_switch;
11430 /* Ensure that the VG save slot has been initialized. Also emit
11431 an instruction to model the effect of the temporary clobber
11432 of VG, so that the prologue/epilogue pass sees the need to
11433 save the old value. */
11439 }
11441 /* Add any ZA-related information.
11443 ZA_REGNUM represents the current function's ZA state, rather than
11444 the contents of the ZA register itself. We ensure that the function's
11445 ZA state is preserved by private-ZA call sequences, so the call itself
11446 does not use or clobber ZA_REGNUM. The same thing applies to
11447 ZT0_REGNUM. */
11449 {
11450 /* The callee requires ZA to be active if the callee is shared-ZA,
11451 otherwise it requires ZA to be dormant or off. The state of ZA is
11452 captured by a combination of SME_STATE_REGNUM, TPIDR2_SETUP_REGNUM,
11453 and ZA_SAVED_REGNUM. */
11461 /* Keep the aarch64_start/end_private_za_call markers live. */
11466 /* If the callee is a shared-ZA function, record whether it uses the
11467 current value of ZA and ZT0. */
11475 }
11476 }
11478 /* Implement TARGET_END_CALL_ARGS. */
11480 static void
11482 {
11485 /* If this is a call to a private ZA function, emit a marker to
11486 indicate where any necessary restoration code could be inserted.
11487 The code itself is inserted by the mode-switching pass. */
11491 /* If this is a call to a shared-ZA function that doesn't share ZT0,
11492 save and restore ZT0 around the call. */
11497 }
11499 /* Emit call insn with PAT and do aarch64-specific handling. */
11501 rtx_call_insn *
11503 {
11510 }
11512 machine_mode
11514 {
11518 /* All floating point compares return CCFP if it is an equality
11519 comparison, and CCFPE otherwise. */
11521 {
11523 {
11544 }
11545 }
11547 /* Equality comparisons of short modes against zero can be performed
11548 using the TST instruction with the appropriate bitmask. */
11554 /* Similarly, comparisons of zero_extends from shorter modes can
11555 be performed using an ANDS with an immediate mask. */
11562 /* Zero extracts support equality comparisons. */
11570 /* ANDS/BICS/TST support equality and all signed comparisons. */
11578 /* ADDS/SUBS correctly set N and Z flags. */
11585 /* A compare with a shifted operand. Because of canonicalization,
11586 the comparison will have to be swapped when we emit the assembly
11587 code. */
11595 /* Similarly for a negated operand, but we can only do this for
11596 equalities. */
11603 /* A test for unsigned overflow from an addition. */
11610 /* A test for unsigned overflow from an add with carry. */
11620 /* A test for signed overflow. */
11627 /* For everything else, return CCmode. */
11629 }
11631 static int
11634 int
11636 {
11643 }
11645 static int
11647 {
11649 {
11653 {
11667 }
11672 {
11684 }
11689 {
11701 }
11706 {
11716 }
11721 {
11729 }
11734 {
11740 }
11745 {
11749 }
11754 {
11758 }
11763 {
11767 }
11772 {
11776 }
11781 }
11784 }
11786 /* Return true if X is a CONST_INT, CONST_WIDE_INT or a constant vector
11787 duplicate of such constants. If so, store in RET_WI the wide_int
11788 representation of the constant paired with the inner mode of the vector mode
11789 or MODE for scalar X constants. If MODE is not provided then TImode is
11790 used. */
11792 static bool
11795 {
11799 scalar_mode smode
11803 }
11805 /* Return true if X is a scalar or a constant vector of integer
11806 immediates that represent the rounding constant used in the fixed-point
11807 arithmetic instructions.
11808 The accepted form of the constant is (1 << (C - 1)) where C is in the range
11809 [1, MODE_WIDTH/2]. */
11811 bool
11813 {
11814 wide_int rnd_cst;
11821 }
11823 /* Return true if RND is a constant vector of integer rounding constants
11824 corresponding to a constant vector of shifts, SHIFT.
11825 The relationship should be RND == (1 << (SHIFT - 1)). */
11827 bool
11829 {
11836 }
11838 bool
11840 HOST_WIDE_INT minval,
11841 HOST_WIDE_INT maxval)
11842 {
11843 rtx elt;
11847 }
11849 /* Some constants can't be made using normal mov instructions in Advanced SIMD
11850 but we can still create them in various ways. If the constant in VAL can be
11851 created using alternate methods then if possible then return true and
11852 additionally set TARGET to the rtx for the sequence if TARGET is not NULL.
11853 Otherwise return false if sequence is not possible. */
11855 bool
11857 {
11858 wide_int wval;
11863 /* For Advanced SIMD we can create an integer with only the top bit set
11864 using fneg (0.0f). */
11866 && !TARGET_SVE
11869 {
11873 /* Use the same base type as aarch64_gen_shareable_zero. */
11879 }
11882 }
11884 /* Check if the value in VAL with mode MODE can be created using special
11885 instruction sequences. */
11888 {
11890 }
11892 bool
11894 {
11896 }
11898 /* Return true if VEC is a constant in which every element is in the range
11899 [MINVAL, MAXVAL]. The elements do not need to have the same value. */
11901 static bool
11903 HOST_WIDE_INT minval,
11904 HOST_WIDE_INT maxval)
11905 {
11917 {
11922 }
11924 }
11926 /* N Z C V. */
11927 #define AARCH64_CC_V 1
11928 #define AARCH64_CC_C (1 << 1)
11929 #define AARCH64_CC_Z (1 << 2)
11930 #define AARCH64_CC_N (1 << 3)
11932 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
11934 {
11951 };
11953 /* Print floating-point vector immediate operand X to F, negating it
11954 first if NEGATE is true. Return true on success, false if it isn't
11955 a constant we can handle. */
11957 static bool
11959 {
11960 rtx elt;
11969 /* Handle the SVE single-bit immediates specially, since they have a
11970 fixed form in the assembly syntax. */
11979 else
11980 {
11986 }
11989 }
11991 /* Return the equivalent letter for size. */
11992 static char
11994 {
11996 {
12002 }
12003 }
12005 /* Print operand X to file F in a target specific manner according to CODE.
12006 The acceptable formatting commands given by CODE are:
12007 'c': An integer or symbol address without a preceding #
12008 sign.
12009 'C': Take the duplicated element in a vector constant
12010 and print it in hex.
12011 'D': Take the duplicated element in a vector constant
12012 and print it as an unsigned integer, in decimal.
12013 'e': Print the sign/zero-extend size as a character 8->b,
12014 16->h, 32->w. Can also be used for masks:
12015 0xff->b, 0xffff->h, 0xffffffff->w.
12016 'I': If the operand is a duplicated vector constant,
12017 replace it with the duplicated scalar. If the
12018 operand is then a floating-point constant, replace
12019 it with the integer bit representation. Print the
12020 transformed constant as a signed decimal number.
12021 'p': Prints N such that 2^N == X (X must be power of 2 and
12022 const int).
12023 'P': Print the number of non-zero bits in X (a const_int).
12024 'H': Print the higher numbered register of a pair (TImode)
12025 of regs.
12026 'm': Print a condition (eq, ne, etc).
12027 'M': Same as 'm', but invert condition.
12028 'N': Take the duplicated element in a vector constant
12029 and print the negative of it in decimal.
12030 'b/h/s/d/q': Print a scalar FP/SIMD register name.
12031 'Z': Same for SVE registers. ('z' was already taken.)
12032 Note that it is not necessary to use %Z for operands
12033 that have SVE modes. The convention is to use %Z
12034 only for non-SVE (or potentially non-SVE) modes.
12035 'S/T/U/V': Print a FP/SIMD register name for a register list.
12036 The register printed is the FP/SIMD register name
12037 of X + 0/1/2/3 for S/T/U/V.
12038 'R': Print a scalar Integer/FP/SIMD register name + 1.
12039 'X': Print bottom 16 bits of integer constant in hex.
12040 'w/x': Print a general register name or the zero register
12041 (32-bit or 64-bit).
12042 '0': Print a normal operand, if it's a general register,
12043 then we assume DImode.
12044 'k': Print NZCV for conditional compare instructions.
12045 'K': Print a predicate register as pn<N> rather than p<N>
12046 'A': Output address constant representing the first
12047 argument of X, specifying a relocation offset
12048 if appropriate.
12049 'L': Output constant address specified by X
12050 with a relocation offset if appropriate.
12051 'G': Prints address of X, specifying a PC relative
12052 relocation mode if appropriate.
12053 'y': Output address of LDP or STP - this is used for
12054 some LDP/STPs which don't use a PARALLEL in their
12055 pattern (so the mode needs to be adjusted).
12056 'z': Output address of a typical LDP or STP. */
12058 static void
12060 {
12061 rtx elt;
12063 {
12067 else
12068 {
12069 poly_int64 offset;
12073 else
12075 }
12079 {
12082 {
12085 }
12094 else
12095 {
12098 }
12099 }
12103 {
12107 {
12110 }
12113 }
12118 {
12121 }
12128 {
12131 }
12134 {
12137 }
12143 {
12147 else
12148 {
12151 }
12153 }
12157 {
12159 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
12161 {
12165 }
12168 {
12171 }
12179 else
12181 }
12186 {
12189 }
12195 ;
12196 else
12197 {
12200 }
12211 {
12212 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
12214 }
12223 {
12226 }
12229 else
12243 else
12245 code);
12250 {
12253 }
12258 {
12259 /* Print a replicated constant in hex. */
12261 {
12264 }
12267 }
12271 {
12272 /* Print a replicated constant in decimal, treating it as
12273 unsigned. */
12275 {
12278 }
12281 }
12287 {
12290 }
12293 {
12296 }
12299 {
12302 }
12304 /* Fall through */
12308 {
12311 }
12314 {
12316 {
12319 }
12322 {
12325 else
12326 {
12327 char suffix
12332 }
12333 }
12334 else
12353 {
12356 }
12357 /* fall through */
12361 {
12364 }
12370 ;
12371 else
12372 {
12375 }
12379 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
12380 be getting CONST_DOUBLEs holding integers. */
12383 {
12386 }
12388 {
12389 #define buf_size 20
12397 #undef buf_size
12398 }
12404 }
12412 {
12439 }
12445 {
12480 }
12486 {
12492 }
12497 {
12498 HOST_WIDE_INT cond_code;
12501 {
12504 }
12509 }
12514 {
12517 }
12523 {
12531 {
12534 }
12538 ? ADDR_QUERY_LDP_STP_N
12541 }
12547 }
12548 }
12550 /* Print address 'x' of a memory access with mode 'mode'.
12551 'op' is the context required by aarch64_classify_address. It can either be
12552 MEM for a normal memory access or PARALLEL for LDP/STP. */
12553 static bool
12555 aarch64_addr_query_type type)
12556 {
12560 /* Check all addresses are Pmode - including ILP32. */
12564 {
12567 }
12574 {
12577 {
12580 }
12584 {
12585 HOST_WIDE_INT vnum
12591 }
12604 else
12613 else
12622 else
12628 /* Writeback is only supported for fixed-width modes. */
12631 {
12654 }
12666 }
12669 }
12671 /* Print address 'x' of a memory access with mode 'mode'. */
12672 static void
12674 {
12677 }
12679 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
12681 static bool
12683 {
12685 {
12688 }
12690 }
12692 bool
12694 {
12701 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
12702 referencing instruction, but they are constant offsets, not
12703 symbols. */
12709 {
12711 {
12717 }
12720 }
12723 }
12725 /* Implement REGNO_REG_CLASS. */
12727 enum reg_class
12729 {
12766 }
12768 /* OFFSET is an address offset for mode MODE, which has SIZE bytes.
12769 If OFFSET is out of range, return an offset of an anchor point
12770 that is in range. Return 0 otherwise. */
12772 static HOST_WIDE_INT
12774 machine_mode mode)
12775 {
12776 /* Does it look like we'll need a 16-byte load/store-pair operation? */
12780 /* For offsets that aren't a multiple of the access size, the limit is
12781 -256...255. */
12783 {
12784 /* BLKmode typically uses LDP of X-registers. */
12788 }
12790 /* Small negative offsets are supported. */
12797 /* Use 12-bit offset by access size. */
12799 }
12801 static rtx
12803 {
12804 #if TARGET_PECOFF
12808 #endif
12810 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
12811 where mask is selected by alignment and size of the offset.
12812 We try to pick as large a range for the offset as possible to
12813 maximize the chance of a CSE. However, for aligned addresses
12814 we limit the range to 4k so that structures with different sized
12815 elements are likely to use the same base. We need to be careful
12816 not to split a CONST for some forms of address expression, otherwise
12817 it will generate sub-optimal code. */
12819 /* First split X + CONST (base, offset) into (base + X) + offset. */
12821 {
12822 poly_int64 offset;
12828 }
12831 {
12837 {
12841 /* Force any scaling into a temp for CSE. */
12845 /* Let the pointer register be in op0. */
12849 /* If the pointer is virtual or frame related, then we know that
12850 virtual register instantiation or register elimination is going
12851 to apply a second constant. We want the two constants folded
12852 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
12854 {
12858 }
12860 /* Otherwise, in order to encourage CSE (and thence loop strength
12861 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
12865 }
12867 HOST_WIDE_INT size;
12869 {
12871 mode);
12873 {
12877 }
12878 }
12879 }
12882 }
12884 static reg_class_t
12886 reg_class_t rclass,
12887 machine_mode mode,
12889 {
12890 /* Use aarch64_sve_reload_mem for SVE memory reloads that cannot use
12891 LDR and STR. See the comment at the head of aarch64-sve.md for
12892 more details about the big-endian handling. */
12900 {
12903 }
12905 /* If we have to disable direct literal pool loads and stores because the
12906 function is too big, then we need a scratch register. */
12911 {
12914 }
12916 /* Without the TARGET_SIMD or TARGET_SVE instructions we cannot move a
12917 Q register to a Q register directly. We need a scratch. */
12924 && !TARGET_SIMD
12927 {
12930 }
12932 /* A TFmode, TImode or TDmode memory access should be handled via an FP_REGS
12933 because AArch64 has richer addressing modes for LDR/STR instructions
12934 than LDP/STP instructions. */
12945 }
12947 /* Implement TARGET_SECONDARY_MEMORY_NEEDED. */
12949 static bool
12951 reg_class_t class2)
12952 {
12956 {
12957 /* We can't do a 128-bit FPR-to-FPR move without TARGET_SIMD,
12958 so we can't easily split a move involving tuples of 128-bit
12959 vectors. Force the copy through memory instead.
12961 (Tuples of 64-bit vectors are fine.) */
12965 }
12967 }
12969 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
12971 static bool
12973 {
12974 /* If the function needs to record the incoming value of PSTATE.SM,
12975 make sure that the slot is accessible from the frame pointer. */
12977 }
12979 static bool
12981 {
12984 /* If we need a frame pointer, ARG_POINTER_REGNUM and FRAME_POINTER_REGNUM
12985 can only eliminate to HARD_FRAME_POINTER_REGNUM. */
12989 }
12991 poly_int64
12993 {
12997 {
13003 }
13006 {
13009 }
13012 }
13015 /* Get return address without mangling. */
13017 rtx
13019 {
13021 /* Note: aarch64_return_address_signing_enabled only
13022 works after cfun->machine->frame.laid_out is set,
13023 so here we don't know if the return address will
13024 be signed or not. */
13029 }
13032 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
13033 previous frame. */
13035 rtx
13037 {
13041 }
13043 static void
13045 {
13046 /* Even if the current function doesn't have branch protection, some
13047 later function might, so since this template is only generated once
13048 we have to add a BTI just in case. */
13052 {
13055 }
13056 else
13057 {
13060 }
13063 /* We always emit a speculation barrier.
13064 This is because the same trampoline template is used for every nested
13065 function. Since nested functions are not particularly common or
13066 performant we don't worry too much about the extra instructions to copy
13067 around.
13068 This is not yet a problem, since we have not yet implemented function
13069 specific attributes to choose between hardening against straight line
13070 speculation or not, but such function specific attributes are likely to
13071 happen in the future. */
13076 }
13078 static void
13080 {
13084 /* Don't need to copy the trailing D-words, we fill those in below. */
13085 /* We create our own memory address in Pmode so that `emit_block_move` can
13086 use parts of the backend which expect Pmode addresses. */
13100 /* XXX We should really define a "clear_cache" pattern and use
13101 gen_clear_cache(). */
13105 a_tramp,
13106 TRAMPOLINE_SIZE));
13107 }
13109 static unsigned char
13111 {
13112 /* ??? Logically we should only need to provide a value when
13113 HARD_REGNO_MODE_OK says that at least one register in REGCLASS
13114 can hold MODE, but at the moment we need to handle all modes.
13115 Just ignore any runtime parts for registers that can't store them. */
13119 {
13159 }
13161 }
13163 static reg_class_t
13165 {
13170 {
13176 }
13178 /* Register eliminiation can result in a request for
13179 SP+constant->FP_REGS. We cannot support such operations which
13180 use SP as source and an FP_REG as destination, so reject out
13181 right now. */
13183 {
13186 /* Look through a possible SUBREG introduced by ILP32. */
13192 POINTER_REGS));
13194 }
13197 }
13199 void
13201 {
13203 }
13205 static void
13207 {
13210 else
13211 {
13213 /* While priority is known to be in range [0, 65535], so 18 bytes
13214 would be enough, the compiler might not know that. To avoid
13215 -Wformat-truncation false positive, use a larger size. */
13222 }
13223 }
13225 static void
13227 {
13230 else
13231 {
13233 /* While priority is known to be in range [0, 65535], so 18 bytes
13234 would be enough, the compiler might not know that. To avoid
13235 -Wformat-truncation false positive, use a larger size. */
13242 }
13243 }
13247 {
13253 {
13254 {
13257 },
13258 {
13261 },
13262 {
13265 },
13266 /* We assume that DImode is only generated when not optimizing and
13267 that we don't really need 64-bit address offsets. That would
13268 imply an object file with 8GB of code in a single function! */
13269 {
13272 }
13273 };
13282 /* Need to implement table size reduction, by chaning the code below. */
13291 operands);
13294 }
13296 /* Return the asm string for an SME ZERO instruction whose 8-bit mask
13297 operand is MASK. */
13300 {
13313 };
13314 /* The last entry in the list has the form "za7.d }", but that's the
13315 same length as "za7.d, ". */
13318 {
13325 {
13327 {
13332 }
13335 }
13337 {
13341 }
13342 }
13344 }
13346 /* Return size in bits of an arithmetic operand which is shifted/scaled and
13347 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
13348 operator. */
13350 int
13352 {
13354 {
13357 {
13361 }
13362 }
13364 }
13366 /* Constant pools are per function only when PC relative
13367 literal loads are true or we are in the large memory
13368 model. */
13372 {
13375 }
13377 static bool
13379 {
13380 /* We can't use blocks for constants when we're using a per-function
13381 constant pool. */
13383 }
13385 /* Select appropriate section for constants depending
13386 on where we place literal pools. */
13390 rtx x,
13392 {
13397 }
13399 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
13400 void
13402 HOST_WIDE_INT offset)
13403 {
13404 /* When using per-function literal pools, we must ensure that any code
13405 section is aligned to the minimal instruction length, lest we get
13406 errors from the assembler re "unaligned instructions". */
13409 }
13411 /* Costs. */
13413 /* Helper function for rtx cost calculation. Strip a shift expression
13414 from X. Returns the inner operand if successful, or the original
13415 expression on failure. */
13416 static rtx
13418 {
13421 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
13422 we can convert both to ROR during final output. */
13437 }
13439 /* Helper function for rtx cost calculation. Strip an extend
13440 expression from X. Returns the inner operand if successful, or the
13441 original expression on failure. We deal with a number of possible
13442 canonicalization variations here. If STRIP_SHIFT is true, then
13443 we can strip off a shift also. */
13444 static rtx
13446 {
13447 scalar_int_mode mode;
13461 /* Now handle extended register, as this may also have an optional
13462 left shift by 1..4. */
13477 }
13479 /* Helper function for rtx cost calculation. Strip extension as well as any
13480 inner VEC_SELECT high-half from X. Returns the inner vector operand if
13481 successful, or the original expression on failure. */
13482 static rtx
13484 {
13486 {
13492 }
13494 }
13496 /* Helper function for rtx cost calculation. Strip VEC_DUPLICATE as well as
13497 any subsequent extend and VEC_SELECT from X. Returns the inner scalar
13498 operand if successful, or the original expression on failure. */
13499 static rtx
13501 {
13504 {
13511 }
13513 }
13515 /* Return true iff CODE is a shift supported in combination
13516 with arithmetic instructions. */
13518 static bool
13520 {
13522 }
13525 /* Return true iff X is a cheap shift without a sign extend. */
13527 static bool
13529 {
13555 }
13557 /* Helper function for rtx cost calculation. Calculate the cost of
13558 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
13559 Return the calculated cost of the expression, recursing manually in to
13560 operands where needed. */
13562 static int
13564 {
13578 {
13581 {
13582 /* The select-operand-high-half versions of the instruction have the
13583 same cost as the three vector version - don't add the costs of the
13584 extension or selection into the costs of the multiply. */
13587 /* The by-element versions of the instruction have the same costs as
13588 the normal 3-vector version. We make an assumption that the input
13589 to the VEC_DUPLICATE is already on the FP & SIMD side. This means
13590 costing of a MUL by element pre RA is a bit optimistic. */
13593 }
13597 {
13600 /* This is to catch the SSRA costing currently flowing here. */
13601 else
13603 }
13605 }
13607 /* Integer multiply/fma. */
13609 {
13610 /* The multiply will be canonicalized as a shift, cost it as such. */
13614 {
13618 {
13620 {
13621 /* If the shift is considered cheap,
13622 then don't add any cost. */
13624 ;
13626 /* ARITH + shift-by-register. */
13629 /* ARITH + extended register. We don't have a cost field
13630 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
13632 else
13633 /* ARITH + shift-by-immediate. */
13635 }
13636 else
13637 /* LSL (immediate). */
13640 }
13641 /* Strip extends as we will have costed them in the case above. */
13648 }
13650 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
13651 compound and let the below cases handle it. After all, MNEG is a
13652 special-case alias of MSUB. */
13654 {
13657 }
13659 /* Integer multiplies or FMAs have zero/sign extending variants. */
13664 {
13669 {
13671 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
13673 else
13674 /* MUL/SMULL/UMULL. */
13676 }
13679 }
13681 /* This is either an integer multiply or a MADD. In both cases
13682 we want to recurse and cost the operands. */
13687 {
13689 /* MADD/MSUB. */
13691 else
13692 /* MUL. */
13694 }
13697 }
13698 else
13699 {
13701 {
13702 /* Floating-point FMA/FMUL can also support negations of the
13703 operands, unless the rounding mode is upward or downward in
13704 which case FNMUL is different than FMUL with operand negation. */
13708 {
13713 }
13716 /* FMADD/FNMADD/FNMSUB/FMSUB. */
13718 else
13719 /* FMUL/FNMUL. */
13721 }
13726 }
13727 }
13729 static int
13731 machine_mode mode,
13732 addr_space_t as ATTRIBUTE_UNUSED,
13734 {
13742 {
13744 {
13745 /* This is a CONST or SYMBOL ref which will be split
13746 in a different way depending on the code model in use.
13747 Cost it through the generic infrastructure. */
13749 /* Divide through by the cost of one instruction to
13750 bring it to the same units as the address costs. */
13752 /* The cost is then the cost of preparing the address,
13753 followed by an immediate (possibly 0) offset. */
13755 }
13756 else
13757 {
13758 /* This is most likely a jump table from a case
13759 statement. */
13761 }
13762 }
13765 {
13776 {
13782 else
13784 }
13785 else
13804 }
13808 {
13809 /* For the sake of calculating the cost of the shifted register
13810 component, we can treat same sized modes in the same way. */
13817 else
13818 /* We can't tell, or this is a 128-bit vector. */
13820 }
13823 }
13825 /* Return the cost of a branch. If SPEED_P is true then the compiler is
13826 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
13827 to be taken. */
13829 int
13831 {
13832 /* When optimizing for speed, use the cost of unpredictable branches. */
13838 else
13840 }
13842 /* Return true if X is a zero or sign extract
13843 usable in an ADD or SUB (extended register) instruction. */
13844 static bool
13846 {
13847 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
13848 No shift. */
13854 }
13856 static bool
13858 {
13860 {
13872 }
13873 }
13875 /* Return true iff X is an rtx that will match an extr instruction
13876 i.e. as described in the *extr<mode>5_insn family of patterns.
13877 OP0 and OP1 will be set to the operands of the shifts involved
13878 on success and will be NULL_RTX otherwise. */
13880 static bool
13882 {
13884 scalar_int_mode mode;
13899 {
13900 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
13912 {
13916 }
13917 }
13920 }
13922 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
13923 storing it in *COST. Result is true if the total cost of the operation
13924 has now been calculated. */
13925 static bool
13927 {
13928 rtx inner;
13929 rtx comparator;
13935 {
13939 }
13940 else
13941 {
13945 }
13948 {
13949 /* Conditional branch. */
13952 else
13953 {
13955 {
13957 {
13958 /* TBZ/TBNZ/CBZ/CBNZ. */
13960 /* TBZ/TBNZ. */
13963 else
13964 /* CBZ/CBNZ. */
13968 }
13971 {
13972 /* SUB and SUBS. */
13977 }
13978 }
13980 {
13981 /* TBZ/TBNZ. */
13984 }
13985 }
13986 }
13988 {
13989 /* CCMP. */
13991 {
13992 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
13996 {
14001 else
14003 }
14005 }
14007 /* It's a conditional operation based on the status flags,
14008 so it must be some flavor of CSEL. */
14010 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
14016 {
14017 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
14020 }
14022 {
14025 /* CSINV/NEG with zero extend + const 0 (*csinv3_uxtw_insn3). */
14027 }
14029 {
14030 /* Use CSINV or CSINC. */
14033 }
14035 {
14036 /* Use CSINV or CSINC. */
14039 }
14044 }
14046 /* We don't know what this is, cost all operands. */
14048 }
14050 /* Check whether X is a bitfield operation of the form shift + extend that
14051 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
14052 operand to which the bitfield operation is applied. Otherwise return
14053 NULL_RTX. */
14055 static rtx
14057 {
14071 {
14089 }
14092 }
14094 /* Return true if the mask and a shift amount from an RTX of the form
14095 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
14096 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
14098 bool
14100 rtx shft_amnt)
14101 {
14108 }
14110 /* Return true if the masks and a shift amount from an RTX of the form
14111 ((x & MASK1) | ((y << SHIFT_AMNT) & MASK2)) are valid to combine into
14112 a BFI instruction of mode MODE. See *arch64_bfi patterns. */
14114 bool
14119 {
14122 /* Verify that there is no overlap in what bits are set in the two masks. */
14126 /* Verify that mask2 is not all zeros or ones. */
14130 /* The shift amount should always be less than the mode size. */
14133 /* Verify that the mask being shifted is contiguous and would be in the
14134 least significant bits after shifting by shft_amnt. */
14137 }
14139 /* Return true if X is an RTX representing an operation in the ABD family
14140 of instructions. */
14142 static bool
14144 {
14162 }
14164 /* Calculate the cost of calculating X, storing it in *COST. Result
14165 is true if the total cost of the operation has now been calculated. */
14166 static bool
14169 {
14174 scalar_int_mode int_mode;
14176 /* By default, assume that everything has equivalent cost to the
14177 cheapest instruction. Any additional costs are applied as a delta
14178 above this default. */
14182 {
14184 /* The cost depends entirely on the operands to SET. */
14190 {
14193 {
14207 }
14216 /* Fall through. */
14218 /* The cost is one per vector-register copied. */
14220 {
14223 }
14224 /* const0_rtx is in general free, but we will use an
14225 instruction to set a register to 0. */
14227 {
14228 /* The cost is 1 per register copied. */
14231 }
14232 else
14233 /* Cost is just the cost of the RHS of the set. */
14239 /* Bit-field insertion. Strip any redundant widening of
14240 the RHS to meet the width of the target. */
14251 {
14252 /* MOV immediate is assumed to always be cheap. */
14254 }
14255 else
14256 {
14257 /* BFM. */
14261 }
14266 /* We can't make sense of this, assume default cost. */
14269 }
14273 /* If an instruction can incorporate a constant within the
14274 instruction, the instruction's expression avoids calling
14275 rtx_cost() on the constant. If rtx_cost() is called on a
14276 constant, then it is usually because the constant must be
14277 moved into a register by one or more instructions.
14279 The exception is constant 0, which can be expressed
14280 as XZR/WZR and is therefore free. The exception to this is
14281 if we have (set (reg) (const0_rtx)) in which case we must cost
14282 the move. However, we can catch that when we cost the SET, so
14283 we don't need to consider that here. */
14286 else
14287 {
14288 /* To an approximation, building any other constant is
14289 proportionally expensive to the number of instructions
14290 required to build that constant. This is true whether we
14291 are compiling for SPEED or otherwise. */
14296 }
14301 /* First determine number of instructions to do the move
14302 as an integer constant. */
14306 {
14317 }
14320 {
14321 /* mov[df,sf]_aarch64. */
14323 /* FMOV (scalar immediate). */
14326 {
14327 /* This will be a load from memory. */
14330 else
14332 }
14333 else
14334 /* Otherwise this is +0.0. We get this using MOVI d0, #0
14335 or MOV v0.s[0], wzr - neither of which are modeled by the
14336 cost tables. Just use the default cost. */
14337 {
14338 }
14339 }
14345 {
14346 /* For loads we want the base cost of a load, plus an
14347 approximation for the additional cost of the addressing
14348 mode. */
14362 }
14370 {
14371 /* Many vector comparison operations are represented as NEG
14372 of a comparison. */
14374 {
14378 /* FACGE/FACGT. */
14382 {
14385 }
14391 }
14393 {
14394 /* FNEG. */
14396 }
14398 }
14401 {
14404 {
14405 /* CSETM. */
14408 }
14410 /* Cost this as SUB wzr, X. */
14414 }
14417 {
14418 /* Support (neg(fma...)) as a single instruction only if
14419 sign of zeros is unimportant. This matches the decision
14420 making in aarch64.md. */
14422 {
14423 /* FNMADD. */
14426 }
14428 {
14429 /* FNMUL. */
14432 }
14434 /* FNEG. */
14437 }
14444 {
14447 else
14449 }
14455 {
14459 }
14461 {
14465 }
14466 else
14467 {
14471 }
14480 {
14484 }
14487 {
14488 /* TODO: A write to the CC flags possibly costs extra, this
14489 needs encoding in the cost tables. */
14492 /* ANDS. */
14494 {
14497 }
14500 {
14501 /* ADDS (and CMN alias). */
14504 }
14507 {
14508 /* SUBS. */
14511 }
14516 {
14517 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
14518 Handle it here directly rather than going to cost_logic
14519 since we know the immediate generated for the TST is valid
14520 so we can avoid creating an intermediate rtx for it only
14521 for costing purposes. */
14528 }
14531 {
14532 /* CMN. */
14539 }
14541 /* CMP.
14543 Compare can freely swap the order of operands, and
14544 canonicalization puts the more complex operation first.
14545 But the integer MINUS logic expects the shift/extend
14546 operation in op1. */
14549 {
14552 }
14554 }
14557 {
14558 /* FCMP. */
14563 {
14565 /* FCMP supports constant 0.0 for no extra cost. */
14567 }
14569 }
14572 {
14573 /* Vector compare. */
14578 {
14579 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
14580 cost. */
14582 }
14584 }
14588 {
14592 cost_minus:
14594 {
14597 {
14598 /* Recognise the SABD and UABD operation here.
14599 Recursion from the PLUS case will catch the accumulating
14600 forms. */
14602 {
14606 }
14607 /* SUBL2 and SUBW2.
14608 The select-operand-high-half versions of the sub instruction
14609 have the same cost as the regular three vector version -
14610 don't add the costs of the select into the costs of the sub.
14611 */
14614 }
14615 }
14619 /* Detect valid immediates. */
14625 {
14627 /* SUB(S) (immediate). */
14630 }
14632 /* Look for SUB (extended register). */
14635 {
14643 }
14647 /* Cost this as an FMA-alike operation. */
14651 {
14654 speed);
14656 }
14661 {
14663 {
14664 /* Vector SUB. */
14666 }
14668 {
14669 /* SUB(S). */
14671 }
14673 {
14674 /* FSUB. */
14676 }
14677 }
14679 }
14682 {
14683 rtx new_op0;
14688 cost_plus:
14690 {
14691 /* ADDL2 and ADDW2. */
14694 {
14695 /* The select-operand-high-half versions of the add instruction
14696 have the same cost as the regular three vector version -
14697 don't add the costs of the select into the costs of the add.
14698 */
14701 }
14702 }
14706 {
14707 /* CSINC. */
14711 }
14716 {
14720 {
14721 /* ADD (immediate). */
14724 /* Some tunings prefer to not use the VL-based scalar ops.
14725 Increase the cost of the poly immediate to prevent their
14726 formation. */
14731 }
14733 }
14736 {
14737 /* 24-bit add in 2 instructions or 12-bit shifted add. */
14743 }
14747 /* Look for ADD (extended register). */
14750 {
14758 }
14760 /* Strip any extend, leave shifts behind as we will
14761 cost them through mult_cost. */
14766 {
14768 speed);
14770 }
14775 {
14777 {
14778 /* Vector ADD. */
14780 }
14782 {
14783 /* ADD. */
14785 }
14787 {
14788 /* FADD. */
14790 }
14791 }
14793 }
14800 {
14803 else
14805 }
14810 {
14814 {
14817 else
14819 }
14821 }
14824 {
14831 }
14832 /* Fall through. */
14835 cost_logic:
14840 {
14844 }
14852 {
14853 /* This is a UBFM/SBFM. */
14858 }
14861 {
14863 {
14864 /* We have a mask + shift version of a UBFIZ
14865 i.e. the *andim_ashift<mode>_bfiz pattern. */
14869 {
14876 }
14878 {
14879 /* We possibly get the immediate for free, this is not
14880 modelled. */
14887 }
14888 }
14889 else
14890 {
14893 /* Handle ORN, EON, or BIC. */
14899 /* If we had a shift on op0 then this is a logical-shift-
14900 by-register/immediate operation. Otherwise, this is just
14901 a logical operation. */
14903 {
14905 {
14906 /* Shift by immediate. */
14909 else
14911 }
14912 else
14914 }
14916 /* In both cases we want to cost both operands. */
14923 }
14924 }
14932 {
14933 /* Vector NOT. */
14936 }
14938 /* MVN-shifted-reg. */
14940 {
14947 }
14948 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
14949 Handle the second form here taking care that 'a' in the above can
14950 be a shift. */
14952 {
14961 {
14964 else
14966 }
14969 }
14970 /* MVN. */
14979 /* If a value is written in SI mode, then zero extended to DI
14980 mode, the operation will in general be free as a write to
14981 a 'w' register implicitly zeroes the upper bits of an 'x'
14982 register. However, if this is
14984 (set (reg) (zero_extend (reg)))
14986 we must cost the explicit register move. */
14989 {
14992 /* If OP_COST is non-zero, then the cost of the zero extend
14993 is effectively the cost of the inner operation. Otherwise
14994 we have a MOV instruction and we take the cost from the MOV
14995 itself. This is true independently of whether we are
14996 optimizing for space or time. */
15001 }
15003 {
15004 /* All loads can zero extend to any size for free. */
15007 }
15011 {
15016 }
15019 {
15021 {
15022 /* UMOV. */
15024 }
15025 else
15026 {
15027 /* We generate an AND instead of UXTB/UXTH. */
15029 }
15030 }
15035 {
15036 /* LDRSH. */
15038 {
15045 }
15047 }
15051 {
15056 }
15059 {
15062 else
15064 }
15076 {
15078 {
15080 {
15081 /* Vector shift (immediate). */
15083 }
15084 else
15085 {
15086 /* LSL (immediate), ASR (immediate), UBMF, UBFIZ and friends.
15087 These are all aliases. */
15089 }
15090 }
15092 /* We can incorporate zero/sign extend for free. */
15099 }
15100 else
15101 {
15103 {
15105 /* Vector shift (register). */
15107 }
15108 else
15109 {
15111 /* LSLV, ASRV. */
15114 /* The register shift amount may be in a shorter mode expressed
15115 as a lowpart SUBREG. For costing purposes just look inside. */
15122 {
15124 /* We already demanded XEXP (op1, 0) to be REG_P, so
15125 don't recurse into it. */
15127 }
15128 }
15130 }
15136 {
15137 /* LDR. */
15140 }
15143 {
15144 /* ADRP, followed by ADD. */
15148 }
15151 {
15152 /* ADR. */
15155 }
15158 {
15159 /* One extra load instruction, after accessing the GOT. */
15163 }
15168 /* ADRP/ADD (immediate). */
15175 /* UBFX/SBFX. */
15177 {
15180 else
15182 }
15184 /* We can trust that the immediates used will be correct (there
15185 are no by-register forms), so we need only cost op0. */
15191 /* aarch64_rtx_mult_cost always handles recursion to its
15192 operands. */
15196 /* We can expand signed mod by power of 2 using a NEGS, two parallel
15197 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
15198 an unconditional negate. This case should only ever be reached through
15199 the set_smod_pow2_cheap check in expmed.cc. */
15203 {
15204 /* We expand to 4 instructions. Reset the baseline. */
15212 }
15214 /* Fall-through. */
15217 {
15218 /* Slighly prefer UMOD over SMOD. */
15225 }
15232 {
15236 /* There is no integer SQRT, so only DIV and UDIV can get
15237 here. */
15239 /* Slighly prefer UDIV over SDIV. */
15241 else
15243 }
15269 {
15272 else
15274 }
15276 /* FMSUB, FNMADD, and FNMSUB are free. */
15283 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
15284 and the by-element operand as operand 0. */
15288 /* Catch vector-by-element operations. The by-element operand can
15289 either be (vec_duplicate (vec_select (x))) or just
15290 (vec_select (x)), depending on whether we are multiplying by
15291 a vector or a scalar.
15293 Canonicalization is not very good in these cases, FMA4 will put the
15294 by-element operand as operand 0, FNMA4 will have it as operand 1. */
15305 /* If the remaining parameters are not registers,
15306 get the cost to put them into registers. */
15320 {
15322 {
15323 /*Vector truncate. */
15325 }
15326 else
15328 }
15333 {
15335 {
15336 /*Vector conversion. */
15338 }
15339 else
15341 }
15347 /* Strip the rounding part. They will all be implemented
15348 by the fcvt* family of instructions anyway. */
15350 {
15359 }
15362 {
15365 else
15367 }
15369 /* We can combine fmul by a power of 2 followed by a fcvt into a single
15370 fixed-point fcvt. */
15375 {
15379 }
15386 {
15387 /* ABS (vector). */
15390 }
15392 {
15395 /* FABD, which is analogous to FADD. */
15397 {
15404 }
15405 /* Simple FABS is analogous to FNEG. */
15408 }
15409 else
15410 {
15411 /* Integer ABS will either be split to
15412 two arithmetic instructions, or will be an ABS
15413 (scalar), which we don't model. */
15417 }
15423 {
15426 else
15427 {
15428 /* FMAXNM/FMINNM/FMAX/FMIN.
15429 TODO: This may not be accurate for all implementations, but
15430 we do not model this in the cost tables. */
15432 }
15433 }
15437 /* The floating point round to integer frint* instructions. */
15439 {
15444 }
15449 /* Decompose <su>muldi3_highpart. */
15451 mode == DImode
15452 /* (lshiftrt:TI */
15455 /* (mult:TI */
15457 /* (ANY_EXTEND:TI (reg:DI))
15458 (ANY_EXTEND:TI (reg:DI))) */
15465 /* (const_int 64) */
15468 {
15469 /* UMULH/SMULH. */
15477 }
15480 {
15481 /* Load using MOVI/MVNI. */
15487 }
15489 /* depending on the operation, either DUP or INS.
15490 For now, keep default costing. */
15493 /* Load using a DUP. */
15497 {
15501 /* cost subreg of 0 as free, otherwise as DUP */
15504 ;
15507 else
15510 }
15513 }
15521 }
15523 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
15524 calculated for X. This cost is stored in *COST. Returns true
15525 if the total cost of X was calculated. */
15526 static bool
15529 {
15534 {
15539 }
15542 }
15544 static int
15547 {
15553 /* Trest any subset of POINTER_REGS as though it were GENERAL_REGS. */
15560 /* Make RDFFR very expensive. In particular, if we know that the FFR
15561 contains a PTRUE (e.g. after a SETFFR), we must never use RDFFR
15562 as a way of obtaining a PTRUE. */
15568 /* Moving between GPR and stack cost is the same as GP2GP. */
15573 /* To/From the stack register, we move via the gprs. */
15581 {
15582 /* 128-bit operations on general registers require 2 instructions. */
15590 /* When AdvSIMD instructions are disabled it is not possible to move
15591 a 128-bit value directly between Q registers. This is handled in
15592 secondary reload. A general register is used as a scratch to move
15593 the upper DI value and the lower DI value is moved directly,
15594 hence the cost is the sum of three moves. */
15599 }
15609 {
15610 /* Needs a round-trip through memory, which can use LDP/STP for pairs.
15611 The cost must be greater than 2 units to indicate that direct
15612 moves aren't possible. */
15616 }
15619 }
15621 /* Implements TARGET_MEMORY_MOVE_COST. */
15622 static int
15624 {
15643 }
15645 /* Implement TARGET_INSN_COST. We have the opportunity to do something
15646 much more productive here, such as using insn attributes to cost things.
15647 But we don't, not yet.
15649 The main point of this current definition is to make calling insn_cost
15650 on one instruction equivalent to calling seq_cost on a sequence that
15651 contains only that instruction. The default definition would instead
15652 only look at SET_SRCs, ignoring SET_DESTs.
15654 This ensures that, for example, storing a 128-bit zero vector is more
15655 expensive than storing a 128-bit vector register. A move of zero
15656 into a 128-bit vector register followed by multiple stores of that
15657 register is then cheaper than multiple stores of zero (which would
15658 use STP of XZR). This in turn allows STP Qs to be formed. */
15659 static int
15661 {
15665 }
15667 /* Implement TARGET_INIT_BUILTINS. */
15668 static void
15670 {
15673 #ifdef SUBTARGET_INIT_BUILTINS
15674 SUBTARGET_INIT_BUILTINS;
15675 #endif
15676 }
15678 /* Implement TARGET_FOLD_BUILTIN. */
15679 static tree
15681 {
15686 {
15692 }
15694 }
15696 /* Implement TARGET_GIMPLE_FOLD_BUILTIN. */
15697 static bool
15699 {
15706 {
15714 }
15721 }
15723 /* Implement TARGET_EXPAND_BUILTIN. */
15724 static rtx
15726 {
15731 {
15737 }
15739 }
15741 /* Implement TARGET_BUILTIN_DECL. */
15742 static tree
15744 {
15747 {
15753 }
15755 }
15757 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
15758 to optimize 1.0/sqrt. */
15760 static bool
15762 {
15764 && flag_unsafe_math_optimizations
15768 }
15770 /* Function to decide when to use the approximate reciprocal square root
15771 builtin. */
15773 static tree
15775 {
15783 {
15789 }
15791 }
15793 /* Emit code to perform the floating-point operation:
15795 DST = SRC1 * SRC2
15797 where all three operands are already known to be registers.
15798 If the operation is an SVE one, PTRUE is a suitable all-true
15799 predicate. */
15801 static void
15803 {
15808 else
15810 }
15812 /* Emit instruction sequence to compute either the approximate square root
15813 or its approximate reciprocal, depending on the flag RECP, and return
15814 whether the sequence was emitted or not. */
15816 bool
15818 {
15822 {
15825 }
15828 {
15835 || flag_trapping_math
15836 || !flag_unsafe_math_optimizations
15839 }
15840 else
15841 /* Caller assumes we cannot fail. */
15852 {
15853 /* When calculating the approximate square root, compare the
15854 argument with 0.0 and create a mask. */
15857 {
15862 }
15863 else
15864 {
15869 }
15870 }
15872 /* Estimate the approximate reciprocal square root. */
15876 /* Iterate over the series twice for SF and thrice for DF. */
15879 /* Optionally iterate over the series once less for faster performance
15880 while sacrificing the accuracy. */
15883 iterations--;
15885 /* Iterate over the series to calculate the approximate reciprocal square
15886 root. */
15889 {
15897 }
15900 {
15902 /* Multiply nonzero source values by the corresponding intermediate
15903 result elements, so that the final calculation is the approximate
15904 square root rather than its reciprocal. Select a zero result for
15905 zero source values, to avoid the Inf * 0 -> NaN that we'd get
15906 otherwise. */
15909 else
15910 {
15911 /* Qualify the approximate reciprocal square root when the
15912 argument is 0.0 by squashing the intermediary result to 0.0. */
15918 /* Calculate the approximate square root. */
15920 }
15921 }
15923 /* Finalize the approximation. */
15927 }
15929 /* Emit the instruction sequence to compute the approximation for the division
15930 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
15932 bool
15934 {
15945 || flag_trapping_math
15946 || !flag_unsafe_math_optimizations
15958 /* Estimate the approximate reciprocal. */
15962 /* Iterate over the series twice for SF and thrice for DF. */
15965 /* Optionally iterate over the series less for faster performance,
15966 while sacrificing the accuracy. The default is 2 for DF and 1 for SF. */
15969 ? aarch64_double_recp_precision
15972 /* Iterate over the series to calculate the approximate reciprocal. */
15975 {
15980 }
15983 {
15984 /* As the approximate reciprocal of DEN is already calculated, only
15985 calculate the approximate division when NUM is not 1.0. */
15988 }
15990 /* Finalize the approximation. */
15993 }
15995 /* Return the number of instructions that can be issued per cycle. */
15996 static int
15998 {
16000 }
16002 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
16003 static int
16005 {
16017 }
16019 static int
16021 {
16025 }
16028 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
16029 autopref_multipass_dfa_lookahead_guard from haifa-sched.cc. It only
16030 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
16032 static int
16035 {
16037 }
16040 /* Vectorizer cost model target hooks. */
16042 /* If a vld1 from address ADDR should be recorded in vector_load_decls,
16043 return the decl that should be recorded. Return null otherwise. */
16044 tree
16046 {
16053 }
16055 /* Return true if STMT_INFO accesses a decl that is known to be the
16056 argument to a vld1 in the same function. */
16057 static bool
16059 {
16067 }
16069 /* Information about how the CPU would issue the scalar, Advanced SIMD
16070 or SVE version of a vector loop, using the scheme defined by the
16071 aarch64_base_vec_issue_info hierarchy of structures. */
16072 class aarch64_vec_op_count
16073 {
16093 /* The number of individual "general" operations. See the comments
16094 in aarch64_base_vec_issue_info for details. */
16097 /* The number of load and store operations, under the same scheme
16098 as above. */
16102 /* The minimum number of cycles needed to execute all loop-carried
16103 operations, which in the vector code become associated with
16104 reductions. */
16107 /* The number of individual predicate operations. See the comments
16108 in aarch64_sve_vec_issue_info for details. */
16112 /* The issue information for the core. */
16115 /* - If M_VEC_FLAGS is zero then this structure describes scalar code
16116 - If M_VEC_FLAGS & VEC_ADVSIMD is nonzero then this structure describes
16117 Advanced SIMD code.
16118 - If M_VEC_FLAGS & VEC_ANY_SVE is nonzero then this structure describes
16119 SVE code. */
16122 /* Assume that, when the code is executing on the core described
16123 by M_ISSUE_INFO, one iteration of the loop will handle M_VF_FACTOR
16124 times more data than the vectorizer anticipates.
16126 This is only ever different from 1 for SVE. It allows us to consider
16127 what would happen on a 256-bit SVE target even when the -mtune
16128 parameters say that the “likely” SVE length is 128 bits. */
16130 };
16138 {
16139 }
16141 /* Return the base issue information (i.e. the parts that make sense
16142 for both scalar and vector code). Return null if we have no issue
16143 information. */
16146 {
16150 }
16152 /* If the structure describes vector code and we have associated issue
16153 information, return that issue information, otherwise return null. */
16156 {
16162 }
16164 /* If the structure describes SVE code and we have associated issue
16165 information, return that issue information, otherwise return null. */
16168 {
16172 }
16174 /* Estimate the minimum number of cycles per iteration needed to rename
16175 the instructions.
16177 ??? For now this is done inline rather than via cost tables, since it
16178 isn't clear how it should be parameterized for the general case. */
16179 fractional_cost
16181 {
16185 /* + 1 for an addition. We've already counted a general op for each
16186 store, so we don't need to account for stores separately. The branch
16187 reads no registers and so does not need to be counted either.
16189 ??? This value is very much on the pessimistic side, but seems to work
16190 pretty well in practice. */
16194 }
16196 /* Like min_cycles_per_iter, but excluding predicate operations. */
16197 fractional_cost
16199 {
16210 }
16212 /* Like min_cycles_per_iter, but including only the predicate operations. */
16213 fractional_cost
16215 {
16219 }
16221 /* Estimate the minimum number of cycles needed to issue the operations.
16222 This is a very simplistic model! */
16223 fractional_cost
16225 {
16228 }
16230 /* Dump information about the structure. */
16231 void
16233 {
16250 {
16252 " estimated min cycles per iteration"
16256 " estimated min cycles per iteration"
16258 }
16263 }
16265 /* Information about vector code that we're in the process of costing. */
16267 {
16282 aarch64_vec_op_count *);
16291 /* True if we have performed one-time initialization based on the
16292 vec_info. */
16295 /* This loop uses an average operation that is not supported by SVE, but is
16296 supported by Advanced SIMD and SVE2. */
16299 /* Additional initialization costs for using gather or scatter operation in
16300 the current loop. */
16303 /* True if the vector body contains a store to a decl and if the
16304 function is known to have a vld1 from the same decl.
16306 In the Advanced SIMD ACLE, the recommended endian-agnostic way of
16307 initializing a vector is:
16309 float f[4] = { elts };
16310 float32x4_t x = vld1q_f32(f);
16312 We should strongly prefer vectorization of the initialization of f,
16313 so that the store to f and the load back can be optimized away,
16314 leaving a vectorization of { elts }. */
16317 /* Non-zero if the last operation we costed is a vector promotion or demotion.
16318 In this case the value is the number of insns in the last operation.
16320 On AArch64 vector promotion and demotions require us to first widen or
16321 narrow the input and only after that emit conversion instructions. For
16322 costing this means we need to emit the cost of the final conversions as
16323 well. */
16326 /* - If M_VEC_FLAGS is zero then we're costing the original scalar code.
16327 - If M_VEC_FLAGS & VEC_ADVSIMD is nonzero then we're costing Advanced
16328 SIMD code.
16329 - If M_VEC_FLAGS & VEC_ANY_SVE is nonzero then we're costing SVE code. */
16332 /* At the moment, we do not model LDP and STP in the vector and scalar costs.
16333 This means that code such as:
16335 a[0] = x;
16336 a[1] = x;
16338 will be costed as two scalar instructions and two vector instructions
16339 (a scalar_to_vec and an unaligned_store). For SLP, the vector form
16340 wins if the costs are equal, because of the fact that the vector costs
16341 include constant initializations whereas the scalar costs don't.
16342 We would therefore tend to vectorize the code above, even though
16343 the scalar version can use a single STP.
16345 We should eventually fix this and model LDP and STP in the main costs;
16346 see the comment in aarch64_sve_adjust_stmt_cost for some of the problems.
16347 Until then, we look specifically for code that does nothing more than
16348 STP-like operations. We cost them on that basis in addition to the
16349 normal latency-based costs.
16351 If the scalar or vector code could be a sequence of STPs +
16352 initialization, this variable counts the cost of the sequence,
16353 with 2 units per instruction. The variable is ~0U for other
16354 kinds of code. */
16357 /* On some CPUs, SVE and Advanced SIMD provide the same theoretical vector
16358 throughput, such as 4x128 Advanced SIMD vs. 2x256 SVE. In those
16359 situations, we try to predict whether an Advanced SIMD implementation
16360 of the loop could be completely unrolled and become straight-line code.
16361 If so, it is generally better to use the Advanced SIMD version rather
16362 than length-agnostic SVE, since the SVE loop would execute an unknown
16363 number of times and so could not be completely unrolled in the same way.
16365 If we're applying this heuristic, M_UNROLLED_ADVSIMD_NITERS is the
16366 number of Advanced SIMD loop iterations that would be unrolled and
16367 M_UNROLLED_ADVSIMD_STMTS estimates the total number of statements
16368 in the unrolled loop. Both values are zero if we're not applying
16369 the heuristic. */
16373 /* If we're vectorizing a loop that executes a constant number of times,
16374 this variable gives the number of times that the vector loop would
16375 iterate, otherwise it is zero. */
16378 /* Used only when vectorizing loops. Estimates the number and kind of
16379 operations that would be needed by one iteration of the scalar
16380 or vector loop. There is one entry for each tuning option of
16381 interest. */
16383 };
16390 {
16392 {
16395 {
16398 vf_factor });
16399 }
16400 }
16401 }
16403 /* Implement TARGET_VECTORIZE_CREATE_COSTS. */
16404 vector_costs *
16406 {
16408 }
16410 /* Return true if the current CPU should use the new costs defined
16411 in GCC 11. This should be removed for GCC 12 and above, with the
16412 costs applying to all CPUs instead. */
16413 static bool
16415 {
16418 }
16420 /* Return the appropriate SIMD costs for vectors of type VECTYPE. */
16423 {
16430 }
16432 /* Return the appropriate SIMD costs for vectors with VEC_* flags FLAGS. */
16435 {
16440 }
16442 /* If STMT_INFO is a memory reference, return the scalar memory type,
16443 otherwise return null. */
16444 static tree
16446 {
16450 }
16452 /* Decide whether to use the unrolling heuristic described above
16453 m_unrolled_advsimd_niters, updating that field if so. LOOP_VINFO
16454 describes the loop that we're vectorizing. */
16455 void
16458 {
16459 /* The heuristic only makes sense on targets that have the same
16460 vector throughput for SVE and Advanced SIMD. */
16465 /* We only want to apply the heuristic if LOOP_VINFO is being
16466 vectorized for SVE. */
16470 /* Check whether it is possible in principle to use Advanced SIMD
16471 instead. */
16475 /* We don't want to apply the heuristic to outer loops, since it's
16476 harder to track two levels of unrolling. */
16480 /* Only handle cases in which the number of Advanced SIMD iterations
16481 would be known at compile time but the number of SVE iterations
16482 would not. */
16487 /* Guess how many times the Advanced SIMD loop would iterate and make
16488 sure that it is within the complete unrolling limit. Even if the
16489 number of iterations is small enough, the number of statements might
16490 not be, which is why we need to estimate the number of statements too. */
16493 unsigned HOST_WIDE_INT unrolled_advsimd_niters
16498 /* Record that we're applying the heuristic and should try to estimate
16499 the number of statements in the Advanced SIMD loop. */
16501 }
16503 /* Do one-time initialization of the aarch64_vector_costs given that we're
16504 costing the loop vectorization described by LOOP_VINFO. */
16505 void
16507 {
16508 /* Record the number of times that the vector loop would execute,
16509 if known. */
16513 {
16517 else
16519 }
16521 /* Detect whether we're vectorizing for SVE and should apply the unrolling
16522 heuristic described above m_unrolled_advsimd_niters. */
16524 }
16526 /* Implement targetm.vectorize.builtin_vectorization_cost. */
16527 static int
16529 tree vectype,
16531 {
16542 {
16595 }
16596 }
16598 /* Return true if an access of kind KIND for STMT_INFO (or NODE if SLP)
16599 represents one vector of an LD[234] or ST[234] operation. Return the total
16600 number of vectors (2, 3 or 4) if so, otherwise return a value outside that
16601 range. */
16602 static int
16604 slp_tree node)
16605 {
16611 {
16616 }
16618 }
16620 /* Return true if creating multiple copies of STMT_INFO for Advanced SIMD
16621 vectors would produce a series of LDP or STP operations. KIND is the
16622 kind of statement that STMT_INFO represents. */
16623 static bool
16625 stmt_vec_info stmt_info)
16626 {
16628 {
16637 }
16640 }
16642 /* Return true if STMT_INFO is the second part of a two-statement multiply-add
16643 or multiply-subtract sequence that might be suitable for fusing into a
16644 single instruction. If VEC_FLAGS is zero, analyze the operation as
16645 a scalar one, otherwise analyze it as an operation on vectors with those
16646 VEC_* flags. */
16647 static bool
16650 {
16659 {
16661 /* ??? Should we try to check for a single use as well? */
16674 {
16675 /* Scalar and SVE code can tie the result to any FMLA input (or none,
16676 although that requires a MOVPRFX for SVE). However, Advanced SIMD
16677 only supports MLA forms, so will require a move if the result
16678 cannot be tied to the accumulator. The most important case in
16679 which this is true is when the accumulator input is invariant. */
16688 }
16691 };
16694 /* Advanced SIMD doesn't have FNMADD/FNMSUB/FNMLA/FNMLS, so the
16695 multiplication must be on the second operand (to form an FMLS).
16696 But if both operands are multiplications and the second operand
16697 is used more than once, we'll instead negate the second operand
16698 and use it as an accumulator for the first operand. */
16704 }
16706 /* Return true if STMT_INFO is the second part of a two-statement boolean AND
16707 expression sequence that might be suitable for fusing into a
16708 single instruction. If VEC_FLAGS is zero, analyze the operation as
16709 a scalar one, otherwise analyze it as an operation on vectors with those
16710 VEC_* flags. */
16712 static bool
16715 {
16724 {
16745 }
16747 }
16749 /* We are considering implementing STMT_INFO using SVE. If STMT_INFO is an
16750 in-loop reduction that SVE supports directly, return its latency in cycles,
16751 otherwise return zero. SVE_COSTS specifies the latencies of the relevant
16752 instructions. */
16753 static unsigned int
16755 stmt_vec_info stmt_info,
16757 {
16759 {
16765 {
16778 }
16780 }
16783 }
16785 /* STMT_INFO describes a loop-carried operation in the original scalar code
16786 that we are considering implementing as a reduction. Return one of the
16787 following values, depending on VEC_FLAGS:
16789 - If VEC_FLAGS is zero, return the loop carry latency of the original
16790 scalar operation.
16792 - If VEC_FLAGS & VEC_ADVSIMD, return the loop carry latency of the
16793 Advanced SIMD implementation.
16795 - If VEC_FLAGS & VEC_ANY_SVE, return the loop carry latency of the
16796 SVE implementation. */
16797 static unsigned int
16800 {
16806 /* If the caller is asking for the SVE latency, check for forms of reduction
16807 that only SVE can handle directly. */
16809 {
16810 unsigned int latency
16814 }
16816 /* Handle scalar costs. */
16819 {
16823 }
16825 /* Otherwise, the loop body just contains normal integer or FP operations,
16826 with a vector reduction outside the loop. */
16832 }
16834 /* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
16835 for STMT_INFO, which has cost kind KIND. If this is a scalar operation,
16836 try to subdivide the target-independent categorization provided by KIND
16837 to get a more accurate cost. */
16838 static fractional_cost
16840 stmt_vec_info stmt_info,
16841 fractional_cost stmt_cost)
16842 {
16843 /* Detect an extension of a loaded value. In general, we'll be able to fuse
16844 the extension with the load. */
16849 }
16851 /* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
16852 for the vectorized form of STMT_INFO possibly using SLP node NODE, which has
16853 cost kind KIND and which when vectorized would operate on vector type
16854 VECTYPE. Try to subdivide the target-independent categorization provided by
16855 KIND to get a more accurate cost. WHERE specifies where the cost associated
16856 with KIND occurs. */
16857 static fractional_cost
16860 tree vectype,
16862 fractional_cost stmt_cost)
16863 {
16869 /* It's generally better to avoid costing inductions, since the induction
16870 will usually be hidden by other operations. This is particularly true
16871 for things like COND_REDUCTIONS. */
16875 /* Detect cases in which vec_to_scalar is describing the extraction of a
16876 vector element in preparation for a scalar store. The store itself is
16877 costed separately. */
16881 /* Detect SVE gather loads, which are costed as a single scalar_load
16882 for each element. We therefore need to divide the full-instruction
16883 cost by the number of elements in the vector. */
16885 && sve_costs
16887 {
16889 /* Test for VNx2 modes, which have 64-bit containers. */
16893 }
16895 /* Detect cases in which a scalar_store is really storing one element
16896 in a scatter operation. */
16898 && sve_costs
16902 /* Detect cases in which vec_to_scalar represents an in-loop reduction. */
16906 {
16907 unsigned int latency
16911 }
16913 /* Detect cases in which vec_to_scalar represents a single reduction
16914 instruction like FADDP or MAXV. */
16919 {
16944 }
16946 /* Otherwise stick with the original categorization. */
16948 }
16950 /* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
16951 for STMT_INFO, which has cost kind KIND and which when vectorized would
16952 operate on vector type VECTYPE. Adjust the cost as necessary for SVE
16953 targets. */
16954 static fractional_cost
16957 fractional_cost stmt_cost)
16958 {
16959 /* Unlike vec_promote_demote, vector_stmt conversions do not change the
16960 vector register size or number of units. Integer promotions of this
16961 type therefore map to SXT[BHW] or UXT[BHW].
16963 Most loads have extending forms that can do the sign or zero extension
16964 on the fly. Optimistically assume that a load followed by an extension
16965 will fold to this form during combine, and that the extension therefore
16966 comes for free. */
16970 /* For similar reasons, vector_stmt integer truncations are a no-op,
16971 because we can just ignore the unused upper bits of the source. */
16975 /* Advanced SIMD can load and store pairs of registers using LDP and STP,
16976 but there are no equivalent instructions for SVE. This means that
16977 (all other things being equal) 128-bit SVE needs twice as many load
16978 and store instructions as Advanced SIMD in order to process vector pairs.
16980 Also, scalar code can often use LDP and STP to access pairs of values,
16981 so it is too simplistic to say that one SVE load or store replaces
16982 VF scalar loads and stores.
16984 Ideally we would account for this in the scalar and Advanced SIMD
16985 costs by making suitable load/store pairs as cheap as a single
16986 load/store. However, that would be a very invasive change and in
16987 practice it tends to stress other parts of the cost model too much.
16988 E.g. stores of scalar constants currently count just a store,
16989 whereas stores of vector constants count a store and a vec_init.
16990 This is an artificial distinction for AArch64, where stores of
16991 nonzero scalar constants need the same kind of register invariant
16992 as vector stores.
16994 An alternative would be to double the cost of any SVE loads and stores
16995 that could be paired in Advanced SIMD (and possibly also paired in
16996 scalar code). But this tends to stress other parts of the cost model
16997 in the same way. It also means that we can fall back to Advanced SIMD
16998 even if full-loop predication would have been useful.
17000 Here we go for a more conservative version: double the costs of SVE
17001 loads and stores if one iteration of the scalar loop processes enough
17002 elements for it to use a whole number of Advanced SIMD LDP or STP
17003 instructions. This makes it very likely that the VF would be 1 for
17004 Advanced SIMD, and so no epilogue should be needed. */
17006 {
17013 }
17016 }
17018 /* STMT_COST is the cost calculated for STMT_INFO, which has cost kind KIND
17019 and which when vectorized would operate on vector type VECTYPE. Add the
17020 cost of any embedded operations. */
17021 static fractional_cost
17025 {
17027 {
17030 /* Detect cases in which a vector load or store represents an
17031 LD[234] or ST[234] instruction. */
17033 {
17045 }
17049 {
17050 /* For MLA we need to reduce the cost since MLA is 1 instruction. */
17055 /* For vector boolean ANDs with a compare operand we just need
17056 one insn. */
17059 }
17063 {
17066 else
17068 }
17069 }
17073 {
17076 else
17078 }
17081 }
17083 /* Return true if STMT_INFO is part of a reduction that has the form:
17085 r = r op ...;
17086 r = r op ...;
17088 with the single accumulator being read and written multiple times. */
17089 static bool
17091 {
17097 }
17099 /* COUNT, KIND and STMT_INFO are the same as for vector_costs::add_stmt_cost
17100 and they describe an operation in the body of a vector loop. Record issue
17101 information relating to the vector operation in OPS. */
17102 void
17106 {
17113 /* Calculate the minimum cycles per iteration imposed by a reduction
17114 operation. */
17117 {
17118 unsigned int base
17121 /* ??? Ideally we'd use a tree to reduce the copies down to 1 vector,
17122 and then accumulate that, but at the moment the loop-carried
17123 dependency includes all copies. */
17125 else
17127 }
17130 {
17131 /* Assume that multiply-adds will become a single operation. */
17135 /* Assume that bool AND with compare operands will become a single
17136 operation. */
17139 }
17142 /* Count the basic operation cost associated with KIND. */
17144 {
17149 /* We currently don't expect these to be used in a loop body. */
17177 }
17179 /* Add any embedded comparison operations. */
17184 /* COND_REDUCTIONS need two sets of VEC_COND_EXPRs, whereas so far we
17185 have only accounted for one. */
17190 /* Count the predicate operations needed by an SVE comparison. */
17193 {
17198 }
17200 /* Add any extra overhead associated with LD[234] and ST[234] operations. */
17203 {
17215 }
17217 /* Add any overhead associated with gather loads and scatter stores. */
17221 {
17225 }
17226 }
17228 /* Return true if STMT_INFO contains a memory access and if the constant
17229 component of the memory address is aligned to SIZE bytes. */
17230 static bool
17232 poly_uint64 size)
17233 {
17240 /* Needed for gathers & scatters, for example. */
17245 }
17247 /* Check if a scalar or vector stmt could be part of a region of code
17248 that does nothing more than store values to memory, in the scalar
17249 case using STP. Return the cost of the stmt if so, counting 2 for
17250 one instruction. Return ~0U otherwise.
17252 The arguments are a subset of those passed to add_stmt_cost. */
17253 unsigned int
17256 {
17257 /* Code that stores vector constants uses a vector_load to create
17258 the constant. We don't apply the heuristic to that case for two
17259 main reasons:
17261 - At the moment, STPs are only formed via peephole2, and the
17262 constant scalar moves would often come between STRs and so
17263 prevent STP formation.
17265 - The scalar code also has to load the constant somehow, and that
17266 isn't costed. */
17268 {
17270 /* Count 2 insns for a GPR->SIMD dup and 1 insn for a FPR->SIMD dup. */
17275 /* Count 1 insn for the maximum number of FP->SIMD INS
17276 instructions. */
17279 /* Count 2 insns for a GPR->SIMD move and 2 insns for the
17280 maximum number of GPR->SIMD INS instructions. */
17285 /* Count 1 insn per vector if we can't form STP Q pairs. */
17290 {
17291 /* Assume we won't be able to use STP if the constant offset
17292 component of the address is misaligned. ??? This could be
17293 removed if we formed STP pairs earlier, rather than relying
17294 on peephole2. */
17298 }
17303 {
17304 /* Check for a mode in which STP pairs can be formed. */
17309 /* Assume we won't be able to use STP if the constant offset
17310 component of the address is misaligned. ??? This could be
17311 removed if we formed STP pairs earlier, rather than relying
17312 on peephole2. */
17315 }
17320 }
17321 }
17323 unsigned
17327 vect_cost_model_location where)
17328 {
17329 fractional_cost stmt_cost
17333 && stmt_info
17336 /* Do one-time initialization based on the vinfo. */
17339 {
17344 }
17346 /* Apply the heuristic described above m_stp_sequence_cost. */
17348 {
17352 }
17354 /* Try to get a more accurate cost by looking at STMT_INFO instead
17355 of just looking at KIND. */
17357 {
17358 /* If we scalarize a strided store, the vectorizer costs one
17359 vec_to_scalar for each element. However, we can store the first
17360 element using an FP store without a separate extract step. */
17371 stmt_cost);
17373 /* Check if we've seen an SVE gather/scatter operation and which size. */
17377 {
17380 {
17381 /* Test for VNx2 modes, which have 64-bit containers. */
17383 aarch64_sve_vg))
17384 m_sve_gather_scatter_init_cost
17386 else
17387 m_sve_gather_scatter_init_cost
17389 }
17390 }
17391 }
17393 /* Do any SVE-specific adjustments to the cost. */
17398 /* Vector promotion and demotion requires us to widen the operation first
17399 and only after that perform the conversion. Unfortunately the mid-end
17400 expects this to be doable as a single operation and doesn't pass on
17401 enough context here for us to tell which operation is happening. To
17402 account for this we count every promote-demote operation twice and if
17403 the previously costed operation was also a promote-demote we reduce
17404 the cost of the currently being costed operation to simulate the final
17405 conversion cost. Note that for SVE we can do better here if the converted
17406 value comes from a load since the widening load would consume the widening
17407 operations. However since we're in stage 3 we can't change the helper
17408 vect_is_extending_load and duplicating the code seems not useful. */
17413 {
17417 }
17418 else
17422 {
17423 /* Account for any extra "embedded" costs that apply additively
17424 to the base cost calculated above. */
17428 /* If we're recording a nonzero vector loop body cost for the
17429 innermost loop, also estimate the operations that would need
17430 to be issued by all relevant implementations of the loop. */
17438 /* If we're applying the SVE vs. Advanced SIMD unrolling heuristic,
17439 estimate the number of statements in the unrolled Advanced SIMD
17440 loop. For simplicitly, we assume that one iteration of the
17441 Advanced SIMD loop would need the same number of statements
17442 as one iteration of the SVE loop. */
17446 /* Detect the use of an averaging operation. */
17450 {
17452 {
17458 }
17459 }
17460 }
17462 /* If the statement stores to a decl that is known to be the argument
17463 to a vld1 in the same function, ignore the store for costing purposes.
17464 See the comment above m_stores_to_vector_load_decl for more details. */
17468 {
17471 }
17474 }
17476 /* Return true if (a) we're applying the Advanced SIMD vs. SVE unrolling
17477 heuristic described above m_unrolled_advsimd_niters and (b) the heuristic
17478 says that we should prefer the Advanced SIMD loop. */
17479 bool
17481 {
17487 " unrolled Advanced SIMD loop = "
17489 m_unrolled_advsimd_stmts);
17491 /* The balance here is tricky. On the one hand, we can't be sure whether
17492 the code is vectorizable with Advanced SIMD or not. However, even if
17493 it isn't vectorizable with Advanced SIMD, there's a possibility that
17494 the scalar code could also be unrolled. Some of the code might then
17495 benefit from SLP, or from using LDP and STP. We therefore apply
17496 the heuristic regardless of can_use_advsimd_p. */
17498 && (m_unrolled_advsimd_stmts
17500 }
17502 /* Subroutine of adjust_body_cost for handling SVE. Use ISSUE_INFO to work out
17503 how fast the SVE code can be issued and compare it to the equivalent value
17504 for scalar code (SCALAR_CYCLES_PER_ITER). If COULD_USE_ADVSIMD is true,
17505 also compare it to the issue rate of Advanced SIMD code
17506 (ADVSIMD_CYCLES_PER_ITER).
17508 ORIG_BODY_COST is the cost originally passed to adjust_body_cost and
17509 *BODY_COST is the current value of the adjusted cost. *SHOULD_DISPARAGE
17510 is true if we think the loop body is too expensive. */
17512 fractional_cost
17515 fractional_cost scalar_cycles_per_iter,
17518 {
17525 /* If the scalar version of the loop could issue at least as
17526 quickly as the predicate parts of the SVE loop, make the SVE loop
17527 prohibitively expensive. In this case vectorization is adding an
17528 overhead that the original scalar code didn't have.
17530 This is mostly intended to detect cases in which WHILELOs dominate
17531 for very tight loops, which is something that normal latency-based
17532 costs would not model. Adding this kind of cliffedge would be
17533 too drastic for scalar_cycles_per_iter vs. sve_cycles_per_iter;
17534 code in the caller handles that case in a more conservative way. */
17537 {
17538 unsigned int min_cost
17541 {
17544 "Increasing body cost to %d because the"
17545 " scalar code could issue within the limit"
17547 min_cost);
17550 }
17551 }
17554 }
17556 unsigned int
17558 {
17560 /* If we are trying to unroll an Advanced SIMD main loop that contains
17561 an averaging operation that we do not support with SVE and we might use a
17562 predicated epilogue, we need to be conservative and block unrolling as
17563 this might lead to a less optimal loop for the first and only epilogue
17564 using the original loop's vectorization factor.
17565 TODO: Remove this constraint when we add support for multiple epilogue
17566 vectorization. */
17572 {
17577 /* Limit unroll factor to a value adjustable by the user, the default
17578 value is 4. */
17580 unsigned int factor
17584 /* Sanity check, this should never happen. */
17588 /* Check stores. */
17590 {
17594 }
17596 /* Check loads + stores. */
17598 {
17602 }
17604 /* Check general ops. */
17606 {
17610 }
17612 }
17614 /* Make sure unroll factor is power of 2. */
17616 }
17618 /* BODY_COST is the cost of a vector loop body. Adjust the cost as necessary
17619 and return the new cost. */
17620 unsigned int
17625 {
17639 /* If we know we have a single partial vector iteration, cap the VF
17640 to the number of scalar iterations for costing purposes. */
17642 {
17646 "Scalar loop iterates at most %wd times. Capping VF "
17650 }
17652 fractional_cost scalar_cycles_per_iter
17658 {
17662 m_num_vector_iterations);
17666 " estimated cycles per vector iteration"
17669 }
17672 {
17675 vector_cycles_per_iter
17680 {
17681 /* Also take Neoverse V1 tuning into account, doubling the
17682 scalar and Advanced SIMD estimates to account for the
17683 doubling in SVE vector length. */
17690 }
17691 }
17692 else
17693 {
17695 {
17699 }
17700 }
17702 /* Decide whether to stick to latency-based costs or whether to try to
17703 take issue rates into account. */
17710 {
17713 "Low iteration count, so using pure latency"
17715 }
17716 /* Increase the cost of the vector code if it looks like the scalar code
17717 could issue more quickly. These values are only rough estimates,
17718 so minor differences should only result in minor changes. */
17720 {
17722 scalar_cycles_per_iter);
17725 "Increasing body cost to %d because scalar code"
17727 }
17728 /* In general, it's expected that the proposed vector code would be able
17729 to issue more quickly than the original scalar code. This should
17730 already be reflected to some extent in the latency-based costs.
17732 However, the latency-based costs effectively assume that the scalar
17733 code and the vector code execute serially, which tends to underplay
17734 one important case: if the real (non-serialized) execution time of
17735 a scalar iteration is dominated by loop-carried dependencies,
17736 and if the vector code is able to reduce both the length of
17737 the loop-carried dependencies *and* the number of cycles needed
17738 to issue the code in general, we can be more confident that the
17739 vector code is an improvement, even if adding the other (non-loop-carried)
17740 latencies tends to hide this saving. We therefore reduce the cost of the
17741 vector loop body in proportion to the saving. */
17746 {
17748 scalar_cycles_per_iter);
17751 "Decreasing body cost to %d account for smaller"
17753 }
17756 }
17758 void
17760 {
17761 /* Record the issue information for any SVE WHILE instructions that the
17762 loop needs. */
17765 && loop_vinfo
17767 {
17778 }
17783 && m_vec_flags
17785 {
17790 /* For gather and scatters there's an additional overhead for the first
17791 iteration. For low count loops they're not beneficial so model the
17792 overhead as loop prologue costs. */
17794 }
17796 /* Apply the heuristic described above m_stp_sequence_cost. Prefer
17797 the scalar code in the event of a tie, since there is more chance
17798 of scalar code being optimized with surrounding operations.
17800 In addition, if the vector body is a simple store to a decl that
17801 is elsewhere loaded using vld1, strongly prefer the vector form,
17802 to the extent of giving the prologue a zero cost. See the comment
17803 above m_stores_to_vector_load_decl for details. */
17805 && scalar_costs
17807 {
17812 }
17815 }
17817 bool
17820 {
17834 /* Apply the unrolling heuristic described above
17835 m_unrolled_advsimd_niters. */
17838 {
17842 {
17845 "Preferring Advanced SIMD loop because"
17848 }
17849 }
17852 {
17854 {
17866 }
17873 /* If it appears that one loop could process the same amount of data
17874 in fewer cycles, prefer that loop over the other one. */
17875 fractional_cost this_cost
17877 fractional_cost other_cost
17880 {
17889 }
17891 {
17894 "Preferring loop with lower cycles"
17897 }
17899 /* If the issue rate of SVE code is limited by predicate operations
17900 (i.e. if sve_pred_cycles_per_iter > sve_nonpred_cycles_per_iter),
17901 and if Advanced SIMD code could issue within the limit imposed
17902 by the predicate operations, the predicate operations are adding an
17903 overhead that the original code didn't have and so we should prefer
17904 the Advanced SIMD version. */
17907 {
17911 {
17914 "Preferring Advanced SIMD loop since"
17917 }
17919 };
17924 }
17927 }
17931 /* Parse the TO_PARSE string and put the architecture struct that it
17932 selects into RES and the architectural features into ISA_FLAGS.
17933 Return an aarch_parse_opt_result describing the parse result.
17934 If there is an error parsing, RES and ISA_FLAGS are left unchanged.
17935 When the TO_PARSE string contains an invalid extension,
17936 a copy of the string is created and stored to INVALID_EXTENSION. */
17938 static enum aarch_parse_opt_result
17942 {
17951 else
17958 /* Loop through the list of supported ARCHes to find a match. */
17960 {
17963 {
17967 {
17968 /* TO_PARSE string contains at least one extension. */
17969 enum aarch_parse_opt_result ext_res
17974 }
17975 /* Extension parsing was successful. Confirm the result
17976 arch and ISA flags. */
17980 }
17981 }
17983 /* ARCH name not found in list. */
17985 }
17987 /* Parse the TO_PARSE string and put the result tuning in RES and the
17988 architecture flags in ISA_FLAGS. Return an aarch_parse_opt_result
17989 describing the parse result. If there is an error parsing, RES and
17990 ISA_FLAGS are left unchanged.
17991 When the TO_PARSE string contains an invalid extension,
17992 a copy of the string is created and stored to INVALID_EXTENSION. */
17994 static enum aarch_parse_opt_result
17998 {
18007 else
18014 /* Loop through the list of supported CPUs to find a match. */
18016 {
18018 {
18022 {
18023 /* TO_PARSE string contains at least one extension. */
18024 enum aarch_parse_opt_result ext_res
18029 }
18030 /* Extension parsing was successfull. Confirm the result
18031 cpu and ISA flags. */
18035 }
18036 }
18038 /* CPU name not found in list. */
18040 }
18042 /* Parse the TO_PARSE string and put the cpu it selects into RES.
18043 Return an aarch_parse_opt_result describing the parse result.
18044 If the parsing fails the RES does not change. */
18046 static enum aarch_parse_opt_result
18048 {
18051 /* Loop through the list of supported CPUs to find a match. */
18053 {
18055 {
18058 }
18059 }
18061 /* CPU name not found in list. */
18063 }
18065 /* Parse TOKEN, which has length LENGTH to see if it is an option
18066 described in FLAG. If it is, return the index bit for that fusion type.
18067 If not, error (printing OPTION_NAME) and return zero. */
18069 static unsigned int
18074 {
18076 {
18080 }
18084 }
18086 /* Parse OPTION which is a comma-separated list of flags to enable.
18087 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
18088 default state we inherit from the CPU tuning structures. OPTION_NAME
18089 gives the top-level option we are parsing in the -moverride string,
18090 for use in error messages. */
18092 static unsigned int
18097 {
18104 {
18107 token_length,
18108 flags,
18109 option_name);
18110 /* If we find "none" (or, for simplicity's sake, an error) anywhere
18111 in the token stream, reset the supported operations. So:
18113 adrp+add.cmp+branch.none.adrp+add
18115 would have the result of turning on only adrp+add fusion. */
18121 }
18123 /* We ended with a comma, print something. */
18125 {
18128 }
18130 /* We still have one more token to parse. */
18133 token_length,
18134 flags,
18135 option_name);
18141 }
18143 /* Support for overriding instruction fusion. */
18145 static void
18148 {
18150 aarch64_fusible_pairs,
18153 }
18155 /* Support for overriding other tuning flags. */
18157 static void
18160 {
18161 tune->extra_tuning_flags
18163 aarch64_tuning_flags,
18166 }
18168 /* Parse the sve_width tuning moverride string in TUNE_STRING.
18169 Accept the valid SVE vector widths allowed by
18170 aarch64_sve_vector_bits_enum and use it to override sve_width
18171 in TUNE. */
18173 static void
18176 {
18181 {
18184 }
18186 {
18195 }
18197 }
18199 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
18200 we understand. If it is, extract the option string and handoff to
18201 the appropriate function. */
18203 void
18207 {
18213 {
18216 }
18218 /* Get the length of the option name. */
18220 /* Skip the '=' to get to the option string. */
18221 option_part++;
18224 {
18226 {
18229 }
18230 }
18234 }
18236 /* A checking mechanism for the implementation of the tls size. */
18238 static void
18240 {
18245 {
18247 /* Both the default and maximum TLS size allowed under tiny is 1M which
18248 needs two instructions to address, so we clamp the size to 24. */
18253 /* The maximum TLS size allowed under small is 4G. */
18258 /* The maximum TLS size allowed under large is 16E.
18259 FIXME: 16E should be 64bit, we only support 48bit offset now. */
18265 }
18268 }
18270 /* Return the CPU corresponding to the enum CPU. */
18274 {
18278 }
18280 /* Return the architecture corresponding to the enum ARCH. */
18284 {
18288 }
18290 /* Parse STRING looking for options in the format:
18291 string :: option:string
18292 option :: name=substring
18293 name :: {a-z}
18294 substring :: defined by option. */
18296 static void
18299 {
18310 {
18312 /* Make this substring look like a string. */
18316 }
18318 /* One last option to parse. */
18321 }
18323 /* Adjust CURRENT_TUNE (a generic tuning struct) with settings that
18324 are best for a generic target with the currently-enabled architecture
18325 extensions. */
18326 static void
18328 {
18329 /* Neoverse V1 is the only core that is known to benefit from
18330 AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS. There is therefore no
18331 point enabling it for SVE2 and above. */
18333 current_tune.extra_tuning_flags
18335 }
18337 static void
18339 {
18340 /* PR 70044: We have to be careful about being called multiple times for the
18341 same function. This means all changes should be repeatable. */
18343 /* Set aarch64_use_frame_pointer based on -fno-omit-frame-pointer.
18344 Disable the frame pointer flag so the mid-end will not use a frame
18345 pointer in leaf functions in order to support -fomit-leaf-frame-pointer.
18346 Set x_flag_omit_frame_pointer to the special value 2 to differentiate
18347 between -fomit-frame-pointer (1) and -fno-omit-frame-pointer (2). */
18352 /* If not optimizing for size, set the default
18353 alignment to what the target wants. */
18355 {
18362 }
18364 /* We default to no pc-relative literal loads. */
18368 /* If -mpc-relative-literal-loads is set on the command line, this
18369 implies that the user asked for PC relative literal loads. */
18373 /* In the tiny memory model it makes no sense to disallow PC relative
18374 literal pool loads. */
18379 /* When enabling the lower precision Newton series for the square root, also
18380 enable it for the reciprocal square root, since the latter is an
18381 intermediary step for the former. */
18384 }
18386 /* 'Unpack' up the internal tuning structs and update the options
18387 in OPTS. The caller must have set up selected_tune and selected_arch
18388 as all the other target-specific codegen decisions are
18389 derived from them. */
18391 void
18393 {
18396 /* Make a copy of the tuning parameters attached to the core, which
18397 we may later overwrite. */
18412 /* This target defaults to strict volatile bitfields. */
18418 {
18421 aarch64_stack_protector_guard_offset_str);
18422 }
18427 {
18429 "%<-mstack-protector-guard-reg%> must be used "
18431 }
18434 {
18437 }
18440 {
18449 }
18458 {
18461 else
18465 " option %<-march%>, or by using the %<target%>"
18470 }
18478 {
18490 }
18492 /* We don't mind passing in global_options_set here as we don't use
18493 the *options_set structs anyway. */
18497 /* Set up parameters to be used in prefetching algorithm. Do not
18498 override the defaults unless we are tuning for a core we have
18499 researched values for. */
18502 param_simultaneous_prefetches,
18506 param_l1_cache_size,
18510 param_l1_cache_line_size,
18514 {
18516 param_destruct_interfere_size,
18519 param_construct_interfere_size,
18521 }
18522 else
18523 {
18524 /* For a generic AArch64 target, cover the current range of cache line
18525 sizes. */
18527 param_destruct_interfere_size,
18530 param_construct_interfere_size,
18532 }
18536 param_l2_cache_size,
18543 param_prefetch_minimum_stride,
18546 /* Use the alternative scheduling-pressure algorithm by default. */
18548 param_sched_pressure_algorithm,
18549 SCHED_PRESSURE_MODEL);
18551 /* Validate the guard size. */
18559 /* Enforce that interval is the same size as size so the mid-end does the
18560 right thing. */
18562 param_stack_clash_protection_probe_interval,
18563 guard_size);
18565 /* The maybe_set calls won't update the value if the user has explicitly set
18566 one. Which means we need to validate that probing interval and guard size
18567 are equal. */
18568 int probe_interval
18574 /* Enable sw prefetching at specified optimization level for
18575 CPUS that have prefetch. Lower optimization level threshold by 1
18576 when profiling is enabled. */
18583 /* Avoid loop-dependant FMA chains. */
18589 /* Consider fully pipelined FMA in reassociation. */
18596 }
18598 /* Print a hint with a suggestion for a core or architecture name that
18599 most closely resembles what the user passed in STR. ARCH is true if
18600 the user is asking for an architecture name. ARCH is false if the user
18601 is asking for a core name. */
18603 static void
18605 {
18611 #ifdef HAVE_LOCAL_CPU_DETECT
18612 /* Add also "native" as possible value. */
18615 #endif
18622 else
18626 }
18628 /* Print a hint with a suggestion for a core name that most closely resembles
18629 what the user passed in STR. */
18633 {
18635 }
18637 /* Print a hint with a suggestion for an architecture name that most closely
18638 resembles what the user passed in STR. */
18642 {
18644 }
18647 /* Print a hint with a suggestion for an extension name
18648 that most closely resembles what the user passed in STR. */
18650 void
18652 {
18660 else
18664 }
18666 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
18667 specified in STR and throw errors if appropriate. Put the results if
18668 they are valid in RES and ISA_FLAGS. Return whether the option is
18669 valid. */
18671 static bool
18674 {
18676 enum aarch_parse_opt_result parse_res
18683 {
18690 /* A common user error is confusing -march and -mcpu.
18691 If the -mcpu string matches a known architecture then suggest
18692 -march=. */
18704 }
18707 }
18709 /* Straight line speculation indicators. */
18710 enum aarch64_sls_hardening_type
18711 {
18716 };
18719 /* Return whether we should mitigatate Straight Line Speculation for the RET
18720 and BR instructions. */
18721 bool
18723 {
18725 }
18727 /* Return whether we should mitigatate Straight Line Speculation for the BLR
18728 instruction. */
18729 bool
18731 {
18733 }
18735 /* As of yet we only allow setting these options globally, in the future we may
18736 allow setting them per function. */
18737 static void
18739 {
18744 {
18747 }
18749 {
18752 }
18761 {
18767 {
18770 }
18771 else
18772 {
18775 }
18777 }
18780 }
18782 /* Validate a command-line -march option. Parse the arch and extensions
18783 (if any) specified in STR and throw errors if appropriate. Put the
18784 results, if they are valid, in RES and ISA_FLAGS. Return whether the
18785 option is valid. */
18787 static bool
18790 {
18792 enum aarch_parse_opt_result parse_res
18799 {
18806 /* A common user error is confusing -march and -mcpu.
18807 If the -march string matches a known CPU suggest -mcpu. */
18819 }
18822 }
18824 /* Validate a command-line -mtune option. Parse the cpu
18825 specified in STR and throw errors if appropriate. Put the
18826 result, if it is valid, in RES. Return whether the option is
18827 valid. */
18829 static bool
18831 {
18832 enum aarch_parse_opt_result parse_res
18839 {
18849 }
18851 }
18853 /* Return the VG value associated with -msve-vector-bits= value VALUE. */
18855 static poly_uint16
18857 {
18858 /* 128-bit SVE and Advanced SIMD modes use different register layouts
18859 on big-endian targets, so we would need to forbid subregs that convert
18860 from one to the other. By default a reinterpret sequence would then
18861 involve a store to memory in one mode and a load back in the other.
18862 Even if we optimize that sequence using reverse instructions,
18863 it would still be a significant potential overhead.
18865 For now, it seems better to generate length-agnostic code for that
18866 case instead. */
18870 else
18872 }
18874 /* Set the global aarch64_asm_isa_flags to FLAGS and update
18875 aarch64_isa_flags accordingly. */
18877 void
18879 {
18881 }
18883 static void
18885 {
18888 }
18890 static void
18892 {
18896 }
18898 static void
18900 {
18903 }
18905 static void
18907 {
18909 }
18911 static void
18913 {
18915 }
18917 static void
18919 {
18921 }
18927 };
18930 {
18937 };
18939 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
18940 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
18941 tuning structs. In particular it must set selected_tune and
18942 aarch64_asm_isa_flags that define the available ISA features and tuning
18943 decisions. It must also set selected_arch as this will be used to
18944 output the .arch asm tags for each function. */
18946 static void
18948 {
18962 aarch64_branch_protection_string,
18965 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
18966 If either of -march or -mtune is given, they override their
18967 respective component of -mcpu. */
18977 #ifdef SUBTARGET_OVERRIDE_OPTIONS
18978 SUBTARGET_OVERRIDE_OPTIONS;
18979 #endif
18982 {
18983 /* If both -mcpu and -march are specified, warn if they are not
18984 feature compatible. feature compatible means that the inclusion of the
18985 cpu features would end up disabling an achitecture feature. In
18986 otherwords the cpu features need to be a strict superset of the arch
18987 features and if so prefer the -march ISA flags. */
18991 {
18994 full_cpu_flags);
18997 aarch64_cpu_string,
18998 aarch64_arch_string,
19000 }
19004 }
19006 {
19009 }
19011 {
19015 }
19016 else
19017 {
19018 /* No -mcpu or -march specified, so use the default CPU. */
19022 }
19027 {
19028 #ifdef TARGET_ENABLE_BTI
19030 #else
19032 #endif
19033 }
19035 /* Return address signing is currently not supported for ILP32 targets. For
19036 LP64 targets use the configured option in the absence of a command-line
19037 option for -mbranch-protection. */
19039 {
19040 #ifdef TARGET_ENABLE_PAC_RET
19042 #else
19044 #endif
19045 }
19047 #ifndef HAVE_AS_MABI_OPTION
19048 /* The compiler may have been configured with 2.23.* binutils, which does
19049 not have support for ILP32. */
19052 #endif
19054 /* Convert -msve-vector-bits to a VG count. */
19060 /* The pass to insert speculation tracking runs before
19061 shrink-wrapping and the latter does not know how to update the
19062 tracking status. So disable it in this case. */
19068 /* Save these options as the default ones in case we push and pop them later
19069 while processing functions with potential target attributes. */
19070 target_option_default_node = target_option_current_node
19072 }
19074 /* Implement targetm.override_options_after_change. */
19076 static void
19078 {
19080 }
19082 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
19085 {
19088 else
19090 }
19094 {
19098 }
19100 void
19102 {
19104 }
19106 /* A checking mechanism for the implementation of the various code models. */
19107 static void
19109 {
19112 {
19119 {
19120 #ifdef HAVE_AS_SMALL_PIC_RELOCS
19122 ? AARCH64_CMODEL_SMALL_PIC
19124 #else
19126 #endif
19127 }
19140 }
19141 }
19143 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
19144 using the information saved in PTR. */
19146 static void
19150 {
19152 }
19154 /* Implement TARGET_OPTION_PRINT. */
19156 static void
19158 {
19169 }
19173 void
19175 {
19177 }
19179 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
19180 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
19181 make sure optab availability predicates are recomputed when necessary. */
19183 void
19185 {
19190 else
19192 }
19194 /* Return the target_option_node for FNDECL, or the current options
19195 if FNDECL is null. */
19197 static tree
19199 {
19207 }
19209 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
19210 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
19211 of the function, if such exists. This function may be called multiple
19212 times on a single function so use aarch64_previous_fndecl to avoid
19213 setting up identical state. */
19215 static void
19217 {
19229 && fndecl
19231 {
19235 " option %<-march%>, or by using the %<target%>"
19238 }
19240 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
19241 the default have been handled by aarch64_save_restore_target_globals from
19242 aarch64_pragma_target_parse. */
19246 {
19249 }
19253 /* First set the target options. */
19257 /* The ISA mode can vary based on function type attributes and
19258 function declaration attributes. Make sure that the target
19259 options correctly reflect these attributes. */
19261 {
19275 }
19280 }
19282 /* Enum describing the various ways we can handle attributes.
19283 In many cases we can reuse the generic option handling machinery. */
19285 enum aarch64_attr_opt_type
19286 {
19290 aarch64_attr_custom /* Attribute requires a custom handling function. */
19291 };
19293 /* All the information needed to handle a target attribute.
19294 NAME is the name of the attribute.
19295 ATTR_TYPE specifies the type of behavior of the attribute as described
19296 in the definition of enum aarch64_attr_opt_type.
19297 ALLOW_NEG is true if the attribute supports a "no-" form.
19298 HANDLER is the function that takes the attribute string as an argument
19299 It is needed only when the ATTR_TYPE is aarch64_attr_custom.
19300 OPT_NUM is the enum specifying the option that the attribute modifies.
19301 This is needed for attributes that mirror the behavior of a command-line
19302 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
19303 aarch64_attr_enum. */
19305 struct aarch64_attribute_info
19306 {
19312 };
19314 /* Handle the ARCH_STR argument to the arch= target attribute. */
19316 static bool
19318 {
19321 aarch64_feature_flags tmp_flags;
19322 enum aarch_parse_opt_result parse_res
19326 {
19332 }
19335 {
19350 }
19353 }
19355 /* Handle the argument CPU_STR to the cpu= target attribute. */
19357 static bool
19359 {
19362 aarch64_feature_flags tmp_flags;
19363 enum aarch_parse_opt_result parse_res
19367 {
19374 }
19377 {
19392 }
19395 }
19397 /* Handle the argument STR to the branch-protection= attribute. */
19399 static bool
19401 {
19404 }
19406 /* Handle the argument STR to the tune= target attribute. */
19408 static bool
19410 {
19412 enum aarch_parse_opt_result parse_res
19416 {
19420 }
19423 {
19430 }
19433 }
19435 /* Parse an architecture extensions target attribute string specified in STR.
19436 For example "+fp+nosimd". Show any errors if needed. Return TRUE
19437 if successful. Update aarch64_isa_flags to reflect the ISA features
19438 modified. */
19440 static bool
19442 {
19446 /* We allow "+nothing" in the beginning to clear out all architectural
19447 features if the user wants to handpick specific features. */
19449 {
19452 }
19458 {
19461 }
19464 {
19476 }
19479 }
19481 /* The target attributes that we support. On top of these we also support just
19482 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
19483 handled explicitly in aarch64_process_one_target_attr. */
19486 {
19488 OPT_mgeneral_regs_only },
19490 OPT_mfix_cortex_a53_835769 },
19492 OPT_mfix_cortex_a53_843419 },
19496 OPT_momit_leaf_frame_pointer },
19499 OPT_march_ },
19502 OPT_mtune_ },
19506 OPT_msign_return_address_ },
19508 OPT_moutline_atomics},
19510 };
19512 /* Parse ARG_STR which contains the definition of one target attribute.
19513 Show appropriate errors if any or return true if the attribute is valid. */
19515 static bool
19517 {
19523 {
19526 }
19533 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
19534 It is easier to detect and handle it explicitly here rather than going
19535 through the machinery for the rest of the target attributes in this
19536 function. */
19541 {
19544 }
19547 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
19548 and point ARG to "foo". */
19550 {
19552 arg++;
19553 }
19557 {
19558 /* If the names don't match up, or the user has given an argument
19559 to an attribute that doesn't accept one, or didn't give an argument
19560 to an attribute that expects one, fail to match. */
19569 {
19572 }
19574 /* If the name matches but the attribute does not allow "no-" versions
19575 then we can't match. */
19577 {
19580 }
19583 {
19584 /* Has a custom handler registered.
19585 For example, cpu=, arch=, tune=. */
19592 /* Either set or unset a boolean option. */
19594 {
19602 }
19603 /* Set or unset a bit in the target_flags. aarch64_handle_option
19604 should know what mask to apply given the option number. */
19606 {
19608 /* We only need to specify the option number.
19609 aarch64_handle_option will know which mask to apply. */
19615 }
19616 /* Use the option setting machinery to set an option to an enum. */
19618 {
19625 {
19628 global_dc);
19629 }
19630 else
19631 {
19633 }
19635 }
19638 }
19639 }
19641 /* If we reached here we either have found an attribute and validated
19642 it or didn't match any. If we matched an attribute but its arguments
19643 were malformed we will have returned false already. */
19645 }
19647 /* Count how many times the character C appears in
19648 NULL-terminated string STR. */
19650 static unsigned int
19652 {
19655 {
19657 res++;
19659 str++;
19660 }
19663 }
19665 /* Parse the tree in ARGS that contains the target attribute information
19666 and update the global target options space. */
19668 bool
19670 {
19672 {
19673 do
19674 {
19677 {
19680 }
19685 }
19688 {
19691 }
19700 {
19703 }
19705 /* Used to catch empty spaces between commas i.e.
19706 attribute ((target ("attr1,,attr2"))). */
19709 /* Handle multiple target attributes separated by ','. */
19714 {
19715 num_attrs++;
19717 {
19718 /* Check if token is possibly an arch extension without
19719 leading '+'. */
19722 enum aarch_parse_opt_result ext_res
19727 token);
19728 else
19731 }
19734 }
19737 {
19740 }
19743 }
19747 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
19748 process attribute ((target ("..."))). */
19750 static bool
19752 {
19755 tree old_optimize;
19759 /* If what we're processing is the current pragma string then the
19760 target option node is already stored in target_option_current_node
19761 by aarch64_pragma_target_parse in aarch64-c.cc. Use that to avoid
19762 having to re-parse the string. This is especially useful to keep
19763 arm_neon.h compile times down since that header contains a lot
19764 of intrinsics enclosed in pragmas. */
19766 {
19769 }
19772 old_optimize
19776 /* If the function changed the optimization levels as well as setting
19777 target options, start with the optimizations specified. */
19782 /* Save the current target options to restore at the end. */
19785 /* If fndecl already has some target attributes applied to it, unpack
19786 them so that we add this attribute on top of them, rather than
19787 overwriting them. */
19789 {
19795 existing_options);
19796 }
19797 else
19803 {
19807 {
19808 /* Reapply any target_version attribute after target attribute.
19809 This should be equivalent to applying the target_version once
19810 after processing all target attributes. */
19813 }
19814 }
19816 /* Set up any additional state. */
19818 {
19822 }
19823 else
19830 {
19835 }
19843 }
19848 {
19850 aarch64_fmv_feature_mask feature_mask;
19851 aarch64_feature_flags opt_flags;
19854 #define AARCH64_FMV_FEATURE(NAME, FEAT_NAME, C) \
19855 {NAME, 1ULL << FEAT_##FEAT_NAME, ::feature_deps::fmv_deps_##FEAT_NAME},
19857 /* The "rdma" alias uses a different FEAT_NAME to avoid a duplicate
19858 feature_deps name. */
19859 #define FEAT_RDMA FEAT_RDM
19861 /* FMV features are listed in priority order, to make it easier to sort target
19862 strings. */
19865 };
19867 /* Parse a function multiversioning feature string STR, as found in a
19868 target_version or target_clones attribute.
19870 If ISA_FLAGS is nonnull, then update it with the specified architecture
19871 features turned on. If FEATURE_MASK is nonnull, then assign to it a bitmask
19872 representing the set of features explicitly specified in the feature string.
19873 Return an aarch_parse_opt_result describing the result.
19875 When the STR string contains an invalid or duplicate extension, a copy of
19876 the extension string is created and stored to INVALID_EXTENSION. */
19878 static enum aarch_parse_opt_result
19882 {
19890 {
19898 else
19907 {
19910 {
19914 {
19918 {
19919 /* Duplicate feature. */
19923 }
19924 }
19926 }
19927 }
19930 {
19931 /* Feature not found in list. */
19935 }
19939 /* Skip over the next '+'. */
19940 str++;
19941 }
19944 }
19946 /* Parse the tree in ARGS that contains the target_version attribute
19947 information and update the global target options space. */
19949 static bool
19951 {
19953 {
19955 {
19958 }
19960 }
19963 {
19966 }
19978 {
19981 }
19984 {
19992 str);
19998 str);
20003 }
20006 }
20008 /* Implement TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P. This is used to
20009 process attribute ((target_version ("..."))). */
20011 static bool
20013 {
20016 tree new_target;
20019 /* Save the current target options to restore at the end. */
20022 /* If fndecl already has some target attributes applied to it, unpack
20023 them so that we add this attribute on top of them, rather than
20024 overwriting them. */
20026 {
20032 existing_options);
20033 }
20034 else
20040 /* Set up any additional state. */
20042 {
20046 }
20047 else
20056 }
20058 /* This parses the attribute arguments to target_version in DECL and the
20059 feature mask required to select those targets. No adjustments are made to
20060 add or remove redundant feature requirements. */
20062 static aarch64_fmv_feature_mask
20064 {
20073 aarch64_fmv_feature_mask feature_mask;
20076 NULL);
20078 /* We should have detected any errors before getting here. */
20082 }
20084 /* Compare priorities of two feature masks. Return:
20085 1: mask1 is higher priority
20086 -1: mask2 is higher priority
20087 0: masks are equal. */
20089 static int
20091 aarch64_fmv_feature_mask mask2)
20092 {
20105 {
20109 }
20111 }
20113 /* Compare priorities of two version decls. */
20115 int
20117 {
20122 }
20124 /* Build the struct __ifunc_arg_t type:
20126 struct __ifunc_arg_t
20127 {
20128 unsigned long _size; // Size of the struct, so it can grow.
20129 unsigned long _hwcap;
20130 unsigned long _hwcap2;
20131 }
20132 */
20134 static tree
20136 {
20140 long_unsigned_type_node);
20143 long_unsigned_type_node);
20146 long_unsigned_type_node);
20162 }
20164 /* Implement TARGET_MANGLE_DECL_ASSEMBLER_NAME, to add function multiversioning
20165 suffixes. */
20167 tree
20169 {
20170 /* For function version, add the target suffix to the assembler name. */
20173 {
20178 /* For the default version, append ".default". */
20180 {
20183 }
20189 {
20191 {
20194 }
20195 }
20201 }
20203 }
20205 /* Return an identifier for the base assembler name of a versioned function.
20206 This is computed by taking the default version's assembler name, and
20207 stripping off the ".default" suffix if it's already been appended. */
20209 static tree
20211 {
20219 }
20221 /* Make the resolver function decl to dispatch the versions of
20222 a multi-versioned function, DEFAULT_DECL. IFUNC_ALIAS_DECL is
20223 ifunc alias that will point to the created resolver. Create an
20224 empty basic block in the resolver and store the pointer in
20225 EMPTY_BB. Return the decl of the resolver function. */
20227 static tree
20231 {
20234 /* Create resolver function name based on default_decl. We need to remove an
20235 existing ".default" suffix if this has already been appended. */
20239 /* The resolver function should have signature
20240 (void *) resolver (uint64_t, const __ifunc_arg_t *) */
20242 uint64_type_node,
20244 NULL_TREE);
20256 /* Resolver is not external, body is generated. */
20266 {
20267 /* In this case, each translation unit with a call to this
20268 versioned function will put out a resolver. Ensure it
20269 is comdat to keep just one copy. */
20272 }
20273 else
20276 /* Build result decl and add to function_decl. */
20283 /* Build parameter decls and add to function_decl. */
20286 uint64_type_node);
20312 /* Mark ifunc_alias_decl as "ifunc" with resolver as resolver_name. */
20317 /* Create the alias for dispatch to resolver here. */
20320 }
20322 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
20323 to return a pointer to VERSION_DECL if all feature bits specified in
20324 FEATURE_MASK are not set in MASK_VAR. This function will be called during
20325 version dispatch to decide which function version to execute. It returns
20326 the basic block at the end, to which more conditions can be added. */
20327 static basic_block
20329 aarch64_fmv_feature_mask feature_mask,
20331 {
20340 gimple_seq gseq;
20354 {
20355 /* Default version. */
20363 }
20367 long_long_unsigned_type_node,
20368 mask_var,
20370 feature_mask));
20407 }
20409 /* This function generates the dispatch function for
20410 multi-versioned functions. DISPATCH_DECL is the function which will
20411 contain the dispatch logic. FNDECLS are the function choices for
20412 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
20413 in DISPATCH_DECL in which the dispatch code is generated. */
20415 static int
20419 {
20421 gimple_seq gseq;
20431 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
20432 constructors, so explicity call __init_cpu_features_resolver here. */
20434 long_unsigned_type_node,
20436 NULL);
20446 /* Build the struct type for __aarch64_cpu_features. */
20450 long_long_unsigned_type_node);
20457 global_type);
20478 /* fndecls_p is actually a vector. */
20481 /* At least one more version other than the default. */
20485 struct function_version_info
20486 {
20487 tree version_decl;
20488 aarch64_fmv_feature_mask feature_mask;
20497 {
20498 aarch64_fmv_feature_mask feature_mask;
20499 /* Get attribute string, parse it and find the right features. */
20503 actual_versions++;
20504 }
20510 };
20512 /* Sort the versions according to descending order of dispatch priority. */
20520 mask_var,
20525 }
20527 /* Implement TARGET_GENERATE_VERSION_DISPATCHER_BODY. */
20529 tree
20531 {
20532 tree resolver_decl;
20533 basic_block empty_bb;
20534 tree default_ver_decl;
20550 /* The first version in the chain corresponds to the default version. */
20553 /* node is going to be an alias, so remove the finalized bit. */
20567 {
20569 /* Check for virtual functions here again, as by this time it should
20570 have been determined if this function needs a vtable index or
20571 not. This happens for methods in derived classes that override
20572 virtual methods in base classes but are not explicitly marked as
20573 virtual. */
20578 }
20584 /* Fix up symbol names. First we need to obtain the base name, which may
20585 have already been mangled. */
20588 /* We need to redo the version mangling on the non-default versions for the
20589 target_clones case. Redoing the mangling for the target_version case is
20590 redundant but does no harm. We need to skip the default version, because
20591 expand_clones will append ".default" later; fortunately that suffix is the
20592 one we want anyway. */
20595 {
20598 base_name);
20600 }
20602 /* We also need to use the base name for the ifunc declaration. */
20606 }
20608 /* Make a dispatcher declaration for the multi-versioned function DECL.
20609 Calls to DECL function will be replaced with calls to the dispatcher
20610 by the front-end. Returns the decl of the dispatcher function. */
20612 tree
20614 {
20636 /* Find the default version and make it the first node. */
20638 /* Go to the beginning of the chain. */
20643 {
20648 }
20650 /* If there is no default node, just return NULL. */
20654 /* Make default info the first node. */
20656 {
20663 }
20668 {
20673 /* Right now, the dispatching is done via ifunc. */
20680 dispatcher_version_info
20685 /* Set the dispatcher for all the versions. */
20688 {
20691 }
20692 }
20693 else
20694 {
20696 "multiversioning needs %<ifunc%> which is not supported "
20698 }
20701 }
20703 /* This function returns true if FN1 and FN2 are versions of the same function,
20704 that is, the target_version attributes of the function decls are different.
20705 This assumes that FN1 and FN2 have the same signature. */
20707 bool
20709 {
20715 }
20717 /* Implement TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P. Use an opt-out
20718 rather than an opt-in list. */
20720 static bool
20722 {
20723 /* A function that has local SME state cannot be inlined into its caller,
20724 since we only support managing PSTATE.ZA switches at function scope. */
20727 }
20729 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
20730 tri-bool options (yes, no, don't care) and the default value is
20731 DEF, determine whether to reject inlining. */
20733 static bool
20736 {
20737 /* If the callee doesn't care, always allow inlining. */
20741 /* If the caller doesn't care, always allow inlining. */
20745 /* Otherwise, allow inlining if either the callee and caller values
20746 agree, or if the callee is using the default value. */
20748 }
20750 /* Bit allocations for ipa_fn_summary::target_info. */
20752 /* Set if the function contains a stmt that relies on the function's
20753 choice of PSTATE.SM setting (0 for non-streaming, 1 for streaming).
20754 Not meaningful for streaming-compatible functions. */
20757 /* Set if the function clobbers ZA and ZT0. Not meaningful for functions that
20758 have ZA state. */
20762 /* Implement TARGET_NEED_IPA_FN_TARGET_INFO. */
20764 static bool
20766 {
20767 /* We could in principle skip this for streaming-compatible functions
20768 that have ZA state, but that's a rare combination. */
20770 }
20772 /* Implement TARGET_UPDATE_IPA_FN_TARGET_INFO. */
20774 static bool
20776 {
20778 {
20779 /* We don't know what the asm does, so conservatively assume that
20780 it requires the function's current SM mode. */
20783 {
20790 }
20791 }
20793 {
20795 {
20796 /* The attributes on AArch64 builtins are supposed to be accurate.
20797 If the function isn't marked streaming-compatible then it
20798 needs whichever SM mode it selects. */
20802 }
20803 }
20805 }
20807 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
20808 to inline CALLEE into CALLER based on target-specific info.
20809 Make sure that the caller and callee have compatible architectural
20810 features. Then go through the other possible target attributes
20811 and see if they can block inlining. Try not to reject always_inline
20812 callees unless they are incompatible architecturally. */
20814 static bool
20816 {
20828 /* Callee's ISA flags should be a subset of the caller's. */
20843 /* Return true if the callee might have target_info property PROPERTY.
20844 The answer must be true unless we have positive proof to the contrary. */
20846 {
20852 };
20854 /* Streaming-compatible code can be inlined into functions with any
20855 PSTATE.SM mode. Otherwise the caller and callee must agree on
20856 PSTATE.SM mode, unless we can prove that the callee is naturally
20857 streaming-compatible. */
20865 /* aarch64_function_attribute_inlinable_p prevents new-ZA and new-ZT0
20866 functions from being inlined into others. We also need to prevent
20867 inlining of shared-ZA functions into functions without ZA state,
20868 since this is an error condition.
20870 The only other problematic case for ZA is inlining a function that
20871 directly clobbers ZA or ZT0 into a function that has ZA or ZT0 state. */
20885 /* Allow non-strict aligned functions inlining into strict
20886 aligned ones. */
20896 /* If the architectural features match up and the callee is always_inline
20897 then the other attributes don't matter. */
20909 /* Honour explicit requests to workaround errata. */
20922 /* If the user explicitly specified -momit-leaf-frame-pointer for the
20923 caller and calle and they don't match up, reject inlining. */
20930 /* If the callee has specific tuning overrides, respect them. */
20935 /* If the user specified tuning override strings for the
20936 caller and callee and they don't match up, reject inlining.
20937 We just do a string compare here, we don't analyze the meaning
20938 of the string, as it would be too costly for little gain. */
20946 }
20948 /* Return the ID of the TLDESC ABI, initializing the descriptor if hasn't
20949 been already. */
20951 arm_pcs
20953 {
20956 {
20957 HARD_REG_SET full_reg_clobbers;
20964 }
20966 }
20968 /* Return true if SYMBOL_REF X binds locally. */
20970 static bool
20972 {
20976 }
20978 /* Return true if SYMBOL_REF X is thread local */
20979 static bool
20981 {
20990 }
20992 /* Classify a TLS symbol into one of the TLS kinds. */
20993 enum aarch64_symbol_type
20995 {
20999 {
21006 {
21012 }
21023 else
21032 }
21033 }
21035 /* Return the correct method for accessing X + OFFSET, where X is either
21036 a SYMBOL_REF or LABEL_REF. */
21038 enum aarch64_symbol_type
21040 {
21044 {
21046 {
21061 }
21062 }
21065 {
21070 {
21073 /* With -fPIC non-local symbols use the GOT. For orthogonality
21074 always use the GOT for extern weak symbols. */
21079 /* When we retrieve symbol + offset address, we have to make sure
21080 the offset does not cause overflow of the final address. But
21081 we have no way of knowing the address of symbol at compile time
21082 so we can't accurately say if the distance between the PC and
21083 symbol + offset is outside the addressible range of +/-1MB in the
21084 TINY code model. So we limit the maximum offset to +/-64KB and
21085 assume the offset to the symbol is not larger than +/-(1MB - 64KB).
21086 If offset_within_block_p is true we allow larger offsets. */
21102 /* Same reasoning as the tiny code model, but the offset cap here is
21103 1MB, allowing +/-3.9GB for the offset to the symbol. */
21111 /* This is alright even in PIC code as the constant
21112 pool reference is always PC relative and within
21113 the same translation unit. */
21116 else
21121 }
21122 }
21124 /* By default push everything into the constant pool. */
21126 }
21128 bool
21130 {
21132 }
21134 bool
21136 {
21137 poly_int64 offset;
21143 }
21145 /* Implement TARGET_LEGITIMATE_CONSTANT_P hook. Return true for constants
21146 that should be rematerialized rather than spilled. */
21148 static bool
21150 {
21151 /* Support CSE and rematerialization of common constants. */
21156 /* Only accept variable-length vector constants if they can be
21157 handled directly.
21159 ??? It would be possible (but complex) to handle rematerialization
21160 of other constants via secondary reloads. */
21164 /* Otherwise, accept any CONST_VECTOR that, if all else fails, can at
21165 least be forced to memory and loaded from there. */
21169 /* Do not allow vector struct mode constants for Advanced SIMD.
21170 We could support 0 and -1 easily, but they need support in
21171 aarch64-simd.md. */
21179 /* Accept polynomial constants that can be calculated by using the
21180 destination of a move as the sole temporary. Constants that
21181 require a second temporary cannot be rematerialized (they can't be
21182 forced to memory and also aren't legitimate constants). */
21183 poly_int64 offset;
21187 /* If an offset is being added to something else, we need to allow the
21188 base to be moved into the destination register, meaning that there
21189 are no free temporaries for the offset. */
21194 /* Do not allow const (plus (anchor_symbol, const_int)). */
21198 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
21199 so spilling them is better than rematerialization. */
21203 /* Label references are always constant. */
21208 }
21210 rtx
21212 {
21218 /* Can return in any reg. */
21221 }
21223 /* On AAPCS systems, this is the "struct __va_list". */
21226 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
21227 Return the type to use as __builtin_va_list.
21229 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
21231 struct __va_list
21232 {
21233 void *__stack;
21234 void *__gr_top;
21235 void *__vr_top;
21236 int __gr_offs;
21237 int __vr_offs;
21238 }; */
21240 static tree
21242 {
21243 tree va_list_name;
21246 /* Create the type. */
21248 /* Give it the required name. */
21250 TYPE_DECL,
21252 va_list_type);
21257 /* Create the fields. */
21260 ptr_type_node);
21263 ptr_type_node);
21266 ptr_type_node);
21269 integer_type_node);
21272 integer_type_node);
21274 /* Tell tree-stdarg pass about our internal offset fields.
21275 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
21276 purpose to identify whether the code is updating va_list internal
21277 offset fields through irregular way. */
21299 /* Compute its layout. */
21303 }
21305 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
21306 static void
21308 {
21312 tree t;
21326 {
21329 }
21338 NULL_TREE);
21340 NULL_TREE);
21342 NULL_TREE);
21344 NULL_TREE);
21346 NULL_TREE);
21348 /* Emit code to initialize STACK, which points to the next varargs stack
21349 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
21350 by named arguments. STACK is 8-byte aligned. */
21357 /* Emit code to initialize GRTOP, the top of the GR save area.
21358 virtual_incoming_args_rtx should have been 16 byte aligned. */
21363 /* Emit code to initialize VRTOP, the top of the VR save area.
21364 This address is gr_save_area_bytes below GRTOP, rounded
21365 down to the next 16-byte boundary. */
21375 /* Emit code to initialize GROFF, the offset from GRTOP of the
21376 next GPR argument. */
21381 /* Likewise emit code to initialize VROFF, the offset from FTOP
21382 of the next VR argument. */
21386 }
21388 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
21390 static tree
21393 {
21394 tree addr;
21400 machine_mode mode;
21426 align
21435 {
21436 /* No frontends can create types with variable-sized modes, so we
21437 shouldn't be asked to pass or return them. */
21440 /* TYPE passed in fp/simd registers. */
21452 {
21455 }
21458 {
21460 }
21461 }
21462 else
21463 {
21464 /* TYPE passed in general registers. */
21473 && abi_break_gcc_13
21474 && warn_psabi
21480 && abi_break_gcc_14
21487 {
21489 && warn_psabi
21494 }
21498 {
21500 }
21501 }
21503 /* Get a local temporary for the field value. */
21506 /* Emit code to branch if off >= 0. */
21512 {
21513 /* Emit: offs = (offs + 15) & -16. */
21519 }
21520 else
21523 /* Update ap.__[g|v]r_offs */
21528 /* String up. */
21532 /* [cond2] if (ap.__[g|v]r_offs > 0) */
21537 /* String up: make sure the assignment happens before the use. */
21541 /* Prepare the trees handling the argument that is passed on the stack;
21542 the top level node will store in ON_STACK. */
21545 {
21546 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
21551 }
21552 else
21554 /* Advance ap.__stack */
21559 /* String up roundup and advance. */
21562 /* String up with arg */
21564 /* Big-endianness related address adjustment. */
21567 {
21571 }
21576 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
21586 {
21587 /* type ha; // treat as "struct {ftype field[n];}"
21588 ... [computing offs]
21589 for (i = 0; i <nregs; ++i, offs += 16)
21590 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
21591 return ha; */
21595 /* Declare a local variable. */
21599 /* Establish the base type. */
21601 {
21636 {
21640 }
21644 }
21646 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
21655 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
21657 {
21667 }
21671 }
21681 }
21683 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
21685 static void
21689 {
21691 CUMULATIVE_ARGS local_cum;
21695 /* The caller has advanced CUM up to, but not beyond, the last named
21696 argument. Advance a local copy of CUM past the last "real" named
21697 argument, to find out how many registers are left over. */
21702 /* Found out how many registers we need to save.
21703 Honor tree-stdvar analysis results. */
21712 {
21715 }
21718 {
21720 {
21723 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
21731 }
21733 {
21734 /* We can't use move_block_from_reg, because it will use
21735 the wrong mode, storing D regs only. */
21739 /* Set OFF to the offset from virtual_incoming_args_rtx of
21740 the first vector register. The VR save area lies below
21741 the GR one, and is aligned to 16 bytes. */
21748 {
21756 }
21757 }
21758 }
21760 /* We don't save the size into *PRETEND_SIZE because we want to avoid
21761 any complication of having crtl->args.pretend_args_size changed. */
21766 }
21768 static void
21770 {
21773 {
21775 {
21779 }
21780 }
21783 {
21786 }
21788 /* Only allow these registers to be accessed via special patterns. */
21795 /* When tracking speculation, we need a couple of call-clobbered registers
21796 to track the speculation state. It would be nice to just use
21797 IP0 and IP1, but currently there are numerous places that just
21798 assume these registers are free for other uses (eg pointer
21799 authentication). */
21801 {
21806 }
21807 }
21809 /* Implement TARGET_MEMBER_TYPE_FORCES_BLK. */
21811 bool
21813 {
21814 /* For records we're passed a FIELD_DECL, for arrays we're passed
21815 an ARRAY_TYPE. In both cases we're interested in the TREE_TYPE. */
21818 /* Assign BLKmode to anything that contains more than 2 SVE predicates.
21819 For structures, the "multiple" case is indicated by MODE being
21820 VOIDmode. */
21823 {
21828 }
21831 }
21833 /* Bitmasks that indicate whether earlier versions of GCC would have
21834 taken a different path through the ABI logic. This should result in
21835 a -Wpsabi warning if the earlier path led to a different ABI decision.
21837 WARN_PSABI_EMPTY_CXX17_BASE
21838 Indicates that the type includes an artificial empty C++17 base field
21839 that, prior to GCC 10.1, would prevent the type from being treated as
21840 a HFA or HVA. See PR94383 for details.
21842 WARN_PSABI_NO_UNIQUE_ADDRESS
21843 Indicates that the type includes an empty [[no_unique_address]] field
21844 that, prior to GCC 10.1, would prevent the type from being treated as
21845 a HFA or HVA. */
21850 /* Walk down the type tree of TYPE counting consecutive base elements.
21851 If *MODEP is VOIDmode, then set it to the first valid floating point
21852 type. If a non-floating point type is found, or if a floating point
21853 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
21854 otherwise return the count in the sub-tree.
21856 The WARN_PSABI_FLAGS argument allows the caller to check whether this
21857 function has changed its behavior relative to earlier versions of GCC.
21858 Normally the argument should be nonnull and point to a zero-initialized
21859 variable. The function then records whether the ABI decision might
21860 be affected by a known fix to the ABI logic, setting the associated
21861 WARN_PSABI_* bits if so.
21863 When the argument is instead a null pointer, the function tries to
21864 simulate the behavior of GCC before all such ABI fixes were made.
21865 This is useful to check whether the function returns something
21866 different after the ABI fixes. */
21867 static int
21870 {
21871 machine_mode mode;
21872 HOST_WIDE_INT size;
21878 {
21909 /* Use V2SImode and V4SImode as representatives of all 64-bit
21910 and 128-bit vector types. */
21913 {
21922 }
21927 /* Vector modes are considered to be opaque: two vectors are
21928 equivalent for the purposes of being homogeneous aggregates
21929 if they are the same size. */
21936 {
21940 /* Can't handle incomplete types nor sizes that are not
21941 fixed. */
21947 warn_psabi_flags);
21949 || !index
21960 /* There must be no padding. */
21966 }
21969 {
21972 tree field;
21974 /* Can't handle incomplete types nor sizes that are not
21975 fixed. */
21981 {
21986 {
21987 /* See whether this is something that earlier versions of
21988 GCC failed to ignore. */
21995 else
21996 /* No compatibility problem. */
21999 /* Simulate the old behavior when WARN_PSABI_FLAGS is null. */
22001 {
22004 }
22005 }
22006 /* A zero-width bitfield may affect layout in some
22007 circumstances, but adds no members. The determination
22008 of whether or not a type is an HFA is performed after
22009 layout is complete, so if the type still looks like an
22010 HFA afterwards, it is still classed as one. This is
22011 potentially an ABI break for the hard-float ABI. */
22014 {
22015 /* Prior to GCC-12 these fields were striped early,
22016 hiding them from the back-end entirely and
22017 resulting in the correct behaviour for argument
22018 passing. Simulate that old behaviour without
22019 generating a warning. */
22023 {
22026 }
22027 }
22030 warn_psabi_flags);
22034 }
22036 /* There must be no padding. */
22042 }
22046 {
22047 /* These aren't very interesting except in a degenerate case. */
22050 tree field;
22052 /* Can't handle incomplete types nor sizes that are not
22053 fixed. */
22059 {
22064 warn_psabi_flags);
22068 }
22070 /* There must be no padding. */
22076 }
22080 }
22083 }
22085 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
22086 type as described in AAPCS64 \S 4.1.2.
22088 See the comment above aarch64_composite_type_p for the notes on MODE. */
22090 static bool
22092 machine_mode mode)
22093 {
22097 {
22101 }
22104 {
22105 /* The containing "else if" is too loose: it means that we look at TYPE
22106 if the type is a vector type (good), but that we otherwise ignore TYPE
22107 and look only at the mode. This is wrong because the type describes
22108 the language-level information whereas the mode is purely an internal
22109 GCC concept. We can therefore reach here for types that are not
22110 vectors in the AAPCS64 sense.
22112 We can't "fix" that for the traditional Advanced SIMD vector modes
22113 without breaking backwards compatibility. However, there's no such
22114 baggage for the structure modes, which were introduced in GCC 12. */
22118 /* For similar reasons, rely only on the type, not the mode, when
22119 processing SVE types. */
22121 /* Leave later code to report an error if SVE is disabled. */
22123 else
22125 }
22127 {
22128 /* 64-bit and 128-bit vectors should only acquire an SVE mode if
22129 they are being treated as scalable AAPCS64 types. */
22133 }
22135 }
22137 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
22138 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
22139 array types. The C99 floating-point complex types are also considered
22140 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
22141 types, which are GCC extensions and out of the scope of AAPCS64, are
22142 treated as composite types here as well.
22144 Note that MODE itself is not sufficient in determining whether a type
22145 is such a composite type or not. This is because
22146 stor-layout.cc:compute_record_mode may have already changed the MODE
22147 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
22148 structure with only one field may have its MODE set to the mode of the
22149 field. Also an integer mode whose size matches the size of the
22150 RECORD_TYPE type may be used to substitute the original mode
22151 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
22152 solely relied on. */
22154 static bool
22156 machine_mode mode)
22157 {
22175 }
22177 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
22178 shall be passed or returned in simd/fp register(s) (providing these
22179 parameter passing registers are available).
22181 Upon successful return, *COUNT returns the number of needed registers,
22182 *BASE_MODE returns the mode of the individual register and when IS_HA
22183 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
22184 floating-point aggregate or a homogeneous short-vector aggregate.
22186 SILENT_P is true if the function should refrain from reporting any
22187 diagnostics. This should only be used if the caller is certain that
22188 any ABI decisions would eventually come through this function with
22189 SILENT_P set to false. */
22191 static bool
22193 const_tree type,
22198 {
22208 {
22211 }
22213 {
22217 }
22219 {
22224 {
22229 && warn_psabi
22230 && warn_psabi_flags
22234 {
22241 /* Use TYPE_MAIN_VARIANT to strip any redundant const
22242 qualification. */
22245 "type %qT with %<[[no_unique_address]]%> members "
22250 "type %qT when C++17 is enabled changed to match "
22257 }
22261 }
22262 else
22264 }
22265 else
22271 }
22273 /* Implement TARGET_STRUCT_VALUE_RTX. */
22275 static rtx
22278 {
22280 }
22282 /* Implements target hook vector_mode_supported_p. */
22283 static bool
22285 {
22288 }
22290 /* Implements target hook vector_mode_supported_any_target_p. */
22291 static bool
22293 {
22296 }
22298 /* Return the full-width SVE vector mode for element mode MODE, if one
22299 exists. */
22300 opt_machine_mode
22302 {
22304 {
22323 }
22324 }
22326 /* Return the 128-bit Advanced SIMD vector mode for element mode MODE,
22327 if it exists. */
22328 opt_machine_mode
22330 {
22332 {
22351 }
22352 }
22354 /* Return appropriate SIMD container
22355 for MODE within a vector of WIDTH bits. */
22356 static machine_mode
22358 {
22366 {
22369 else
22371 {
22386 }
22387 }
22389 }
22391 /* Compare an SVE mode SVE_M and an Advanced SIMD mode ASIMD_M
22392 and return whether the SVE mode should be preferred over the
22393 Advanced SIMD one in aarch64_autovectorize_vector_modes. */
22394 static bool
22396 {
22397 /* Take into account the aarch64-autovec-preference param if non-zero. */
22406 /* The preference in case of a tie in costs. */
22412 /* If the CPU information does not have an SVE width registered use the
22413 generic poly_int comparison that prefers SVE. If a preference is
22414 explicitly requested avoid this path. */
22416 && !prefer_asimd
22420 /* Otherwise estimate the runtime width of the modes involved. */
22424 /* Preferring SVE means picking it first unless the Advanced SIMD mode
22425 is clearly wider. */
22428 /* Conversely, preferring Advanced SIMD means picking SVE only if SVE
22429 is clearly wider. */
22433 /* In the default case prefer Advanced SIMD over SVE in case of a tie. */
22435 }
22437 /* Return 128-bit container as the preferred SIMD mode for MODE. */
22438 static machine_mode
22440 {
22441 /* Take into account explicit auto-vectorization ISA preferences through
22442 aarch64_cmp_autovec_modes. */
22448 }
22450 /* Return a list of possible vector sizes for the vectorizer
22451 to iterate over. */
22452 static unsigned int
22454 {
22456 /* Try using full vectors for all element types. */
22457 VNx16QImode,
22459 /* Try using 16-bit containers for 8-bit elements and full vectors
22460 for wider elements. */
22461 VNx8QImode,
22463 /* Try using 32-bit containers for 8-bit and 16-bit elements and
22464 full vectors for wider elements. */
22465 VNx4QImode,
22467 /* Try using 64-bit containers for all element types. */
22468 VNx2QImode
22469 };
22472 /* Try using 128-bit vectors for all element types. */
22473 V16QImode,
22475 /* Try using 64-bit vectors for 8-bit elements and 128-bit vectors
22476 for wider elements. */
22477 V8QImode,
22479 /* Try using 64-bit vectors for 16-bit elements and 128-bit vectors
22480 for wider elements.
22482 TODO: We could support a limited form of V4QImode too, so that
22483 we use 32-bit vectors for 8-bit elements. */
22484 V4HImode,
22486 /* Try using 64-bit vectors for 32-bit elements and 128-bit vectors
22487 for 64-bit elements.
22489 TODO: We could similarly support limited forms of V2QImode and V2HImode
22490 for this case. */
22491 V2SImode
22492 };
22494 /* Try using N-byte SVE modes only after trying N-byte Advanced SIMD mode.
22495 This is because:
22497 - If we can't use N-byte Advanced SIMD vectors then the placement
22498 doesn't matter; we'll just continue as though the Advanced SIMD
22499 entry didn't exist.
22501 - If an SVE main loop with N bytes ends up being cheaper than an
22502 Advanced SIMD main loop with N bytes then by default we'll replace
22503 the Advanced SIMD version with the SVE one.
22505 - If an Advanced SIMD main loop with N bytes ends up being cheaper
22506 than an SVE main loop with N bytes then by default we'll try to
22507 use the SVE loop to vectorize the epilogue instead. */
22516 {
22521 else
22523 }
22531 }
22533 /* Implement TARGET_MANGLE_TYPE. */
22537 {
22538 /* The AArch64 ABI documents say that "__va_list" has to be
22539 mangled as if it is in the "std" namespace. */
22543 /* Half-precision floating point types. */
22545 {
22550 else
22552 }
22554 /* Modal 8 bit floating point types. */
22558 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
22559 builtin types. */
22561 {
22566 }
22568 /* Use the default mangling. */
22570 }
22572 /* Implement TARGET_INVALID_CONVERSION. */
22576 {
22577 /* Do not allow conversions to/from FP8. But do allow conversions between
22578 volatile and const variants of __mfp8. */
22579 bool fromtype_is_fp8
22591 /* Conversion allowed. */
22593 }
22595 /* Implement TARGET_VERIFY_TYPE_CONTEXT. */
22597 static bool
22600 {
22602 }
22604 /* Find the first rtx_insn before insn that will generate an assembly
22605 instruction. */
22609 {
22613 do
22614 {
22616 }
22620 }
22622 static bool
22624 {
22626 /* A number of these may be AArch32 only. */
22631 };
22634 {
22637 }
22640 }
22642 /* Check if there is a register dependency between a load and the insn
22643 for which we hold recog_data. */
22645 static bool
22647 {
22648 rtx load_reg;
22658 {
22664 }
22666 }
22669 /* When working around the Cortex-A53 erratum 835769,
22670 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
22671 instruction and has a preceding memory instruction such that a NOP
22672 should be inserted between them. */
22674 bool
22676 {
22679 rtx body;
22692 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
22693 Restore recog state to INSN to avoid state corruption. */
22701 /* If the previous insn is a memory op and there is no dependency between
22702 it and the DImode madd, emit a NOP between them. If body is NULL then we
22703 have a complex memory operation, probably a load/store pair.
22704 Be conservative for now and emit a NOP. */
22711 }
22714 /* Implement FINAL_PRESCAN_INSN. */
22716 void
22718 {
22721 }
22724 /* Return true if BASE_OR_STEP is a valid immediate operand for an SVE INDEX
22725 instruction. */
22727 bool
22729 {
22732 }
22734 /* Return true if X is a valid immediate for the SVE ADD and SUB instructions
22735 when applied to mode MODE. Negate X first if NEGATE_P is true. */
22737 bool
22739 {
22752 }
22754 /* Return true if X is a valid immediate for the SVE SQADD and SQSUB
22755 instructions when applied to mode MODE. Negate X first if NEGATE_P
22756 is true. */
22758 bool
22760 {
22764 /* After the optional negation, the immediate must be nonnegative.
22765 E.g. a saturating add of -127 must be done via SQSUB Zn.B, Zn.B, #127
22766 instead of SQADD Zn.B, Zn.B, #129. */
22769 }
22771 /* Return true if X is a valid immediate operand for an SVE logical
22772 instruction such as AND. */
22774 bool
22776 {
22777 rtx elt;
22783 }
22785 /* Return true if X is a valid immediate for the SVE DUP and CPY
22786 instructions. */
22788 bool
22790 {
22799 }
22801 /* Return true if X is a valid immediate operand for an SVE CMP instruction.
22802 SIGNED_P says whether the operand is signed rather than unsigned. */
22804 bool
22806 {
22809 && (signed_p
22812 }
22814 /* Return true if X is a valid immediate operand for an SVE FADD or FSUB
22815 instruction. Negate X first if NEGATE_P is true. */
22817 bool
22819 {
22820 rtx elt;
22821 REAL_VALUE_TYPE r;
22837 }
22839 /* Return true if X is a valid immediate operand for an SVE FMUL
22840 instruction. */
22842 bool
22844 {
22845 rtx elt;
22851 }
22853 /* Return true if replicating VAL32 is a valid 2-byte or 4-byte immediate
22854 for the Advanced SIMD operation described by WHICH and INSN. If INFO
22855 is nonnull, use it to describe valid immediates. */
22856 static bool
22861 {
22862 /* Try a 4-byte immediate with LSL. */
22865 {
22870 }
22872 /* Try a 2-byte immediate with LSL. */
22877 {
22882 }
22884 /* Try a 4-byte immediate with MSL, except for cases that MVN
22885 can handle. */
22888 {
22891 {
22896 }
22897 }
22900 }
22902 /* Return true if replicating VAL64 is a valid immediate for the
22903 Advanced SIMD operation described by WHICH. If INFO is nonnull,
22904 use it to describe valid immediates. */
22905 static bool
22909 {
22915 {
22926 /* Try using a replicated byte. */
22930 {
22934 }
22935 }
22937 /* Try using a bit-to-bytemask. */
22939 {
22942 {
22946 }
22948 {
22952 }
22953 }
22955 }
22957 /* Return true if replicating VAL64 gives a valid immediate for an SVE MOV
22958 instruction. If INFO is nonnull, use it to describe valid immediates. */
22960 static bool
22963 {
22967 {
22971 {
22976 }
22977 }
22980 {
22981 /* DUP with no shift. */
22985 }
22987 {
22988 /* DUP with LSL #8. */
22992 }
22994 {
22995 /* DUPM. */
22999 }
23001 }
23003 /* Return true if X is an UNSPEC_PTRUE constant of the form:
23005 (const (unspec [PATTERN ZERO] UNSPEC_PTRUE))
23007 where PATTERN is the svpattern as a CONST_INT and where ZERO
23008 is a zero constant of the required PTRUE mode (which can have
23009 fewer elements than X's mode, if zero bits are significant).
23011 If so, and if INFO is nonnull, describe the immediate in INFO. */
23012 bool
23014 {
23023 {
23024 aarch64_svpattern pattern
23029 }
23031 }
23033 /* Return true if X is a valid SVE predicate. If INFO is nonnull, use
23034 it to describe valid immediates. */
23036 static bool
23038 {
23043 {
23047 }
23049 /* Analyze the value as a VNx16BImode. This should be relatively
23050 efficient, since rtx_vector_builder has enough built-in capacity
23051 to store all VLA predicate constants without needing the heap. */
23052 rtx_vector_builder builder;
23058 {
23062 {
23064 {
23067 }
23069 }
23070 }
23072 }
23074 /* Return true if OP is a valid SIMD immediate for the operation
23075 described by WHICH. If INFO is nonnull, use it to describe valid
23076 immediates. */
23077 bool
23080 {
23102 && TARGET_SVE
23104 {
23111 {
23112 /* Get the corresponding container mode. E.g. an INDEX on V2SI
23113 should yield two integer values per 128-bit block, meaning
23114 that we need to treat it in the same way as V2DI and then
23115 ignore the upper 32 bits of each element. */
23118 }
23120 }
23124 else
23127 scalar_float_mode elt_float_mode;
23130 {
23134 {
23138 }
23139 }
23141 /* If all elements in an SVE vector have the same value, we have a free
23142 choice between using the element mode and using the container mode.
23143 Using the element mode means that unused parts of the vector are
23144 duplicates of the used elements, while using the container mode means
23145 that the unused parts are an extension of the used elements. Using the
23146 element mode is better for (say) VNx4HI 0x101, since 0x01010101 is valid
23147 for its container mode VNx4SI while 0x00000101 isn't.
23149 If not all elements in an SVE vector have the same value, we need the
23150 transition from one element to the next to occur at container boundaries.
23151 E.g. a fixed-length VNx4HI containing { 1, 2, 3, 4 } should be treated
23152 in the same way as a VNx4SI containing { 1, 2, 3, 4 }. */
23153 scalar_int_mode elt_int_mode;
23156 else
23163 /* Expand the vector constant out into a byte vector, with the least
23164 significant byte of the register first. */
23168 {
23169 /* The vector is provided in gcc endian-neutral fashion.
23170 For aarch64_be Advanced SIMD, it must be laid out in the vector
23171 register in reverse order. */
23183 {
23186 }
23187 }
23189 /* The immediate must repeat every eight bytes. */
23195 /* Get the repeating 8-byte value as an integer. No endian correction
23196 is needed here because bytes is already in lsb-first order. */
23204 else
23206 }
23208 /* Check whether X is a VEC_SERIES-like constant that starts at 0 and
23209 has a step in the range of INDEX. Return the index expression if so,
23210 otherwise return null. */
23211 rtx
23213 {
23220 }
23222 /* Check of immediate shift constants are within range. */
23223 bool
23225 {
23232 else
23234 }
23236 /* Return the bitmask CONST_INT to select the bits required by a zero extract
23237 operation of width WIDTH at bit position POS. */
23239 rtx
23241 {
23245 unsigned HOST_WIDE_INT mask
23248 }
23250 bool
23252 {
23261 {
23262 /* Require predicate constants to be VNx16BI before RA, so that we
23263 force everything to have a canonical form. */
23265 && !reload_completed
23272 }
23274 /* Remove UNSPEC_SALT_ADDR before checking symbol reference. */
23277 /* GOT accesses are valid moves. */
23295 }
23297 /* Return a function-invariant register that contains VALUE. *CACHED_INSN
23298 caches instructions that set up such registers, so that they can be
23299 reused by future calls. */
23301 static rtx
23303 {
23306 {
23309 {
23315 }
23316 }
23319 function_beg_insn);
23321 }
23323 /* Create a 0 constant that is based on V4SI to allow CSE to optimally share
23324 the constant creation. */
23326 rtx
23328 {
23332 }
23334 /* INSN is some form of extension or shift that can be split into a
23335 permutation involving a shared zero. Return true if we should
23336 perform such a split.
23338 ??? For now, make sure that the split instruction executes more
23339 frequently than the zero that feeds it. In future it would be good
23340 to split without that restriction and instead recombine shared zeros
23341 if they turn out not to be worthwhile. This would allow splits in
23342 single-block functions and would also cope more naturally with
23343 rematerialization. The downside of not doing this is that we lose the
23344 optimizations for vector epilogues as well. */
23346 bool
23348 {
23353 }
23355 /* Return a const_int vector of VAL. */
23356 rtx
23358 {
23361 }
23363 /* Check OP is a legal scalar immediate for the MOVI instruction. */
23365 bool
23367 {
23368 machine_mode vmode;
23373 }
23375 /* Construct and return a PARALLEL RTX vector with elements numbering the
23376 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
23377 the vector - from the perspective of the architecture. This does not
23378 line up with GCC's perspective on lane numbers, so we end up with
23379 different masks depending on our target endian-ness. The diagram
23380 below may help. We must draw the distinction when building masks
23381 which select one half of the vector. An instruction selecting
23382 architectural low-lanes for a big-endian target, must be described using
23383 a mask selecting GCC high-lanes.
23385 Big-Endian Little-Endian
23387 GCC 0 1 2 3 3 2 1 0
23388 | x | x | x | x | | x | x | x | x |
23389 Architecture 3 2 1 0 3 2 1 0
23391 Low Mask: { 2, 3 } { 0, 1 }
23392 High Mask: { 0, 1 } { 2, 3 }
23394 MODE Is the mode of the vector and NUNITS is the number of units in it. */
23396 rtx
23398 {
23403 rtx t1;
23408 else
23416 }
23418 /* Check OP for validity as a PARALLEL RTX vector with elements
23419 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
23420 from the perspective of the architecture. See the diagram above
23421 aarch64_simd_vect_par_cnst_half for more details. */
23423 bool
23426 {
23440 {
23447 }
23449 }
23451 /* Return a PARALLEL containing NELTS elements, with element I equal
23452 to BASE + I * STEP. */
23454 rtx
23456 {
23461 }
23463 /* Return true if OP is a PARALLEL of CONST_INTs that form a linear
23464 series with step STEP. */
23466 bool
23468 {
23479 }
23481 /* Return true if OPERANDS[0] to OPERANDS[NUM_OPERANDS - 1] form a
23482 sequence of strided registers, with the stride being equal STRIDE.
23483 The operands are already known to be FPRs. */
23484 bool
23487 {
23492 }
23494 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
23495 HIGH (exclusive). */
23496 void
23498 const_tree exp)
23499 {
23500 HOST_WIDE_INT lane;
23505 {
23509 else
23511 }
23512 }
23514 /* Peform endian correction on lane number N, which indexes a vector
23515 of mode MODE, and return the result as an SImode rtx. */
23517 rtx
23519 {
23521 }
23523 /* Return TRUE if OP is a valid vector addressing mode. */
23525 bool
23527 {
23531 }
23533 /* Return true if OP is a valid MEM operand for an SVE LD1R instruction. */
23535 bool
23537 {
23539 scalar_mode mode;
23546 }
23548 /* Return true if OP is a valid MEM operand for an SVE LD1R{Q,O} instruction
23549 where the size of the read data is specified by `mode` and the size of the
23550 vector elements are specified by `elem_mode`. */
23551 bool
23553 scalar_mode elem_mode)
23554 {
23567 }
23569 /* Return true if OP is a valid MEM operand for an SVE LD1RQ instruction. */
23570 bool
23572 {
23575 }
23577 /* Return true if OP is a valid MEM operand for an SVE LD1RO instruction for
23578 accessing a vector where the element size is specified by `elem_mode`. */
23579 bool
23581 {
23583 }
23585 /* Return true if OP is a valid MEM operand for an SVE LDFF1 instruction. */
23586 bool
23588 {
23600 }
23602 /* Return true if OP is a valid MEM operand for an SVE LDNF1 instruction. */
23603 bool
23605 {
23612 }
23614 /* Return true if OP is a valid MEM operand for an SVE LDR instruction.
23615 The conditions for STR are the same. */
23616 bool
23618 {
23625 }
23627 /* Return true if OP is a valid address for an SVE PRF[BHWD] instruction,
23628 addressing memory of mode MODE. */
23629 bool
23631 {
23640 }
23642 /* Return true if OP is a valid MEM operand for an SVE_STRUCT mode.
23643 We need to be able to access the individual pieces, so the range
23644 is different from LD[234] and ST[234]. */
23645 bool
23647 {
23654 ADDR_QUERY_ANY)
23662 }
23664 /* Return true if OFFSET is a constant integer and if VNUM is
23665 OFFSET * the number of bytes in an SVE vector. This is the requirement
23666 that exists in SME LDR and STR instructions, where the VL offset must
23667 equal the ZA slice offset. */
23668 bool
23670 {
23675 {
23676 poly_int64 const_vnum;
23680 }
23681 else
23682 {
23683 HOST_WIDE_INT factor;
23686 }
23687 }
23689 /* Emit a register copy from operand to operand, taking care not to
23690 early-clobber source registers in the process.
23692 COUNT is the number of components into which the copy needs to be
23693 decomposed. */
23694 void
23697 {
23707 else
23711 }
23713 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
23714 one of VSTRUCT modes: OI, CI, or XI. */
23715 int
23717 {
23718 /* This is only used (and only meaningful) for Advanced SIMD, not SVE. */
23720 }
23722 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
23723 alignment of a vector to 128 bits. SVE predicates have an alignment of
23724 16 bits. */
23725 static HOST_WIDE_INT
23727 {
23728 /* ??? Checking the mode isn't ideal, but VECTOR_BOOLEAN_TYPE_P can
23729 be set for non-predicate vectors of booleans. Modes are the most
23730 direct way we have of identifying real SVE predicate types. */
23733 widest_int min_size
23736 }
23738 /* Implement target hook TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT. */
23739 static poly_uint64
23741 {
23743 {
23744 /* If the length of the vector is a fixed power of 2, try to align
23745 to that length, otherwise don't try to align at all. */
23746 HOST_WIDE_INT result;
23751 }
23753 }
23755 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
23756 static bool
23758 {
23762 /* For fixed-length vectors, check that the vectorizer will aim for
23763 full-vector alignment. This isn't true for generic GCC vectors
23764 that are wider than the ABI maximum of 128 bits. */
23765 poly_uint64 preferred_alignment =
23769 preferred_alignment))
23772 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
23774 }
23776 /* Return true if the vector misalignment factor is supported by the
23777 target. */
23778 static bool
23782 {
23784 {
23785 /* Return if movmisalign pattern is not supported for this mode. */
23789 /* Misalignment factor is unknown at compile time. */
23792 }
23794 is_packed);
23795 }
23797 /* If VALS is a vector constant that can be loaded into a register
23798 using DUP, generate instructions to do so and return an RTX to
23799 assign to the register. Otherwise return NULL_RTX. */
23800 static rtx
23802 {
23805 rtx x;
23810 /* We can load this constant by using DUP and a constant in a
23811 single ARM register. This will be cheaper than a vector
23812 load. */
23815 }
23818 /* Generate code to load VALS, which is a PARALLEL containing only
23819 constants (for vec_init) or CONST_VECTOR, efficiently into a
23820 register. Returns an RTX to copy into the register, or NULL_RTX
23821 for a PARALLEL that cannot be converted into a CONST_VECTOR. */
23822 static rtx
23824 {
23826 rtx const_dup;
23834 {
23835 /* A CONST_VECTOR must contain only CONST_INTs and
23836 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
23837 Only store valid constants in a CONST_VECTOR. */
23840 {
23843 n_const++;
23844 }
23847 }
23848 else
23853 /* Load using MOVI/MVNI. */
23856 /* Loaded using DUP. */
23859 /* Load from constant pool. We cannot take advantage of single-cycle
23860 LD1 because we need a PC-relative addressing mode. */
23862 else
23863 /* A PARALLEL containing something not valid inside CONST_VECTOR.
23864 We cannot construct an initializer. */
23866 }
23868 /* A subroutine of aarch64_expand_vector_init, with the same interface.
23869 The caller has already tried a divide-and-conquer approach, so do
23870 not consider that case here. */
23872 void
23874 {
23877 /* The number of vector elements. */
23879 /* The number of vector elements which are not constant. */
23882 /* The first element of vals. */
23886 /* This is a special vec_init<M><N> where N is not an element mode but a
23887 vector mode with half the elements of M. We expect to find two entries
23888 of mode N in VALS and we must put their concatentation into TARGET. */
23890 {
23899 }
23901 /* Count the number of variable elements to initialise. */
23903 {
23907 else
23911 }
23913 /* No variable elements, hand off to aarch64_simd_make_constant which knows
23914 how best to handle this. */
23916 {
23919 {
23922 }
23923 }
23925 /* Splat a single non-constant element if we can. */
23927 {
23931 }
23936 /* If there are only variable elements, try to optimize
23937 the insertion using dup for the most common element
23938 followed by insertions. */
23940 /* The algorithm will fill matches[*][0] with the earliest matching element,
23941 and matches[X][1] with the count of duplicate elements (if X is the
23942 earliest element which has duplicates). */
23945 {
23948 {
23950 {
23952 {
23956 }
23957 }
23958 }
23965 {
23967 {
23970 }
23973 {
23976 }
23977 }
23979 /* Create a duplicate of the most common element, unless all elements
23980 are equally useless to us, in which case just immediately set the
23981 vector register using the first element. */
23984 {
23985 /* For vectors of two 64-bit elements, we can do even better. */
23990 {
23993 /* Combine can pick up this case, but handling it directly
23994 here leaves clearer RTL.
23996 This is load_pair_lanes<mode>, and also gives us a clean-up
23997 for store_pair_lanes<mode>. */
24001 {
24002 rtx t;
24005 else
24009 }
24010 }
24011 /* The subreg-move sequence below will move into lane zero of the
24012 vector register. For big-endian we want that position to hold
24013 the last element of VALS. */
24016 /* If we have a single constant element, use that for duplicating
24017 instead. */
24019 {
24022 }
24023 else
24024 {
24027 }
24028 }
24029 else
24030 {
24033 }
24035 /* Insert the rest. */
24037 {
24043 }
24045 }
24047 /* Initialise a vector which is part-variable. We want to first try
24048 to build those lanes which are constant in the most efficient way we
24049 can. */
24051 {
24054 /* Load constant part of vector. We really don't care what goes into the
24055 parts we will overwrite, but we're more likely to be able to load the
24056 constant efficiently if it has fewer, larger, repeating parts
24057 (see aarch64_simd_valid_immediate). */
24059 {
24065 {
24066 /* Look in the copied vector, as more elements are const. */
24069 {
24072 }
24073 }
24075 }
24077 }
24079 /* Insert the variable lanes directly. */
24081 {
24087 }
24088 }
24090 /* Return even or odd half of VALS depending on EVEN_P. */
24092 static rtx
24094 {
24096 machine_mode new_mode
24104 }
24106 /* Return true if SET is a scalar move. */
24108 static bool
24110 {
24115 }
24117 /* Similar to seq_cost, but ignore cost for scalar moves. */
24119 static unsigned
24121 {
24126 {
24128 {
24131 }
24132 else
24133 {
24137 else
24138 cost++;
24139 }
24140 }
24143 }
24145 /* Expand a vector initialization sequence, such that TARGET is
24146 initialized to contain VALS. */
24148 void
24150 {
24151 /* Try decomposing the initializer into even and odd halves and
24152 then ZIP them together. Use the resulting sequence if it is
24153 strictly cheaper than loading VALS directly.
24155 Prefer the fallback sequence in the event of a tie, since it
24156 will tend to use fewer registers. */
24163 {
24166 }
24172 {
24182 }
24185 rtx_insn *zip1_insn
24187 unsigned seq_total_cost
24197 unsigned fallback_seq_cost
24202 }
24204 /* Emit RTL corresponding to:
24205 insr TARGET, ELEM. */
24207 static void
24209 {
24217 }
24219 /* Subroutine of aarch64_sve_expand_vector_init for handling
24220 trailing constants.
24221 This function works as follows:
24222 (a) Create a new vector consisting of trailing constants.
24223 (b) Initialize TARGET with the constant vector using emit_move_insn.
24224 (c) Insert remaining elements in TARGET using insr.
24225 NELTS is the total number of elements in original vector while
24226 while NELTS_REQD is the number of elements that are actually
24227 significant.
24229 ??? The heuristic used is to do above only if number of constants
24230 is at least half the total number of elements. May need fine tuning. */
24232 static bool
24233 aarch64_sve_expand_vector_init_handle_trailing_constants
24235 {
24242 i--)
24243 n_trailing_constants++;
24246 {
24247 /* Try to use the natural pattern of BUILDER to extend the trailing
24248 constant elements to a full vector. Replace any variables in the
24249 extra elements with zeros.
24251 ??? It would be better if the builders supported "don't care"
24252 elements, with the builder filling in whichever elements
24253 give the most compact encoding. */
24256 {
24261 }
24269 }
24272 }
24274 /* Subroutine of aarch64_sve_expand_vector_init.
24275 Works as follows:
24276 (a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER.
24277 (b) Skip trailing elements from BUILDER, which are the same as
24278 element NELTS_REQD - 1.
24279 (c) Insert earlier elements in reverse order in TARGET using insr. */
24281 static void
24285 {
24300 }
24302 /* Subroutine of aarch64_sve_expand_vector_init to handle case
24303 when all trailing elements of builder are same.
24304 This works as follows:
24305 (a) Use expand_insn interface to broadcast last vector element in TARGET.
24306 (b) Insert remaining elements in TARGET using insr.
24308 ??? The heuristic used is to do above if number of same trailing elements
24309 is at least 3/4 of total number of elements, loosely based on
24310 heuristic from mostly_zeros_p. May need fine-tuning. */
24312 static bool
24313 aarch64_sve_expand_vector_init_handle_trailing_same_elem
24315 {
24318 {
24322 }
24325 }
24327 /* Initialize register TARGET from BUILDER. NELTS is the constant number
24328 of elements in BUILDER.
24330 The function tries to initialize TARGET from BUILDER if it fits one
24331 of the special cases outlined below.
24333 Failing that, the function divides BUILDER into two sub-vectors:
24334 v_even = even elements of BUILDER;
24335 v_odd = odd elements of BUILDER;
24337 and recursively calls itself with v_even and v_odd.
24339 if (recursive call succeeded for v_even or v_odd)
24340 TARGET = zip (v_even, v_odd)
24342 The function returns true if it managed to build TARGET from BUILDER
24343 with one of the special cases, false otherwise.
24345 Example: {a, 1, b, 2, c, 3, d, 4}
24347 The vector gets divided into:
24348 v_even = {a, b, c, d}
24349 v_odd = {1, 2, 3, 4}
24351 aarch64_sve_expand_vector_init(v_odd) hits case 1 and
24352 initialize tmp2 from constant vector v_odd using emit_move_insn.
24354 aarch64_sve_expand_vector_init(v_even) fails since v_even contains
24355 4 elements, so we construct tmp1 from v_even using insr:
24356 tmp1 = dup(d)
24357 insr tmp1, c
24358 insr tmp1, b
24359 insr tmp1, a
24361 And finally:
24362 TARGET = zip (tmp1, tmp2)
24363 which sets TARGET to {a, 1, b, 2, c, 3, d, 4}. */
24365 static bool
24368 {
24371 /* Case 1: Vector contains trailing constants. */
24377 /* Case 2: Vector contains leading constants. */
24386 {
24389 }
24391 /* Case 3: Vector contains trailing same element. */
24397 /* Case 4: Vector contains leading same element. */
24401 {
24404 }
24406 /* Avoid recursing below 4-elements.
24407 ??? The threshold 4 may need fine-tuning. */
24416 {
24419 }
24435 /* Initialize v_even and v_odd using INSR if it didn't match any of the
24436 special cases and zip v_even, v_odd. */
24447 }
24449 /* Initialize register TARGET from the elements in PARALLEL rtx VALS. */
24451 void
24453 {
24462 /* If neither sub-vectors of v could be initialized specially,
24463 then use INSR to insert all elements from v into TARGET.
24464 ??? This might not be optimal for vectors with large
24465 initializers like 16-element or above.
24466 For nelts < 4, it probably isn't useful to handle specially. */
24471 }
24473 /* Check whether VALUE is a vector constant in which every element
24474 is either a power of 2 or a negated power of 2. If so, return
24475 a constant vector of log2s, and flip CODE between PLUS and MINUS
24476 if VALUE contains negated powers of 2. Return NULL_RTX otherwise. */
24478 static rtx
24480 {
24484 rtx_vector_builder builder;
24489 /* 1 if the result of the multiplication must be negated,
24490 0 if it mustn't, or -1 if we don't yet care. */
24494 {
24501 {
24502 /* It matters whether we negate or not. Make that choice,
24503 and make sure that it's consistent with previous elements. */
24509 }
24510 /* POW2 is now the value that we want to be a power of 2. */
24515 }
24517 /* PLUS and MINUS are equivalent; canonicalize on PLUS. */
24522 }
24524 /* Prepare for an integer SVE multiply-add or multiply-subtract pattern;
24525 CODE is PLUS for the former and MINUS for the latter. OPERANDS is the
24526 operands array, in the same order as for fma_optab. Return true if
24527 the function emitted all the necessary instructions, false if the caller
24528 should generate the pattern normally with the new OPERANDS array. */
24530 bool
24532 {
24535 {
24540 OPTAB_DIRECT);
24542 }
24545 }
24547 /* Likewise, but for a conditional pattern. */
24549 bool
24551 {
24554 {
24560 }
24563 }
24565 static unsigned HOST_WIDE_INT
24567 {
24571 }
24573 /* Select a format to encode pointers in exception handling data. */
24574 int
24576 {
24579 {
24585 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
24586 for everything. */
24590 /* No assumptions here. 8-byte relocs required. */
24593 }
24595 }
24597 /* Output .variant_pcs for aarch64_vector_pcs function symbols. */
24599 static void
24601 {
24603 {
24606 {
24610 }
24611 }
24612 }
24614 /* The last .arch and .tune assembly strings that we printed. */
24618 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
24619 by the function fndecl. */
24621 void
24623 tree fndecl)
24624 {
24630 else
24641 /* Only update the assembler .arch string if it is distinct from the last
24642 such string we printed. */
24645 {
24648 }
24650 /* Print the cpu name we're tuning for in the comments, might be
24651 useful to readers of the generated asm. Do it only when it changes
24652 from function to function and verbose assembly is requested. */
24657 {
24661 }
24665 /* Don't forget the type directive for ELF. */
24670 }
24672 /* Implement PRINT_PATCHABLE_FUNCTION_ENTRY. */
24674 void
24678 {
24680 {
24681 /* Emit the patching area before the entry label, if any. */
24683 record_p);
24685 }
24693 {
24694 /* Emit the patchable_area at the beginning of the function. */
24698 }
24705 {
24706 /* Emit a BTI_C. */
24708 }
24710 /* Emit the patchable_area after BTI_C. */
24713 }
24715 /* Output patchable area. */
24717 void
24719 {
24721 record_p);
24722 }
24724 /* Implement ASM_OUTPUT_DEF_FROM_DECLS. Output .variant_pcs for aliases. */
24726 void
24728 {
24733 }
24735 /* Implement ASM_OUTPUT_EXTERNAL. Output .variant_pcs for undefined
24736 function symbol references. */
24738 void
24740 {
24743 }
24745 /* Triggered after a .cfi_startproc directive is emitted into the assembly file.
24746 Used to output the .cfi_b_key_frame directive when signing the current
24747 function with the B key. */
24749 void
24751 {
24755 }
24757 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
24759 static void
24761 {
24778 }
24780 /* Emit load exclusive. */
24782 static void
24785 {
24790 else
24792 }
24794 /* Emit store exclusive. */
24796 static void
24799 {
24804 else
24806 }
24808 /* Mark the previous jump instruction as unlikely. */
24810 static void
24812 {
24815 }
24817 /* We store the names of the various atomic helpers in a 5x5 array.
24818 Return the libcall function given MODE, MODEL and NAMES. */
24820 rtx
24823 {
24828 {
24846 }
24849 {
24871 }
24874 VISIBILITY_HIDDEN);
24875 }
24877 #define DEF0(B, N) \
24884 #define DEF4(B) DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), \
24885 { NULL, NULL, NULL, NULL }
24886 #define DEF5(B) DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), DEF0(B, 16)
24895 #undef DEF0
24896 #undef DEF4
24897 #undef DEF5
24899 /* Expand a compare and swap pattern. */
24901 void
24903 {
24917 /* Normally the succ memory model must be stronger than fail, but in the
24918 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
24919 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
24926 {
24929 }
24932 {
24933 /* The CAS insn requires oldval and rval overlap, but we need to
24934 have a copy of oldval saved across the operation to tell if
24935 the operation is successful. */
24938 else
24946 }
24948 {
24949 /* Oldval must satisfy compare afterward. */
24957 }
24958 else
24959 {
24960 /* The oldval predicate varies by mode. Test it and force to reg. */
24968 }
24976 }
24978 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
24979 sequence implementing an atomic operation. */
24981 static void
24983 {
24990 {
24992 }
24993 }
24995 /* Split a compare and swap pattern. */
24997 void
24999 {
25000 /* Split after prolog/epilog to avoid interactions with shrinkwrapping. */
25004 machine_mode mode;
25019 /* When OLDVAL is zero and we want the strong version we can emit a tighter
25020 loop:
25021 .label1:
25022 LD[A]XR rval, [mem]
25023 CBNZ rval, .label2
25024 ST[L]XR scratch, newval, [mem]
25025 CBNZ scratch, .label1
25026 .label2:
25027 CMP rval, 0. */
25033 {
25036 }
25039 /* The initial load can be relaxed for a __sync operation since a final
25040 barrier will be emitted to stop code hoisting. */
25043 else
25048 else
25049 {
25052 }
25060 {
25063 }
25064 else
25067 /* 128-bit LDAXP is not atomic unless STLXP succeeds. So for a mismatch,
25068 store the returned value and loop if the STLXP fails. */
25070 {
25082 }
25086 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
25087 to set the condition flags. If this is not used it will be removed by
25088 later passes. */
25092 /* Emit any final barrier needed for a __sync operation. */
25095 }
25097 /* Split an atomic operation. */
25099 void
25102 {
25103 /* Split after prolog/epilog to avoid interactions with shrinkwrapping. */
25111 rtx x;
25113 /* Split the atomic operation into a sequence. */
25121 else
25125 /* The initial load can be relaxed for a __sync operation since a final
25126 barrier will be emitted to stop code hoisting. */
25130 else
25134 {
25148 {
25151 }
25152 /* Fall through. */
25158 }
25166 /* Emit any final barrier needed for a __sync operation. */
25169 }
25171 static void
25173 {
25174 /* Half-precision float operations. The compiler handles all operations
25175 with NULL libfuncs by converting to SFmode. */
25177 /* Conversions. */
25181 /* Arithmetic. */
25188 /* Comparisons. */
25196 }
25198 /* Target hook for c_mode_for_suffix. */
25199 static machine_mode
25201 {
25206 }
25208 /* We can only represent floating point constants which will fit in
25209 "quarter-precision" values. These values are characterised by
25210 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
25211 by:
25213 (-1)^s * (n/16) * 2^r
25215 Where:
25216 's' is the sign bit.
25217 'n' is an integer in the range 16 <= n <= 31.
25218 'r' is an integer in the range -3 <= r <= 4. */
25220 /* Return true iff X can be represented by a quarter-precision
25221 floating point immediate operand X. Note, we cannot represent 0.0. */
25222 bool
25224 {
25225 /* This represents our current view of how many bits
25226 make up the mantissa. */
25243 /* We cannot represent infinities, NaNs or +/-zero. We won't
25244 know if we have +zero until we analyse the mantissa, but we
25245 can reject the other invalid values. */
25250 /* For BFmode, only handle 0.0. */
25254 /* Extract exponent. */
25258 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
25259 highest (sign) bit, with a fixed binary point at bit point_pos.
25260 m1 holds the low part of the mantissa, m2 the high part.
25261 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
25262 bits for the mantissa, this can fail (low bits will be lost). */
25266 /* If the low part of the mantissa has bits set we cannot represent
25267 the value. */
25270 /* We have rejected the lower HOST_WIDE_INT, so update our
25271 understanding of how many bits lie in the mantissa and
25272 look only at the high HOST_WIDE_INT. */
25276 /* We can only represent values with a mantissa of the form 1.xxxx. */
25281 /* Having filtered unrepresentable values, we may now remove all
25282 but the highest 5 bits. */
25285 /* We cannot represent the value 0.0, so reject it. This is handled
25286 elsewhere. */
25290 /* Then, as bit 4 is always set, we can mask it off, leaving
25291 the mantissa in the range [0, 15]. */
25295 /* GCC internally does not use IEEE754-like encoding (where normalized
25296 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.cc).
25297 Our mantissa values are shifted 4 places to the left relative to
25298 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
25299 by 5 places to correct for GCC's representation. */
25303 }
25305 /* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR or BIC
25306 immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether to
25307 output MOVI/MVNI, ORR or BIC immediate. */
25311 {
25321 /* This will return true to show const_vector is legal for use as either
25322 a AdvSIMD MOVI instruction (or, implicitly, MVNI), ORR or BIC immediate.
25323 It will also update INFO to show how the immediate should be generated.
25324 WHICH selects whether to check for MOVI/MVNI, ORR or BIC. */
25332 {
25335 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
25336 move immediate path. */
25339 else
25340 {
25349 else
25353 }
25354 }
25359 {
25361 {
25368 }
25381 else
25385 }
25386 else
25387 {
25388 /* For AARCH64_CHECK_BIC and AARCH64_CHECK_ORR. */
25395 else
25399 }
25401 }
25405 {
25407 /* If a floating point number was passed and we desire to use it in an
25408 integer mode do the conversion to integer. */
25410 {
25415 }
25417 machine_mode vmode;
25418 /* use a 64 bit mode for everything except for DI/DF/DD mode, where we use
25419 a 128 bit vector mode. */
25425 }
25427 /* Return the output string to use for moving immediate CONST_VECTOR
25428 into an SVE register. */
25432 {
25444 {
25447 {
25450 }
25451 else
25452 {
25459 else
25462 }
25464 }
25467 {
25473 }
25476 {
25479 else
25480 {
25490 }
25491 }
25496 }
25498 /* Return the asm template for a PTRUES. CONST_UNSPEC is the
25499 aarch64_sve_ptrue_svpattern_immediate that describes the predicate
25500 pattern. */
25504 {
25515 }
25517 /* Split operands into moves from op[1] + op[2] into op[0]. */
25519 void
25521 {
25536 {
25537 /* No-op move. Can't split to nothing; emit something. */
25540 }
25542 /* Special case of reversed high/low parts. */
25545 {
25549 }
25551 {
25552 /* Try to avoid unnecessary moves if part of the result
25553 is in the right place already. */
25558 }
25559 else
25560 {
25565 }
25566 }
25568 /* vec_perm support. */
25570 struct expand_vec_perm_d
25571 {
25573 vec_perm_indices perm;
25574 machine_mode vmode;
25575 machine_mode op_mode;
25581 };
25585 /* Generate a variable permutation. */
25587 static void
25589 {
25600 {
25602 {
25603 /* Expand the argument to a V16QI mode by duplicating it. */
25607 }
25608 else
25609 {
25611 }
25612 }
25613 else
25614 {
25615 rtx pair;
25618 {
25622 }
25623 else
25624 {
25628 }
25629 }
25630 }
25632 /* Expand a vec_perm with the operands given by TARGET, OP0, OP1 and SEL.
25633 NELT is the number of elements in the vector. */
25635 void
25638 {
25641 rtx mask;
25643 /* The TBL instruction does not use a modulo index, so we must take care
25644 of that ourselves. */
25649 /* For big-endian, we also need to reverse the index within the vector
25650 (but not which vector). */
25652 {
25653 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
25658 }
25660 }
25662 /* Generate (set TARGET (unspec [OP0 OP1] CODE)). */
25664 static void
25666 {
25670 }
25672 /* Expand an SVE vec_perm with the given operands. */
25674 void
25676 {
25679 /* Enforced by the pattern condition. */
25682 /* Note: vec_perm indices are supposed to wrap when they go beyond the
25683 size of the two value vectors, i.e. the upper bits of the indices
25684 are effectively ignored. SVE TBL instead produces 0 for any
25685 out-of-range indices, so we need to modulo all the vec_perm indices
25686 to ensure they are all in range. */
25689 /* Check if the sel only references the first values vector. */
25692 {
25695 }
25697 /* Check if the two values vectors are the same. */
25699 {
25705 }
25707 /* Run TBL on for each value vector and combine the results. */
25714 {
25719 }
25726 else
25728 }
25730 /* Recognize patterns suitable for the TRN instructions. */
25731 static bool
25733 {
25734 HOST_WIDE_INT odd;
25742 /* Note that these are little-endian tests.
25743 We correct for big-endian later. */
25750 /* Success! */
25756 /* We don't need a big-endian lane correction for SVE; see the comment
25757 at the head of aarch64-sve.md for details. */
25759 {
25762 }
25768 }
25770 /* Try to re-encode the PERM constant so it combines odd and even elements.
25771 This rewrites constants such as {0, 1, 4, 5}/V4SF to {0, 2}/V2DI.
25772 We retry with this new constant with the full suite of patterns. */
25773 static bool
25775 {
25776 expand_vec_perm_d newd;
25778 /* The subregs that we'd create are not supported for big-endian SVE;
25779 see aarch64_modes_compatible_p for details. */
25783 /* Get the new mode. Always twice the size of the inner
25784 and half the elements. */
25785 machine_mode new_mode;
25789 vec_perm_indices newpermindices;
25806 }
25808 /* Recognize patterns suitable for the UZP instructions. */
25809 static bool
25811 {
25812 HOST_WIDE_INT odd;
25819 /* Note that these are little-endian tests.
25820 We correct for big-endian later. */
25826 /* Success! */
25832 /* We don't need a big-endian lane correction for SVE; see the comment
25833 at the head of aarch64-sve.md for details. */
25835 {
25838 }
25844 }
25846 /* Recognize patterns suitable for the ZIP instructions. */
25847 static bool
25849 {
25858 /* Note that these are little-endian tests.
25859 We correct for big-endian later. */
25867 /* Success! */
25873 /* We don't need a big-endian lane correction for SVE; see the comment
25874 at the head of aarch64-sve.md for details. */
25876 {
25879 }
25885 }
25887 /* Recognize patterns for the EXT insn. */
25889 static bool
25891 {
25892 HOST_WIDE_INT location;
25893 rtx offset;
25895 /* The first element always refers to the first vector.
25896 Check if the extracted indices are increasing by one. */
25902 /* Success! */
25906 /* The case where (location == 0) is a no-op for both big- and little-endian,
25907 and is removed by the mid-end at optimization levels -O1 and higher.
25909 We don't need a big-endian lane correction for SVE; see the comment
25910 at the head of aarch64-sve.md for details. */
25912 {
25913 /* After setup, we want the high elements of the first vector (stored
25914 at the LSB end of the register), and the low elements of the second
25915 vector (stored at the MSB end of the register). So swap. */
25917 /* location != 0 (above), so safe to assume (nelt - location) < nelt.
25918 to_constant () is safe since this is restricted to Advanced SIMD
25919 vectors. */
25921 }
25927 UNSPEC_EXT));
25929 }
25931 /* Recognize patterns for the REV{64,32,16} insns, which reverse elements
25932 within each 64-bit, 32-bit or 16-bit granule. */
25934 static bool
25936 {
25937 HOST_WIDE_INT diff;
25939 machine_mode pred_mode;
25949 else
25952 {
25955 }
25957 {
25960 }
25962 {
25965 }
25966 else
25974 /* Success! */
25979 {
25984 }
25988 }
25990 /* Recognize patterns for the REV insn, which reverses elements within
25991 a full vector. */
25993 static bool
25995 {
26004 /* Success! */
26011 }
26013 static bool
26015 {
26017 rtx in0;
26018 HOST_WIDE_INT elt;
26020 rtx lane;
26031 /* Success! */
26035 /* The generic preparation in aarch64_expand_vec_perm_const_1
26036 swaps the operand order and the permute indices if it finds
26037 d->perm[0] to be in the second operand. Thus, we can always
26038 use d->op0 and need not do any extra arithmetic to get the
26039 correct lane number. */
26047 }
26049 static bool
26051 {
26055 /* Make sure that the indices are constant. */
26064 /* Generic code will try constant permutation twice. Once with the
26065 original mode and again with the elements lowered to QImode.
26066 So wait and don't do the selector expansion ourselves. */
26070 /* to_constant is safe since this routine is specific to Advanced SIMD
26071 vectors. */
26074 /* If one register is the constant vector of 0 then we only need
26075 a one reg TBL and we map any accesses to the vector of 0 to -1. We can't
26076 do this earlier since vec_perm_indices clamps elements to within range so
26077 we can only do it during codegen. */
26084 {
26087 /* If we're selecting from a 0 vector, we can just use an out of range
26088 index instead. */
26091 else
26092 {
26093 /* If we are remapping a zero register as the first parameter we need
26094 to adjust the indices of the non-zero register. */
26098 /* If big-endian and two vectors we end up with a weird mixed-endian
26099 mode on NEON. Reverse the index within each word but not the word
26100 itself. to_constant is safe because we checked is_constant
26101 above. */
26103 }
26104 }
26111 }
26113 /* Try to implement D using an SVE TBL instruction. */
26115 static bool
26117 {
26120 /* Permuting two variable-length vectors could overflow the
26121 index range. */
26132 else
26135 }
26137 /* Try to implement D using SVE dup instruction. */
26139 static bool
26141 {
26162 }
26164 /* Try to implement D using SVE SEL instruction. */
26166 static bool
26168 {
26194 /* Build a predicate that is true when op0 elements should be used. */
26197 {
26201 }
26205 /* TARGET = PRED ? OP0 : OP1. */
26208 }
26210 /* Recognize patterns suitable for the INS instructions. */
26211 static bool
26213 {
26220 /* to_constant is safe since this routine is specific to Advanced SIMD
26221 vectors. */
26228 {
26229 HOST_WIDE_INT elt;
26235 {
26238 }
26240 }
26243 {
26246 {
26252 }
26256 }
26266 {
26269 }
26282 }
26284 static bool
26286 {
26289 /* The pattern matching functions above are written to look for a small
26290 number to begin the sequence (0, 1, N/2). If we begin with an index
26291 from the second operand, we can swap the operands. */
26294 {
26297 }
26304 {
26306 {
26332 }
26333 else
26334 {
26337 }
26338 }
26340 }
26342 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
26344 static bool
26348 {
26351 /* Check whether the mask can be applied to a single vector. */
26356 {
26359 }
26361 {
26364 }
26365 else
26380 else
26392 }
26393 /* Generate a byte permute mask for a register of mode MODE,
26394 which has NUNITS units. */
26396 rtx
26398 {
26399 /* We have to reverse each vector because we dont have
26400 a permuted load that can reverse-load according to ABI rules. */
26401 rtx mask;
26414 }
26416 /* Expand an SVE integer comparison using the SVE equivalent of:
26418 (set TARGET (CODE OP0 OP1)). */
26420 void
26422 {
26429 }
26431 /* Return the UNSPEC_COND_* code for comparison CODE. */
26433 static unsigned int
26435 {
26437 {
26454 }
26455 }
26457 /* Emit:
26459 (set TARGET (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X>))
26461 where <X> is the operation associated with comparison CODE.
26462 KNOWN_PTRUE_P is true if PRED is known to be a PTRUE. */
26464 static void
26467 {
26473 }
26475 /* Emit the SVE equivalent of:
26477 (set TMP1 (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X1>))
26478 (set TMP2 (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X2>))
26479 (set TARGET (ior:PRED_MODE TMP1 TMP2))
26481 where <Xi> is the operation associated with comparison CODEi.
26482 KNOWN_PTRUE_P is true if PRED is known to be a PTRUE. */
26484 static void
26487 {
26494 }
26496 /* Emit the SVE equivalent of:
26498 (set TMP (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X>))
26499 (set TARGET (not TMP))
26501 where <X> is the operation associated with comparison CODE.
26502 KNOWN_PTRUE_P is true if PRED is known to be a PTRUE. */
26504 static void
26507 {
26512 }
26514 /* Expand an SVE floating-point comparison using the SVE equivalent of:
26516 (set TARGET (CODE OP0 OP1))
26518 If CAN_INVERT_P is true, the caller can also handle inverted results;
26519 return true if the result is in fact inverted. */
26521 bool
26524 {
26530 {
26532 /* UNORDERED has no immediate form. */
26534 /* fall through */
26541 {
26542 /* There is native support for the comparison. */
26545 }
26548 /* This is a trapping operation (LT or GT). */
26554 {
26555 /* This would trap for signaling NaNs. */
26560 }
26561 /* fall through */
26567 {
26568 /* Work out which elements are ordered. */
26574 /* Test the opposite condition for the ordered elements,
26575 then invert the result. */
26578 else
26581 {
26585 }
26589 }
26593 /* ORDERED has no immediate form. */
26599 }
26601 /* There is native support for the inverse comparison. */
26604 {
26607 }
26610 }
26612 /* Expand an SVE vcond pattern with operands OPS. DATA_MODE is the mode
26613 of the data being selected and CMP_MODE is the mode of the values being
26614 compared. */
26616 void
26619 {
26623 {
26627 }
26628 else
26633 /* The "false" value can only be zero if the "true" value is a constant. */
26640 }
26642 /* Return true if:
26644 (a) MODE1 and MODE2 use the same layout for bytes that are common
26645 to both modes;
26647 (b) subregs involving the two modes behave as the target-independent
26648 subreg rules require; and
26650 (c) there is at least one register that can hold both modes.
26652 Return false otherwise. */
26654 static bool
26656 {
26674 /* Don't allow changes between predicate modes and other modes.
26675 Only predicate registers can hold predicate modes and only
26676 non-predicate registers can hold non-predicate modes, so any
26677 attempt to mix them would require a round trip through memory. */
26681 /* The contents of partial SVE modes are distributed evenly across
26682 the register, whereas GCC expects them to be clustered together.
26683 We therefore need to be careful about mode changes involving them. */
26685 {
26686 /* Reject changes between partial SVE modes that have different
26687 patterns of significant and insignificant bits. */
26692 }
26694 {
26695 /* The first lane of MODE1 is where GCC expects it, but anything
26696 bigger than that is not. */
26699 }
26701 {
26702 /* Similarly in reverse. */
26705 }
26707 /* Don't allow changes between partial Advanced SIMD structure modes
26708 and other modes that are bigger than 8 bytes. E.g. V16QI and V2x8QI
26709 are the same size, but the former occupies one Q register while the
26710 latter occupies two D registers. */
26717 {
26718 /* Don't allow changes between SVE modes and other modes that might
26719 be bigger than 128 bits. In particular, OImode, CImode and XImode
26720 divide into 128-bit quantities while SVE modes divide into
26721 BITS_PER_SVE_VECTOR quantities. */
26726 }
26729 {
26730 /* Don't allow changes between SVE data modes and non-SVE modes.
26731 See the comment at the head of aarch64-sve.md for details. */
26735 /* Don't allow changes in element size: lane 0 of the new vector
26736 would not then be lane 0 of the old vector. See the comment
26737 above aarch64_maybe_expand_sve_subreg_move for a more detailed
26738 description.
26740 In the worst case, this forces a register to be spilled in
26741 one mode and reloaded in the other, which handles the
26742 endianness correctly. */
26745 }
26747 }
26749 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always defer
26750 to aarch64_modes_compatible_p. However due to issues with register
26751 allocation it is preferable to avoid tieing integer scalar and FP
26752 scalar modes. Executing integer operations in general registers is
26753 better than treating them as scalar vector operations. This reduces
26754 latency and avoids redundant int<->FP moves. So tie modes if they
26755 are either the same class, or one of them is a vector mode. */
26757 static bool
26759 {
26761 {
26766 }
26768 }
26770 /* Return a new RTX holding the result of moving POINTER forward by
26771 AMOUNT bytes. */
26773 static rtx
26775 {
26780 }
26782 /* Expand a cpymem/movmem using the MOPS extension. OPERANDS are taken
26783 from the cpymem/movmem pattern. IS_MEMMOVE is true if this is a memmove
26784 rather than memcpy. Return true iff we succeeded. */
26785 bool
26787 {
26791 /* All three registers are changed by the instruction, so each one
26792 must be a fresh pseudo. */
26800 else
26803 }
26805 /* Expand cpymem/movmem, as if from a __builtin_memcpy/memmove.
26806 OPERANDS are taken from the cpymem/movmem pattern. IS_MEMMOVE is true
26807 if this is a memmove rather than memcpy. Return true if we succeed,
26808 otherwise return false, indicating that a libcall should be emitted. */
26809 bool
26811 {
26816 rtx base;
26819 /* Variable-sized or strict-align copies may use the MOPS expansion. */
26825 /* Set inline limits for memmove/memcpy. MOPS has a separate threshold. */
26830 /* Reduce the maximum size with -Os. */
26834 /* Large copies use MOPS when available or a library call. */
26838 /* Default to 32-byte LDP/STP on large copies, however small copies or
26839 no SIMD support fall back to 16-byte chunks.
26840 ??? Although it would be possible to use LDP/STP Qn in streaming mode
26841 (so using TARGET_BASE_SIMD instead of TARGET_SIMD), it isn't clear
26842 whether that would improve performance. */
26855 {
26856 /* Find the largest mode in which to do the copy in without over reading
26857 or writing. */
26858 opt_scalar_int_mode mode_iter;
26867 /* Prefer Q-register accesses. */
26878 /* Emit trailing copies using overlapping unaligned accesses
26879 (when !STRICT_ALIGNMENT) - this is smaller and faster. */
26881 {
26882 next_mode = smallest_mode_for_size
26888 }
26889 }
26891 /* Memcpy interleaves loads with stores, memmove emits all loads first. */
26896 {
26898 /* Emit loads. */
26901 /* Emit stores. */
26904 }
26906 }
26908 /* Expand a setmem using the MOPS instructions. OPERANDS are the same
26909 as for the setmem pattern. Return true iff we succeed. */
26910 static bool
26912 {
26916 /* The first two registers are changed by the instruction, so both
26917 of them must be a fresh pseudo. */
26926 }
26928 /* Expand setmem, as if from a __builtin_memset. Return true if
26929 we succeed, otherwise return false. */
26931 bool
26933 {
26939 rtx base;
26942 /* Variable-sized or strict-align memset may use the MOPS expansion. */
26947 /* Set inline limits for memset. MOPS has a separate threshold. */
26953 /* Large memset uses MOPS when available or a library call. */
26960 /* Prepare the val using a DUP/MOVI v0.16B, val. */
26966 {
26967 /* Find the largest mode in which to do the copy without
26968 over writing. */
26969 opt_scalar_int_mode mode_iter;
26980 /* Prefer Q-register accesses. */
26983 else
26990 /* Emit trailing writes using overlapping unaligned accesses
26991 (when !STRICT_ALIGNMENT) - this is smaller and faster. */
26993 {
26994 next_mode = smallest_mode_for_size
27000 }
27001 }
27004 }
27007 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
27008 SImode stores. Handle the case when the constant has identical
27009 bottom and top halves. This is beneficial when the two stores can be
27010 merged into an STP and we avoid synthesising potentially expensive
27011 immediates twice. Return true if such a split is possible. */
27013 bool
27015 {
27022 unsigned int orig_cost
27024 unsigned int lo_cost
27027 /* We want to transform:
27028 MOV x1, 49370
27029 MOVK x1, 0x140, lsl 16
27030 MOVK x1, 0xc0da, lsl 32
27031 MOVK x1, 0x140, lsl 48
27032 STR x1, [x0]
27033 into:
27034 MOV w1, 49370
27035 MOVK w1, 0x140, lsl 16
27036 STP w1, w1, [x0]
27037 So we want to perform this when we save at least one instruction. */
27048 /* Don't emit an explicit store pair as this may not be always profitable.
27049 Let the sched-fusion logic decide whether to merge them. */
27054 }
27056 /* Generate RTL for a conditional branch with rtx comparison CODE in
27057 mode CC_MODE. The destination of the unlikely conditional branch
27058 is LABEL_REF. */
27060 void
27062 rtx label_ref)
27063 {
27064 rtx x;
27067 const0_rtx);
27071 pc_rtx);
27073 }
27075 /* Generate DImode scratch registers for 128-bit (TImode) addition.
27077 OP1 represents the TImode destination operand 1
27078 OP2 represents the TImode destination operand 2
27079 LOW_DEST represents the low half (DImode) of TImode operand 0
27080 LOW_IN1 represents the low half (DImode) of TImode operand 1
27081 LOW_IN2 represents the low half (DImode) of TImode operand 2
27082 HIGH_DEST represents the high half (DImode) of TImode operand 0
27083 HIGH_IN1 represents the high half (DImode) of TImode operand 1
27084 HIGH_IN2 represents the high half (DImode) of TImode operand 2. */
27086 void
27091 {
27098 }
27100 /* Generate DImode scratch registers for 128-bit (TImode) subtraction.
27102 OP1 represents the TImode destination operand 1
27103 OP2 represents the TImode destination operand 2
27104 LOW_DEST represents the low half (DImode) of TImode operand 0
27105 LOW_IN1 represents the low half (DImode) of TImode operand 1
27106 LOW_IN2 represents the low half (DImode) of TImode operand 2
27107 HIGH_DEST represents the high half (DImode) of TImode operand 0
27108 HIGH_IN1 represents the high half (DImode) of TImode operand 1
27109 HIGH_IN2 represents the high half (DImode) of TImode operand 2. */
27112 void
27117 {
27125 }
27127 /* Generate RTL for 128-bit (TImode) subtraction with overflow.
27129 OP0 represents the TImode destination operand 0
27130 LOW_DEST represents the low half (DImode) of TImode operand 0
27131 LOW_IN1 represents the low half (DImode) of TImode operand 1
27132 LOW_IN2 represents the low half (DImode) of TImode operand 2
27133 HIGH_DEST represents the high half (DImode) of TImode operand 0
27134 HIGH_IN1 represents the high half (DImode) of TImode operand 1
27135 HIGH_IN2 represents the high half (DImode) of TImode operand 2
27136 UNSIGNED_P is true if the operation is being performed on unsigned
27137 values. */
27138 void
27142 {
27144 {
27149 else
27151 }
27152 else
27153 {
27157 else
27158 {
27161 }
27166 else
27168 }
27173 }
27175 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
27177 static unsigned HOST_WIDE_INT
27179 {
27182 else
27184 }
27186 static rtx
27189 {
27193 insn_code icode;
27204 {
27232 }
27237 {
27240 }
27249 {
27252 }
27258 }
27260 static rtx
27263 rtx_code bit_code)
27264 {
27268 insn_code icode;
27280 {
27304 }
27311 {
27314 }
27322 {
27323 /* Treat the ccmp patterns as canonical and use them where possible,
27324 but fall back to ccmp_rev patterns if there's no other option. */
27333 else
27334 {
27337 }
27339 }
27350 {
27353 }
27359 }
27361 #undef TARGET_GEN_CCMP_FIRST
27362 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
27364 #undef TARGET_GEN_CCMP_NEXT
27365 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
27367 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
27368 instruction fusion of some sort. */
27370 static bool
27372 {
27374 }
27377 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
27378 should be kept together during scheduling. */
27380 static bool
27382 {
27383 rtx set_dest;
27386 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
27393 {
27394 /* We are trying to match:
27395 prev (mov) == (set (reg r0) (const_int imm16))
27396 curr (movk) == (set (zero_extract (reg r0)
27397 (const_int 16)
27398 (const_int 16))
27399 (const_int imm16_1)) */
27411 {
27413 }
27414 }
27417 {
27419 /* We're trying to match:
27420 prev (adrp) == (set (reg r1)
27421 (high (symbol_ref ("SYM"))))
27422 curr (add) == (set (reg r0)
27423 (lo_sum (reg r1)
27424 (symbol_ref ("SYM"))))
27425 Note that r0 need not necessarily be the same as r1, especially
27426 during pre-regalloc scheduling. */
27430 {
27438 }
27439 }
27442 {
27444 /* We're trying to match:
27445 prev (movk) == (set (zero_extract (reg r0)
27446 (const_int 16)
27447 (const_int 32))
27448 (const_int imm16_1))
27449 curr (movk) == (set (zero_extract (reg r0)
27450 (const_int 16)
27451 (const_int 48))
27452 (const_int imm16_2)) */
27468 }
27470 {
27471 /* We're trying to match:
27472 prev (adrp) == (set (reg r0)
27473 (high (symbol_ref ("SYM"))))
27474 curr (ldr) == (set (reg r1)
27475 (mem (lo_sum (reg r0)
27476 (symbol_ref ("SYM")))))
27477 or
27478 curr (ldr) == (set (reg r1)
27479 (zero_extend (mem
27480 (lo_sum (reg r0)
27481 (symbol_ref ("SYM")))))) */
27484 {
27497 }
27498 }
27500 /* Fuse compare (CMP/CMN/TST/BICS) and conditional branch. */
27508 /* Fuse CMP and CSEL/CSET. */
27513 {
27523 == RTX_COMPARE
27526 }
27528 /* Fuse flag-setting ALU instructions and conditional branch. */
27531 {
27533 rtx cc_reg_1;
27538 && prev
27540 {
27543 /* FIXME: this misses some which is considered simple arthematic
27544 instructions for ThunderX. Simple shifts are missed here. */
27550 }
27551 }
27553 /* Fuse ALU instructions and CBZ/CBNZ. */
27555 && curr_set
27558 {
27559 /* We're trying to match:
27560 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
27561 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
27562 (const_int 0))
27563 (label_ref ("SYM"))
27564 (pc)) */
27571 {
27572 /* Fuse ALU operations followed by conditional branch instruction. */
27574 {
27595 }
27596 }
27597 }
27599 /* Fuse A+B+1 and A-B-1 */
27602 {
27603 /* We're trying to match:
27604 prev == (set (r0) (plus (r0) (r1)))
27605 curr == (set (r0) (plus (r0) (const_int 1)))
27606 or:
27607 prev == (set (r0) (minus (r0) (r1)))
27608 curr == (set (r0) (plus (r0) (const_int -1))) */
27625 }
27628 }
27630 /* Return true iff the instruction fusion described by OP is enabled. */
27632 bool
27634 {
27636 }
27638 /* If MEM is in the form of [base+offset], extract the two parts
27639 of address and set to BASE and OFFSET, otherwise return false
27640 after clearing BASE and OFFSET. */
27642 bool
27644 {
27645 rtx addr;
27652 {
27656 }
27660 {
27664 }
27670 }
27672 /* Types for scheduling fusion. */
27673 enum sched_fusion_type
27674 {
27676 SCHED_FUSION_LD_SIGN_EXTEND,
27677 SCHED_FUSION_LD_ZERO_EXTEND,
27678 SCHED_FUSION_LD,
27679 SCHED_FUSION_ST,
27680 SCHED_FUSION_NUM
27681 };
27683 /* If INSN is a load or store of address in the form of [base+offset],
27684 extract the two parts and set to BASE and OFFSET. Return scheduling
27685 fusion type this INSN is. */
27687 static enum sched_fusion_type
27689 {
27707 {
27712 }
27714 {
27719 }
27724 {
27727 }
27728 else
27735 }
27737 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
27739 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
27740 and PRI are only calculated for these instructions. For other instruction,
27741 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
27742 type instruction fusion can be added by returning different priorities.
27744 It's important that irrelevant instructions get the largest FUSION_PRI. */
27746 static void
27749 {
27759 {
27763 }
27765 /* Set FUSION_PRI according to fusion type and base register. */
27768 /* Calculate PRI. */
27771 /* INSN with smaller offset goes first. */
27775 else
27780 }
27782 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
27783 Adjust priority of sha1h instructions so they are scheduled before
27784 other SHA1 instructions. */
27786 static int
27788 {
27792 {
27797 }
27800 }
27802 /* If REVERSED is null, return true if memory reference *MEM2 comes
27803 immediately after memory reference *MEM1. Do not change the references
27804 in this case.
27806 Otherwise, check if *MEM1 and *MEM2 are consecutive memory references and,
27807 if they are, try to make them use constant offsets from the same base
27808 register. Return true on success. When returning true, set *REVERSED
27809 to true if *MEM1 comes after *MEM2, false if *MEM1 comes before *MEM2. */
27810 static bool
27812 {
27830 /* Make sure at least one memory is in base+offset form. */
27834 /* If both mems already use the same base register, just check the
27835 offsets. */
27837 {
27845 {
27848 }
27851 }
27853 /* Otherwise, check whether the MEM_EXPRs and MEM_OFFSETs together
27854 guarantee that the values are consecutive. */
27859 {
27860 poly_int64 expr_offset1;
27861 poly_int64 expr_offset2;
27867 || !expr_base2
27876 ;
27879 else
27883 {
27885 {
27889 }
27890 else
27891 {
27895 }
27896 }
27898 }
27901 }
27903 /* Test if MODE is suitable for a single transfer register in an ldp or stp
27904 instruction. */
27906 bool
27908 {
27915 }
27917 /* Return true if MEM1 and MEM2 can be combined into a single access
27918 of mode MODE, with the combined access having the same address as MEM1. */
27920 bool
27922 {
27926 }
27928 /* Return true if MEM agrees with the ldp-stp policy model.
27929 Otherwise, false. */
27931 bool
27933 {
27938 /* If we have AARCH64_LDP_STP_POLICY_NEVER, reject the load pair. */
27942 /* If we have AARCH64_LDP_STP_POLICY_ALIGNED,
27943 do not emit the load pair unless the alignment is checked to be
27944 at least double the alignment of the type. */
27951 }
27953 /* Given OPERANDS of consecutive load/store, check if we can merge
27954 them into ldp/stp. LOAD is true if they are load instructions. */
27956 bool
27958 {
27963 {
27973 }
27974 else
27975 {
27980 }
27982 /* The mems cannot be volatile. */
27986 /* Check if the addresses are in the form of [base+offset]. */
27991 /* The operands must be of the same size. */
27995 /* The lower memory access must be a mem-pair operand. */
28001 /* Check if lower_mem is ok with the ldp-stp policy model. */
28003 lower_mem_mode))
28008 else
28013 else
28016 /* Check if the registers are of same class. */
28021 }
28023 /* Given OPERANDS of consecutive load/store that can be merged,
28024 swap them if they are not in ascending order. */
28025 void
28027 {
28035 {
28036 /* Irrespective of whether this is a load or a store,
28037 we do the same swap. */
28040 }
28041 }
28043 /* Helper function used for generation of load/store pair instructions, called
28044 from peepholes in aarch64-ldpstp.md. OPERANDS is an array of
28045 operands as matched by the peepholes in that file. LOAD_P is true if we're
28046 generating a load pair, otherwise we're generating a store pair. CODE is
28047 either {ZERO,SIGN}_EXTEND for extending loads or UNKNOWN if we're generating a
28048 standard load/store pair. */
28050 void
28052 {
28058 else
28059 {
28063 }
28064 }
28066 /* Taking X and Y to be HOST_WIDE_INT pointers, return the result of a
28067 comparison between the two. */
28068 int
28070 {
28073 }
28075 /* Taking X and Y to be pairs of RTX, one pointing to a MEM rtx and the
28076 other pointing to a REG rtx containing an offset, compare the offsets
28077 of the two pairs.
28079 Return:
28081 1 iff offset (X) > offset (Y)
28082 0 iff offset (X) == offset (Y)
28083 -1 iff offset (X) < offset (Y) */
28084 int
28086 {
28093 else
28098 else
28101 /* Extract the offsets. */
28108 }
28110 /* Given OPERANDS of consecutive load/store, check if we can merge
28111 them into ldp/stp by adjusting the offset. LOAD is true if they
28112 are load instructions. MODE is the mode of memory operands.
28114 Given below consecutive stores:
28116 str w1, [xb, 0x100]
28117 str w1, [xb, 0x104]
28118 str w1, [xb, 0x108]
28119 str w1, [xb, 0x10c]
28121 Though the offsets are out of the range supported by stp, we can
28122 still pair them after adjusting the offset, like:
28124 add scratch, xb, 0x100
28125 stp w1, w1, [scratch]
28126 stp w1, w1, [scratch, 0x8]
28128 The peephole patterns detecting this opportunity should guarantee
28129 the scratch register is avaliable. */
28131 bool
28133 machine_mode mode)
28134 {
28141 {
28143 {
28148 }
28150 /* Do not attempt to merge the loads if the loads clobber each other. */
28155 }
28156 else
28158 {
28161 }
28163 /* Skip if memory operand is by itself valid for ldp/stp. */
28168 {
28169 /* The mems cannot be volatile. */
28173 /* Check if the addresses are in the form of [base+offset]. */
28177 }
28179 /* Check if the registers are of same class. */
28185 {
28188 }
28189 else
28190 {
28193 }
28195 /* Only the last register in the order in which they occur
28196 may be clobbered by the load. */
28202 /* Check if the bases are same. */
28212 /* Check if the offsets can be put in the right order to do a ldp/stp. */
28214 aarch64_host_wide_int_compare);
28220 /* Check that offsets are within range of each other. The ldp/stp
28221 instructions have 7 bit immediate offsets, so use 0x80. */
28225 /* The offsets must be aligned with respect to each other. */
28229 /* Check if mem[0] is ok with the ldp-stp policy model. */
28234 }
28236 /* Given OPERANDS of consecutive load/store, this function pairs them
28237 into LDP/STP after adjusting the offset. It depends on the fact
28238 that the operands can be sorted so the offsets are correct for STP.
28239 MODE is the mode of memory operands. CODE is the rtl operator
28240 which should be applied to all memory operands, it's SIGN_EXTEND,
28241 ZERO_EXTEND or UNKNOWN. */
28243 bool
28246 {
28253 /* We make changes on a copy as we may still bail out. */
28257 /* Sort the operands. Note for cases as below:
28258 [base + 0x310] = A
28259 [base + 0x320] = B
28260 [base + 0x330] = C
28261 [base + 0x320] = D
28262 We need stable sorting otherwise wrong data may be store to offset 0x320.
28263 Also note the dead store in above case should be optimized away, but no
28264 guarantees here. */
28266 aarch64_ldrstr_offset_compare);
28268 /* Copy the memory operands so that if we have to bail for some
28269 reason the original addresses are unchanged. */
28271 {
28274 }
28275 else
28276 {
28280 }
28287 /* Adjust offset so it can fit in LDP/STP instruction. */
28295 /* The base offset is optimally half way between the two STP/LDP offsets. */
28298 else
28299 /* However, due to issues with negative LDP/STP offset generation for
28300 larger modes, for DF, DD, DI and vector modes. we must not use negative
28301 addresses smaller than 9 signed unadjusted bits can store. This
28302 provides the most range in this case. */
28305 /* Adjust the base so that it is aligned with the addresses but still
28306 optimal. */
28308 /* Fix the offset, bearing in mind we want to make it bigger not
28309 smaller. */
28312 /* The negative range of LDP/STP is one larger than the positive range. */
28315 /* Check if base offset is too big or too small. We can attempt to resolve
28316 this issue by setting it to the maximum value and seeing if the offsets
28317 still fit. */
28319 {
28321 /* We must still make sure that the base offset is aligned with respect
28322 to the address. But it may not be made any bigger. */
28324 }
28326 /* Likewise for the case where the base is too small. */
28328 {
28331 }
28333 /* Offset of the first STP/LDP. */
28336 /* Offset of the second STP/LDP. */
28339 /* The offsets must be within the range of the LDP/STP instructions. */
28354 {
28361 }
28362 else
28363 {
28370 }
28372 /* Emit adjusting instruction. */
28374 /* Emit ldp/stp instructions. */
28376 {
28381 }
28382 else
28383 {
28388 }
28390 }
28392 /* Implement TARGET_VECTORIZE_CONDITIONAL_OPERATION_IS_EXPENSIVE. Assume that
28393 predicated operations when available are beneficial. */
28395 static bool
28397 {
28399 }
28401 /* Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. Assume for now that
28402 it isn't worth branching around empty masked ops (including masked
28403 stores). */
28405 static bool
28407 {
28409 }
28411 /* Return 1 if pseudo register should be created and used to hold
28412 GOT address for PIC code. */
28414 bool
28416 {
28418 }
28420 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
28422 static int
28424 {
28426 {
28433 }
28436 }
28439 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
28440 return the log2 of that value. Otherwise return -1. */
28442 int
28444 {
28459 }
28461 /* If X is a positive CONST_DOUBLE with a value that is the reciprocal of a
28462 power of 2 (i.e 1/2^n) return the number of float bits. e.g. for x==(1/2^n)
28463 return n. Otherwise return -1. */
28465 int
28467 {
28468 REAL_VALUE_TYPE r0;
28476 {
28480 }
28482 }
28484 /* If X is a vector of equal CONST_DOUBLE values and that value is
28485 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
28487 int
28489 {
28507 }
28509 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
28510 to float.
28512 __fp16 always promotes through this hook.
28513 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
28514 through the generic excess precision logic rather than here. */
28516 static tree
28518 {
28524 }
28526 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
28528 static bool
28530 optimization_type opt_type)
28531 {
28533 {
28539 }
28540 }
28542 /* Implement the TARGET_DWARF_POLY_INDETERMINATE_VALUE hook. */
28544 static unsigned int
28547 {
28548 /* Polynomial invariant 1 == (VG / 2) - 1. */
28553 }
28555 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
28556 if MODE is [BH]Fmode, and punt to the generic implementation otherwise. */
28558 static bool
28560 {
28564 }
28566 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
28567 if MODE is [BH]Fmode, and punt to the generic implementation otherwise. */
28569 static bool
28571 {
28578 }
28580 /* Set the value of FLT_EVAL_METHOD.
28581 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
28583 0: evaluate all operations and constants, whose semantic type has at
28584 most the range and precision of type float, to the range and
28585 precision of float; evaluate all other operations and constants to
28586 the range and precision of the semantic type;
28588 N, where _FloatN is a supported interchange floating type
28589 evaluate all operations and constants, whose semantic type has at
28590 most the range and precision of _FloatN type, to the range and
28591 precision of the _FloatN type; evaluate all other operations and
28592 constants to the range and precision of the semantic type;
28594 If we have the ARMv8.2-A extensions then we support _Float16 in native
28595 precision, so we should set this to 16. Otherwise, we support the type,
28596 but want to evaluate expressions in float precision, so set this to
28597 0. */
28599 static enum flt_eval_method
28601 {
28603 {
28606 /* We can calculate either in 16-bit range and precision or
28607 32-bit range and precision. Make that decision based on whether
28608 we have native support for the ARMv8.2-A 16-bit floating-point
28609 instructions or not. */
28611 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
28618 }
28620 }
28622 /* Implement TARGET_C_BITINT_TYPE_INFO.
28623 Return true if _BitInt(N) is supported and fill its details into *INFO. */
28624 bool
28626 {
28640 else
28641 /* The AAPCS for AArch64 defines _BitInt(N > 128) as an array with
28642 type {signed,unsigned} __int128[M] where M*128 >= N. However, to be
28643 able to use libgcc's implementation to support large _BitInt's we need
28644 to use a LIMB_MODE that is no larger than 'long long'. This is why we
28645 use DImode for our internal LIMB_MODE and we define the ABI_LIMB_MODE to
28646 be TImode to ensure we are ABI compliant. */
28651 else
28656 }
28658 /* Implement TARGET_C_MODE_FOR_FLOATING_TYPE. Return TFmode for
28659 TI_LONG_DOUBLE_TYPE which is for long double type, go with the default
28660 one for the others. */
28662 static machine_mode
28664 {
28668 }
28670 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
28671 scheduled for speculative execution. Reject the long-running division
28672 and square-root instructions. */
28674 static bool
28676 {
28678 {
28696 }
28697 }
28699 /* Implement TARGET_COMPUTE_PRESSURE_CLASSES. */
28701 static int
28703 {
28707 /* PR_REGS isn't a useful pressure class because many predicate pseudo
28708 registers need to go in PR_LO_REGS at some point during their
28709 lifetime. Splitting it into two halves has the effect of making
28710 all predicates count against PR_LO_REGS, so that we try whenever
28711 possible to restrict the number of live predicates to 8. This
28712 greatly reduces the amount of spilling in certain loops. */
28716 }
28718 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
28720 static bool
28723 {
28725 }
28727 /* Implement TARGET_EARLY_REMAT_MODES. */
28729 static void
28731 {
28732 /* SVE values are not normally live across a call, so it should be
28733 worth doing early rematerialization even in VL-specific mode. */
28737 }
28739 /* Override the default target speculation_safe_value. */
28740 static rtx
28743 {
28744 /* Maybe we should warn if falling back to hard barriers. They are
28745 likely to be noticably more expensive than the alternative below. */
28757 }
28759 /* Implement TARGET_ESTIMATED_POLY_VALUE.
28760 Look into the tuning structure for an estimate.
28761 KIND specifies the type of requested estimate: min, max or likely.
28762 For cores with a known SVE width all three estimates are the same.
28763 For generic SVE tuning we want to distinguish the maximum estimate from
28764 the minimum and likely ones.
28765 The likely estimate is the same as the minimum in that case to give a
28766 conservative behavior of auto-vectorizing with SVE when it is a win
28767 even for 128-bit SVE.
28768 When SVE width information is available VAL.coeffs[1] is multiplied by
28769 the number of VQ chunks over the initial Advanced SIMD 128 bits. */
28771 static HOST_WIDE_INT
28773 poly_value_estimate_kind kind
28775 {
28778 /* If there is no core-specific information then the minimum and likely
28779 values are based on 128-bit vectors and the maximum is based on
28780 the architectural maximum of 2048 bits. */
28783 {
28789 }
28791 /* Allow sve_width to be a bitmask of different VL, treating the lowest
28792 as likely. This could be made more general if future -mtune options
28793 need it to be. */
28796 else
28799 /* If the core provides width information, use that. */
28802 }
28805 /* Return true for types that could be supported as SIMD return or
28806 argument types. */
28808 static bool
28810 {
28812 {
28815 }
28817 }
28819 /* Determine the lane size for the clone argument/return type. This follows
28820 the LS(P) rule in the VFABIA64. */
28822 static unsigned
28824 {
28827 /* For non map-to-vector types that are pointers we use the element type it
28828 points to. */
28831 {
28839 }
28841 /* For types (or pointers of non map-to-vector types point to) that are
28842 integers or floating point, we use their size if they are 1, 2, 4 or 8.
28843 */
28847 {
28855 }
28856 /* For any other we use the size of uintptr_t. For map-to-vector types that
28857 are pointers, using the size of uintptr_t is the same as using the size of
28858 their type, seeing all pointers are the same size as uintptr_t. */
28860 }
28863 /* Implement TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN. */
28865 static int
28868 tree base_type ATTRIBUTE_UNUSED,
28870 {
28878 /* For now, SVE simdclones won't produce illegal simdlen, So only check
28879 const simdlens here. */
28885 {
28890 }
28893 /* According to AArch64's Vector ABI the type that determines the simdlen is
28894 the narrowest of types, so we ignore base_type for AArch64. */
28897 {
28899 ;
28902 "GCC does not currently support return type %qT "
28904 else
28907 ret_type);
28909 }
28913 /* We are looking for the NDS type here according to the VFABIA64. */
28915 {
28918 }
28919 else
28927 {
28931 {
28933 ;
28936 "GCC does not currently support argument type %qT "
28938 else
28941 arg_type);
28943 }
28949 }
28953 poly_uint64 simdlen;
28955 /* Keep track of the possible simdlens the clones of this function can have,
28956 and check them later to see if we support them. */
28958 {
28963 }
28964 else
28970 /* We currently do not support generating simdclones where vector arguments
28971 do not fit into a single vector register, i.e. vector types that are more
28972 than 128-bits large. This is because of how we currently represent such
28973 types in ACLE, where we use a struct to allow us to pass them as arguments
28974 and return.
28975 Hence why we have to check whether the simdlens available for this
28976 simdclone would cause a vector type to be larger than 128-bits, and reject
28977 such a clone. */
28980 {
28984 {
28985 /* Don't issue a warning for every simdclone when there is no
28986 specific simdlen clause. */
28989 "GCC does not currently support simdlen %wd for "
28994 }
28997 else
28998 j++;
28999 }
29004 {
29006 {
29007 /* Warn the user if we can't generate any simdclone. */
29010 "GCC does not currently support a simdclone with simdlens"
29014 }
29016 }
29021 }
29023 /* Implement TARGET_SIMD_CLONE_ADJUST. */
29025 static void
29027 {
29028 /* Add aarch64_vector_pcs target attribute to SIMD clones so they
29029 use the correct ABI. */
29034 }
29036 /* Implement TARGET_SIMD_CLONE_USABLE. */
29038 static int
29040 {
29042 {
29049 }
29050 }
29052 /* Implement TARGET_COMP_TYPE_ATTRIBUTES */
29054 static int
29056 {
29064 };
29085 }
29087 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
29089 static tree
29091 {
29099 {
29103 newdecl);
29104 }
29105 else
29106 {
29108 {
29112 }
29115 }
29118 }
29120 /* Implement TARGET_GET_MULTILIB_ABI_NAME */
29124 {
29128 }
29130 /* Implement TARGET_STACK_PROTECT_GUARD. In case of a
29131 global variable based guard use the default else
29132 return a null tree. */
29133 static tree
29135 {
29140 }
29142 /* Implement TARGET_INVALID_UNARY_OP. */
29146 {
29147 /* Reject all single-operand operations on __mfp8 except for &. */
29151 /* Operation allowed. */
29153 }
29155 /* Implement TARGET_INVALID_BINARY_OP. */
29159 const_tree type2)
29160 {
29169 /* Reject all 2-operand operations on __mfp8. */
29174 /* Operation allowed. */
29176 }
29178 /* Implement TARGET_MEMTAG_CAN_TAG_ADDRESSES. Here we tell the rest of the
29179 compiler that we automatically ignore the top byte of our pointers, which
29180 allows using -fsanitize=hwaddress. */
29181 bool
29183 {
29185 }
29187 /* Implement TARGET_ASM_FILE_END for AArch64. This adds the AArch64 GNU NOTE
29188 section at the end if needed. */
29189 #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
29190 #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0)
29191 #define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1)
29192 void
29194 {
29205 {
29206 /* Generate .note.gnu.property section. */
29210 /* PT_NOTE header: namesz, descsz, type.
29211 namesz = 4 ("GNU\0")
29212 descsz = 16 (Size of the program property array)
29213 [(12 + padding) * Number of array elements]
29214 type = 5 (NT_GNU_PROPERTY_TYPE_0). */
29220 /* PT_NOTE name. */
29223 /* PT_NOTE contents for NT_GNU_PROPERTY_TYPE_0:
29224 type = GNU_PROPERTY_AARCH64_FEATURE_1_AND
29225 datasz = 4
29226 data = feature_1_and. */
29231 /* Pad the size of the note to the required alignment. */
29233 }
29234 }
29235 #undef GNU_PROPERTY_AARCH64_FEATURE_1_PAC
29236 #undef GNU_PROPERTY_AARCH64_FEATURE_1_BTI
29237 #undef GNU_PROPERTY_AARCH64_FEATURE_1_AND
29239 /* Helper function for straight line speculation.
29240 Return what barrier should be emitted for straight line speculation
29241 mitigation.
29242 When not mitigating against straight line speculation this function returns
29243 an empty string.
29244 When mitigating against straight line speculation, use:
29245 * SB when the v8.5-A SB extension is enabled.
29246 * DSB+ISB otherwise. */
29249 {
29250 return mitigation_required
29253 }
29288 };
29290 /* Function to create a BLR thunk. This thunk is used to mitigate straight
29291 line speculation. Instead of a simple BLR that can be speculated past,
29292 we emit a BL to this thunk, and this thunk contains a BR to the relevant
29293 register. These thunks have the relevant speculation barries put after
29294 their indirect branch so that speculation is blocked.
29296 We use such a thunk so the speculation barriers are kept off the
29297 architecturally executed path in order to reduce the performance overhead.
29299 When optimizing for size we use stubs shared by the linked object.
29300 When optimizing for performance we emit stubs for each function in the hope
29301 that the branch predictor can better train on jumps specific for a given
29302 function. */
29303 rtx
29305 {
29308 {
29309 /* For the thunks shared between different functions in this compilation
29310 unit we use a named symbol -- this is just for users to more easily
29311 understand the generated assembly. */
29315 {
29316 /* Build a decl representing this function stub and record it for
29317 later. We build a decl here so we can use the GCC machinery for
29318 handling sections automatically (through `get_named_section` and
29319 `make_decl_one_only`). That saves us a lot of trouble handling
29320 the specifics of different output file formats. */
29324 NULL_TREE));
29334 }
29337 }
29343 }
29345 /* Helper function for aarch64_sls_emit_blr_function_thunks and
29346 aarch64_sls_emit_shared_blr_thunks below. */
29347 static void
29349 {
29350 /* Save in x16 and branch to that function so this transformation does
29351 not prevent jumping to `BTI c` instructions. */
29354 }
29356 /* Emit all BLR stubs for this particular function.
29357 Here we emit all the BLR stubs needed for the current function. Since we
29358 emit these stubs in a consecutive block we know there will be no speculation
29359 gadgets between each stub, and hence we only emit a speculation barrier at
29360 the end of the stub sequences.
29362 This is called in the TARGET_ASM_FUNCTION_EPILOGUE hook. */
29363 void
29365 {
29370 /* We must save and restore the current function section since this assembly
29371 is emitted at the end of the function. This means it can be emitted *just
29372 after* the cold section of a function. That cold part would be emitted in
29373 a different section. That switch would trigger a `.cfi_endproc` directive
29374 to be emitted in the original section and a `.cfi_startproc` directive to
29375 be emitted in the new section. Switching to the original section without
29376 restoring would mean that the `.cfi_endproc` emitted as a function ends
29377 would happen in a different section -- leaving an unmatched
29378 `.cfi_startproc` in the cold text section and an unmatched `.cfi_endproc`
29379 in the standard text section. */
29383 {
29392 }
29394 /* Can use the SB if needs be here, since this stub will only be used
29395 by the current function, and hence for the current target. */
29398 }
29400 /* Emit shared BLR stubs for the current compilation unit.
29401 Over the course of compiling this unit we may have converted some BLR
29402 instructions to a BL to a shared stub function. This is where we emit those
29403 stub functions.
29404 This function is for the stubs shared between different functions in this
29405 compilation unit. We share when optimizing for size instead of speed.
29407 This function is called through the TARGET_ASM_FILE_END hook. */
29408 void
29410 {
29415 {
29424 /* Only emits if the compiler is configured for an assembler that can
29425 handle visibility directives. */
29430 /* Use the most conservative target to ensure it can always be used by any
29431 function in the translation unit. */
29434 }
29435 }
29437 /* Implement TARGET_ASM_FILE_END. */
29438 void
29440 {
29442 /* Since this function will be called for the ASM_FILE_END hook, we ensure
29443 that what would be called otherwise (e.g. `file_end_indicate_exec_stack`
29444 for FreeBSD) still gets called. */
29445 #ifdef TARGET_ASM_FILE_END
29447 #endif
29448 }
29452 {
29455 {
29458 }
29459 else
29462 }
29464 /* Emit the assembly instruction to load the thread pointer into DEST.
29465 Select between different tpidr_elN registers depending on -mtp= setting. */
29469 {
29477 }
29479 /* Set up the value of REG_ALLOC_ORDER from scratch.
29481 It was previously good practice to put call-clobbered registers ahead
29482 of call-preserved registers, but that isn't necessary these days.
29483 IRA's model of register save/restore costs is much more sophisticated
29484 than the model that a simple ordering could provide. We leave
29485 HONOR_REG_ALLOC_ORDER undefined so that we can get the full benefit
29486 of IRA's model.
29488 However, it is still useful to list registers that are members of
29489 multiple classes after registers that are members of fewer classes.
29490 For example, we have:
29492 - FP_LO8_REGS: v0-v7
29493 - FP_LO_REGS: v0-v15
29494 - FP_REGS: v0-v31
29496 If, as a tie-breaker, we allocate FP_REGS in the order v0-v31,
29497 we run the risk of starving other (lower-priority) pseudos that
29498 require FP_LO8_REGS or FP_LO_REGS. Allocating FP_LO_REGS in the
29499 order v0-v15 could similarly starve pseudos that require FP_LO8_REGS.
29500 Allocating downwards rather than upwards avoids this problem, at least
29501 in code that has reasonable register pressure.
29503 The situation for predicate registers is similar. */
29505 void
29507 {
29513 else
29515 }
29517 /* Return true if the PARALLEL PAR can be used in a VEC_SELECT expression
29518 of vector mode MODE to select half the elements of that vector.
29519 Allow any combination of indices except duplicates (or out of range of
29520 the mode units). */
29522 bool
29524 {
29529 /* Put all the elements of PAR into a hash_set and use its
29530 uniqueness guarantees to check that we don't try to insert the same
29531 element twice. */
29534 {
29540 }
29542 }
29544 /* Return true if PAR1 and PAR2, two PARALLEL rtxes of CONST_INT values,
29545 contain any common elements. */
29547 bool
29549 {
29559 }
29561 /* Implement OPTIMIZE_MODE_SWITCHING. */
29563 bool
29565 {
29573 {
29576 {
29579 }
29580 }
29583 {
29587 }
29589 }
29591 /* Implement TARGET_MODE_EMIT for ZA_SAVE_BUFFER. */
29593 static void
29595 aarch64_tristate_mode prev_mode)
29596 {
29598 {
29601 }
29602 else
29604 }
29606 /* Implement TARGET_MODE_EMIT for LOCAL_SME_STATE. */
29608 static void
29610 aarch64_local_sme_state prev_mode)
29611 {
29612 /* Back-propagation should ensure that we're always starting from
29613 a known mode. */
29617 {
29618 /* Commit any uncommitted lazy save. This leaves ZA either active
29619 and zero (lazy save case) or off (normal case).
29621 The sequence is:
29623 mrs <temp>, tpidr2_el0
29624 cbz <temp>, no_save
29625 bl __arm_tpidr2_save
29626 msr tpidr2_el0, xzr
29627 zero { za } // Only if ZA is live
29628 zero { zt0 } // Only if ZT0 is live
29629 no_save: */
29640 {
29645 }
29647 }
29651 {
29653 {
29654 /* Make ZA active after being inactive.
29656 First handle the case in which the lazy save we set up was
29657 committed by a callee. If the function's source-level ZA state
29658 is live then we must conditionally restore it from the lazy
29659 save buffer. Otherwise we can just force PSTATE.ZA to 1. */
29662 else
29665 /* Now handle the case in which the lazy save was not committed.
29666 In that case, ZA still contains the current function's ZA state,
29667 and we just need to cancel the lazy save. */
29670 /* Restore the ZT0 state, if we have some. */
29675 }
29678 {
29679 /* Retrieve the current function's ZA state from the lazy save
29680 buffer. */
29683 /* Restore the ZT0 state, if we have some. */
29687 }
29691 {
29692 /* INACTIVE_CALLER means that we are enabling ZA for the first
29693 time in this function. The code above means that ZA is either
29694 active and zero (if we committed a lazy save) or off. Handle
29695 the latter case by forcing ZA on.
29697 OFF means that PSTATE.ZA is guaranteed to be 0. We just need
29698 to force it to 1.
29700 Both cases leave ZA zeroed. */
29703 /* Restore the ZT0 state, if we have some. */
29708 }
29712 /* A simple change in liveness, such as in a CFG structure where
29713 ZA is only conditionally defined. No code is needed. */
29717 }
29720 {
29724 {
29725 /* Save the ZT0 state, if we have some. */
29729 /* A transition from ACTIVE_LIVE to INACTIVE_LOCAL is the usual
29730 case of setting up a lazy save buffer before a call.
29731 A transition from INACTIVE_CALLER is similar, except that
29732 the contents of ZA are known to be zero.
29734 A transition from ACTIVE_DEAD means that ZA is live at the
29735 point of the transition, but is dead on at least one incoming
29736 edge. (That is, ZA is only conditionally initialized.)
29737 For efficiency, we want to set up a lazy save even for
29738 dead contents, since forcing ZA off would make later code
29739 restore ZA from the lazy save buffer. */
29742 }
29746 /* We're simply discarding the information about which inactive
29747 state applies. */
29751 }
29755 {
29756 /* Save the ZT0 state, if we have some. */
29763 /* The transition to INACTIVE_CALLER is used before returning from
29764 new("za") functions. Any state in ZA belongs to the current
29765 function rather than a caller, but that state is no longer
29766 needed. Clear any pending lazy save and turn ZA off.
29768 The transition to OFF is used before calling a private-ZA function.
29769 We committed any incoming lazy save above, so at this point any
29770 contents in ZA belong to the current function. */
29779 }
29782 {
29783 /* This is a transition to an exception handler. */
29787 }
29790 }
29792 /* Implement TARGET_MODE_EMIT. */
29794 static void
29796 {
29802 {
29812 }
29816 /* Get the set of clobbered registers that are currently live. */
29817 HARD_REG_SET clobbers = {};
29819 {
29822 vec_rtx_properties properties;
29827 }
29830 /* Emit instructions to save clobbered registers to pseudos. Queue
29831 instructions to restore the registers afterwards.
29833 This should only needed in rare situations. */
29837 {
29842 }
29844 {
29848 }
29850 /* Emit the transition instructions themselves. */
29853 /* Restore the clobbered registers. */
29856 }
29858 /* Return true if INSN references the SME state represented by hard register
29859 REGNO. */
29861 static bool
29863 {
29864 df_ref ref;
29873 }
29875 /* Implement TARGET_MODE_NEEDED for LOCAL_SME_STATE. */
29877 static aarch64_local_sme_state
29879 {
29882 {
29885 {
29888 }
29889 /* Aim for graceful error recovery by picking the value that is
29890 least likely to generate an ICE. */
29892 }
29894 /* A non-local goto is equivalent to a return. We disallow non-local
29895 receivers in functions with SME state, so we know that the target
29896 expects ZA to be dormant or off. */
29901 /* start_private_za_call and end_private_za_call bracket a sequence
29902 that calls a private-ZA function. Force ZA to be turned off if the
29903 function doesn't have any live ZA state, otherwise require ZA to be
29904 inactive. */
29912 /* Force ZA to contain the current function's ZA state if INSN wants
29913 to access it. Do the same for accesses to ZT0, since ZA and ZT0
29914 are both controlled by PSTATE.ZA. */
29922 }
29924 /* Implement TARGET_MODE_NEEDED for ZA_SAVE_BUFFER. */
29926 static aarch64_tristate_mode
29928 {
29929 /* We need to set up a lazy save buffer no later than the first
29930 transition to INACTIVE_LOCAL (which involves setting up a lazy save). */
29935 /* Also make sure that the lazy save buffer is set up before the first
29936 insn that throws internally. The exception handler will sometimes
29937 load from it. */
29942 }
29944 /* Implement TARGET_MODE_NEEDED. */
29946 static int
29948 {
29950 {
29956 }
29958 }
29960 /* Implement TARGET_MODE_AFTER for LOCAL_SME_STATE. */
29962 static aarch64_local_sme_state
29964 HARD_REG_SET live)
29965 {
29966 /* Note places where ZA dies, so that we can try to avoid saving and
29967 restoring state that isn't needed. */
29972 /* Note where ZA is born, e.g. when moving past an __arm_out("za")
29973 function. */
29979 }
29981 /* Implement TARGET_MODE_AFTER. */
29983 static int
29985 {
29987 {
29994 }
29996 }
29998 /* Implement TARGET_MODE_CONFLUENCE for LOCAL_SME_STATE. */
30000 static aarch64_local_sme_state
30002 aarch64_local_sme_state mode2)
30003 {
30004 /* Perform a symmetrical check for two values. */
30006 aarch64_local_sme_state val2)
30007 {
30010 };
30012 /* INACTIVE_CALLER means ZA is off or it has dormant contents belonging
30013 to a caller. OFF is one of the options. */
30018 /* Similarly for dormant contents belonging to the current function. */
30023 /* Treat a conditionally-initialized value as a fully-initialized value. */
30029 }
30031 /* Implement TARGET_MODE_CONFLUENCE. */
30033 static int
30035 {
30038 {
30046 }
30048 }
30050 /* Implement TARGET_MODE_BACKPROP for an entity that either stays
30051 NO throughput, or makes one transition from NO to YES. */
30053 static aarch64_tristate_mode
30055 aarch64_tristate_mode mode2)
30056 {
30057 /* Keep bringing the transition forward until it starts from NO. */
30063 }
30065 /* Implement TARGET_MODE_BACKPROP for LOCAL_SME_STATE. */
30067 static aarch64_local_sme_state
30069 aarch64_local_sme_state mode2)
30070 {
30071 /* We always need to know what the current state is when transitioning
30072 to a new state. Force any location with indeterminate starting state
30073 to be active. */
30076 {
30080 /* The current function's ZA state is not live. */
30085 /* The current function's ZA state is live. */
30089 /* This is a transition to an exception handler. Since we don't
30090 support non-call exceptions for SME functions, the source of
30091 the transition must be known. We'll assert later if that's
30092 not the case. */
30097 }
30100 }
30102 /* Implement TARGET_MODE_BACKPROP. */
30104 static int
30106 {
30108 {
30117 }
30119 }
30121 /* Implement TARGET_MODE_ENTRY. */
30123 static int
30125 {
30127 {
30137 }
30139 }
30141 /* Implement TARGET_MODE_EXIT. */
30143 static int
30145 {
30147 {
30157 }
30159 }
30161 /* Implement TARGET_MODE_EH_HANDLER. */
30163 static int
30165 {
30167 {
30169 /* Require a lazy save buffer to be allocated before the first
30170 insn that can throw. */
30175 }
30177 }
30179 /* Implement TARGET_MODE_PRIORITY. */
30181 static int
30183 {
30185 }
30187 /* Implement TARGET_MD_ASM_ADJUST. */
30195 {
30199 /* "za" in the clobber list of a function with ZA state is defined to
30200 mean that the asm can read from and write to ZA. We can model the
30201 read using a USE, but unfortunately, it's not possible to model the
30202 write directly. Use a separate insn to model the effect.
30204 We must ensure that ZA is active on entry, which is enforced by using
30205 SME_STATE_REGNUM. The asm must ensure that ZA is active on return.
30207 The same thing applies to ZT0. */
30210 {
30214 {
30233 }
30234 }
30236 }
30238 /* BB is the target of an exception or nonlocal goto edge, which means
30239 that PSTATE.SM is known to be 0 on entry. Put it into the state that
30240 the current function requires. */
30242 static bool
30244 {
30252 AARCH64_ISA_MODE_SM_OFF);
30253 aarch64_sme_mode_switch_regs args_switch;
30265 }
30267 /* JUMP is a nonlocal goto. Its target requires PSTATE.SM to be 0 on entry,
30268 so arrange to make it so. */
30270 static bool
30272 {
30280 AARCH64_ISA_MODE_SM_OFF);
30289 }
30291 /* If CALL involves a change in PSTATE.SM, emit the instructions needed
30292 to switch to the new mode and the instructions needed to restore the
30293 original mode. Return true if something changed. */
30294 static bool
30296 {
30297 /* Mode switches for sibling calls are handled via the epilogue. */
30305 /* Switch mode before the call, preserving any argument registers
30306 across the switch. */
30311 callee_isa_mode);
30312 aarch64_sme_mode_switch_regs args_switch;
30326 /* Switch mode after the call, preserving any return registers across
30327 the switch. */
30332 callee_isa_mode);
30333 aarch64_sme_mode_switch_regs return_switch;
30344 }
30349 {
30359 };
30362 {
30366 {}
30368 // opt_pass methods:
30371 };
30373 bool
30375 {
30378 }
30380 /* Emit any instructions needed to switch PSTATE.SM. */
30381 unsigned int
30383 {
30384 basic_block bb;
30389 {
30395 {
30401 }
30408 }
30412 }
30414 }
30416 rtl_opt_pass *
30418 {
30420 }
30422 /* Parse an implementation-defined system register name of
30423 the form S[0-3]_[0-7]_C[0-15]_C[0-15]_[0-7].
30424 Return true if name matched against above pattern, false
30425 otherwise. */
30426 bool
30428 {
30435 {
30442 pos++;
30444 {
30454 }
30458 };
30462 pos++;
30465 pos++;
30470 pos++;
30484 }
30486 /* Return true if REGNAME matches either a known permitted system
30487 register name, or a generic sysreg specification. For use in
30488 back-end predicate `aarch64_sysreg_string'. */
30489 bool
30491 {
30498 }
30500 /* Return the generic sysreg specification for a valid system register
30501 name, otherwise NULL. WRITE_P is true iff the register is being
30502 written to. IS128OP indicates the requested system register should
30503 be checked for a 128-bit implementation. */
30506 {
30509 {
30512 else
30514 }
30523 }
30525 /* Target-specific selftests. */
30527 #if CHECKING_P
30531 /* Selftest for the RTL loader.
30532 Verify that the RTL loader copes with a dump from
30533 print_rtx_function. This is essentially just a test that class
30534 function_reader can handle a real dump, but it also verifies
30535 that lookup_reg_by_dump_name correctly handles hard regs.
30536 The presence of hard reg names in the dump means that the test is
30537 target-specific, hence it is in this file. */
30539 static void
30541 {
30553 /* Verify crtl->return_rtx. */
30557 }
30559 /* Test the fractional_cost class. */
30561 static void
30563 {
30650 }
30652 /* Calculate whether our system register data, as imported from
30653 `aarch64-sys-reg.def' has any duplicate entries. */
30654 static void
30656 {
30660 dup_instances_t duplicate_instances;
30662 /* Every time an encoding is established to come up more than once
30663 we add it to a "clash-analysis queue", which is then used to extract
30664 necessary information from our hash map when establishing whether
30665 repeated encodings are valid. */
30667 /* 1) Collect recurrence information. */
30669 {
30676 }
30678 /* 2) Carry out analysis on collected data. */
30680 {
30685 {
30690 }
30691 }
30692 }
30694 /* Run all target-specific selftests. */
30696 static void
30698 {
30702 }
30708 #undef TARGET_STACK_PROTECT_GUARD
30709 #define TARGET_STACK_PROTECT_GUARD aarch64_stack_protect_guard
30711 #undef TARGET_ADDRESS_COST
30712 #define TARGET_ADDRESS_COST aarch64_address_cost
30714 /* This hook will determines whether unnamed bitfields affect the alignment
30715 of the containing structure. The hook returns true if the structure
30716 should inherit the alignment requirements of an unnamed bitfield's
30717 type. */
30718 #undef TARGET_ALIGN_ANON_BITFIELD
30719 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
30721 #undef TARGET_ASM_ALIGNED_DI_OP
30724 #undef TARGET_ASM_ALIGNED_HI_OP
30727 #undef TARGET_ASM_ALIGNED_SI_OP
30730 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
30731 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
30732 hook_bool_const_tree_hwi_hwi_const_tree_true
30734 #undef TARGET_ASM_FILE_START
30735 #define TARGET_ASM_FILE_START aarch64_start_file
30737 #undef TARGET_ASM_OUTPUT_MI_THUNK
30738 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
30740 #undef TARGET_ASM_SELECT_RTX_SECTION
30741 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
30743 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
30744 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
30746 #undef TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY
30747 #define TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY aarch64_print_patchable_function_entry
30749 #undef TARGET_BUILD_BUILTIN_VA_LIST
30750 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
30752 #undef TARGET_CALLEE_COPIES
30753 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_arg_info_false
30755 #undef TARGET_FRAME_POINTER_REQUIRED
30756 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
30758 #undef TARGET_CAN_ELIMINATE
30759 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
30761 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
30762 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P \
30763 aarch64_function_attribute_inlinable_p
30765 #undef TARGET_NEED_IPA_FN_TARGET_INFO
30766 #define TARGET_NEED_IPA_FN_TARGET_INFO aarch64_need_ipa_fn_target_info
30768 #undef TARGET_UPDATE_IPA_FN_TARGET_INFO
30769 #define TARGET_UPDATE_IPA_FN_TARGET_INFO aarch64_update_ipa_fn_target_info
30771 #undef TARGET_CAN_INLINE_P
30772 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
30774 #undef TARGET_CANNOT_FORCE_CONST_MEM
30775 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
30777 #undef TARGET_CASE_VALUES_THRESHOLD
30778 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
30780 #undef TARGET_CONDITIONAL_REGISTER_USAGE
30781 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
30783 #undef TARGET_MEMBER_TYPE_FORCES_BLK
30784 #define TARGET_MEMBER_TYPE_FORCES_BLK aarch64_member_type_forces_blk
30786 /* Only the least significant bit is used for initialization guard
30787 variables. */
30788 #undef TARGET_CXX_GUARD_MASK_BIT
30789 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
30791 #undef TARGET_C_MODE_FOR_SUFFIX
30792 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
30794 #ifdef TARGET_BIG_ENDIAN_DEFAULT
30795 #undef TARGET_DEFAULT_TARGET_FLAGS
30796 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
30797 #endif
30799 #undef TARGET_CLASS_MAX_NREGS
30800 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
30802 #undef TARGET_BUILTIN_DECL
30803 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
30805 #undef TARGET_BUILTIN_RECIPROCAL
30806 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
30808 #undef TARGET_C_EXCESS_PRECISION
30809 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
30811 #undef TARGET_C_BITINT_TYPE_INFO
30812 #define TARGET_C_BITINT_TYPE_INFO aarch64_bitint_type_info
30814 #undef TARGET_C_MODE_FOR_FLOATING_TYPE
30815 #define TARGET_C_MODE_FOR_FLOATING_TYPE aarch64_c_mode_for_floating_type
30817 #undef TARGET_EXPAND_BUILTIN
30818 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
30820 #undef TARGET_EXPAND_BUILTIN_VA_START
30821 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
30823 #undef TARGET_FOLD_BUILTIN
30824 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
30826 #undef TARGET_FUNCTION_ARG
30827 #define TARGET_FUNCTION_ARG aarch64_function_arg
30829 #undef TARGET_FUNCTION_ARG_ADVANCE
30830 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
30832 #undef TARGET_FUNCTION_ARG_BOUNDARY
30833 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
30835 #undef TARGET_FUNCTION_ARG_PADDING
30836 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
30838 #undef TARGET_GET_RAW_RESULT_MODE
30839 #define TARGET_GET_RAW_RESULT_MODE aarch64_get_reg_raw_mode
30840 #undef TARGET_GET_RAW_ARG_MODE
30841 #define TARGET_GET_RAW_ARG_MODE aarch64_get_reg_raw_mode
30843 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
30844 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
30846 #undef TARGET_FUNCTION_VALUE
30847 #define TARGET_FUNCTION_VALUE aarch64_function_value
30849 #undef TARGET_FUNCTION_VALUE_REGNO_P
30850 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
30852 #undef TARGET_START_CALL_ARGS
30853 #define TARGET_START_CALL_ARGS aarch64_start_call_args
30855 #undef TARGET_END_CALL_ARGS
30856 #define TARGET_END_CALL_ARGS aarch64_end_call_args
30858 #undef TARGET_GIMPLE_FOLD_BUILTIN
30859 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
30861 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
30862 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
30864 #undef TARGET_INIT_BUILTINS
30865 #define TARGET_INIT_BUILTINS aarch64_init_builtins
30867 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
30868 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
30869 aarch64_ira_change_pseudo_allocno_class
30871 #undef TARGET_LEGITIMATE_ADDRESS_P
30872 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
30874 #undef TARGET_LEGITIMATE_CONSTANT_P
30875 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
30877 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
30878 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
30879 aarch64_legitimize_address_displacement
30881 #undef TARGET_LIBGCC_CMP_RETURN_MODE
30882 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
30884 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
30885 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
30886 aarch64_libgcc_floating_mode_supported_p
30888 #undef TARGET_MANGLE_TYPE
30889 #define TARGET_MANGLE_TYPE aarch64_mangle_type
30891 #undef TARGET_INVALID_CONVERSION
30892 #define TARGET_INVALID_CONVERSION aarch64_invalid_conversion
30894 #undef TARGET_INVALID_UNARY_OP
30895 #define TARGET_INVALID_UNARY_OP aarch64_invalid_unary_op
30897 #undef TARGET_INVALID_BINARY_OP
30898 #define TARGET_INVALID_BINARY_OP aarch64_invalid_binary_op
30900 #undef TARGET_VERIFY_TYPE_CONTEXT
30901 #define TARGET_VERIFY_TYPE_CONTEXT aarch64_verify_type_context
30903 #undef TARGET_MEMORY_MOVE_COST
30904 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
30906 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
30907 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
30909 #undef TARGET_MUST_PASS_IN_STACK
30910 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
30912 /* This target hook should return true if accesses to volatile bitfields
30913 should use the narrowest mode possible. It should return false if these
30914 accesses should use the bitfield container type. */
30915 #undef TARGET_NARROW_VOLATILE_BITFIELD
30916 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
30918 #undef TARGET_OPTION_OVERRIDE
30919 #define TARGET_OPTION_OVERRIDE aarch64_override_options
30921 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
30922 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
30923 aarch64_override_options_after_change
30925 #undef TARGET_OFFLOAD_OPTIONS
30926 #define TARGET_OFFLOAD_OPTIONS aarch64_offload_options
30928 #undef TARGET_OPTION_RESTORE
30929 #define TARGET_OPTION_RESTORE aarch64_option_restore
30931 #undef TARGET_OPTION_PRINT
30932 #define TARGET_OPTION_PRINT aarch64_option_print
30934 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
30935 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
30937 #undef TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P
30938 #define TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P \
30939 aarch64_option_valid_version_attribute_p
30941 #undef TARGET_SET_CURRENT_FUNCTION
30942 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
30944 #undef TARGET_PASS_BY_REFERENCE
30945 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
30947 #undef TARGET_PREFERRED_RELOAD_CLASS
30948 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
30950 #undef TARGET_SCHED_REASSOCIATION_WIDTH
30951 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
30953 #undef TARGET_DWARF_FRAME_REG_MODE
30954 #define TARGET_DWARF_FRAME_REG_MODE aarch64_dwarf_frame_reg_mode
30956 #undef TARGET_OUTPUT_CFI_DIRECTIVE
30957 #define TARGET_OUTPUT_CFI_DIRECTIVE aarch64_output_cfi_directive
30959 #undef TARGET_DW_CFI_OPRND1_DESC
30960 #define TARGET_DW_CFI_OPRND1_DESC aarch64_dw_cfi_oprnd1_desc
30962 #undef TARGET_PROMOTED_TYPE
30963 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
30965 #undef TARGET_SECONDARY_RELOAD
30966 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
30968 #undef TARGET_SECONDARY_MEMORY_NEEDED
30969 #define TARGET_SECONDARY_MEMORY_NEEDED aarch64_secondary_memory_needed
30971 #undef TARGET_SHIFT_TRUNCATION_MASK
30972 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
30974 #undef TARGET_SETUP_INCOMING_VARARGS
30975 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
30977 #undef TARGET_STRUCT_VALUE_RTX
30978 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
30980 #undef TARGET_REGISTER_MOVE_COST
30981 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
30983 #undef TARGET_RETURN_IN_MEMORY
30984 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
30986 #undef TARGET_RETURN_IN_MSB
30987 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
30989 #undef TARGET_RTX_COSTS
30990 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
30992 #undef TARGET_INSN_COST
30993 #define TARGET_INSN_COST aarch64_insn_cost
30995 #undef TARGET_SCALAR_MODE_SUPPORTED_P
30996 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
30998 #undef TARGET_SCHED_ISSUE_RATE
30999 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
31001 #undef TARGET_SCHED_VARIABLE_ISSUE
31002 #define TARGET_SCHED_VARIABLE_ISSUE aarch64_sched_variable_issue
31004 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
31005 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
31006 aarch64_sched_first_cycle_multipass_dfa_lookahead
31008 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
31009 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
31010 aarch64_first_cycle_multipass_dfa_lookahead_guard
31012 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
31013 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
31014 aarch64_get_separate_components
31016 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
31017 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
31018 aarch64_components_for_bb
31020 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
31021 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
31022 aarch64_disqualify_components
31024 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
31025 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
31026 aarch64_emit_prologue_components
31028 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
31029 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
31030 aarch64_emit_epilogue_components
31032 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
31033 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
31034 aarch64_set_handled_components
31036 #undef TARGET_TRAMPOLINE_INIT
31037 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
31039 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
31040 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
31042 #undef TARGET_VECTOR_MODE_SUPPORTED_P
31043 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
31045 #undef TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P
31046 #define TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P aarch64_vector_mode_supported_any_target_p
31048 #undef TARGET_COMPATIBLE_VECTOR_TYPES_P
31049 #define TARGET_COMPATIBLE_VECTOR_TYPES_P aarch64_compatible_vector_types_p
31051 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
31052 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
31053 aarch64_builtin_support_vector_misalignment
31055 #undef TARGET_ARRAY_MODE
31056 #define TARGET_ARRAY_MODE aarch64_array_mode
31058 #undef TARGET_ARRAY_MODE_SUPPORTED_P
31059 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
31061 #undef TARGET_VECTORIZE_CREATE_COSTS
31062 #define TARGET_VECTORIZE_CREATE_COSTS aarch64_vectorize_create_costs
31064 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
31065 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
31066 aarch64_builtin_vectorization_cost
31068 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
31069 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
31071 #undef TARGET_VECTORIZE_BUILTINS
31072 #define TARGET_VECTORIZE_BUILTINS
31074 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES
31075 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES \
31076 aarch64_autovectorize_vector_modes
31078 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
31079 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
31080 aarch64_atomic_assign_expand_fenv
31082 /* Section anchor support. */
31084 #undef TARGET_MIN_ANCHOR_OFFSET
31085 #define TARGET_MIN_ANCHOR_OFFSET -256
31087 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
31088 byte offset; we can do much more for larger data types, but have no way
31089 to determine the size of the access. We assume accesses are aligned. */
31090 #undef TARGET_MAX_ANCHOR_OFFSET
31091 #define TARGET_MAX_ANCHOR_OFFSET 4095
31093 #undef TARGET_VECTORIZE_PREFERRED_DIV_AS_SHIFTS_OVER_MULT
31094 #define TARGET_VECTORIZE_PREFERRED_DIV_AS_SHIFTS_OVER_MULT \
31095 aarch64_vectorize_preferred_div_as_shifts_over_mult
31097 #undef TARGET_VECTOR_ALIGNMENT
31098 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
31100 #undef TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT
31101 #define TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT \
31102 aarch64_vectorize_preferred_vector_alignment
31103 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
31104 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
31105 aarch64_simd_vector_alignment_reachable
31107 /* vec_perm support. */
31109 #undef TARGET_VECTORIZE_VEC_PERM_CONST
31110 #define TARGET_VECTORIZE_VEC_PERM_CONST \
31111 aarch64_vectorize_vec_perm_const
31113 #undef TARGET_VECTORIZE_RELATED_MODE
31114 #define TARGET_VECTORIZE_RELATED_MODE aarch64_vectorize_related_mode
31115 #undef TARGET_VECTORIZE_GET_MASK_MODE
31116 #define TARGET_VECTORIZE_GET_MASK_MODE aarch64_get_mask_mode
31117 #undef TARGET_VECTORIZE_CONDITIONAL_OPERATION_IS_EXPENSIVE
31118 #define TARGET_VECTORIZE_CONDITIONAL_OPERATION_IS_EXPENSIVE \
31119 aarch64_conditional_operation_is_expensive
31120 #undef TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE
31121 #define TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE \
31122 aarch64_empty_mask_is_expensive
31123 #undef TARGET_PREFERRED_ELSE_VALUE
31124 #define TARGET_PREFERRED_ELSE_VALUE \
31125 aarch64_preferred_else_value
31127 #undef TARGET_INIT_LIBFUNCS
31128 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
31130 #undef TARGET_FIXED_CONDITION_CODE_REGS
31131 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
31133 #undef TARGET_FLAGS_REGNUM
31134 #define TARGET_FLAGS_REGNUM CC_REGNUM
31136 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
31137 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
31139 #undef TARGET_ASAN_SHADOW_OFFSET
31140 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
31142 #undef TARGET_LEGITIMIZE_ADDRESS
31143 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
31145 #undef TARGET_SCHED_CAN_SPECULATE_INSN
31146 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
31148 #undef TARGET_CAN_USE_DOLOOP_P
31149 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
31151 #undef TARGET_SCHED_ADJUST_PRIORITY
31152 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
31154 #undef TARGET_SCHED_MACRO_FUSION_P
31155 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
31157 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
31158 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
31160 #undef TARGET_SCHED_FUSION_PRIORITY
31161 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
31163 #undef TARGET_UNSPEC_MAY_TRAP_P
31164 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
31166 #undef TARGET_USE_PSEUDO_PIC_REG
31167 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
31169 #undef TARGET_PRINT_OPERAND
31170 #define TARGET_PRINT_OPERAND aarch64_print_operand
31172 #undef TARGET_PRINT_OPERAND_ADDRESS
31173 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
31175 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
31176 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA aarch64_output_addr_const_extra
31178 #undef TARGET_OPTAB_SUPPORTED_P
31179 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
31181 #undef TARGET_OMIT_STRUCT_RETURN_REG
31182 #define TARGET_OMIT_STRUCT_RETURN_REG true
31184 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
31185 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE \
31186 aarch64_dwarf_poly_indeterminate_value
31188 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
31189 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
31190 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
31192 #undef TARGET_HARD_REGNO_NREGS
31193 #define TARGET_HARD_REGNO_NREGS aarch64_hard_regno_nregs
31194 #undef TARGET_HARD_REGNO_MODE_OK
31195 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
31197 #undef TARGET_MODES_TIEABLE_P
31198 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
31200 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
31201 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
31202 aarch64_hard_regno_call_part_clobbered
31204 #undef TARGET_INSN_CALLEE_ABI
31205 #define TARGET_INSN_CALLEE_ABI aarch64_insn_callee_abi
31207 #undef TARGET_CONSTANT_ALIGNMENT
31208 #define TARGET_CONSTANT_ALIGNMENT aarch64_constant_alignment
31210 #undef TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE
31211 #define TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE \
31212 aarch64_stack_clash_protection_alloca_probe_range
31214 #undef TARGET_COMPUTE_PRESSURE_CLASSES
31215 #define TARGET_COMPUTE_PRESSURE_CLASSES aarch64_compute_pressure_classes
31217 #undef TARGET_CAN_CHANGE_MODE_CLASS
31218 #define TARGET_CAN_CHANGE_MODE_CLASS aarch64_can_change_mode_class
31220 #undef TARGET_SELECT_EARLY_REMAT_MODES
31221 #define TARGET_SELECT_EARLY_REMAT_MODES aarch64_select_early_remat_modes
31223 #undef TARGET_SPECULATION_SAFE_VALUE
31224 #define TARGET_SPECULATION_SAFE_VALUE aarch64_speculation_safe_value
31226 #undef TARGET_ESTIMATED_POLY_VALUE
31227 #define TARGET_ESTIMATED_POLY_VALUE aarch64_estimated_poly_value
31229 #undef TARGET_ATTRIBUTE_TABLE
31230 #define TARGET_ATTRIBUTE_TABLE aarch64_attribute_table
31232 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
31233 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
31234 aarch64_simd_clone_compute_vecsize_and_simdlen
31236 #undef TARGET_SIMD_CLONE_ADJUST
31237 #define TARGET_SIMD_CLONE_ADJUST aarch64_simd_clone_adjust
31239 #undef TARGET_SIMD_CLONE_USABLE
31240 #define TARGET_SIMD_CLONE_USABLE aarch64_simd_clone_usable
31242 #undef TARGET_COMP_TYPE_ATTRIBUTES
31243 #define TARGET_COMP_TYPE_ATTRIBUTES aarch64_comp_type_attributes
31245 #undef TARGET_MERGE_DECL_ATTRIBUTES
31246 #define TARGET_MERGE_DECL_ATTRIBUTES aarch64_merge_decl_attributes
31248 #undef TARGET_GET_MULTILIB_ABI_NAME
31249 #define TARGET_GET_MULTILIB_ABI_NAME aarch64_get_multilib_abi_name
31251 #undef TARGET_FNTYPE_ABI
31252 #define TARGET_FNTYPE_ABI aarch64_fntype_abi
31254 #undef TARGET_MEMTAG_CAN_TAG_ADDRESSES
31255 #define TARGET_MEMTAG_CAN_TAG_ADDRESSES aarch64_can_tag_addresses
31257 #if CHECKING_P
31258 #undef TARGET_RUN_TARGET_SELFTESTS
31259 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests
31262 #undef TARGET_ASM_POST_CFI_STARTPROC
31263 #define TARGET_ASM_POST_CFI_STARTPROC aarch64_post_cfi_startproc
31265 #undef TARGET_STRICT_ARGUMENT_NAMING
31266 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
31268 #undef TARGET_MODE_EMIT
31269 #define TARGET_MODE_EMIT aarch64_mode_emit
31271 #undef TARGET_MODE_NEEDED
31272 #define TARGET_MODE_NEEDED aarch64_mode_needed
31274 #undef TARGET_MODE_AFTER
31275 #define TARGET_MODE_AFTER aarch64_mode_after
31277 #undef TARGET_MODE_CONFLUENCE
31278 #define TARGET_MODE_CONFLUENCE aarch64_mode_confluence
31280 #undef TARGET_MODE_BACKPROP
31281 #define TARGET_MODE_BACKPROP aarch64_mode_backprop
31283 #undef TARGET_MODE_ENTRY
31284 #define TARGET_MODE_ENTRY aarch64_mode_entry
31286 #undef TARGET_MODE_EXIT
31287 #define TARGET_MODE_EXIT aarch64_mode_exit
31289 #undef TARGET_MODE_EH_HANDLER
31290 #define TARGET_MODE_EH_HANDLER aarch64_mode_eh_handler
31292 #undef TARGET_MODE_PRIORITY
31293 #define TARGET_MODE_PRIORITY aarch64_mode_priority
31295 #undef TARGET_MD_ASM_ADJUST
31296 #define TARGET_MD_ASM_ADJUST aarch64_md_asm_adjust
31298 #undef TARGET_ASM_FILE_END
31299 #define TARGET_ASM_FILE_END aarch64_asm_file_end
31301 #undef TARGET_ASM_FUNCTION_EPILOGUE
31302 #define TARGET_ASM_FUNCTION_EPILOGUE aarch64_sls_emit_blr_function_thunks
31304 #undef TARGET_HAVE_SHADOW_CALL_STACK
31305 #define TARGET_HAVE_SHADOW_CALL_STACK true
31307 #undef TARGET_CONST_ANCHOR
31308 #define TARGET_CONST_ANCHOR 0x1000000
31310 #undef TARGET_EXTRA_LIVE_ON_ENTRY
31311 #define TARGET_EXTRA_LIVE_ON_ENTRY aarch64_extra_live_on_entry
31313 #undef TARGET_USE_LATE_PROLOGUE_EPILOGUE
31314 #define TARGET_USE_LATE_PROLOGUE_EPILOGUE aarch64_use_late_prologue_epilogue
31316 #undef TARGET_EMIT_EPILOGUE_FOR_SIBCALL
31317 #define TARGET_EMIT_EPILOGUE_FOR_SIBCALL aarch64_expand_epilogue
31319 #undef TARGET_OPTION_FUNCTION_VERSIONS
31320 #define TARGET_OPTION_FUNCTION_VERSIONS aarch64_common_function_versions
31322 #undef TARGET_COMPARE_VERSION_PRIORITY
31323 #define TARGET_COMPARE_VERSION_PRIORITY aarch64_compare_version_priority
31325 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
31326 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
31327 aarch64_generate_version_dispatcher_body
31329 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
31330 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
31331 aarch64_get_function_versions_dispatcher
31333 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
31334 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME aarch64_mangle_decl_assembler_name