gcc/config/aarch64/tuning_models/neoversev1.h

   1 /* Tuning model description for AArch64 architecture.
   2    Copyright (C) 2009-2024 Free Software Foundation, Inc.
   3
   4    This file is part of GCC.
   5
   6    GCC is free software; you can redistribute it and/or modify it
   7    under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    GCC is distributed in the hope that it will be useful, but
  12    WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14    General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GCC; see the file COPYING3.  If not see
  18    <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef GCC_AARCH64_H_NEOVERSEV1
  21 #define GCC_AARCH64_H_NEOVERSEV1
  22
  23 #include "generic.h"
  24
  25 static const struct cpu_addrcost_table neoversev1_addrcost_table =
  26 {
  27     {
  28       1, /* hi  */
  29       0, /* si  */
  30       0, /* di  */
  31       1, /* ti  */
  32     },
  33   0, /* pre_modify  */
  34   0, /* post_modify  */
  35   3, /* post_modify_ld3_st3  */
  36   3, /* post_modify_ld4_st4  */
  37   0, /* register_offset  */
  38   0, /* register_sextend  */
  39   0, /* register_zextend  */
  40   0 /* imm_offset  */
  41 };
  42
  43 static const struct cpu_regmove_cost neoversev1_regmove_cost =
  44 {
  45   1, /* GP2GP  */
  46   /* Spilling to int<->fp instead of memory is recommended so set
  47      realistic costs compared to memmov_cost.  */
  48   3, /* GP2FP  */
  49   2, /* FP2GP  */
  50   2 /* FP2FP  */
  51 };
  52
  53 static const advsimd_vec_cost neoversev1_advsimd_vector_cost =
  54 {
  55   2, /* int_stmt_cost  */
  56   2, /* fp_stmt_cost  */
  57   4, /* ld2_st2_permute_cost */
  58   4, /* ld3_st3_permute_cost  */
  59   5, /* ld4_st4_permute_cost  */
  60   3, /* permute_cost  */
  61   4, /* reduc_i8_cost  */
  62   4, /* reduc_i16_cost  */
  63   2, /* reduc_i32_cost  */
  64   2, /* reduc_i64_cost  */
  65   6, /* reduc_f16_cost  */
  66   3, /* reduc_f32_cost  */
  67   2, /* reduc_f64_cost  */
  68   2, /* store_elt_extra_cost  */
  69   /* This value is just inherited from the Cortex-A57 table.  */
  70   8, /* vec_to_scalar_cost  */
  71   /* This depends very much on what the scalar value is and
  72      where it comes from.  E.g. some constants take two dependent
  73      instructions or a load, while others might be moved from a GPR.
  74      4 seems to be a reasonable compromise in practice.  */
  75   4, /* scalar_to_vec_cost  */
  76   4, /* align_load_cost  */
  77   4, /* unalign_load_cost  */
  78   /* Although stores have a latency of 2 and compete for the
  79      vector pipes, in practice it's better not to model that.  */
  80   1, /* unalign_store_cost  */
  81   1  /* store_cost  */
  82 };
  83
  84 static const sve_vec_cost neoversev1_sve_vector_cost =
  85 {
  86   {
  87     2, /* int_stmt_cost  */
  88     2, /* fp_stmt_cost  */
  89     4, /* ld2_st2_permute_cost  */
  90     7, /* ld3_st3_permute_cost  */
  91     8, /* ld4_st4_permute_cost  */
  92     3, /* permute_cost  */
  93     /* Theoretically, a reduction involving 31 scalar ADDs could
  94        complete in ~9 cycles and would have a cost of 31.  [SU]ADDV
  95        completes in 14 cycles, so give it a cost of 31 + 5.  */
  96     36, /* reduc_i8_cost  */
  97     /* Likewise for 15 scalar ADDs (~5 cycles) vs. 12: 15 + 7.  */
  98     22, /* reduc_i16_cost  */
  99     /* Likewise for 7 scalar ADDs (~3 cycles) vs. 10: 7 + 7.  */
 100     14, /* reduc_i32_cost  */
 101     /* Likewise for 3 scalar ADDs (~2 cycles) vs. 10: 3 + 8.  */
 102     11, /* reduc_i64_cost  */
 103     /* Theoretically, a reduction involving 15 scalar FADDs could
 104        complete in ~9 cycles and would have a cost of 30.  FADDV
 105        completes in 13 cycles, so give it a cost of 30 + 4.  */
 106     34, /* reduc_f16_cost  */
 107     /* Likewise for 7 scalar FADDs (~6 cycles) vs. 11: 14 + 5.  */
 108     19, /* reduc_f32_cost  */
 109     /* Likewise for 3 scalar FADDs (~4 cycles) vs. 9: 6 + 5.  */
 110     11, /* reduc_f64_cost  */
 111     2, /* store_elt_extra_cost  */
 112     /* This value is just inherited from the Cortex-A57 table.  */
 113     8, /* vec_to_scalar_cost  */
 114     /* See the comment above the Advanced SIMD versions.  */
 115     4, /* scalar_to_vec_cost  */
 116     4, /* align_load_cost  */
 117     4, /* unalign_load_cost  */
 118     /* Although stores have a latency of 2 and compete for the
 119        vector pipes, in practice it's better not to model that.  */
 120     1, /* unalign_store_cost  */
 121     1  /* store_cost  */
 122   },
 123   3, /* clast_cost  */
 124   19, /* fadda_f16_cost  */
 125   11, /* fadda_f32_cost  */
 126   8, /* fadda_f64_cost  */
 127   32, /* gather_load_x32_cost  */
 128   16, /* gather_load_x64_cost  */
 129   96, /* gather_load_x32_init_cost  */
 130   32, /* gather_load_x64_init_cost  */
 131   3 /* scatter_store_elt_cost  */
 132 };
 133
 134 static const aarch64_scalar_vec_issue_info neoversev1_scalar_issue_info =
 135 {
 136   3, /* loads_stores_per_cycle  */
 137   2, /* stores_per_cycle  */
 138   4, /* general_ops_per_cycle  */
 139   0, /* fp_simd_load_general_ops  */
 140   1 /* fp_simd_store_general_ops  */
 141 };
 142
 143 static const aarch64_advsimd_vec_issue_info neoversev1_advsimd_issue_info =
 144 {
 145   {
 146     3, /* loads_stores_per_cycle  */
 147     2, /* stores_per_cycle  */
 148     4, /* general_ops_per_cycle  */
 149     0, /* fp_simd_load_general_ops  */
 150     1 /* fp_simd_store_general_ops  */
 151   },
 152   2, /* ld2_st2_general_ops  */
 153   2, /* ld3_st3_general_ops  */
 154   3 /* ld4_st4_general_ops  */
 155 };
 156
 157 static const aarch64_sve_vec_issue_info neoversev1_sve_issue_info =
 158 {
 159   {
 160     {
 161       2, /* loads_per_cycle  */
 162       2, /* stores_per_cycle  */
 163       2, /* general_ops_per_cycle  */
 164       0, /* fp_simd_load_general_ops  */
 165       1 /* fp_simd_store_general_ops  */
 166     },
 167     2, /* ld2_st2_general_ops  */
 168     2, /* ld3_st3_general_ops  */
 169     3 /* ld4_st4_general_ops  */
 170   },
 171   1, /* pred_ops_per_cycle  */
 172   2, /* while_pred_ops  */
 173   2, /* int_cmp_pred_ops  */
 174   1, /* fp_cmp_pred_ops  */
 175   1, /* gather_scatter_pair_general_ops  */
 176   1 /* gather_scatter_pair_pred_ops  */
 177 };
 178
 179 static const aarch64_vec_issue_info neoversev1_vec_issue_info =
 180 {
 181   &neoversev1_scalar_issue_info,
 182   &neoversev1_advsimd_issue_info,
 183   &neoversev1_sve_issue_info
 184 };
 185
 186 /* Neoverse V1 costs for vector insn classes.  */
 187 static const struct cpu_vector_cost neoversev1_vector_cost =
 188 {
 189   1, /* scalar_int_stmt_cost  */
 190   2, /* scalar_fp_stmt_cost  */
 191   4, /* scalar_load_cost  */
 192   1, /* scalar_store_cost  */
 193   1, /* cond_taken_branch_cost  */
 194   1, /* cond_not_taken_branch_cost  */
 195   &neoversev1_advsimd_vector_cost, /* advsimd  */
 196   &neoversev1_sve_vector_cost, /* sve  */
 197   &neoversev1_vec_issue_info /* issue_info  */
 198 };
 199
 200 static const struct tune_params neoversev1_tunings =
 201 {
 202   &cortexa76_extra_costs,
 203   &neoversev1_addrcost_table,
 204   &neoversev1_regmove_cost,
 205   &neoversev1_vector_cost,
 206   &generic_branch_cost,
 207   &generic_approx_modes,
 208   SVE_256, /* sve_width  */
 209   { 4, /* load_int.  */
 210     2, /* store_int.  */
 211     6, /* load_fp.  */
 212     2, /* store_fp.  */
 213     6, /* load_pred.  */
 214     1 /* store_pred.  */
 215   }, /* memmov_cost.  */
 216   3, /* issue_rate  */
 217   (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_CMP_BRANCH), /* fusible_ops  */
 218   "32:16",      /* function_align.  */
 219   "4",          /* jump_align.  */
 220   "32:16",      /* loop_align.  */
 221   2,    /* int_reassoc_width.  */
 222   4,    /* fp_reassoc_width.  */
 223   4,    /* fma_reassoc_width.  */
 224   2,    /* vec_reassoc_width.  */
 225   2,    /* min_div_recip_mul_sf.  */
 226   2,    /* min_div_recip_mul_df.  */
 227   0,    /* max_case_values.  */
 228   tune_params::AUTOPREFETCHER_WEAK,     /* autoprefetcher_model.  */
 229   (AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
 230    | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
 231    | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT
 232    | AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND
 233    | AARCH64_EXTRA_TUNE_AVOID_PRED_RMW),        /* tune_flags.  */
 234   &generic_prefetch_tune,
 235   AARCH64_LDP_STP_POLICY_ALWAYS,   /* ldp_policy_model.  */
 236   AARCH64_LDP_STP_POLICY_ALWAYS    /* stp_policy_model.  */
 237 };
 238
 239
 240 #endif /* GCC_AARCH64_H_NEOVERSEV1.  */