gcc/config/aarch64/tuning_models/tsv110.h

   1 /* Tuning model description for AArch64 architecture.
   2    Copyright (C) 2009-2024 Free Software Foundation, Inc.
   3
   4    This file is part of GCC.
   5
   6    GCC is free software; you can redistribute it and/or modify it
   7    under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    GCC is distributed in the hope that it will be useful, but
  12    WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14    General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GCC; see the file COPYING3.  If not see
  18    <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef GCC_AARCH64_H_TSV110
  21 #define GCC_AARCH64_H_TSV110
  22
  23 #include "generic.h"
  24
  25 static const struct cpu_addrcost_table tsv110_addrcost_table =
  26 {
  27     {
  28       1, /* hi  */
  29       0, /* si  */
  30       0, /* di  */
  31       1, /* ti  */
  32     },
  33   0, /* pre_modify  */
  34   0, /* post_modify  */
  35   0, /* post_modify_ld3_st3  */
  36   0, /* post_modify_ld4_st4  */
  37   0, /* register_offset  */
  38   1, /* register_sextend  */
  39   1, /* register_zextend  */
  40   0, /* imm_offset  */
  41 };
  42
  43 static const struct cpu_regmove_cost tsv110_regmove_cost =
  44 {
  45   1, /* GP2GP  */
  46   /* Avoid the use of slow int<->fp moves for spilling by setting
  47      their cost higher than memmov_cost.  */
  48   2, /* GP2FP  */
  49   3, /* FP2GP  */
  50   2  /* FP2FP  */
  51 };
  52
  53 static const advsimd_vec_cost tsv110_advsimd_vector_cost =
  54 {
  55   2, /* int_stmt_cost  */
  56   2, /* fp_stmt_cost  */
  57   0, /* ld2_st2_permute_cost  */
  58   0, /* ld3_st3_permute_cost  */
  59   0, /* ld4_st4_permute_cost  */
  60   2, /* permute_cost  */
  61   3, /* reduc_i8_cost  */
  62   3, /* reduc_i16_cost  */
  63   3, /* reduc_i32_cost  */
  64   3, /* reduc_i64_cost  */
  65   3, /* reduc_f16_cost  */
  66   3, /* reduc_f32_cost  */
  67   3, /* reduc_f64_cost  */
  68   3, /* store_elt_extra_cost  */
  69   3, /* vec_to_scalar_cost  */
  70   2, /* scalar_to_vec_cost  */
  71   5, /* align_load_cost  */
  72   5, /* unalign_load_cost  */
  73   1, /* unalign_store_cost  */
  74   1  /* store_cost  */
  75 };
  76
  77 static const struct cpu_vector_cost tsv110_vector_cost =
  78 {
  79   1, /* scalar_int_stmt_cost  */
  80   1, /* scalar_fp_stmt_cost  */
  81   5, /* scalar_load_cost  */
  82   1, /* scalar_store_cost  */
  83   1, /* cond_taken_branch_cost  */
  84   1, /* cond_not_taken_branch_cost  */
  85   &tsv110_advsimd_vector_cost, /* advsimd  */
  86   nullptr, /* sve  */
  87   nullptr /* issue_info  */
  88 };
  89
  90 static const cpu_prefetch_tune tsv110_prefetch_tune =
  91 {
  92   0,                    /* num_slots  */
  93   64,                   /* l1_cache_size  */
  94   64,                   /* l1_cache_line_size  */
  95   512,                  /* l2_cache_size  */
  96   true,                 /* prefetch_dynamic_strides */
  97   -1,                   /* minimum_stride */
  98   -1                    /* default_opt_level  */
  99 };
 100
 101 static const struct tune_params tsv110_tunings =
 102 {
 103   &tsv110_extra_costs,
 104   &tsv110_addrcost_table,
 105   &tsv110_regmove_cost,
 106   &tsv110_vector_cost,
 107   &generic_branch_cost,
 108   &generic_approx_modes,
 109   SVE_NOT_IMPLEMENTED, /* sve_width  */
 110   { 4, /* load_int.  */
 111     4, /* store_int.  */
 112     4, /* load_fp.  */
 113     4, /* store_fp.  */
 114     4, /* load_pred.  */
 115     4 /* store_pred.  */
 116   }, /* memmov_cost.  */
 117   4,    /* issue_rate  */
 118   (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_ALU_BRANCH
 119    | AARCH64_FUSE_ALU_CBZ), /* fusible_ops  */
 120   "16", /* function_align.  */
 121   "4",  /* jump_align.  */
 122   "8",  /* loop_align.  */
 123   2,    /* int_reassoc_width.  */
 124   4,    /* fp_reassoc_width.  */
 125   1,    /* fma_reassoc_width.  */
 126   1,    /* vec_reassoc_width.  */
 127   2,    /* min_div_recip_mul_sf.  */
 128   2,    /* min_div_recip_mul_df.  */
 129   0,    /* max_case_values.  */
 130   tune_params::AUTOPREFETCHER_WEAK,     /* autoprefetcher_model.  */
 131   (AARCH64_EXTRA_TUNE_NONE),     /* tune_flags.  */
 132   &tsv110_prefetch_tune,
 133   AARCH64_LDP_STP_POLICY_ALWAYS,   /* ldp_policy_model.  */
 134   AARCH64_LDP_STP_POLICY_ALWAYS    /* stp_policy_model.  */
 135 };
 136
 137 #endif /* GCC_AARCH64_H_TSV110.  */