gcc/config/gcn/gcn-opts.h

   1 /* Copyright (C) 2016-2024 Free Software Foundation, Inc.
   2
   3    This file is free software; you can redistribute it and/or modify it under
   4    the terms of the GNU General Public License as published by the Free
   5    Software Foundation; either version 3 of the License, or (at your option)
   6    any later version.
   7
   8    This file is distributed in the hope that it will be useful, but WITHOUT
   9    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  11    for more details.
  12
  13    You should have received a copy of the GNU General Public License
  14    along with GCC; see the file COPYING3.  If not see
  15    <http://www.gnu.org/licenses/>.  */
  16
  17 #ifndef GCN_OPTS_H
  18 #define GCN_OPTS_H
  19
  20 /* Which processor to generate code or schedule for.  */
  21 enum processor_type
  22 {
  23   PROCESSOR_VEGA10,  // gfx900
  24   PROCESSOR_VEGA20,  // gfx906
  25   PROCESSOR_GFX908,
  26   PROCESSOR_GFX90a,
  27   PROCESSOR_GFX90c,
  28   PROCESSOR_GFX1030,
  29   PROCESSOR_GFX1036,
  30   PROCESSOR_GFX1100,
  31   PROCESSOR_GFX1103
  32 };
  33
  34 #define TARGET_VEGA10 (gcn_arch == PROCESSOR_VEGA10)
  35 #define TARGET_VEGA20 (gcn_arch == PROCESSOR_VEGA20)
  36 #define TARGET_GFX908 (gcn_arch == PROCESSOR_GFX908)
  37 #define TARGET_GFX90a (gcn_arch == PROCESSOR_GFX90a)
  38 #define TARGET_GFX90c (gcn_arch == PROCESSOR_GFX90c)
  39 #define TARGET_GFX1030 (gcn_arch == PROCESSOR_GFX1030)
  40 #define TARGET_GFX1036 (gcn_arch == PROCESSOR_GFX1036)
  41 #define TARGET_GFX1100 (gcn_arch == PROCESSOR_GFX1100)
  42 #define TARGET_GFX1103 (gcn_arch == PROCESSOR_GFX1103)
  43
  44 /* Set in gcn_option_override.  */
  45 extern enum gcn_isa {
  46   ISA_UNKNOWN,
  47   ISA_GCN5,
  48   ISA_RDNA2,
  49   ISA_RDNA3,
  50   ISA_CDNA1,
  51   ISA_CDNA2
  52 } gcn_isa;
  53
  54 #define TARGET_GCN5 (gcn_isa == ISA_GCN5)
  55 #define TARGET_CDNA1 (gcn_isa == ISA_CDNA1)
  56 #define TARGET_CDNA1_PLUS (gcn_isa >= ISA_CDNA1)
  57 #define TARGET_CDNA2 (gcn_isa == ISA_CDNA2)
  58 #define TARGET_CDNA2_PLUS (gcn_isa >= ISA_CDNA2)
  59 #define TARGET_RDNA2 (gcn_isa == ISA_RDNA2)
  60 #define TARGET_RDNA2_PLUS (gcn_isa >= ISA_RDNA2 && gcn_isa < ISA_CDNA1)
  61 #define TARGET_RDNA3 (gcn_isa == ISA_RDNA3)
  62
  63
  64 #define TARGET_PACKED_WORK_ITEMS (TARGET_CDNA2_PLUS || TARGET_RDNA3)
  65
  66 #define TARGET_XNACK (flag_xnack != HSACO_ATTR_OFF)
  67
  68 enum hsaco_attr_type
  69 {
  70   HSACO_ATTR_OFF,
  71   HSACO_ATTR_ON,
  72   HSACO_ATTR_ANY,
  73   HSACO_ATTR_DEFAULT
  74 };
  75
  76 /* Device has an AVGPR register file.  */
  77 #define TARGET_AVGPRS TARGET_CDNA1_PLUS
  78 /* There are load/store instructions for AVGPRS.  */
  79 #define TARGET_AVGPR_MEMOPS TARGET_CDNA2_PLUS
  80 /* AVGPRS may have their own register file, or be combined with VGPRS.  */
  81 #define TARGET_AVGPR_COMBINED TARGET_CDNA2_PLUS
  82 /* global_load/store has reduced offset.  */
  83 #define TARGET_11BIT_GLOBAL_OFFSET TARGET_RDNA2_PLUS
  84 /* The work item details are all encoded into v0.  */
  85 //#define TARGET_PACKED_WORK_ITEMS TARGET_PACKED_WORK_ITEMS
  86 /* CDNA2 load/store costs are reduced.
  87  * TODO: what does this mean?  */
  88 #define TARGET_CDNA2_MEM_COSTS TARGET_CDNA2_PLUS
  89 /* Wave32 devices running in wave64 compatibility mode.  */
  90 #define TARGET_WAVE64_COMPAT TARGET_RDNA2_PLUS
  91 /* RDNA devices have different DPP with reduced capabilities.  */
  92 #define TARGET_DPP_FULL !TARGET_RDNA2_PLUS
  93 #define TARGET_DPP16 TARGET_RDNA2_PLUS
  94 #define TARGET_DPP8 TARGET_RDNA2_PLUS
  95 /* Device requires CDNA1-style manually inserted wait states for AVGPRs.  */
  96 #define TARGET_AVGPR_CDNA1_NOPS TARGET_CDNA1
  97 /* The metadata on different devices need different granularity.  */
  98 #define TARGET_VGPR_GRANULARITY \
  99   (TARGET_RDNA3 ? 12 \
 100    : TARGET_RDNA2_PLUS || TARGET_CDNA2_PLUS ? 8 \
 101    : 4)
 102 /* This mostly affects the metadata.  */
 103 #define TARGET_ARCHITECTED_FLAT_SCRATCH TARGET_RDNA3
 104 /* Device has Sub-DWord Addressing instrucions.  */
 105 #define TARGET_SDWA (!TARGET_RDNA3)
 106 /* Different devices uses different cache control instructions.  */
 107 #define TARGET_WBINVL1_CACHE (!TARGET_RDNA2_PLUS)
 108 #define TARGET_GLn_CACHE TARGET_RDNA2_PLUS
 109
 110 #endif