| blob | c7146e37ec9a8a81afcfc427fe5556284d3749eb |
1 /* Copyright (C) 2024 Free Software Foundation, Inc.
3 This file is part of GCC.
5 GCC is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
8 any later version.
10 GCC is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 Under Section 7 of GPL version 3, you are granted additional
16 permissions described in the GCC Runtime Library Exception, version
17 3.1, as published by the Free Software Foundation.
19 You should have received a copy of the GNU General Public License and
20 a copy of the GCC Runtime Library Exception along with this program;
21 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
22 <http://www.gnu.org/licenses/>. */
24 #ifndef _IMMINTRIN_H_INCLUDED
26 #endif
28 #ifndef _AVX10_2ROUNDINGINTRIN_H_INCLUDED
29 #define _AVX10_2ROUNDINGINTRIN_H_INCLUDED
31 #ifndef __AVX10_2_256__
32 #pragma GCC push_options
34 #define __DISABLE_AVX10_2_256__
37 #ifdef __OPTIMIZE__
38 extern __inline __m256d
41 {
47 __R);
48 }
50 extern __inline __m256d
54 {
59 __R);
60 }
62 extern __inline __m256d
66 {
72 __R);
73 }
75 extern __inline __m256h
78 {
84 __R);
85 }
87 extern __inline __m256h
91 {
96 __R);
97 }
99 extern __inline __m256h
103 {
109 __R);
110 }
112 extern __inline __m256
115 {
121 __R);
122 }
124 extern __inline __m256
128 {
133 __R);
134 }
136 extern __inline __m256
140 {
146 __R);
147 }
149 extern __inline __mmask8
153 {
156 __C,
158 __R);
159 }
161 extern __inline __mmask8
165 {
168 __C,
170 __R);
171 }
173 extern __inline __mmask16
177 {
180 __C,
182 __R);
183 }
185 extern __inline __mmask16
189 {
192 __C,
194 __R);
195 }
197 extern __inline __mmask8
200 {
203 __C,
205 __R);
206 }
208 extern __inline __mmask8
212 {
215 __C,
217 __R);
218 }
220 extern __inline __m128h
223 {
228 __R);
229 }
231 extern __inline __m128h
235 {
239 __R);
240 }
242 extern __inline __m128h
245 {
250 __R);
251 }
253 extern __inline __m256
256 {
261 __R);
262 }
264 extern __inline __m256
268 {
272 __R);
273 }
275 extern __inline __m256
278 {
283 __R);
284 }
286 extern __inline __m128h
289 {
294 __R);
295 }
297 extern __inline __m128h
301 {
305 __R);
306 }
308 extern __inline __m128h
311 {
316 __R);
317 }
319 extern __inline __m128
322 {
327 __R);
328 }
330 extern __inline __m128
334 {
338 __R);
339 }
341 extern __inline __m128
344 {
349 __R);
350 }
352 extern __inline __m128i
355 {
356 return
361 __R);
362 }
364 extern __inline __m128i
368 {
372 __R);
373 }
375 extern __inline __m128i
378 {
383 __R);
384 }
386 extern __inline __m256i
389 {
390 return
395 __R);
396 }
398 extern __inline __m256i
402 {
406 __R);
407 }
409 extern __inline __m256i
412 {
413 return
418 __R);
419 }
421 extern __inline __m128i
424 {
425 return
430 __R);
431 }
433 extern __inline __m128i
437 {
441 __R);
442 }
444 extern __inline __m128i
447 {
452 __R);
453 }
455 extern __inline __m256i
458 {
459 return
464 __R);
465 }
467 extern __inline __m256i
471 {
475 __R);
476 }
478 extern __inline __m256i
481 {
482 return
487 __R);
488 }
490 extern __inline __m256i
493 {
494 return
499 __R);
500 }
502 extern __inline __m256i
506 {
510 __R);
511 }
513 extern __inline __m256i
516 {
517 return
522 __R);
523 }
525 extern __inline __m256d
528 {
533 __R);
534 }
536 extern __inline __m256d
540 {
544 __R);
545 }
547 extern __inline __m256d
550 {
555 __R);
556 }
558 extern __inline __m256
561 {
562 return
567 __R);
568 }
570 extern __inline __m256
574 {
578 __R);
579 }
581 extern __inline __m256
584 {
589 __R);
590 }
592 extern __inline __m256
595 {
600 __R);
601 }
603 extern __inline __m256
607 {
611 __R);
612 }
614 extern __inline __m256
617 {
622 __R);
623 }
625 extern __inline __m256i
628 {
629 return
634 __R);
635 }
637 extern __inline __m256i
641 {
645 __R);
646 }
648 extern __inline __m256i
651 {
652 return
657 __R);
658 }
660 extern __inline __m256i
663 {
664 return
669 __R);
670 }
672 extern __inline __m256i
676 {
680 __R);
681 }
683 extern __inline __m256i
686 {
687 return
692 __R);
693 }
695 extern __inline __m256i
698 {
699 return
704 __R);
705 }
707 extern __inline __m256i
711 {
715 __R);
716 }
718 extern __inline __m256i
721 {
722 return
727 __R);
728 }
730 extern __inline __m256i
733 {
734 return
739 __R);
740 }
742 extern __inline __m256i
746 {
750 __R);
751 }
753 extern __inline __m256i
756 {
757 return
762 __R);
763 }
765 extern __inline __m256i
768 {
769 return
774 __R);
775 }
777 extern __inline __m256i
781 {
785 __R);
786 }
788 extern __inline __m256i
791 {
792 return
797 __R);
798 }
800 extern __inline __m256d
803 {
804 return
809 __R);
810 }
812 extern __inline __m256d
816 {
820 __R);
821 }
823 extern __inline __m256d
826 {
831 __R);
832 }
834 extern __inline __m128h
837 {
842 __R);
843 }
845 extern __inline __m128h
849 {
853 __R);
854 }
856 extern __inline __m128h
859 {
864 __R);
865 }
867 extern __inline __m256i
870 {
871 return
876 __R);
877 }
879 extern __inline __m256i
883 {
887 __R);
888 }
890 extern __inline __m256i
893 {
894 return
899 __R);
900 }
902 extern __inline __m256i
905 {
906 return
911 __R);
912 }
914 extern __inline __m256i
918 {
922 __R);
923 }
925 extern __inline __m256i
928 {
929 return
934 __R);
935 }
937 extern __inline __m256i
940 {
941 return
946 __R);
947 }
949 extern __inline __m256i
953 {
957 __R);
958 }
960 extern __inline __m256i
963 {
964 return
969 __R);
970 }
972 extern __inline __m256i
975 {
976 return
981 __R);
982 }
984 extern __inline __m256i
988 {
992 __R);
993 }
995 extern __inline __m256i
998 {
999 return
1004 __R);
1005 }
1007 extern __inline __m256d
1010 {
1015 __R);
1016 }
1018 extern __inline __m256d
1022 {
1026 __R);
1027 }
1029 extern __inline __m256d
1032 {
1037 __R);
1038 }
1040 extern __inline __m128h
1043 {
1048 __R);
1049 }
1051 extern __inline __m128h
1055 {
1059 __R);
1060 }
1062 extern __inline __m128h
1065 {
1070 __R);
1071 }
1073 extern __inline __m128
1076 {
1081 __R);
1082 }
1084 extern __inline __m128
1088 {
1092 __R);
1093 }
1095 extern __inline __m128
1098 {
1103 __R);
1104 }
1106 extern __inline __m128i
1109 {
1110 return
1115 __R);
1116 }
1118 extern __inline __m128i
1122 {
1126 __R);
1127 }
1129 extern __inline __m128i
1132 {
1137 __R);
1138 }
1140 extern __inline __m256i
1143 {
1144 return
1149 __R);
1150 }
1152 extern __inline __m256i
1156 {
1160 __R);
1161 }
1163 extern __inline __m256i
1166 {
1167 return
1172 __R);
1173 }
1175 extern __inline __m128i
1178 {
1179 return
1184 __R);
1185 }
1187 extern __inline __m128i
1191 {
1195 __R);
1196 }
1198 extern __inline __m128i
1201 {
1202 return
1207 __R);
1208 }
1210 extern __inline __m256i
1213 {
1214 return
1219 __R);
1220 }
1222 extern __inline __m256i
1226 {
1230 __R);
1231 }
1233 extern __inline __m256i
1236 {
1237 return
1242 __R);
1243 }
1245 extern __inline __m256i
1248 {
1249 return
1254 __R);
1255 }
1257 extern __inline __m256i
1261 {
1265 __R);
1266 }
1268 extern __inline __m256i
1271 {
1272 return
1277 __R);
1278 }
1280 extern __inline __m256i
1283 {
1284 return
1289 __R);
1290 }
1292 extern __inline __m256i
1296 {
1300 __R);
1301 }
1303 extern __inline __m256i
1306 {
1307 return
1312 __R);
1313 }
1315 extern __inline __m256i
1318 {
1319 return
1324 __R);
1325 }
1327 extern __inline __m256i
1331 {
1335 __R);
1336 }
1338 extern __inline __m256i
1341 {
1342 return
1347 __R);
1348 }
1350 extern __inline __m256i
1353 {
1354 return
1359 __R);
1360 }
1362 extern __inline __m256i
1366 {
1370 __R);
1371 }
1373 extern __inline __m256i
1376 {
1377 return
1382 __R);
1383 }
1385 extern __inline __m256i
1388 {
1389 return
1394 __R);
1395 }
1397 extern __inline __m256i
1401 {
1405 __R);
1406 }
1408 extern __inline __m256i
1411 {
1412 return
1417 __R);
1418 }
1420 extern __inline __m256i
1423 {
1424 return
1429 __R);
1430 }
1432 extern __inline __m256i
1436 {
1440 __R);
1441 }
1443 extern __inline __m256i
1446 {
1447 return
1452 __R);
1453 }
1455 extern __inline __m256i
1458 {
1459 return
1464 __R);
1465 }
1467 extern __inline __m256i
1471 {
1475 __R);
1476 }
1478 extern __inline __m256i
1481 {
1482 return
1487 __R);
1488 }
1490 extern __inline __m256i
1493 {
1494 return
1499 __R);
1500 }
1502 extern __inline __m256i
1506 {
1510 __R);
1511 }
1513 extern __inline __m256i
1516 {
1517 return
1522 __R);
1523 }
1525 extern __inline __m256i
1528 {
1529 return
1534 __R);
1535 }
1537 extern __inline __m256i
1541 {
1545 __R);
1546 }
1548 extern __inline __m256i
1551 {
1552 return
1557 __R);
1558 }
1560 extern __inline __m256i
1563 {
1564 return
1569 __R);
1570 }
1572 extern __inline __m256i
1576 {
1580 __R);
1581 }
1583 extern __inline __m256i
1586 {
1587 return
1592 __R);
1593 }
1595 extern __inline __m128h
1598 {
1603 __R);
1604 }
1606 extern __inline __m128h
1610 {
1614 __R);
1615 }
1617 extern __inline __m128h
1620 {
1625 __R);
1626 }
1628 extern __inline __m256
1631 {
1632 return
1637 __R);
1638 }
1640 extern __inline __m256
1644 {
1648 __R);
1649 }
1651 extern __inline __m256
1654 {
1659 __R);
1660 }
1662 extern __inline __m256d
1665 {
1670 __R);
1671 }
1673 extern __inline __m256d
1677 {
1681 __R);
1682 }
1684 extern __inline __m256d
1687 {
1692 __R);
1693 }
1695 extern __inline __m128h
1698 {
1703 __R);
1704 }
1706 extern __inline __m128h
1710 {
1714 __R);
1715 }
1717 extern __inline __m128h
1720 {
1725 __R);
1726 }
1728 extern __inline __m128
1731 {
1736 __R);
1737 }
1739 extern __inline __m128
1743 {
1747 __R);
1748 }
1750 extern __inline __m128
1753 {
1758 __R);
1759 }
1761 extern __inline __m256h
1764 {
1769 __R);
1770 }
1772 extern __inline __m256h
1776 {
1780 __R);
1781 }
1783 extern __inline __m256h
1786 {
1791 __R);
1792 }
1794 extern __inline __m256h
1797 {
1802 __R);
1803 }
1805 extern __inline __m256h
1809 {
1813 __R);
1814 }
1816 extern __inline __m256h
1819 {
1824 __R);
1825 }
1827 extern __inline __m256d
1830 {
1836 __R);
1837 }
1839 extern __inline __m256d
1843 {
1848 __R);
1849 }
1851 extern __inline __m256d
1855 {
1861 __R);
1862 }
1864 extern __inline __m256h
1867 {
1873 __R);
1874 }
1876 extern __inline __m256h
1880 {
1885 __R);
1886 }
1888 extern __inline __m256h
1892 {
1898 __R);
1899 }
1901 extern __inline __m256
1904 {
1910 __R);
1911 }
1913 extern __inline __m256
1917 {
1922 __R);
1923 }
1925 extern __inline __m256
1929 {
1935 __R);
1936 }
1937 extern __inline __m256h
1940 {
1944 __R);
1945 }
1947 extern __inline __m256h
1951 {
1955 __U,
1956 __R);
1957 }
1959 extern __inline __m256h
1963 {
1967 __U,
1968 __R);
1969 }
1971 extern __inline __m256h
1975 {
1979 __U,
1980 __R);
1981 }
1983 extern __inline __m256h
1986 {
1987 return
1990 __R);
1991 }
1993 extern __inline __m256h
1997 {
2002 __R);
2003 }
2005 extern __inline __m256h
2009 {
2015 __R);
2016 }
2018 extern __inline __m256d
2022 {
2026 __C,
2028 __R);
2029 }
2031 extern __inline __m256d
2035 {
2039 __C,
2041 __R);
2042 }
2044 extern __inline __m256d
2048 {
2052 __C,
2054 __R);
2055 }
2057 extern __inline __m256
2061 {
2065 __C,
2067 __R);
2068 }
2070 extern __inline __m256
2074 {
2078 __C,
2080 __R);
2081 }
2083 extern __inline __m256
2087 {
2091 __C,
2093 __R);
2094 }
2096 extern __inline __m256d
2099 {
2104 __R);
2105 }
2107 extern __inline __m256d
2111 {
2116 }
2118 extern __inline __m256d
2122 {
2127 __R);
2128 }
2130 extern __inline __m256d
2134 {
2139 __R);
2140 }
2142 extern __inline __m256h
2145 {
2150 __R);
2151 }
2153 extern __inline __m256h
2157 {
2162 __R);
2163 }
2165 extern __inline __m256h
2169 {
2174 __R);
2175 }
2177 extern __inline __m256h
2181 {
2186 __R);
2187 }
2189 extern __inline __m256
2192 {
2197 __R);
2198 }
2200 extern __inline __m256
2204 {
2209 __R);
2210 }
2212 extern __inline __m256
2216 {
2221 __R);
2222 }
2224 extern __inline __m256
2228 {
2233 __R);
2234 }
2236 extern __inline __m256h
2239 {
2243 __R);
2244 }
2246 extern __inline __m256h
2250 {
2254 __U,
2255 __R);
2256 }
2258 extern __inline __m256h
2262 {
2266 __U,
2267 __R);
2268 }
2270 extern __inline __m256h
2274 {
2278 __U,
2279 __R);
2280 }
2282 extern __inline __m256d
2285 {
2290 __R);
2291 }
2293 extern __inline __m256d
2297 {
2302 __R);
2303 }
2305 extern __inline __m256d
2309 {
2314 __R);
2315 }
2317 extern __inline __m256d
2321 {
2326 __R);
2327 }
2329 extern __inline __m256h
2332 {
2337 __R);
2338 }
2340 extern __inline __m256h
2344 {
2349 __R);
2350 }
2352 extern __inline __m256h
2356 {
2361 __R);
2362 }
2364 extern __inline __m256h
2368 {
2373 __R);
2374 }
2376 extern __inline __m256
2379 {
2384 __R);
2385 }
2387 extern __inline __m256
2391 {
2396 __R);
2397 }
2399 extern __inline __m256
2403 {
2408 __R);
2409 }
2411 extern __inline __m256
2415 {
2420 __R);
2421 }
2423 extern __inline __m256d
2426 {
2431 }
2433 extern __inline __m256d
2437 {
2442 }
2444 extern __inline __m256d
2448 {
2453 }
2455 extern __inline __m256d
2459 {
2464 }
2466 extern __inline __m256h
2469 {
2475 }
2477 extern __inline __m256h
2481 {
2487 }
2489 extern __inline __m256h
2493 {
2499 }
2501 extern __inline __m256h
2505 {
2511 }
2513 extern __inline __m256
2516 {
2521 }
2523 extern __inline __m256
2527 {
2532 }
2534 extern __inline __m256
2538 {
2543 }
2545 extern __inline __m256
2549 {
2554 }
2556 extern __inline __m256d
2559 {
2564 __R);
2565 }
2567 extern __inline __m256d
2571 {
2576 __R);
2577 }
2579 extern __inline __m256d
2583 {
2588 __R);
2589 }
2591 extern __inline __m256d
2595 {
2600 __R);
2601 }
2603 extern __inline __m256h
2606 {
2612 __R);
2613 }
2615 extern __inline __m256h
2619 {
2625 __R);
2626 }
2628 extern __inline __m256h
2632 {
2638 __R);
2639 }
2641 extern __inline __m256h
2645 {
2651 __R);
2652 }
2654 extern __inline __m256
2657 {
2662 __R);
2663 }
2665 extern __inline __m256
2669 {
2674 __R);
2675 }
2677 extern __inline __m256
2681 {
2686 __R);
2687 }
2689 extern __inline __m256
2693 {
2698 __R);
2699 }
2701 extern __inline __m256h
2704 {
2707 __R);
2708 }
2710 extern __inline __m256h
2714 {
2719 __R);
2720 }
2722 extern __inline __m256h
2726 {
2732 __R);
2733 }
2735 extern __inline __m256d
2738 {
2743 __R);
2744 }
2746 extern __inline __m256d
2750 {
2755 __R);
2756 }
2758 extern __inline __m256d
2762 {
2767 __R);
2768 }
2770 extern __inline __m256d
2774 {
2779 __R);
2780 }
2782 extern __inline __m256h
2785 {
2791 __R);
2792 }
2794 extern __inline __m256h
2798 {
2804 __R);
2805 }
2807 extern __inline __m256h
2811 {
2817 __R);
2818 }
2820 extern __inline __m256h
2824 {
2830 __R);
2831 }
2833 extern __inline __m256
2836 {
2841 __R);
2842 }
2844 extern __inline __m256
2848 {
2853 __R);
2854 }
2856 extern __inline __m256
2860 {
2865 __R);
2866 }
2868 extern __inline __m256
2872 {
2877 __R);
2878 }
2880 extern __inline __m256d
2883 {
2888 __R);
2889 }
2891 extern __inline __m256d
2895 {
2900 __R);
2901 }
2903 extern __inline __m256d
2907 {
2912 __R);
2913 }
2915 extern __inline __m256d
2919 {
2924 __R);
2925 }
2927 extern __inline __m256h
2930 {
2936 __R);
2937 }
2939 extern __inline __m256h
2943 {
2949 __R);
2950 }
2952 extern __inline __m256h
2956 {
2962 __R);
2963 }
2965 extern __inline __m256h
2969 {
2975 __R);
2976 }
2978 extern __inline __m256
2981 {
2986 __R);
2987 }
2989 extern __inline __m256
2993 {
2998 __R);
2999 }
3001 extern __inline __m256
3005 {
3010 __R);
3011 }
3013 extern __inline __m256
3017 {
3022 __R);
3023 }
3025 extern __inline __m256d
3028 {
3029 return
3034 __R);
3035 }
3037 extern __inline __m256d
3041 {
3045 __R);
3046 }
3048 extern __inline __m256d
3051 {
3056 __R);
3057 }
3059 extern __inline __m256h
3062 {
3067 __R);
3068 }
3070 extern __inline __m256h
3074 {
3078 __R);
3079 }
3081 extern __inline __m256h
3084 {
3089 __R);
3090 }
3092 extern __inline __m256
3095 {
3100 __R);
3101 }
3103 extern __inline __m256
3107 {
3111 __R);
3112 }
3114 extern __inline __m256
3117 {
3122 __R);
3123 }
3125 extern __inline __m256d
3129 {
3130 return
3135 }
3137 extern __inline __m256d
3140 _MM_MANTISSA_NORM_ENUM __B,
3142 {
3146 __R);
3147 }
3149 extern __inline __m256d
3152 _MM_MANTISSA_NORM_ENUM __B,
3154 {
3160 }
3162 extern __inline __m256h
3166 {
3167 return
3172 }
3174 extern __inline __m256h
3177 _MM_MANTISSA_NORM_ENUM __B,
3179 {
3183 __R);
3184 }
3186 extern __inline __m256h
3189 _MM_MANTISSA_NORM_ENUM __B,
3191 {
3197 }
3199 extern __inline __m256
3203 {
3204 return
3209 }
3211 extern __inline __m256
3214 _MM_MANTISSA_NORM_ENUM __B,
3216 {
3220 __R);
3221 }
3223 extern __inline __m256
3226 _MM_MANTISSA_NORM_ENUM __B,
3228 {
3234 }
3236 extern __inline __m256d
3239 {
3245 __R);
3246 }
3248 extern __inline __m256d
3252 {
3257 __R);
3258 }
3260 extern __inline __m256d
3264 {
3270 __R);
3271 }
3273 extern __inline __m256h
3276 {
3282 __R);
3283 }
3285 extern __inline __m256h
3289 {
3294 __R);
3295 }
3297 extern __inline __m256h
3301 {
3307 __R);
3308 }
3310 extern __inline __m256
3313 {
3319 __R);
3320 }
3322 extern __inline __m256
3326 {
3331 __R);
3332 }
3334 extern __inline __m256
3338 {
3344 __R);
3345 }
3347 extern __inline __m256d
3350 {
3356 __R);
3357 }
3359 extern __inline __m256d
3363 {
3368 __R);
3369 }
3371 extern __inline __m256d
3375 {
3381 __R);
3382 }
3384 extern __inline __m256h
3387 {
3393 __R);
3394 }
3396 extern __inline __m256h
3400 {
3405 __R);
3406 }
3408 extern __inline __m256h
3412 {
3418 __R);
3419 }
3421 extern __inline __m256
3424 {
3430 __R);
3431 }
3433 extern __inline __m256
3437 {
3442 __R);
3443 }
3445 extern __inline __m256
3449 {
3455 __R);
3456 }
3458 extern __inline __m256d
3461 {
3467 __R);
3468 }
3470 extern __inline __m256d
3474 {
3479 __R);
3480 }
3482 extern __inline __m256d
3486 {
3492 __R);
3493 }
3495 extern __inline __m256h
3498 {
3504 __R);
3505 }
3507 extern __inline __m256h
3511 {
3516 __R);
3517 }
3519 extern __inline __m256h
3523 {
3529 __R);
3530 }
3532 extern __inline __m256
3535 {
3541 __R);
3542 }
3544 extern __inline __m256
3548 {
3553 __R);
3554 }
3556 extern __inline __m256
3560 {
3566 __R);
3567 }
3569 extern __inline __m256d
3573 {
3576 __C,
3580 __R);
3581 }
3583 extern __inline __m256d
3587 {
3590 __C,
3593 __R);
3594 }
3596 extern __inline __m256d
3600 {
3603 __C,
3607 __R);
3608 }
3610 extern __inline __m256
3613 {
3616 __C,
3620 __R);
3621 }
3623 extern __inline __m256
3627 {
3630 __C,
3633 __R);
3634 }
3636 extern __inline __m256
3640 {
3643 __C,
3647 __R);
3648 }
3650 extern __inline __m256d
3653 {
3655 __C,
3659 __R);
3660 }
3662 extern __inline __m256d
3666 {
3668 __C,
3671 __R);
3672 }
3674 extern __inline __m256d
3678 {
3680 __C,
3684 __R);
3685 }
3687 extern __inline __m256h
3690 {
3692 __C,
3696 __R);
3697 }
3699 extern __inline __m256h
3703 {
3705 __C,
3708 __R);
3709 }
3711 extern __inline __m256h
3715 {
3717 __C,
3721 __R);
3722 }
3724 extern __inline __m256
3727 {
3729 __C,
3733 __R);
3734 }
3736 extern __inline __m256
3740 {
3742 __C,
3745 __R);
3746 }
3748 extern __inline __m256
3752 {
3754 __C,
3758 __R);
3759 }
3761 extern __inline __m256d
3764 {
3765 return
3767 __C,
3771 __R);
3772 }
3774 extern __inline __m256d
3778 {
3780 __C,
3783 __R);
3784 }
3786 extern __inline __m256d
3790 {
3791 return
3793 __C,
3797 __R);
3798 }
3800 extern __inline __m256h
3803 {
3804 return
3806 __C,
3810 __R);
3811 }
3813 extern __inline __m256h
3817 {
3819 __C,
3822 __R);
3823 }
3825 extern __inline __m256h
3829 {
3830 return
3832 __C,
3836 __R);
3837 }
3839 extern __inline __m256
3842 {
3843 return
3845 __C,
3849 __R);
3850 }
3852 extern __inline __m256
3856 {
3858 __C,
3861 __R);
3862 }
3864 extern __inline __m256
3868 {
3870 __C,
3874 __R);
3875 }
3877 extern __inline __m256d
3880 {
3881 return
3887 __R);
3888 }
3890 extern __inline __m256d
3894 {
3899 __R);
3900 }
3902 extern __inline __m256d
3906 {
3912 __R);
3913 }
3915 extern __inline __m256h
3918 {
3919 return
3925 __R);
3926 }
3928 extern __inline __m256h
3932 {
3937 __R);
3938 }
3940 extern __inline __m256h
3944 {
3950 __R);
3951 }
3953 extern __inline __m256
3956 {
3962 __R);
3963 }
3965 extern __inline __m256
3969 {
3974 __R);
3975 }
3977 extern __inline __m256
3981 {
3987 __R);
3988 }
3990 extern __inline __m256d
3993 {
3998 __R);
3999 }
4001 extern __inline __m256d
4005 {
4009 __R);
4010 }
4012 extern __inline __m256d
4015 {
4020 __R);
4021 }
4023 extern __inline __m256h
4026 {
4031 __R);
4032 }
4034 extern __inline __m256h
4038 {
4042 __R);
4043 }
4045 extern __inline __m256h
4048 {
4053 __R);
4054 }
4056 extern __inline __m256
4059 {
4064 __R);
4065 }
4067 extern __inline __m256
4071 {
4075 __R);
4076 }
4078 extern __inline __m256
4081 {
4086 __R);
4087 }
4089 extern __inline __m256d
4092 {
4098 __R);
4099 }
4101 extern __inline __m256d
4105 {
4110 __R);
4111 }
4113 extern __inline __m256d
4117 {
4123 __R);
4124 }
4126 extern __inline __m256h
4129 {
4135 __R);
4136 }
4138 extern __inline __m256h
4142 {
4147 __R);
4148 }
4150 extern __inline __m256h
4154 {
4160 __R);
4161 }
4163 extern __inline __m256
4166 {
4172 __R);
4173 }
4175 extern __inline __m256
4179 {
4184 __R);
4185 }
4187 extern __inline __m256
4191 {
4197 __R);
4198 }
4199 #else
4200 #define _mm256_add_round_pd(A, B, R) \
4201 ((__m256d) __builtin_ia32_addpd256_mask_round ((__v4df) (A), \
4202 (__v4df) (B), \
4203 (__v4df) \
4204 (_mm256_undefined_pd ()), \
4205 (__mmask8) (-1), \
4206 (R)))
4208 #define _mm256_mask_add_round_pd(W, U, A, B, R) \
4209 ((__m256d) __builtin_ia32_addpd256_mask_round ((__v4df) (A), \
4210 (__v4df) (B), \
4211 (__v4df) (W), \
4212 (__mmask8) (U), \
4213 (R)))
4215 #define _mm256_maskz_add_round_pd(U, A, B, R) \
4216 ((__m256d) __builtin_ia32_addpd256_mask_round ((__v4df) (A), \
4217 (__v4df) (B), \
4218 (__v4df) \
4219 (_mm256_setzero_pd ()), \
4220 (__mmask8) (U), \
4221 (R)))
4223 #define _mm256_add_round_ph(A, B, R) \
4224 ((__m256h) __builtin_ia32_addph256_mask_round ((__v16hf) (A), \
4225 (__v16hf) (B), \
4226 (__v16hf) \
4227 (_mm256_undefined_ph ()), \
4228 (__mmask16) (-1), \
4229 (R)))
4231 #define _mm256_mask_add_round_ph(W, U, A, B, R) \
4232 ((__m256h) __builtin_ia32_addph256_mask_round ((__v16hf) (A), \
4233 (__v16hf) (B), \
4234 (__v16hf) (W), \
4235 (__mmask16) (U), \
4236 (R)))
4238 #define _mm256_maskz_add_round_ph(U, A, B, R) \
4239 ((__m256h) __builtin_ia32_addph256_mask_round ((__v16hf) (A), \
4240 (__v16hf) (B), \
4241 (__v16hf) \
4242 (_mm256_setzero_ph ()), \
4243 (__mmask16) (U), \
4244 (R)))
4246 #define _mm256_add_round_ps(A, B, R) \
4247 ((__m256) __builtin_ia32_addps256_mask_round ((__v8sf) (A), \
4248 (__v8sf) (B), \
4249 (__v8sf) \
4250 (_mm256_undefined_ps ()), \
4251 (__mmask8) (-1), \
4252 (R)))
4254 #define _mm256_mask_add_round_ps(W, U, A, B, R) \
4255 ((__m256) __builtin_ia32_addps256_mask_round ((__v8sf) (A), \
4256 (__v8sf) (B), \
4257 (__v8sf) (W), \
4258 (__mmask8) (U), \
4259 (R)))
4261 #define _mm256_maskz_add_round_ps(U, A, B, R)\
4262 ((__m256) __builtin_ia32_addps256_mask_round ((__v8sf) (A), \
4263 (__v8sf) (B), \
4264 (__v8sf) \
4265 (_mm256_setzero_ps ()), \
4266 (__mmask8) (U), \
4267 (R)))
4269 #define _mm256_cmp_round_pd_mask(A, B, C, R) \
4270 ((__mmask8) __builtin_ia32_cmppd256_mask_round ((__v4df) (A), \
4271 (__v4df) (B), \
4272 (C), \
4273 (__mmask8) (-1), \
4274 (R)))
4276 #define _mm256_mask_cmp_round_pd_mask(U, A, B, C, R) \
4277 ((__mmask8) __builtin_ia32_cmppd256_mask_round ((__v4df) (A), \
4278 (__v4df) (B), \
4279 (C), \
4280 (__mmask8) (U), \
4281 (R)))
4283 #define _mm256_cmp_round_ph_mask(A, B, C, R) \
4284 ((__mmask16) __builtin_ia32_cmpph256_mask_round ((__v16hf) (A), \
4285 (__v16hf) (B), \
4286 (C), \
4287 (__mmask16) (-1), \
4288 (R)))
4290 #define _mm256_mask_cmp_round_ph_mask(U, A, B, C, R) \
4291 ((__mmask16) __builtin_ia32_cmpph256_mask_round ((__v16hf) (A), \
4292 (__v16hf) (B), \
4293 (C), \
4294 (__mmask16) (U), \
4295 (R)))
4297 #define _mm256_cmp_round_ps_mask(A, B, C, R) \
4298 ((__mmask8) __builtin_ia32_cmpps256_mask_round ((__v8sf) (A), \
4299 (__v8sf) (B), \
4300 (C), \
4301 (__mmask8) (-1), \
4302 (R)))
4304 #define _mm256_mask_cmp_round_ps_mask(U, A, B, C, R) \
4305 ((__mmask8) __builtin_ia32_cmpps256_mask_round ((__v8sf) (A), \
4306 (__v8sf) (B), \
4307 (C), \
4308 (__mmask8) (U), \
4309 (R)))
4311 #define _mm256_cvt_roundepi32_ph(A, R) \
4312 ((__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) (A), \
4313 (__v8hf) \
4314 (_mm_setzero_ph ()), \
4315 (__mmask8) (-1), \
4316 (R)))
4318 #define _mm256_mask_cvt_roundepi32_ph(W, U, A, R) \
4319 ((__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) (A), \
4320 (__v8hf) (W), \
4321 (__mmask8) (U), \
4322 (R)))
4324 #define _mm256_maskz_cvt_roundepi32_ph(U, A, R) \
4325 ((__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) (A), \
4326 (__v8hf) \
4327 (_mm_setzero_ph ()), \
4328 (__mmask8) (U), \
4329 (R)))
4331 #define _mm256_cvt_roundepi32_ps(A, R) \
4332 ((__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) (A), \
4333 (__v8sf) \
4334 (_mm256_undefined_ps ()), \
4335 (__mmask8) (-1), \
4336 (R)))
4338 #define _mm256_mask_cvt_roundepi32_ps(W, U, A, R) \
4339 ((__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) (A), \
4340 (__v8sf) (W), \
4341 (__mmask8) (U), \
4342 (R)))
4344 #define _mm256_maskz_cvt_roundepi32_ps(U, A, R) \
4345 ((__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) (A), \
4346 (__v8sf) \
4347 (_mm256_setzero_ps ()), \
4348 (__mmask8) (U), \
4349 (R)))
4351 #define _mm256_cvt_roundpd_ph(A, R) \
4352 ((__m128h) __builtin_ia32_vcvtpd2ph256_mask_round ((__v4df) (A), \
4353 (_mm_setzero_ph ()), \
4354 (__mmask8) (-1), \
4355 (R)))
4357 #define _mm256_mask_cvt_roundpd_ph(W, U, A, R) \
4358 ((__m128h) __builtin_ia32_vcvtpd2ph256_mask_round ((__v4df) (A), \
4359 (__v8hf) (W), \
4360 (__mmask8) (U), \
4361 (R)))
4363 #define _mm256_maskz_cvt_roundpd_ph(U, A, R) \
4364 ((__m128h) __builtin_ia32_vcvtpd2ph256_mask_round ((__v4df) (A), \
4365 (_mm_setzero_ph ()), \
4366 (__mmask8) (U), \
4367 (R)))
4369 #define _mm256_cvt_roundpd_ps(A, R) \
4370 ((__m128) __builtin_ia32_cvtpd2ps256_mask_round ((__v4df) (A), \
4371 (__v4sf) \
4372 (_mm_undefined_ps ()), \
4373 (__mmask8) (-1), \
4374 (R)))
4376 #define _mm256_mask_cvt_roundpd_ps(W, U, A, R) \
4377 ((__m128) __builtin_ia32_cvtpd2ps256_mask_round ((__v4df) (A), \
4378 (__v4sf) (W), \
4379 (__mmask8) (U), \
4380 (R)))
4382 #define _mm256_maskz_cvt_roundpd_ps(U, A, R) \
4383 ((__m128) __builtin_ia32_cvtpd2ps256_mask_round ((__v4df) (A), \
4384 (__v4sf) \
4385 (_mm_setzero_ps ()), \
4386 (__mmask8) (U), \
4387 (R)))
4389 #define _mm256_cvt_roundpd_epi32(A, R) \
4390 ((__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) (A), \
4391 (__v4si) \
4392 (_mm_undefined_si128 ()), \
4393 (__mmask8) (-1), \
4394 (R)))
4396 #define _mm256_mask_cvt_roundpd_epi32(W, U, A, R) \
4397 ((__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) (A), \
4398 (__v4si) (W), \
4399 (__mmask8) (U), \
4400 (R)))
4402 #define _mm256_maskz_cvt_roundpd_epi32(U, A, R)\
4403 ((__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) (A), \
4404 (__v4si) \
4405 (_mm_setzero_si128 ()), \
4406 (__mmask8) (U), \
4407 (R)))
4409 #define _mm256_cvt_roundpd_epi64(A, R) \
4410 ((__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) (A), \
4411 (__v4di) \
4412 (_mm256_setzero_si256 ()), \
4413 (__mmask8) (-1), \
4414 (R)))
4416 #define _mm256_mask_cvt_roundpd_epi64(W, U, A, R) \
4417 ((__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) (A), \
4418 (__v4di) (W), \
4419 (__mmask8) (U), \
4420 (R)))
4422 #define _mm256_maskz_cvt_roundpd_epi64(U, A, R) \
4423 ((__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) (A), \
4424 (__v4di) \
4425 (_mm256_setzero_si256 ()), \
4426 (__mmask8) (U), \
4427 (R)))
4429 #define _mm256_cvt_roundpd_epu32(A, R) \
4430 ((__m128i) __builtin_ia32_cvtpd2udq256_mask_round ((__v4df) (A), \
4431 (__v4si) \
4432 (_mm_undefined_si128 ()), \
4433 (__mmask8) (-1), \
4434 (R)))
4436 #define _mm256_mask_cvt_roundpd_epu32(W, U, A, R) \
4437 ((__m128i) __builtin_ia32_cvtpd2udq256_mask_round ((__v4df) (A), \
4438 (__v4si) (W), \
4439 (__mmask8) (U), \
4440 (R)))
4442 #define _mm256_maskz_cvt_roundpd_epu32(U, A, R) \
4443 ((__m128i) __builtin_ia32_cvtpd2udq256_mask_round ((__v4df) (A), \
4444 (__v4si) \
4445 (_mm_setzero_si128 ()), \
4446 (__mmask8) (U), \
4447 (R)))
4449 #define _mm256_cvt_roundpd_epu64(A, R) \
4450 ((__m256i) __builtin_ia32_cvtpd2uqq256_mask_round ((__v4df) (A), \
4451 (__v4di) \
4452 (_mm256_setzero_si256 ()),\
4453 (__mmask8) (-1), \
4454 (R)))
4456 #define _mm256_mask_cvt_roundpd_epu64(W, U, A, R) \
4457 ((__m256i) __builtin_ia32_cvtpd2uqq256_mask_round ((__v4df) (A), \
4458 (__v4di) (W), \
4459 (__mmask8) (U), \
4460 (R)))
4462 #define _mm256_maskz_cvt_roundpd_epu64(U, A, R) \
4463 ((__m256i) __builtin_ia32_cvtpd2uqq256_mask_round ((__v4df) (A), \
4464 (__v4di) \
4465 (_mm256_setzero_si256 ()),\
4466 (__mmask8) (U), \
4467 (R)))
4469 #define _mm256_cvt_roundph_epi32(A, R) \
4470 ((__m256i) __builtin_ia32_vcvtph2dq256_mask_round ((__v8hf) (A), \
4471 (__v8si) \
4472 (_mm256_setzero_si256 ()),\
4473 (__mmask8) (-1), \
4474 (R)))
4476 #define _mm256_mask_cvt_roundph_epi32(W, U, A, R) \
4477 ((__m256i) __builtin_ia32_vcvtph2dq256_mask_round ((__v8hf) (A), \
4478 (__v8si) (W), \
4479 (__mmask8) (U), \
4480 (R)))
4482 #define _mm256_maskz_cvt_roundph_epi32(U, A, R) \
4483 ((__m256i) __builtin_ia32_vcvtph2dq256_mask_round ((__v8hf) (A), \
4484 (__v8si) \
4485 (_mm256_setzero_si256 ()),\
4486 (__mmask8) (U), \
4487 (R)))
4489 #define _mm256_cvt_roundph_pd(A, R) \
4490 ((__m256d) __builtin_ia32_vcvtph2pd256_mask_round ((__v8hf) (A), \
4491 (__v4df) \
4492 (_mm256_setzero_pd ()), \
4493 (__mmask8) (-1), \
4494 (R)))
4496 #define _mm256_mask_cvt_roundph_pd(W, U, A, R) \
4497 ((__m256d) __builtin_ia32_vcvtph2pd256_mask_round ((__v8hf) (A), \
4498 (__v4df) (W), \
4499 (__mmask8) (U), \
4500 (R)))
4502 #define _mm256_maskz_cvt_roundph_pd(U, A, R) \
4503 ((__m256d) __builtin_ia32_vcvtph2pd256_mask_round ((__v8hf) (A), \
4504 (__v4df) \
4505 (_mm256_setzero_pd ()), \
4506 (__mmask8) (U), \
4507 (R)))
4509 #define _mm256_cvt_roundph_ps(A, R) \
4510 ((__m256) __builtin_ia32_vcvtph2ps256_mask_round ((__v8hf) (A), \
4511 (__v8sf) \
4512 (_mm256_undefined_ps ()), \
4513 (__mmask8) (-1), \
4514 (R)))
4516 #define _mm256_mask_cvt_roundph_ps(W, U, A, R) \
4517 ((__m256) __builtin_ia32_vcvtph2ps256_mask_round ((__v8hf) (A), \
4518 (__v8sf) (W), \
4519 (__mmask8) (U), \
4520 (R)))
4522 #define _mm256_maskz_cvt_roundph_ps(U, A, R) \
4523 ((__m256) __builtin_ia32_vcvtph2ps256_mask_round ((__v8hf) (A), \
4524 (__v8sf) \
4525 (_mm256_setzero_ps ()), \
4526 (__mmask8) (U), \
4527 (R)))
4529 #define _mm256_cvtx_roundph_ps(A, R) \
4530 ((__m256) __builtin_ia32_vcvtph2psx256_mask_round ((__v8hf) (A), \
4531 (__v8sf) \
4532 (_mm256_setzero_ps ()), \
4533 (__mmask8) (-1), \
4534 (R)))
4536 #define _mm256_mask_cvtx_roundph_ps(W, U, A, R) \
4537 ((__m256) __builtin_ia32_vcvtph2psx256_mask_round ((__v8hf) (A), \
4538 (__v8sf) (W), \
4539 (__mmask8) (U), \
4540 (R)))
4542 #define _mm256_maskz_cvtx_roundph_ps(U, A, R) \
4543 ((__m256) __builtin_ia32_vcvtph2psx256_mask_round ((__v8hf) (A), \
4544 (__v8sf) \
4545 (_mm256_setzero_ps ()), \
4546 (__mmask8) (U), \
4547 (R)))
4549 #define _mm256_cvt_roundph_epi64(A, R) \
4550 ((__m256i) __builtin_ia32_vcvtph2qq256_mask_round ((__v8hf) (A), \
4551 (__v4di) \
4552 (_mm256_setzero_si256 ()),\
4553 (__mmask8) (-1), \
4554 (R)))
4556 #define _mm256_mask_cvt_roundph_epi64(W, U, A, R) \
4557 ((__m256i) __builtin_ia32_vcvtph2qq256_mask_round ((__v8hf) (A), \
4558 (__v4di) (W), \
4559 (__mmask8) (U), \
4560 (R)))
4562 #define _mm256_maskz_cvt_roundph_epi64(U, A, R) \
4563 ((__m256i) __builtin_ia32_vcvtph2qq256_mask_round ((__v8hf) (A), \
4564 (__v4di) \
4565 (_mm256_setzero_si256 ()),\
4566 (__mmask8) (U), \
4567 (R)))
4569 #define _mm256_cvt_roundph_epu32(A, R) \
4570 ((__m256i) \
4571 __builtin_ia32_vcvtph2udq256_mask_round ((__v8hf) (A), \
4572 (__v8si) \
4573 (_mm256_setzero_si256 ()), \
4574 (__mmask8) (-1), \
4575 (R)))
4577 #define _mm256_mask_cvt_roundph_epu32(W, U, A, R) \
4578 ((__m256i) __builtin_ia32_vcvtph2udq256_mask_round ((__v8hf) (A), \
4579 (__v8si) (W), \
4580 (__mmask8) (U), \
4581 (R)))
4583 #define _mm256_maskz_cvt_roundph_epu32(U, A, R) \
4584 ((__m256i) \
4585 __builtin_ia32_vcvtph2udq256_mask_round ((__v8hf) (A), \
4586 (__v8si) \
4587 (_mm256_setzero_si256 ()), \
4588 (__mmask8) (U), \
4589 (R)))
4591 #define _mm256_cvt_roundph_epu64(A, R) \
4592 ((__m256i) \
4593 __builtin_ia32_vcvtph2uqq256_mask_round ((__v8hf) (A), \
4594 (__v4di) \
4595 (_mm256_setzero_si256 ()), \
4596 (__mmask8) (-1), \
4597 (R)))
4599 #define _mm256_mask_cvt_roundph_epu64(W, U, A, R) \
4600 ((__m256i) __builtin_ia32_vcvtph2uqq256_mask_round ((__v8hf) (A), \
4601 (__v4di) (W), \
4602 (__mmask8) (U), \
4603 (R)))
4605 #define _mm256_maskz_cvt_roundph_epu64(U, A, R) \
4606 ((__m256i) \
4607 __builtin_ia32_vcvtph2uqq256_mask_round ((__v8hf) (A), \
4608 (__v4di) \
4609 (_mm256_setzero_si256 ()), \
4610 (__mmask8) (U), \
4611 (R)))
4613 #define _mm256_cvt_roundph_epu16(A, R) \
4614 ((__m256i) \
4615 __builtin_ia32_vcvtph2uw256_mask_round ((__v16hf) (A), \
4616 (__v16hi) \
4617 (_mm256_undefined_si256 ()), \
4618 (__mmask16) (-1), \
4619 (R)))
4621 #define _mm256_mask_cvt_roundph_epu16(W, U, A, R) \
4622 ((__m256i) __builtin_ia32_vcvtph2uw256_mask_round ((__v16hf) (A), \
4623 (__v16hi) (W), \
4624 (__mmask16) (U), \
4625 (R)))
4627 #define _mm256_maskz_cvt_roundph_epu16(U, A, R) \
4628 ((__m256i) \
4629 __builtin_ia32_vcvtph2uw256_mask_round ((__v16hf) (A), \
4630 (__v16hi) \
4631 (_mm256_setzero_si256 ()), \
4632 (__mmask16) (U), \
4633 (R)))
4635 #define _mm256_cvt_roundph_epi16(A, R) \
4636 ((__m256i) \
4637 __builtin_ia32_vcvtph2w256_mask_round ((__v16hf) (A), \
4638 (__v16hi) \
4639 (_mm256_undefined_si256 ()), \
4640 (__mmask16) (-1), \
4641 (R)))
4643 #define _mm256_mask_cvt_roundph_epi16(W, U, A, R) \
4644 ((__m256i) __builtin_ia32_vcvtph2w256_mask_round ((__v16hf) (A), \
4645 (__v16hi) (W), \
4646 (__mmask16) (U), \
4647 (R)))
4649 #define _mm256_maskz_cvt_roundph_epi16(U, A, R) \
4650 ((__m256i) __builtin_ia32_vcvtph2w256_mask_round ((__v16hf) (A), \
4651 (__v16hi) \
4652 (_mm256_setzero_si256 ()), \
4653 (__mmask16) (U), \
4654 (R)))
4656 #define _mm256_cvt_roundps_pd(A, R) \
4657 ((__m256d) __builtin_ia32_vcvtps2pd256_mask_round ((__v4sf) (A), \
4658 (__v4df) \
4659 (_mm256_undefined_pd ()), \
4660 (__mmask8) (-1), \
4661 (R)))
4663 #define _mm256_mask_cvt_roundps_pd(W, U, A, R) \
4664 ((__m256d) __builtin_ia32_vcvtps2pd256_mask_round ((__v4sf) (A), \
4665 (__v4df) (W), \
4666 (__mmask8) (U), \
4667 (R)))
4669 #define _mm256_maskz_cvt_roundps_pd(U, A, R) \
4670 ((__m256d) __builtin_ia32_vcvtps2pd256_mask_round ((__v4sf) (A), \
4671 (__v4df) \
4672 (_mm256_setzero_pd ()), \
4673 (__mmask8) (U), \
4674 (R)))
4676 #define _mm256_cvtx_roundps_ph(A, R) \
4677 ((__m128h) __builtin_ia32_vcvtps2phx256_mask_round ((__v8sf) (A), \
4678 (__v8hf) \
4679 (_mm_setzero_ph ()), \
4680 (__mmask8) (-1), \
4681 (R)))
4683 #define _mm256_mask_cvtx_roundps_ph(W, U, A, R) \
4684 ((__m128h) __builtin_ia32_vcvtps2phx256_mask_round ((__v8sf) (A), \
4685 (__v8hf) (W), \
4686 (__mmask8) (U), \
4687 (R)))
4689 #define _mm256_maskz_cvtx_roundps_ph(U, A, R) \
4690 ((__m128h) __builtin_ia32_vcvtps2phx256_mask_round ((__v8sf) (A), \
4691 (__v8hf) \
4692 (_mm_setzero_ph ()), \
4693 (__mmask8) (U), \
4694 (R)))
4696 #define _mm256_cvt_roundps_epi32(A, R) \
4697 ((__m256i) \
4698 __builtin_ia32_vcvtps2dq256_mask_round ((__v8sf) (A), \
4699 (__v8si) \
4700 (_mm256_undefined_si256 ()), \
4701 (__mmask8) (-1), \
4702 (R)))
4704 #define _mm256_mask_cvt_roundps_epi32(W, U, A, R) \
4705 ((__m256i) __builtin_ia32_vcvtps2dq256_mask_round ((__v8sf) (A), \
4706 (__v8si) (W), \
4707 (__mmask8) (U), \
4708 (R)))
4710 #define _mm256_maskz_cvt_roundps_epi32(U, A, R) \
4711 ((__m256i) \
4712 __builtin_ia32_vcvtps2dq256_mask_round ((__v8sf) (A), \
4713 (__v8si) \
4714 (_mm256_setzero_si256 ()), \
4715 (__mmask8) (U), \
4716 (R)))
4718 #define _mm256_cvt_roundps_epi64(A, R) \
4719 ((__m256i) __builtin_ia32_cvtps2qq256_mask_round ((__v4sf) (A), \
4720 (__v4di) \
4721 (_mm256_setzero_si256 ()), \
4722 (__mmask8) (-1), \
4723 (R)))
4725 #define _mm256_mask_cvt_roundps_epi64(W, U, A, R) \
4726 ((__m256i) __builtin_ia32_cvtps2qq256_mask_round ((__v4sf) (A), \
4727 (__v4di) (W), \
4728 (__mmask8) (U), \
4729 (R)))
4731 #define _mm256_maskz_cvt_roundps_epi64(U, A, R) \
4732 ((__m256i) __builtin_ia32_cvtps2qq256_mask_round ((__v4sf) (A), \
4733 (__v4di) \
4734 (_mm256_setzero_si256 ()), \
4735 (__mmask8) (U), \
4736 (R)))
4738 #define _mm256_cvt_roundps_epu32(A, R) \
4739 ((__m256i) \
4740 __builtin_ia32_cvtps2udq256_mask_round ((__v8sf) (A), \
4741 (__v8si) \
4742 (_mm256_undefined_si256 ()), \
4743 (__mmask8) (-1), \
4744 (R)))
4746 #define _mm256_mask_cvt_roundps_epu32(W, U, A, R) \
4747 ((__m256i) __builtin_ia32_cvtps2udq256_mask_round ((__v8sf) (A), \
4748 (__v8si) (W), \
4749 (__mmask8) (U), \
4750 (R)))
4752 #define _mm256_maskz_cvt_roundps_epu32(U, A, R) \
4753 ((__m256i) \
4754 __builtin_ia32_cvtps2udq256_mask_round ((__v8sf) (A), \
4755 (__v8si) \
4756 (_mm256_setzero_si256 ()), \
4757 (__mmask8) (U), \
4758 (R)))
4760 #define _mm256_cvt_roundps_epu64(B, R) \
4761 ((__m256i) \
4762 __builtin_ia32_cvtps2uqq256_mask_round ((__v4sf) (B), \
4763 (__v4di) \
4764 (_mm256_setzero_si256 ()), \
4765 (__mmask8) (-1), \
4766 (R)))
4768 #define _mm256_mask_cvt_roundps_epu64(W, U, A, R) \
4769 ((__m256i) __builtin_ia32_cvtps2uqq256_mask_round ((__v4sf) (A), \
4770 (__v4di) (W), \
4771 (__mmask8) (U), \
4772 (R)))
4774 #define _mm256_maskz_cvt_roundps_epu64(U, A, R) \
4775 ((__m256i) \
4776 __builtin_ia32_cvtps2uqq256_mask_round ((__v4sf) (A), \
4777 (__v4di) \
4778 (_mm256_setzero_si256 ()), \
4779 (__mmask8) (U), \
4780 (R)))
4782 #define _mm256_cvt_roundepi64_pd(A, R) \
4783 ((__m256d) __builtin_ia32_cvtqq2pd256_mask_round ((__v4di) (A), \
4784 (__v4df) \
4785 (_mm256_setzero_pd ()), \
4786 (__mmask8) (-1), \
4787 (R)))
4789 #define _mm256_mask_cvt_roundepi64_pd(W, U, A, R) \
4790 ((__m256d) __builtin_ia32_cvtqq2pd256_mask_round ((__v4di) (A), \
4791 (__v4df) (W), \
4792 (__mmask8) (U), \
4793 (R)))
4795 #define _mm256_maskz_cvt_roundepi64_pd(U, A, R) \
4796 ((__m256d) __builtin_ia32_cvtqq2pd256_mask_round ((__v4di) (A), \
4797 (__v4df) \
4798 (_mm256_setzero_pd ()), \
4799 (__mmask8) (U), \
4800 (R)))
4802 #define _mm256_cvt_roundepi64_ph(A, R) \
4803 ((__m128h) __builtin_ia32_vcvtqq2ph256_mask_round ((__v4di) (A), \
4804 (__v8hf) \
4805 (_mm_setzero_ph ()), \
4806 (__mmask8) (-1), \
4807 (R)))
4809 #define _mm256_mask_cvt_roundepi64_ph(W, U, A, R) \
4810 ((__m128h) __builtin_ia32_vcvtqq2ph256_mask_round ((__v4di) (A), \
4811 (__v8hf) (W), \
4812 (__mmask8) (U), \
4813 (R)))
4815 #define _mm256_maskz_cvt_roundepi64_ph(U, A, R) \
4816 ((__m128h) __builtin_ia32_vcvtqq2ph256_mask_round ((__v4di) (A), \
4817 (__v8hf) \
4818 (_mm_setzero_ph ()), \
4819 (__mmask8) (U), \
4820 (R)))
4822 #define _mm256_cvt_roundepi64_ps(A, R) \
4823 ((__m128) __builtin_ia32_cvtqq2ps256_mask_round ((__v4di) (A), \
4824 (__v4sf) \
4825 (_mm_setzero_ps ()), \
4826 (__mmask8) (-1), \
4827 (R)))
4829 #define _mm256_mask_cvt_roundepi64_ps(W, U, A, R) \
4830 ((__m128) __builtin_ia32_cvtqq2ps256_mask_round ((__v4di) (A), \
4831 (__v4sf) (W), \
4832 (__mmask8) (U), \
4833 (R)))
4835 #define _mm256_maskz_cvt_roundepi64_ps(U, A, R) \
4836 ((__m128) __builtin_ia32_cvtqq2ps256_mask_round ((__v4di) (A), \
4837 (__v4sf) \
4838 (_mm_setzero_ps ()), \
4839 (__mmask8) (U), \
4840 (R)))
4842 #define _mm256_cvtt_roundpd_epi32(A, R) \
4843 ((__m128i) __builtin_ia32_cvttpd2dq256_mask_round ((__v4df) (A), \
4844 (__v4si) \
4845 (_mm_undefined_si128 ()), \
4846 (__mmask8) (-1), \
4847 (R)))
4849 #define _mm256_mask_cvtt_roundpd_epi32(W, U, A, R) \
4850 ((__m128i) __builtin_ia32_cvttpd2dq256_mask_round ((__v4df) (A), \
4851 (__v4si) (W), \
4852 (__mmask8) (U), \
4853 (R)))
4855 #define _mm256_maskz_cvtt_roundpd_epi32(U, A, R) \
4856 ((__m128i) __builtin_ia32_cvttpd2dq256_mask_round ((__v4df) (A), \
4857 (__v4si) \
4858 (_mm_setzero_si128 ()), \
4859 (__mmask8) (U), \
4860 (R)))
4862 #define _mm256_cvtt_roundpd_epi64(A, R) \
4863 ((__m256i) \
4864 __builtin_ia32_cvttpd2qq256_mask_round ((__v4df) (A), \
4865 (__v4di) \
4866 (_mm256_setzero_si256 ()), \
4867 (__mmask8) (-1), \
4868 (R)))
4870 #define _mm256_mask_cvtt_roundpd_epi64(W, U, A, R) \
4871 ((__m256i) __builtin_ia32_cvttpd2qq256_mask_round ((__v4df) (A), \
4872 (__v4di) (W), \
4873 (__mmask8) (U), \
4874 (R)))
4876 #define _mm256_maskz_cvtt_roundpd_epi64(U, A, R) \
4877 ((__m256i) \
4878 __builtin_ia32_cvttpd2qq256_mask_round ((__v4df) (A), \
4879 (__v4di) \
4880 (_mm256_setzero_si256 ()), \
4881 (__mmask8) (U), \
4882 (R)))
4884 #define _mm256_cvtt_roundpd_epu32(A, R) \
4885 ((__m128i) \
4886 __builtin_ia32_cvttpd2udq256_mask_round ((__v4df) (A), \
4887 (__v4si) \
4888 (_mm_undefined_si128 ()), \
4889 (__mmask8) (-1), \
4890 (R)))
4892 #define _mm256_mask_cvtt_roundpd_epu32(W, U, A, R) \
4893 ((__m128i) __builtin_ia32_cvttpd2udq256_mask_round ((__v4df) (A), \
4894 (__v4si) (W), \
4895 (__mmask8) (U), \
4896 (R)))
4898 #define _mm256_maskz_cvtt_roundpd_epu32(U, A, R) \
4899 ((__m128i) __builtin_ia32_cvttpd2udq256_mask_round ((__v4df) (A), \
4900 (__v4si) \
4901 (_mm_setzero_si128 ()), \
4902 (__mmask8) (U), \
4903 (R)))
4905 #define _mm256_cvtt_roundpd_epu64(A, R) \
4906 ((__m256i) \
4907 __builtin_ia32_cvttpd2uqq256_mask_round ((__v4df) (A), \
4908 (__v4di) \
4909 (_mm256_setzero_si256 ()), \
4910 (__mmask8) (-1), \
4911 (R)))
4913 #define _mm256_mask_cvtt_roundpd_epu64(W, U, A, R) \
4914 ((__m256i) __builtin_ia32_cvttpd2uqq256_mask_round ((__v4df) (A), \
4915 (__v4di) (W), \
4916 (__mmask8) (U), \
4917 (R)))
4919 #define _mm256_maskz_cvtt_roundpd_epu64(U, A, R) \
4920 ((__m256i) \
4921 __builtin_ia32_cvttpd2uqq256_mask_round ((__v4df) (A), \
4922 (__v4di) \
4923 (_mm256_setzero_si256 ()), \
4924 (__mmask8) (U), \
4925 (R)))
4927 #define _mm256_cvtt_roundph_epi32(A, R) \
4928 ((__m256i) \
4929 __builtin_ia32_vcvttph2dq256_mask_round ((__v8hf) (A), \
4930 (__v8si) \
4931 (_mm256_setzero_si256 ()), \
4932 (__mmask8) (-1), \
4933 (R)))
4935 #define _mm256_mask_cvtt_roundph_epi32(W, U, A, R) \
4936 ((__m256i) __builtin_ia32_vcvttph2dq256_mask_round ((__v8hf) (A), \
4937 (__v8si) (W), \
4938 (__mmask8) (U), \
4939 (R)))
4941 #define _mm256_maskz_cvtt_roundph_epi32(U, A, R) \
4942 ((__m256i) \
4943 __builtin_ia32_vcvttph2dq256_mask_round ((__v8hf) (A), \
4944 (__v8si) \
4945 (_mm256_setzero_si256 ()), \
4946 (__mmask8) (U), \
4947 (R)))
4949 #define _mm256_cvtt_roundph_epi64(A, R) \
4950 ((__m256i) \
4951 __builtin_ia32_vcvttph2qq256_mask_round ((__v8hf) (A), \
4952 (__v4di) \
4953 (_mm256_setzero_si256 ()), \
4954 (__mmask8) (-1), \
4955 (R)))
4957 #define _mm256_mask_cvtt_roundph_epi64(W, U, A, R) \
4958 ((__m256i) __builtin_ia32_vcvttph2qq256_mask_round ((__v8hf) (A), \
4959 (__v4di) (W), \
4960 (__mmask8) (U), \
4961 (R)))
4963 #define _mm256_maskz_cvtt_roundph_epi64(U, A, R) \
4964 ((__m256i) \
4965 __builtin_ia32_vcvttph2qq256_mask_round ((__v8hf) (A), \
4966 (__v4di) \
4967 (_mm256_setzero_si256 ()), \
4968 (__mmask8) (U), \
4969 (R)))
4971 #define _mm256_cvtt_roundph_epu32(A, R) \
4972 ((__m256i) \
4973 __builtin_ia32_vcvttph2udq256_mask_round ((__v8hf) (A), \
4974 (__v8si) \
4975 (_mm256_setzero_si256 ()), \
4976 (__mmask8) (-1), \
4977 (R)))
4979 #define _mm256_mask_cvtt_roundph_epu32(W, U, A, R) \
4980 ((__m256i) __builtin_ia32_vcvttph2udq256_mask_round ((__v8hf) (A), \
4981 (__v8si) (W), \
4982 (__mmask8) (U), \
4983 (R)))
4985 #define _mm256_maskz_cvtt_roundph_epu32(U, A, R) \
4986 ((__m256i) \
4987 __builtin_ia32_vcvttph2udq256_mask_round ((__v8hf) (A), \
4988 (__v8si) \
4989 (_mm256_setzero_si256 ()), \
4990 (__mmask8) (U), \
4991 (R)))
4993 #define _mm256_cvtt_roundph_epu64(A, R) \
4994 ((__m256i) \
4995 __builtin_ia32_vcvttph2uqq256_mask_round ((__v8hf) (A), \
4996 (__v4di) \
4997 (_mm256_setzero_si256 ()), \
4998 (__mmask8) (-1), \
4999 (R)))
5001 #define _mm256_mask_cvtt_roundph_epu64(W, U, A, R) \
5002 ((__m256i) __builtin_ia32_vcvttph2uqq256_mask_round ((__v8hf) (A), \
5003 (__v4di) (W), \
5004 (__mmask8) (U), \
5005 (R)))
5007 #define _mm256_maskz_cvtt_roundph_epu64(U, A, R) \
5008 ((__m256i) \
5009 __builtin_ia32_vcvttph2uqq256_mask_round ((__v8hf) (A), \
5010 (__v4di) \
5011 (_mm256_setzero_si256 ()), \
5012 (__mmask8) (U), \
5013 (R)))
5015 #define _mm256_cvtt_roundph_epu16(A, R) \
5016 ((__m256i) \
5017 __builtin_ia32_vcvttph2uw256_mask_round ((__v16hf) (A), \
5018 (__v16hi) \
5019 (_mm256_setzero_si256 ()), \
5020 (__mmask16) (-1), \
5021 (R)))
5023 #define _mm256_mask_cvtt_roundph_epu16(W, U, A, R) \
5024 ((__m256i) __builtin_ia32_vcvttph2uw256_mask_round ((__v16hf) (A), \
5025 (__v16hi) (W), \
5026 (__mmask16) (U), \
5027 (R)))
5029 #define _mm256_maskz_cvtt_roundph_epu16(U, A, R) \
5030 ((__m256i) \
5031 __builtin_ia32_vcvttph2uw256_mask_round ((__v16hf) (A), \
5032 (__v16hi) \
5033 (_mm256_setzero_si256 ()), \
5034 (__mmask16) (U), \
5035 (R)))
5037 #define _mm256_cvtt_roundph_epi16(A, R) \
5038 ((__m256i) \
5039 __builtin_ia32_vcvttph2uw256_mask_round ((__v16hf) (A), \
5040 (__v16hi) \
5041 (_mm256_setzero_si256 ()), \
5042 (__mmask16) (-1), \
5043 (R)))
5045 #define _mm256_mask_cvtt_roundph_epi16(W, U, A, R) \
5046 ((__m256i) __builtin_ia32_vcvttph2uw256_mask_round ((__v16hf) (A), \
5047 (__v16hi) (W), \
5048 (__mmask16) (U), \
5049 (R)))
5051 #define _mm256_maskz_cvtt_roundph_epi16(U, A, R)\
5052 ((__m256i) \
5053 __builtin_ia32_vcvttph2uw256_mask_round ((__v16hf) (A), \
5054 (__v16hi) \
5055 (_mm256_setzero_si256 ()), \
5056 (__mmask16) (U), \
5057 (R)))
5059 #define _mm256_cvtt_roundps_epi32(A, R) \
5060 ((__m256i) \
5061 __builtin_ia32_cvttps2dq256_mask_round ((__v8sf) (A), \
5062 (__v8si) \
5063 (_mm256_undefined_si256 ()), \
5064 (__mmask8) (-1), \
5065 (R)))
5067 #define _mm256_mask_cvtt_roundps_epi32(W, U, A, R) \
5068 ((__m256i) __builtin_ia32_cvttps2dq256_mask_round ((__v8sf) (A), \
5069 (__v8si) (W), \
5070 (__mmask8) (U), \
5071 (R)))
5073 #define _mm256_maskz_cvtt_roundps_epi32(U, A, R) \
5074 ((__m256i) \
5075 __builtin_ia32_cvttps2dq256_mask_round ((__v8sf) (A), \
5076 (__v8si) \
5077 (_mm256_setzero_si256 ()), \
5078 (__mmask8) (U), \
5079 (R)))
5081 #define _mm256_cvtt_roundps_epi64(A, R) \
5082 ((__m256i) __builtin_ia32_cvttps2qq256_mask_round ((__v4sf) (A), \
5083 (__v4di) \
5084 (_mm256_setzero_si256 ()),\
5085 (__mmask8) (-1), \
5086 (R)))
5088 #define _mm256_mask_cvtt_roundps_epi64(W, U, A, R) \
5089 ((__m256i) __builtin_ia32_cvttps2qq256_mask_round ((__v4sf) (A), \
5090 (__v4di) (W), \
5091 (__mmask8) (U), \
5092 (R)))
5094 #define _mm256_maskz_cvtt_roundps_epi64(U, A, R) \
5095 ((__m256i) __builtin_ia32_cvttps2qq256_mask_round ((__v4sf) (A), \
5096 (__v4di) \
5097 (_mm256_setzero_si256 ()),\
5098 (__mmask8) (U), \
5099 (R)))
5101 #define _mm256_cvtt_roundps_epu32(A, R) \
5102 ((__m256i) \
5103 __builtin_ia32_cvttps2udq256_mask_round ((__v8sf) (A), \
5104 (__v8si) \
5105 (_mm256_undefined_si256 ()), \
5106 (__mmask8) (-1), \
5107 (R)))
5109 #define _mm256_mask_cvtt_roundps_epu32(W, U, A, R) \
5110 ((__m256i) __builtin_ia32_cvttps2udq256_mask_round ((__v8sf) (A), \
5111 (__v8si) (W), \
5112 (__mmask8) (U), \
5113 (R)))
5115 #define _mm256_maskz_cvtt_roundps_epu32(U, A, R) \
5116 ((__m256i) \
5117 __builtin_ia32_cvttps2udq256_mask_round ((__v8sf) (A), \
5118 (__v8si) \
5119 (_mm256_setzero_si256 ()), \
5120 (__mmask8) (U), \
5121 (R)))
5123 #define _mm256_cvtt_roundps_epu64(A, R) \
5124 ((__m256i) \
5125 __builtin_ia32_cvttps2uqq256_mask_round ((__v4sf) (A), \
5126 (__v4di) \
5127 (_mm256_setzero_si256 ()), \
5128 (__mmask8) (-1), \
5129 (R)))
5131 #define _mm256_mask_cvtt_roundps_epu64(W, U, A, R) \
5132 ((__m256i) __builtin_ia32_cvttps2uqq256_mask_round ((__v4sf) (A), \
5133 (__v4di) (W), \
5134 (__mmask8) (U), \
5135 (R)))
5137 #define _mm256_maskz_cvtt_roundps_epu64(U, A, R) \
5138 ((__m256i) \
5139 __builtin_ia32_cvttps2uqq256_mask_round ((__v4sf) (A), \
5140 (__v4di) \
5141 (_mm256_setzero_si256 ()), \
5142 (__mmask8) (U), \
5143 (R)))
5145 #define _mm256_cvt_roundepu32_ph(A, R) \
5146 ((__m128h) __builtin_ia32_vcvtudq2ph256_mask_round ((__v8si) (A), \
5147 (__v8hf) \
5148 (_mm_setzero_ph ()), \
5149 (__mmask8) (-1), \
5150 (R)))
5152 #define _mm256_mask_cvt_roundepu32_ph(W, U, A, R) \
5153 ((__m128h) __builtin_ia32_vcvtudq2ph256_mask_round ((__v8si) (A), \
5154 (__v8hf) (W), \
5155 (__mmask8) (U), \
5156 (R)))
5158 #define _mm256_maskz_cvt_roundepu32_ph(U, A, R) \
5159 ((__m128h) __builtin_ia32_vcvtudq2ph256_mask_round ((__v8si) (A), \
5160 (__v8hf) \
5161 (_mm_setzero_ph ()), \
5162 (__mmask8) (U), \
5163 (R)))
5165 #define _mm256_cvt_roundepu32_ps(A, R) \
5166 ((__m256) __builtin_ia32_cvtudq2ps256_mask_round ((__v8si) (A), \
5167 (__v8sf) \
5168 (_mm256_undefined_ps ()), \
5169 (__mmask8) (-1), \
5170 (R)))
5172 #define _mm256_mask_cvt_roundepu32_ps(W, U, A, R) \
5173 ((__m256) __builtin_ia32_cvtudq2ps256_mask_round ((__v8si) (A), \
5174 (__v8sf) (W), \
5175 (__mmask8) (U), \
5176 (R)))
5178 #define _mm256_maskz_cvt_roundepu32_ps(U, A, R) \
5179 ((__m256) __builtin_ia32_cvtudq2ps256_mask_round ((__v8si) (A), \
5180 (__v8sf) \
5181 (_mm256_setzero_ps ()), \
5182 (__mmask8) (U), \
5183 (R)))
5185 #define _mm256_cvt_roundepu64_pd(A, R) \
5186 ((__m256d) __builtin_ia32_cvtuqq2pd256_mask_round ((__v4di) (A), \
5187 (__v4df) \
5188 (_mm256_setzero_pd ()), \
5189 (__mmask8) (-1), \
5190 (R)))
5192 #define _mm256_mask_cvt_roundepu64_pd(W, U, A, R) \
5193 ((__m256d) __builtin_ia32_cvtuqq2pd256_mask_round ((__v4di) (A), \
5194 (__v4df) (W), \
5195 (__mmask8) (U), \
5196 (R)))
5198 #define _mm256_maskz_cvt_roundepu64_pd(U, A, R) \
5199 ((__m256d) __builtin_ia32_cvtuqq2pd256_mask_round ((__v4di) (A), \
5200 (__v4df) \
5201 (_mm256_setzero_pd ()), \
5202 (__mmask8) (U), \
5203 (R)))
5205 #define _mm256_cvt_roundepu64_ph(A, R) \
5206 ((__m128h) __builtin_ia32_vcvtuqq2ph256_mask_round ((__v4di) (A), \
5207 (__v8hf) \
5208 (_mm_setzero_ph ()), \
5209 (__mmask8) (-1), \
5210 (R)))
5212 #define _mm256_mask_cvt_roundepu64_ph(W, U, A, R) \
5213 ((__m128h) __builtin_ia32_vcvtuqq2ph256_mask_round ((__v4di) (A), \
5214 (__v8hf) (W), \
5215 (__mmask8) (U), \
5216 (R)))
5218 #define _mm256_maskz_cvt_roundepu64_ph(U, A, R) \
5219 ((__m128h) __builtin_ia32_vcvtuqq2ph256_mask_round ((__v4di) (A), \
5220 (__v8hf) \
5221 (_mm_setzero_ph ()), \
5222 (__mmask8) (U), \
5223 (R)))
5225 #define _mm256_cvt_roundepu64_ps(A, R) \
5226 ((__m128) __builtin_ia32_cvtuqq2ps256_mask_round ((__v4di) (A), \
5227 (__v4sf) \
5228 (_mm_setzero_ps ()), \
5229 (__mmask8) (-1), \
5230 (R)))
5232 #define _mm256_mask_cvt_roundepu64_ps(W, U, A, R) \
5233 ((__m128) __builtin_ia32_cvtuqq2ps256_mask_round ((__v4di) (A), \
5234 (__v4sf) (W), \
5235 (__mmask8) (U), \
5236 (R)))
5238 #define _mm256_maskz_cvt_roundepu64_ps(U, A, R) \
5239 ((__m128) __builtin_ia32_cvtuqq2ps256_mask_round ((__v4di) (A), \
5240 (__v4sf) \
5241 (_mm_setzero_ps ()), \
5242 (__mmask8) (U), \
5243 (R)))
5245 #define _mm256_cvt_roundepu16_ph(A, R) \
5246 ((__m256h) __builtin_ia32_vcvtuw2ph256_mask_round ((__v16hi) (A), \
5247 (__v16hf) \
5248 (_mm256_setzero_ph ()), \
5249 (__mmask16) (-1), \
5250 (R)))
5252 #define _mm256_mask_cvt_roundepu16_ph(W, U, A, R) \
5253 ((__m256h) __builtin_ia32_vcvtuw2ph256_mask_round ((__v16hi) (A), \
5254 (__v16hf) (W), \
5255 (__mmask16) (U), \
5256 (R)))
5258 #define _mm256_maskz_cvt_roundepu16_ph(U, A, R) \
5259 ((__m256h) __builtin_ia32_vcvtuw2ph256_mask_round ((__v16hi) (A), \
5260 (__v16hf) \
5261 (_mm256_setzero_ph ()), \
5262 (__mmask16) (U), \
5263 (R)))
5265 #define _mm256_cvt_roundepi16_ph(A, R) \
5266 ((__m256h) __builtin_ia32_vcvtw2ph256_mask_round ((__v16hi) (A), \
5267 (__v16hf) \
5268 (_mm256_setzero_ph ()), \
5269 (__mmask16) (-1), \
5270 (R)))
5272 #define _mm256_mask_cvt_roundepi16_ph(W, U, A, R) \
5273 ((__m256h) __builtin_ia32_vcvtw2ph256_mask_round ((__v16hi) (A), \
5274 (__v16hf) (W), \
5275 (__mmask16) (U), \
5276 (R)))
5278 #define _mm256_maskz_cvt_roundepi16_ph(U, A, R) \
5279 ((__m256h) __builtin_ia32_vcvtw2ph256_mask_round ((__v16hi) (A), \
5280 (__v16hf) \
5281 (_mm256_setzero_ph ()), \
5282 (__mmask16) (U), \
5283 (R)))
5285 #define _mm256_div_round_pd(A, B, R) \
5286 ((__m256d) __builtin_ia32_divpd256_mask_round ((__v4df) (A), \
5287 (__v4df) (B), \
5288 (__v4df) \
5289 (_mm256_undefined_pd ()), \
5290 (__mmask8) (-1), \
5291 (R)))
5293 #define _mm256_mask_div_round_pd(W, U, A, B, R) \
5294 ((__m256d) __builtin_ia32_divpd256_mask_round ((__v4df) (A), \
5295 (__v4df) (B), \
5296 (__v4df) (W), \
5297 (__mmask8) (U), \
5298 (R)))
5300 #define _mm256_maskz_div_round_pd(U, A, B, R) \
5301 ((__m256d) __builtin_ia32_divpd256_mask_round ((__v4df) (A), \
5302 (__v4df) (B), \
5303 (__v4df) \
5304 (_mm256_setzero_pd ()), \
5305 (__mmask8) (U), \
5306 (R)))
5308 #define _mm256_div_round_ph(A, B, R) \
5309 ((__m256h) __builtin_ia32_divph256_mask_round ((__v16hf) (A), \
5310 (__v16hf) (B), \
5311 (__v16hf) \
5312 (_mm256_setzero_ph ()), \
5313 (__mmask16) (-1), \
5314 (R)))
5316 #define _mm256_mask_div_round_ph(W, U, A, B, R) \
5317 ((__m256h) __builtin_ia32_divph256_mask_round ((__v16hf) (A), \
5318 (__v16hf) (B), \
5319 (__v16hf) (W), \
5320 (__mmask16) (U), \
5321 (R)))
5323 #define _mm256_maskz_div_round_ph(U, A, B, R) \
5324 ((__m256h) __builtin_ia32_divph256_mask_round ((__v16hf) (A), \
5325 (__v16hf) (B), \
5326 (__v16hf) \
5327 (_mm256_setzero_ph ()), \
5328 (__mmask16) (U), \
5329 (R)))
5331 #define _mm256_div_round_ps(A, B, R) \
5332 ((__m256) __builtin_ia32_divps256_mask_round ((__v8sf) (A), \
5333 (__v8sf) (B), \
5334 (__v8sf) \
5335 (_mm256_undefined_ps ()), \
5336 (__mmask8) (-1), \
5337 (R)))
5339 #define _mm256_mask_div_round_ps(W, U, A, B, R) \
5340 ((__m256) __builtin_ia32_divps256_mask_round ((__v8sf) (A), \
5341 (__v8sf) (B), \
5342 (__v8sf) (W), \
5343 (__mmask8) (U), \
5344 (R)))
5346 #define _mm256_maskz_div_round_ps(U, A, B, R) \
5347 ((__m256) __builtin_ia32_divps256_mask_round ((__v8sf) (A), \
5348 (__v8sf) (B), \
5349 (__v8sf) \
5350 (_mm256_setzero_ps ()), \
5351 (__mmask8) (U), \
5352 (R)))
5354 #define _mm256_fcmadd_round_pch(A, B, D, R) \
5355 (__m256h) __builtin_ia32_vfcmaddcph256_round ((A), (B), (D), (R))
5357 #define _mm256_mask_fcmadd_round_pch(A, U, B, D, R) \
5358 ((__m256h) __builtin_ia32_vfcmaddcph256_mask_round ((__v16hf)(A), \
5359 (__v16hf)(B), \
5360 (__v16hf)(D), \
5361 (U), (R)))
5363 #define _mm256_mask3_fcmadd_round_pch(A, B, D, U, R) \
5364 ((__m256h) __builtin_ia32_vfcmaddcph256_mask3_round ((A), (B), (D), (U), (R)))
5366 #define _mm256_maskz_fcmadd_round_pch(U, A, B, D, R) \
5367 ((__m256h) __builtin_ia32_vfcmaddcph256_maskz_round ((A), (B), (D), (U), (R)))
5369 #define _mm256_fcmul_round_pch(A, B, R) \
5370 ((__m256h) __builtin_ia32_vfcmulcph256_round ((__v16hf) (A), \
5371 (__v16hf) (B), \
5372 (R)))
5374 #define _mm256_mask_fcmul_round_pch(W, U, A, B, R) \
5375 ((__m256h) __builtin_ia32_vfcmulcph256_mask_round ((__v16hf) (A), \
5376 (__v16hf) (B), \
5377 (__v16hf) (W), \
5378 (__mmask16) (U), \
5379 (R)))
5381 #define _mm256_maskz_fcmul_round_pch(U, A, B, R) \
5382 ((__m256h) __builtin_ia32_vfcmulcph256_mask_round ((__v16hf) (A), \
5383 (__v16hf) (B), \
5384 (__v16hf) \
5385 (_mm256_setzero_ph ()), \
5386 (__mmask16) (U), \
5387 (R)))
5389 #define _mm256_fixupimm_round_pd(A, B, D, C, R) \
5390 ((__m256d) __builtin_ia32_fixupimmpd256_mask_round ((__v4df) (A), \
5391 (__v4df) (B), \
5392 (__v4di) (D), \
5393 (C), \
5394 (__mmask8) (-1), \
5395 (R)))
5397 #define _mm256_mask_fixupimm_round_pd(A, U, B, D, C, R)\
5398 ((__m256d) __builtin_ia32_fixupimmpd256_mask_round ((__v4df) (A), \
5399 (__v4df) (B), \
5400 (__v4di) (D), \
5401 (C), \
5402 (__mmask8) (U), \
5403 (R)))
5405 #define _mm256_maskz_fixupimm_round_pd(U, A, B, D, C, R)\
5406 ((__m256d) __builtin_ia32_fixupimmpd256_maskz_round ((__v4df) (A), \
5407 (__v4df) (B), \
5408 (__v4di) (D), \
5409 (C), \
5410 (__mmask8) (U), \
5411 (R)))
5413 #define _mm256_fixupimm_round_ps(A, B, D, C, R)\
5414 ((__m256) __builtin_ia32_fixupimmps256_mask_round ((__v8sf) (A), \
5415 (__v8sf) (B), \
5416 (__v8si) (D), \
5417 (C), \
5418 (__mmask8) (-1), \
5419 (R)))
5421 #define _mm256_mask_fixupimm_round_ps(A, U, B, D, C, R)\
5422 ((__m256) __builtin_ia32_fixupimmps256_mask_round ((__v8sf) (A), \
5423 (__v8sf) (B), \
5424 (__v8si) (D), \
5425 (C), \
5426 (__mmask8) (U), \
5427 (R)))
5429 #define _mm256_maskz_fixupimm_round_ps(U, A, B, D, C, R)\
5430 ((__m256) __builtin_ia32_fixupimmps256_maskz_round ((__v8sf) (A), \
5431 (__v8sf) (B), \
5432 (__v8si) (D), \
5433 (C), \
5434 (__mmask8) (U), \
5435 (R)))
5437 #define _mm256_fmadd_round_pd(A, B, D, R) \
5438 ((__m256d) __builtin_ia32_vfmaddpd256_mask_round (A, B, D, -1, R))
5440 #define _mm256_mask_fmadd_round_pd(A, U, B, D, R) \
5441 ((__m256d) __builtin_ia32_vfmaddpd256_mask_round (A, B, D, U, R))
5443 #define _mm256_mask3_fmadd_round_pd(A, B, D, U, R) \
5444 ((__m256d) __builtin_ia32_vfmaddpd256_mask3_round (A, B, D, U, R))
5446 #define _mm256_maskz_fmadd_round_pd(U, A, B, D, R) \
5447 ((__m256d) __builtin_ia32_vfmaddpd256_maskz_round (A, B, D, U, R))
5449 #define _mm256_fmadd_round_ph(A, B, D, R) \
5450 ((__m256h) __builtin_ia32_vfmaddph256_mask_round (A, B, D, -1, R))
5452 #define _mm256_mask_fmadd_round_ph(A, U, B, D, R) \
5453 ((__m256h) __builtin_ia32_vfmaddph256_mask_round (A, B, D, U, R))
5455 #define _mm256_mask3_fmadd_round_ph(A, B, D, U, R) \
5456 ((__m256h) __builtin_ia32_vfmaddph256_mask3_round (A, B, D, U, R))
5458 #define _mm256_maskz_fmadd_round_ph(U, A, B, D, R) \
5459 ((__m256h) __builtin_ia32_vfmaddph256_maskz_round (A, B, D, U, R))
5461 #define _mm256_fmadd_round_ps(A, B, D, R) \
5462 ((__m256)__builtin_ia32_vfmaddps256_mask_round (A, B, D, -1, R))
5464 #define _mm256_mask_fmadd_round_ps(A, U, B, D, R) \
5465 ((__m256)__builtin_ia32_vfmaddps256_mask_round (A, B, D, U, R))
5467 #define _mm256_mask3_fmadd_round_ps(A, B, D, U, R) \
5468 ((__m256)__builtin_ia32_vfmaddps256_mask3_round (A, B, D, U, R))
5470 #define _mm256_maskz_fmadd_round_ps(U, A, B, D, R) \
5471 ((__m256)__builtin_ia32_vfmaddps256_maskz_round (A, B, D, U, R))
5473 #define _mm256_fmadd_round_pch(A, B, D, R) \
5474 (__m256h) __builtin_ia32_vfmaddcph256_round ((A), (B), (D), (R))
5476 #define _mm256_mask_fmadd_round_pch(A, U, B, D, R) \
5477 ((__m256h) __builtin_ia32_vfmaddcph256_mask_round ((__v16hf) (A), \
5478 (__v16hf) (B), \
5479 (__v16hf) (D), \
5480 (U), (R)))
5482 #define _mm256_mask3_fmadd_round_pch(A, B, D, U, R) \
5483 (__m256h) __builtin_ia32_vfmaddcph256_mask3_round ((A), (B), (D), (U), (R))
5485 #define _mm256_maskz_fmadd_round_pch(U, A, B, D, R) \
5486 (__m256h) __builtin_ia32_vfmaddcph256_maskz_round ((A), (B), (D), (U), (R))
5488 #define _mm256_fmaddsub_round_pd(A, B, D, R) \
5489 (__m256d) __builtin_ia32_vfmaddsubpd256_mask_round (A, B, D, -1, R)
5491 #define _mm256_mask_fmaddsub_round_pd(A, U, B, D, R) \
5492 (__m256d) __builtin_ia32_vfmaddsubpd256_mask_round (A, B, D, U, R)
5494 #define _mm256_mask3_fmaddsub_round_pd(A, B, D, U, R) \
5495 (__m256d)__builtin_ia32_vfmaddsubpd256_mask3_round (A, B, D, U, R)
5497 #define _mm256_maskz_fmaddsub_round_pd(U, A, B, D, R) \
5498 (__m256d)__builtin_ia32_vfmaddsubpd256_maskz_round (A, B, D, U, R)
5500 #define _mm256_fmaddsub_round_ph(A, B, D, R) \
5501 ((__m256h)__builtin_ia32_vfmaddsubph256_mask_round ((A), (B), (D), -1, (R)))
5503 #define _mm256_mask_fmaddsub_round_ph(A, U, B, D, R) \
5504 ((__m256h)__builtin_ia32_vfmaddsubph256_mask_round ((A), (B), (D), (U), (R)))
5506 #define _mm256_mask3_fmaddsub_round_ph(A, B, D, U, R) \
5507 ((__m256h)__builtin_ia32_vfmaddsubph256_mask3_round ((A), (B), (D), (U), (R)))
5509 #define _mm256_maskz_fmaddsub_round_ph(U, A, B, D, R) \
5510 ((__m256h)__builtin_ia32_vfmaddsubph256_maskz_round ((A), (B), (D), (U), (R)))
5512 #define _mm256_fmaddsub_round_ps(A, B, D, R) \
5513 (__m256)__builtin_ia32_vfmaddsubps256_mask_round (A, B, D, -1, R)
5515 #define _mm256_mask_fmaddsub_round_ps(A, U, B, D, R) \
5516 (__m256)__builtin_ia32_vfmaddsubps256_mask_round (A, B, D, U, R)
5518 #define _mm256_mask3_fmaddsub_round_ps(A, B, D, U, R) \
5519 (__m256)__builtin_ia32_vfmaddsubps256_mask3_round (A, B, D, U, R)
5521 #define _mm256_maskz_fmaddsub_round_ps(U, A, B, D, R) \
5522 (__m256)__builtin_ia32_vfmaddsubps256_maskz_round (A, B, D, U, R)
5524 #define _mm256_fmsub_round_pd(A, B, D, R) \
5525 (__m256d)__builtin_ia32_vfmsubpd256_mask_round (A, B, D, -1, R)
5527 #define _mm256_mask_fmsub_round_pd(A, U, B, D, R) \
5528 (__m256d)__builtin_ia32_vfmsubpd256_mask_round (A, B, D, U, R)
5530 #define _mm256_mask3_fmsub_round_pd(A, B, D, U, R) \
5531 (__m256d)__builtin_ia32_vfmsubpd256_mask3_round (A, B, D, U, R)
5533 #define _mm256_maskz_fmsub_round_pd(U, A, B, D, R) \
5534 (__m256d)__builtin_ia32_vfmsubpd256_maskz_round (A, B, D, U, R)
5536 #define _mm256_fmsub_round_ph(A, B, D, R) \
5537 ((__m256h)__builtin_ia32_vfmsubph256_mask_round ((A), (B), (D), -1, (R)))
5539 #define _mm256_mask_fmsub_round_ph(A, U, B, D, R) \
5540 ((__m256h)__builtin_ia32_vfmsubph256_mask_round ((A), (B), (D), (U), (R)))
5542 #define _mm256_mask3_fmsub_round_ph(A, B, D, U, R) \
5543 ((__m256h)__builtin_ia32_vfmsubph256_mask3_round ((A), (B), (D), (U), (R)))
5545 #define _mm256_maskz_fmsub_round_ph(U, A, B, D, R) \
5546 ((__m256h)__builtin_ia32_vfmsubph256_maskz_round ((A), (B), (D), (U), (R)))
5548 #define _mm256_fmsub_round_ps(A, B, D, R) \
5549 (__m256)__builtin_ia32_vfmsubps256_mask_round (A, B, D, -1, R)
5551 #define _mm256_mask_fmsub_round_ps(A, U, B, D, R) \
5552 (__m256)__builtin_ia32_vfmsubps256_mask_round (A, B, D, U, R)
5554 #define _mm256_mask3_fmsub_round_ps(A, B, D, U, R) \
5555 (__m256)__builtin_ia32_vfmsubps256_mask3_round (A, B, D, U, R)
5557 #define _mm256_maskz_fmsub_round_ps(U, A, B, D, R) \
5558 (__m256)__builtin_ia32_vfmsubps256_maskz_round (A, B, D, U, R)
5560 #define _mm256_fmsubadd_round_pd(A, B, D, R) \
5561 (__m256d)__builtin_ia32_vfmsubaddpd256_mask_round (A, B, D, -1, R)
5563 #define _mm256_mask_fmsubadd_round_pd(A, U, B, D, R) \
5564 (__m256d)__builtin_ia32_vfmsubaddpd256_mask_round (A, B, D, U, R)
5566 #define _mm256_mask3_fmsubadd_round_pd(A, B, D, U, R) \
5567 (__m256d)__builtin_ia32_vfmsubaddpd256_mask3_round (A, B, D, U, R)
5569 #define _mm256_maskz_fmsubadd_round_pd(U, A, B, D, R) \
5570 (__m256d)__builtin_ia32_vfmsubaddpd256_maskz_round (A, B, D, U, R)
5572 #define _mm256_fmsubadd_round_ph(A, B, D, R) \
5573 ((__m256h)__builtin_ia32_vfmsubaddph256_mask_round ((A), (B), (D), -1, (R)))
5575 #define _mm256_mask_fmsubadd_round_ph(A, U, B, D, R) \
5576 ((__m256h)__builtin_ia32_vfmsubaddph256_mask_round ((A), (B), (D), (U), (R)))
5578 #define _mm256_mask3_fmsubadd_round_ph(A, B, D, U, R) \
5579 ((__m256h)__builtin_ia32_vfmsubaddph256_mask3_round ((A), (B), (D), (U), (R)))
5581 #define _mm256_maskz_fmsubadd_round_ph(U, A, B, D, R) \
5582 ((__m256h)__builtin_ia32_vfmsubaddph256_maskz_round ((A), (B), (D), (U), (R)))
5584 #define _mm256_fmsubadd_round_ps(A, B, D, R) \
5585 (__m256)__builtin_ia32_vfmsubaddps256_mask_round (A, B, D, -1, R)
5587 #define _mm256_mask_fmsubadd_round_ps(A, U, B, D, R) \
5588 (__m256)__builtin_ia32_vfmsubaddps256_mask_round (A, B, D, U, R)
5590 #define _mm256_mask3_fmsubadd_round_ps(A, B, D, U, R) \
5591 (__m256)__builtin_ia32_vfmsubaddps256_mask3_round (A, B, D, U, R)
5593 #define _mm256_maskz_fmsubadd_round_ps(U, A, B, D, R) \
5594 (__m256)__builtin_ia32_vfmsubaddps256_maskz_round (A, B, D, U, R)
5596 #define _mm256_fmul_round_pch(B, D, R) \
5597 ((__m256h) __builtin_ia32_vfmulcph256_round ((__v16hf) (B), \
5598 (__v16hf) (D), \
5599 (R)))
5601 #define _mm256_mask_fmul_round_pch(A, U, B, D, R) \
5602 ((__m256h) __builtin_ia32_vfmulcph256_mask_round ((__v16hf) (B), \
5603 (__v16hf) (D), \
5604 (__v16hf) (A), \
5605 (__mmask16) (U), \
5606 (R)))
5608 #define _mm256_maskz_fmul_round_pch(U, B, D, R) \
5609 ((__m256h) __builtin_ia32_vfmulcph256_mask_round ((__v16hf) (B), \
5610 (__v16hf) (D), \
5611 (__v16hf) \
5612 (_mm256_setzero_ph ()), \
5613 (__mmask16) (U), \
5614 (R)))
5616 #define _mm256_fnmadd_round_pd(A, B, D, R) \
5617 (__m256d)__builtin_ia32_vfnmaddpd256_mask_round (A, B, D, -1, R)
5619 #define _mm256_mask_fnmadd_round_pd(A, U, B, D, R) \
5620 (__m256d)__builtin_ia32_vfnmaddpd256_mask_round (A, B, D, U, R)
5622 #define _mm256_mask3_fnmadd_round_pd(A, B, D, U, R) \
5623 (__m256d)__builtin_ia32_vfnmaddpd256_mask3_round (A, B, D, U, R)
5625 #define _mm256_maskz_fnmadd_round_pd(U, A, B, D, R) \
5626 (__m256d)__builtin_ia32_vfnmaddpd256_maskz_round (A, B, D, U, R)
5628 #define _mm256_fnmadd_round_ph(A, B, D, R) \
5629 ((__m256h)__builtin_ia32_vfnmaddph256_mask_round ((A), (B), (D), -1, (R)))
5631 #define _mm256_mask_fnmadd_round_ph(A, U, B, D, R) \
5632 ((__m256h)__builtin_ia32_vfnmaddph256_mask_round ((A), (B), (D), (U), (R)))
5634 #define _mm256_mask3_fnmadd_round_ph(A, B, D, U, R) \
5635 ((__m256h)__builtin_ia32_vfnmaddph256_mask3_round ((A), (B), (D), (U), (R)))
5637 #define _mm256_maskz_fnmadd_round_ph(U, A, B, D, R) \
5638 ((__m256h)__builtin_ia32_vfnmaddph256_maskz_round ((A), (B), (D), (U), (R)))
5640 #define _mm256_fnmadd_round_ps(A, B, D, R) \
5641 (__m256)__builtin_ia32_vfnmaddps256_mask_round (A, B, D, -1, R)
5643 #define _mm256_mask_fnmadd_round_ps(A, U, B, D, R) \
5644 (__m256)__builtin_ia32_vfnmaddps256_mask_round (A, B, D, U, R)
5646 #define _mm256_mask3_fnmadd_round_ps(A, B, D, U, R) \
5647 (__m256)__builtin_ia32_vfnmaddps256_mask3_round (A, B, D, U, R)
5649 #define _mm256_maskz_fnmadd_round_ps(U, A, B, D, R) \
5650 (__m256)__builtin_ia32_vfnmaddps256_maskz_round (A, B, D, U, R)
5652 #define _mm256_fnmsub_round_pd(A, B, D, R) \
5653 (__m256d)__builtin_ia32_vfnmsubpd256_mask_round (A, B, D, -1, R)
5655 #define _mm256_mask_fnmsub_round_pd(A, U, B, D, R) \
5656 (__m256d)__builtin_ia32_vfnmsubpd256_mask_round (A, B, D, U, R)
5658 #define _mm256_mask3_fnmsub_round_pd(A, B, D, U, R) \
5659 (__m256d)__builtin_ia32_vfnmsubpd256_mask3_round (A, B, D, U, R)
5661 #define _mm256_maskz_fnmsub_round_pd(U, A, B, D, R) \
5662 (__m256d)__builtin_ia32_vfnmsubpd256_maskz_round (A, B, D, U, R)
5664 #define _mm256_fnmsub_round_ph(A, B, D, R) \
5665 ((__m256h)__builtin_ia32_vfnmsubph256_mask_round ((A), (B), (D), -1, (R)))
5667 #define _mm256_mask_fnmsub_round_ph(A, U, B, D, R) \
5668 ((__m256h)__builtin_ia32_vfnmsubph256_mask_round ((A), (B), (D), (U), (R)))
5670 #define _mm256_mask3_fnmsub_round_ph(A, B, D, U, R) \
5671 ((__m256h)__builtin_ia32_vfnmsubph256_mask3_round ((A), (B), (D), (U), (R)))
5673 #define _mm256_maskz_fnmsub_round_ph(U, A, B, D, R) \
5674 ((__m256h)__builtin_ia32_vfnmsubph256_maskz_round ((A), (B), (D), (U), (R)))
5676 #define _mm256_fnmsub_round_ps(A, B, D, R) \
5677 (__m256)__builtin_ia32_vfnmsubps256_mask_round (A, B, D, -1, R)
5679 #define _mm256_mask_fnmsub_round_ps(A, U, B, D, R) \
5680 (__m256)__builtin_ia32_vfnmsubps256_mask_round (A, B, D, U, R)
5682 #define _mm256_mask3_fnmsub_round_ps(A, B, D, U, R) \
5683 (__m256)__builtin_ia32_vfnmsubps256_mask3_round (A, B, D, U, R)
5685 #define _mm256_maskz_fnmsub_round_ps(U, A, B, D, R) \
5686 (__m256)__builtin_ia32_vfnmsubps256_maskz_round (A, B, D, U, R)
5688 #define _mm256_getexp_round_pd(A, R) \
5689 ((__m256d) __builtin_ia32_getexppd256_mask_round ((__v4df) (A), \
5690 (__v4df) \
5691 (_mm256_undefined_pd ()), \
5692 (__mmask8) (-1), \
5693 (R)))
5695 #define _mm256_mask_getexp_round_pd(W, U, A, R) \
5696 ((__m256d) __builtin_ia32_getexppd256_mask_round ((__v4df) (A), \
5697 (__v4df) (W), \
5698 (__mmask8) (U), \
5699 (R)))
5701 #define _mm256_maskz_getexp_round_pd(U, A, R) \
5702 ((__m256d) __builtin_ia32_getexppd256_mask_round ((__v4df) (A), \
5703 (__v4df) \
5704 (_mm256_setzero_pd ()), \
5705 (__mmask8) (U), \
5706 (R)))
5708 #define _mm256_getexp_round_ph(A, R)\
5709 ((__m256h) __builtin_ia32_getexpph256_mask_round ((__v16hf) (A), \
5710 (__v16hf) \
5711 (_mm256_setzero_ph ()), \
5712 (__mmask16) (-1), \
5713 (R)))
5715 #define _mm256_mask_getexp_round_ph(W, U, A, R)\
5716 ((__m256h) __builtin_ia32_getexpph256_mask_round ((__v16hf) (A), \
5717 (__v16hf) (W), \
5718 (__mmask16) (U), \
5719 (R)))
5721 #define _mm256_maskz_getexp_round_ph(U, A, R)\
5722 ((__m256h) __builtin_ia32_getexpph256_mask_round ((__v16hf) (A), \
5723 (__v16hf) \
5724 (_mm256_setzero_ph ()), \
5725 (__mmask16) (U), \
5726 (R)))
5728 #define _mm256_getexp_round_ps(A, R)\
5729 ((__m256) __builtin_ia32_getexpps256_mask_round ((__v8sf) (A), \
5730 (__v8sf) \
5731 (_mm256_undefined_ps ()), \
5732 (__mmask8) (-1), \
5733 (R)))
5735 #define _mm256_mask_getexp_round_ps(W, U, A, R)\
5736 ((__m256) __builtin_ia32_getexpps256_mask_round ((__v8sf) (A), \
5737 (__v8sf) (W), \
5738 (__mmask8) (U), \
5739 (R)))
5741 #define _mm256_maskz_getexp_round_ps(U, A, R)\
5742 ((__m256) __builtin_ia32_getexpps256_mask_round ((__v8sf) (A), \
5743 (__v8sf) \
5744 (_mm256_setzero_ps ()), \
5745 (__mmask8) (U), \
5746 (R)))
5748 #define _mm256_getmant_round_pd(A, B, C, R) \
5749 ((__m256d)__builtin_ia32_getmantpd256_mask_round ((__v4df) (__m256d) (A), \
5750 (int) (((C) << 2) | (B)), \
5751 (__v4df) (__m256d) \
5752 _mm256_undefined_pd (), \
5753 (__mmask8)-1, \
5754 (R)))
5756 #define _mm256_mask_getmant_round_pd(W, U, A, B, C, R) \
5757 ((__m256d)__builtin_ia32_getmantpd256_mask_round ((__v4df) (__m256d) (A), \
5758 (int) (((C) << 2) | (B)), \
5759 (__v4df) (__m256d) (W), \
5760 (__mmask8) (U), \
5761 (R)))
5763 #define _mm256_maskz_getmant_round_pd(U, A, B, C, R) \
5764 ((__m256d)__builtin_ia32_getmantpd256_mask_round ((__v4df) (__m256d) (A), \
5765 (int) (((C) << 2) | (B)), \
5766 (__v4df) (__m256d) \
5767 _mm256_setzero_pd (), \
5768 (__mmask8) (U), \
5769 (R)))
5772 #define _mm256_getmant_round_ph(A, B, C, R) \
5773 ((__m256h)__builtin_ia32_getmantph256_mask_round ((__v16hf) (__m256h) (A), \
5774 (int) (((C)<<2) | (B)), \
5775 (__v16hf) (__m256h) \
5776 _mm256_undefined_ph (), \
5777 (__mmask16)-1, \
5778 (R)))
5780 #define _mm256_mask_getmant_round_ph(W, U, A, B, C, R) \
5781 ((__m256h)__builtin_ia32_getmantph256_mask_round ((__v16hf) (__m256h) (A), \
5782 (int) (((C)<<2) | (B)), \
5783 (__v16hf) (__m256h) (W), \
5784 (__mmask16) (U), \
5785 (R)))
5787 #define _mm256_maskz_getmant_round_ph(U, A, B, C, R) \
5788 ((__m256h)__builtin_ia32_getmantph256_mask_round ((__v16hf) (__m256h) (A), \
5789 (int) (((C)<<2) | (B)), \
5790 (__v16hf) (__m256h) \
5791 _mm256_setzero_ph (), \
5792 (__mmask16) (U), \
5793 (R)))
5795 #define _mm256_getmant_round_ps(A, B, C, R) \
5796 ((__m256)__builtin_ia32_getmantps256_mask_round ((__v8sf) (__m256) (A), \
5797 (int) (((C)<<2) | (B)), \
5798 (__v8sf) (__m256) \
5799 _mm256_undefined_ps (), \
5800 (__mmask8)-1, \
5801 (R)))
5803 #define _mm256_mask_getmant_round_ps(W, U, A, B, C, R) \
5804 ((__m256)__builtin_ia32_getmantps256_mask_round ((__v8sf) (__m256) (A), \
5805 (int) (((C)<<2) | (B)), \
5806 (__v8sf) (__m256) (W), \
5807 (__mmask8) (U), \
5808 (R)))
5810 #define _mm256_maskz_getmant_round_ps(U, A, B, C, R) \
5811 ((__m256)__builtin_ia32_getmantps256_mask_round ((__v8sf) (__m256) (A), \
5812 (int) (((C)<<2) | (B)), \
5813 (__v8sf) (__m256) \
5814 _mm256_setzero_ps (), \
5815 (__mmask8) (U), \
5816 (R)))
5818 #define _mm256_max_round_pd(A, B, R) \
5819 ((__m256d) __builtin_ia32_maxpd256_mask_round ((__v4df) (A), \
5820 (__v4df) (B), \
5821 (__v4df) \
5822 (_mm256_undefined_pd ()), \
5823 (__mmask8) (-1), \
5824 (R)))
5826 #define _mm256_mask_max_round_pd(W, U, A, B, R) \
5827 ((__m256d) __builtin_ia32_maxpd256_mask_round ((__v4df) (A), \
5828 (__v4df) (B), \
5829 (__v4df) (W), \
5830 (__mmask8) (U), \
5831 (R)))
5833 #define _mm256_maskz_max_round_pd(U, A, B, R) \
5834 ((__m256d) __builtin_ia32_maxpd256_mask_round ((__v4df) (A), \
5835 (__v4df) (B), \
5836 (__v4df) \
5837 (_mm256_setzero_pd ()), \
5838 (__mmask8) (U), \
5839 (R)))
5841 #define _mm256_max_round_ph(A, B, R) \
5842 ((__m256h) __builtin_ia32_maxph256_mask_round ((__v16hf) (A), \
5843 (__v16hf) (B), \
5844 (__v16hf) \
5845 (_mm256_undefined_ph ()), \
5846 (__mmask16) (-1), \
5847 (R)))
5849 #define _mm256_mask_max_round_ph(W, U, A, B, R) \
5850 ((__m256h) __builtin_ia32_maxph256_mask_round ((__v16hf) (A), \
5851 (__v16hf) (B), \
5852 (__v16hf) (W), \
5853 (__mmask16) (U), \
5854 (R)))
5856 #define _mm256_maskz_max_round_ph(U, A, B, R) \
5857 ((__m256h) __builtin_ia32_maxph256_mask_round ((__v16hf) (A), \
5858 (__v16hf) (B), \
5859 (__v16hf) \
5860 (_mm256_setzero_ph ()), \
5861 (__mmask16) (U), \
5862 (R)))
5864 #define _mm256_max_round_ps(A, B, R) \
5865 ((__m256) __builtin_ia32_maxps256_mask_round ((__v8sf) (A), \
5866 (__v8sf) (B), \
5867 (__v8sf) \
5868 (_mm256_undefined_ps ()), \
5869 (__mmask8) (-1), \
5870 (R)))
5872 #define _mm256_mask_max_round_ps(W, U, A, B, R) \
5873 ((__m256) __builtin_ia32_maxps256_mask_round ((__v8sf) (A), \
5874 (__v8sf) (B), \
5875 (__v8sf) (W), \
5876 (__mmask8) (U), \
5877 (R)))
5879 #define _mm256_maskz_max_round_ps(U, A, B, R) \
5880 ((__m256) __builtin_ia32_maxps256_mask_round ((__v8sf) (A), \
5881 (__v8sf) (B), \
5882 (__v8sf) \
5883 (_mm256_setzero_ps ()), \
5884 (__mmask8) (U), \
5885 (R)))
5887 #define _mm256_min_round_pd(A, B, R) \
5888 ((__m256d) __builtin_ia32_minpd256_mask_round ((__v4df) (A), \
5889 (__v4df) (B), \
5890 (__v4df) \
5891 (_mm256_undefined_pd ()), \
5892 (__mmask8) (-1), \
5893 (R)))
5895 #define _mm256_mask_min_round_pd(W, U, A, B, R) \
5896 ((__m256d) __builtin_ia32_minpd256_mask_round ((__v4df) (A), \
5897 (__v4df) (B), \
5898 (__v4df) (W), \
5899 (__mmask8) (U), \
5900 (R)))
5902 #define _mm256_maskz_min_round_pd(U, A, B, R) \
5903 ((__m256d) __builtin_ia32_minpd256_mask_round ((__v4df) (A), \
5904 (__v4df) (B), \
5905 (__v4df) \
5906 (_mm256_setzero_pd ()), \
5907 (__mmask8) (U), \
5908 (R)))
5910 #define _mm256_min_round_ph(A, B, R) \
5911 ((__m256h) __builtin_ia32_minph256_mask_round ((__v16hf) (A), \
5912 (__v16hf) (B), \
5913 (__v16hf) \
5914 (_mm256_undefined_ph ()), \
5915 (__mmask16) (-1), \
5916 (R)))
5918 #define _mm256_mask_min_round_ph(W, U, A, B, R) \
5919 ((__m256h) __builtin_ia32_minph256_mask_round ((__v16hf) (A), \
5920 (__v16hf) (B), \
5921 (__v16hf) (W), \
5922 (__mmask16) (U), \
5923 (R)))
5925 #define _mm256_maskz_min_round_ph(U, A, B, R) \
5926 ((__m256h) __builtin_ia32_minph256_mask_round ((__v16hf) (A), \
5927 (__v16hf) (B), \
5928 (__v16hf) \
5929 (_mm256_setzero_ph ()), \
5930 (__mmask16) (U), \
5931 (R)))
5933 #define _mm256_min_round_ps(A, B, R) \
5934 ((__m256) __builtin_ia32_minps256_mask_round ((__v8sf) (A), \
5935 (__v8sf) (B), \
5936 (__v8sf) \
5937 (_mm256_undefined_ps ()), \
5938 (__mmask8) (-1), \
5939 (R)))
5941 #define _mm256_mask_min_round_ps(W, U, A, B, R) \
5942 ((__m256) __builtin_ia32_minps256_mask_round ((__v8sf) (A), \
5943 (__v8sf) (B), \
5944 (__v8sf) (W), \
5945 (__mmask8) (U), \
5946 (R)))
5948 #define _mm256_maskz_min_round_ps(U, A, B, R) \
5949 ((__m256) __builtin_ia32_minps256_mask_round ((__v8sf) (A), \
5950 (__v8sf) (B), \
5951 (__v8sf) \
5952 (_mm256_setzero_ps ()), \
5953 (__mmask8) (U), \
5954 (R)))
5956 #define _mm256_mul_round_pd(A, B, R) \
5957 ((__m256d) __builtin_ia32_mulpd256_mask_round ((__v4df) (A), \
5958 (__v4df) (B), \
5959 (__v4df) \
5960 (_mm256_undefined_pd ()), \
5961 (__mmask8) (-1), \
5962 (R)))
5964 #define _mm256_mask_mul_round_pd(W, U, A, B, R) \
5965 ((__m256d) __builtin_ia32_mulpd256_mask_round ((__v4df) (A), \
5966 (__v4df) (B), \
5967 (__v4df) (W), \
5968 (__mmask8) (U), \
5969 (R)))
5971 #define _mm256_maskz_mul_round_pd(U, A, B, R) \
5972 ((__m256d) __builtin_ia32_mulpd256_mask_round ((__v4df) (A), \
5973 (__v4df) (B), \
5974 (__v4df) \
5975 (_mm256_setzero_pd ()), \
5976 (__mmask8) (U), \
5977 (R)))
5979 #define _mm256_mul_round_ph(A, B, R) \
5980 ((__m256h) __builtin_ia32_mulph256_mask_round ((__v16hf) (A), \
5981 (__v16hf) (B), \
5982 (__v16hf) \
5983 (_mm256_undefined_ph ()), \
5984 (__mmask16) (-1), \
5985 (R)))
5987 #define _mm256_mask_mul_round_ph(W, U, A, B, R) \
5988 ((__m256h) __builtin_ia32_mulph256_mask_round ((__v16hf) (A), \
5989 (__v16hf) (B), \
5990 (__v16hf) (W), \
5991 (__mmask16) (U), \
5992 (R)))
5994 #define _mm256_maskz_mul_round_ph(U, A, B, R) \
5995 ((__m256h) __builtin_ia32_mulph256_mask_round ((__v16hf) (A), \
5996 (__v16hf) (B), \
5997 (__v16hf) \
5998 (_mm256_setzero_ph ()), \
5999 (__mmask16) (U), \
6000 (R)))
6002 #define _mm256_mul_round_ps(A, B, R) \
6003 ((__m256) __builtin_ia32_mulps256_mask_round ((__v8sf) (A), \
6004 (__v8sf) (B), \
6005 (__v8sf) \
6006 (_mm256_undefined_ps ()), \
6007 (__mmask8) (-1), \
6008 (R)))
6010 #define _mm256_mask_mul_round_ps(W, U, A, B, R) \
6011 ((__m256) __builtin_ia32_mulps256_mask_round ((__v8sf) (A), \
6012 (__v8sf) (B), \
6013 (__v8sf) (W), \
6014 (__mmask8) (U), \
6015 (R)))
6017 #define _mm256_maskz_mul_round_ps(U, A, B, R) \
6018 ((__m256) __builtin_ia32_mulps256_mask_round ((__v8sf) (A), \
6019 (__v8sf) (B), \
6020 (__v8sf) \
6021 (_mm256_setzero_ps ()), \
6022 (__mmask8) (U), \
6023 (R)))
6025 #define _mm256_range_round_pd(A, B, C, R) \
6026 ((__m256d) __builtin_ia32_rangepd256_mask_round ((__v4df) (A), \
6027 (__v4df) (B), \
6028 (C), \
6029 (__v4df) \
6030 (_mm256_setzero_pd ()), \
6031 (__mmask8) (-1), \
6032 (R)))
6034 #define _mm256_mask_range_round_pd(W, U, A, B, C, R) \
6035 ((__m256d) __builtin_ia32_rangepd256_mask_round ((__v4df) (A), \
6036 (__v4df) (B), \
6037 (C), \
6038 (__v4df) (W), \
6039 (__mmask8) (U), \
6040 (R)))
6042 #define _mm256_maskz_range_round_pd(U, A, B, C, R) \
6043 ((__m256d) __builtin_ia32_rangepd256_mask_round ((__v4df) (A), \
6044 (__v4df) (B), \
6045 (C), \
6046 (__v4df) \
6047 (_mm256_setzero_pd ()), \
6048 (__mmask8) (U), \
6049 (R)))
6051 #define _mm256_range_round_ps(A, B, C, R) \
6052 ((__m256) __builtin_ia32_rangeps256_mask_round ((__v8sf) (A), \
6053 (__v8sf) (B), \
6054 (C), \
6055 (__v8sf) \
6056 (_mm256_setzero_ps ()), \
6057 (__mmask8) (-1), \
6058 (R)))
6060 #define _mm256_mask_range_round_ps(W, U, A, B, C, R) \
6061 ((__m256) __builtin_ia32_rangeps256_mask_round ((__v8sf) (A), \
6062 (__v8sf) (B), \
6063 (C), \
6064 (__v8sf) (W), \
6065 (__mmask8) (U), \
6066 (R)))
6068 #define _mm256_maskz_range_round_ps(U, A, B, C, R) \
6069 ((__m256) __builtin_ia32_rangeps256_mask_round ((__v8sf) (A), \
6070 (__v8sf) (B), \
6071 (C), \
6072 (__v8sf) \
6073 (_mm256_setzero_ps ()), \
6074 (__mmask8) (U), \
6075 (R)))
6077 #define _mm256_reduce_round_pd(A, C, R) \
6078 ((__m256d) __builtin_ia32_reducepd256_mask_round ((__v4df) (A), \
6079 (C), \
6080 (__v4df) \
6081 (_mm256_setzero_pd ()), \
6082 (__mmask8) (-1), \
6083 (R)))
6085 #define _mm256_mask_reduce_round_pd(W, U, A, C, R) \
6086 ((__m256d) __builtin_ia32_reducepd256_mask_round ((__v4df) (A), \
6087 (C), \
6088 (__v4df) (W), \
6089 (__mmask8) (U), \
6090 (R)))
6092 #define _mm256_maskz_reduce_round_pd(U, A, C, R) \
6093 ((__m256d) __builtin_ia32_reducepd256_mask_round ((__v4df) (A), \
6094 (C), \
6095 (__v4df) \
6096 (_mm256_setzero_pd ()), \
6097 (__mmask8) (U), \
6098 (R)))
6100 #define _mm256_reduce_round_ph(A, C, R) \
6101 ((__m256h) __builtin_ia32_reduceph256_mask_round ((__v16hf) (A), \
6102 (C), \
6103 (__v16hf) \
6104 (_mm256_setzero_ph ()), \
6105 (__mmask16) (-1), \
6106 (R)))
6108 #define _mm256_mask_reduce_round_ph(W, U, A, C, R) \
6109 ((__m256h) __builtin_ia32_reduceph256_mask_round ((__v16hf) (A), \
6110 (C), \
6111 (__v16hf) (W), \
6112 (__mmask16) (U), \
6113 (R)))
6115 #define _mm256_maskz_reduce_round_ph(U, A, C, R) \
6116 ((__m256h) __builtin_ia32_reduceph256_mask_round ((__v16hf) (A), \
6117 (C), \
6118 (__v16hf) \
6119 (_mm256_setzero_ph ()), \
6120 (__mmask16) (U), \
6121 (R)))
6123 #define _mm256_reduce_round_ps(A, C, R) \
6124 ((__m256) __builtin_ia32_reduceps256_mask_round ((__v8sf) (A), \
6125 (C), \
6126 (__v8sf) \
6127 (_mm256_setzero_ps ()), \
6128 (__mmask8) (-1), \
6129 (R)))
6131 #define _mm256_mask_reduce_round_ps(W, U, A, C, R) \
6132 ((__m256) __builtin_ia32_reduceps256_mask_round ((__v8sf) (A), \
6133 (C), \
6134 (__v8sf) (W), \
6135 (__mmask8) (U), \
6136 (R)))
6138 #define _mm256_maskz_reduce_round_ps(U, A, C, R) \
6139 ((__m256) __builtin_ia32_reduceps256_mask_round ((__v8sf) (A), \
6140 (C), \
6141 (__v8sf) \
6142 (_mm256_setzero_ps ()), \
6143 (__mmask8) (U), \
6144 (R)))
6146 #define _mm256_roundscale_round_pd(A, C, R) \
6147 ((__m256d) \
6148 __builtin_ia32_rndscalepd256_mask_round ((__v4df) (A), \
6149 (C), \
6150 (__v4df) \
6151 (_mm256_undefined_pd ()), \
6152 (__mmask8) (-1), \
6153 (R)))
6155 #define _mm256_mask_roundscale_round_pd(W, U, A, C, R) \
6156 ((__m256d) __builtin_ia32_rndscalepd256_mask_round ((__v4df) (A), \
6157 (C), \
6158 (__v4df) (W), \
6159 (__mmask8) (U), \
6160 (R)))
6162 #define _mm256_maskz_roundscale_round_pd(U, A, C, R) \
6163 ((__m256d) __builtin_ia32_rndscalepd256_mask_round ((__v4df) (A), \
6164 (C), \
6165 (__v4df) \
6166 (_mm256_setzero_pd ()), \
6167 (__mmask8) (U), \
6168 (R)))
6170 #define _mm256_roundscale_round_ph(A, C, R) \
6171 ((__m256h) \
6172 __builtin_ia32_rndscaleph256_mask_round ((__v16hf) (A), \
6173 (C), \
6174 (__v16hf) \
6175 (_mm256_undefined_ph ()), \
6176 (__mmask16) (-1), \
6177 (R)))
6179 #define _mm256_mask_roundscale_round_ph(W, U, A, C, R) \
6180 ((__m256h) __builtin_ia32_rndscaleph256_mask_round ((__v16hf) (A), \
6181 (C), \
6182 (__v16hf) (W), \
6183 (__mmask16) (U), \
6184 (R)))
6186 #define _mm256_maskz_roundscale_round_ph(U, A, C, R) \
6187 ((__m256h) __builtin_ia32_rndscaleph256_mask_round ((__v16hf) (A), \
6188 (C), \
6189 (__v16hf) \
6190 (_mm256_setzero_ph ()), \
6191 (__mmask16) (U), \
6192 (R)))
6194 #define _mm256_roundscale_round_ps(A, C, R) \
6195 ((__m256) __builtin_ia32_rndscaleps256_mask_round ((__v8sf) (A), \
6196 (C), \
6197 (__v8sf) \
6198 (_mm256_undefined_ps ()), \
6199 (__mmask8) (-1), \
6200 (R)))
6202 #define _mm256_mask_roundscale_round_ps(W, U, A, C, R) \
6203 ((__m256) __builtin_ia32_rndscaleps256_mask_round ((__v8sf) (A), \
6204 (C), \
6205 (__v8sf) (W), \
6206 (__mmask8) (U), \
6207 (R)))
6209 #define _mm256_maskz_roundscale_round_ps(U, A, C, R) \
6210 ((__m256) __builtin_ia32_rndscaleps256_mask_round ((__v8sf) (A), \
6211 (C), \
6212 (__v8sf) \
6213 (_mm256_setzero_ps ()), \
6214 (__mmask8) (U), \
6215 (R)))
6217 #define _mm256_scalef_round_pd(A, B, R) \
6218 ((__m256d) __builtin_ia32_scalefpd256_mask_round ((__v4df) (A), \
6219 (__v4df) (B), \
6220 (__v4df) \
6221 (_mm256_undefined_pd ()), \
6222 (__mmask8) (-1), \
6223 (R)))
6225 #define _mm256_mask_scalef_round_pd(W, U, A, B, R) \
6226 ((__m256d) __builtin_ia32_scalefpd256_mask_round ((__v4df) (A), \
6227 (__v4df) (B), \
6228 (__v4df) (W), \
6229 (__mmask8) (U), \
6230 (R)))
6232 #define _mm256_maskz_scalef_round_pd(U, A, B, R) \
6233 ((__m256d) __builtin_ia32_scalefpd256_mask_round ((__v4df) (A), \
6234 (__v4df) (B), \
6235 (__v4df) \
6236 (_mm256_setzero_pd ()), \
6237 (__mmask8) (U), \
6238 (R)))
6240 #define _mm256_scalef_round_ph(A, B, R) \
6241 ((__m256h) __builtin_ia32_scalefph256_mask_round ((__v16hf) (A), \
6242 (__v16hf) (B), \
6243 (__v16hf) \
6244 (_mm256_undefined_ph ()), \
6245 (__mmask16) (-1), \
6246 (R)))
6248 #define _mm256_mask_scalef_round_ph(W, U, A, B, R) \
6249 ((__m256h) __builtin_ia32_scalefph256_mask_round ((__v16hf) (A), \
6250 (__v16hf) (B), \
6251 (__v16hf) (W), \
6252 (__mmask16) (U), \
6253 (R)))
6255 #define _mm256_maskz_scalef_round_ph(U, A, B, R) \
6256 ((__m256h) __builtin_ia32_scalefph256_mask_round ((__v16hf) (A), \
6257 (__v16hf) (B), \
6258 (__v16hf) \
6259 (_mm256_setzero_ph ()), \
6260 (__mmask16) (U), \
6261 (R)))
6263 #define _mm256_scalef_round_ps(A, B, R) \
6264 ((__m256) __builtin_ia32_scalefps256_mask_round ((__v8sf) (A), \
6265 (__v8sf) (B), \
6266 (__v8sf) \
6267 (_mm256_undefined_ps ()), \
6268 (__mmask8) (-1), \
6269 (R)))
6271 #define _mm256_mask_scalef_round_ps(W, U, A, B, R) \
6272 ((__m256) __builtin_ia32_scalefps256_mask_round ((__v8sf) (A), \
6273 (__v8sf) (B), \
6274 (__v8sf) (W), \
6275 (__mmask8) (U), \
6276 (R)))
6278 #define _mm256_maskz_scalef_round_ps(U, A, B, R) \
6279 ((__m256) __builtin_ia32_scalefps256_mask_round ((__v8sf) (A), \
6280 (__v8sf) (B), \
6281 (__v8sf) \
6282 (_mm256_setzero_ps ()), \
6283 (__mmask8) (U), \
6284 (R)))
6286 #define _mm256_sqrt_round_pd(A, R) \
6287 ((__m256d) __builtin_ia32_sqrtpd256_mask_round ((__v4df) (A), \
6288 (__v4df) \
6289 (_mm256_undefined_pd ()), \
6290 (__mmask8) (-1), \
6291 (R)))
6293 #define _mm256_mask_sqrt_round_pd(W, U, A, R) \
6294 ((__m256d) __builtin_ia32_sqrtpd256_mask_round ((__v4df) (A), \
6295 (__v4df) (W), \
6296 (__mmask8) (U), \
6297 (R)))
6299 #define _mm256_maskz_sqrt_round_pd(U, A, R) \
6300 ((__m256d) __builtin_ia32_sqrtpd256_mask_round ((__v4df) (A), \
6301 (__v4df) \
6302 (_mm256_setzero_pd ()), \
6303 (__mmask8) (U), \
6304 (R)))
6306 #define _mm256_sqrt_round_ph(A, R) \
6307 ((__m256h) __builtin_ia32_sqrtph256_mask_round ((__v16hf) (A), \
6308 (__v16hf) \
6309 (_mm256_undefined_ph ()), \
6310 (__mmask16) (-1), \
6311 (R)))
6313 #define _mm256_mask_sqrt_round_ph(W, U, A, R) \
6314 ((__m256h) __builtin_ia32_sqrtph256_mask_round ((__v16hf) (A), \
6315 (__v16hf) (W), \
6316 (__mmask16) (U), \
6317 (R)))
6319 #define _mm256_maskz_sqrt_round_ph(U, A, R) \
6320 ((__m256h) __builtin_ia32_sqrtph256_mask_round ((__v16hf) (A), \
6321 (__v16hf) \
6322 (_mm256_setzero_ph ()), \
6323 (__mmask16) (U), \
6324 (R)))
6326 #define _mm256_sqrt_round_ps(A, R) \
6327 ((__m256) __builtin_ia32_sqrtps256_mask_round ((__v8sf) (A), \
6328 (__v8sf) \
6329 (_mm256_undefined_ps ()), \
6330 (__mmask8) (-1), \
6331 (R)))
6333 #define _mm256_mask_sqrt_round_ps(W, U, A, R) \
6334 ((__m256) __builtin_ia32_sqrtps256_mask_round ((__v8sf) (A), \
6335 (__v8sf) (W), \
6336 (__mmask8) (U), \
6337 (R)))
6339 #define _mm256_maskz_sqrt_round_ps(U, A, R) \
6340 ((__m256) __builtin_ia32_sqrtps256_mask_round ((__v8sf) (A), \
6341 (__v8sf) \
6342 (_mm256_setzero_ps ()), \
6343 (__mmask8) (U), \
6344 (R)))
6346 #define _mm256_sub_round_pd(A, B, R) \
6347 ((__m256d) __builtin_ia32_subpd256_mask_round ((__v4df) (A), \
6348 (__v4df) (B), \
6349 (__v4df) \
6350 (_mm256_undefined_pd ()), \
6351 (__mmask8) (-1), \
6352 (R)))
6354 #define _mm256_mask_sub_round_pd(W, U, A, B, R) \
6355 ((__m256d) __builtin_ia32_subpd256_mask_round ((__v4df) (A), \
6356 (__v4df) (B), \
6357 (__v4df) (W), \
6358 (__mmask8) (U), \
6359 (R)))
6361 #define _mm256_maskz_sub_round_pd(U, A, B, R) \
6362 ((__m256d) __builtin_ia32_subpd256_mask_round ((__v4df) (A), \
6363 (__v4df) (B), \
6364 (__v4df) \
6365 (_mm256_setzero_pd ()), \
6366 (__mmask8) (U), \
6367 (R)))
6369 #define _mm256_sub_round_ph(A, B, R) \
6370 ((__m256h) __builtin_ia32_subph256_mask_round ((__v16hf) (A), \
6371 (__v16hf) (B), \
6372 (__v16hf) \
6373 (_mm256_undefined_ph ()), \
6374 (__mmask16) (-1), \
6375 (R)))
6377 #define _mm256_mask_sub_round_ph(W, U, A, B, R) \
6378 ((__m256h) __builtin_ia32_subph256_mask_round ((__v16hf) (A), \
6379 (__v16hf) (B), \
6380 (__v16hf) (W), \
6381 (__mmask16) (U), \
6382 (R)))
6384 #define _mm256_maskz_sub_round_ph(U, A, B, R) \
6385 ((__m256h) __builtin_ia32_subph256_mask_round ((__v16hf) (A), \
6386 (__v16hf) (B), \
6387 (__v16hf) \
6388 (_mm256_setzero_ph ()), \
6389 (__mmask16) (U), \
6390 (R)))
6392 #define _mm256_sub_round_ps(A, B, R) \
6393 ((__m256) __builtin_ia32_subps256_mask_round ((__v8sf) (A), \
6394 (__v8sf) (B), \
6395 (__v8sf) \
6396 (_mm256_undefined_ps ()), \
6397 (__mmask8) (-1), \
6398 (R)))
6400 #define _mm256_mask_sub_round_ps(W, U, A, B, R) \
6401 ((__m256) __builtin_ia32_subps256_mask_round ((__v8sf) (A), \
6402 (__v8sf) (B), \
6403 (__v8sf) (W), \
6404 (__mmask8) (U), \
6405 (R)))
6407 #define _mm256_maskz_sub_round_ps(U, A, B, R) \
6408 ((__m256) __builtin_ia32_subps256_mask_round ((__v8sf) (A), \
6409 (__v8sf) (B), \
6410 (__v8sf) \
6411 (_mm256_setzero_ps ()), \
6412 (__mmask8) (U), \
6413 (R)))
6414 #endif
6416 #define _mm256_cmul_round_pch(A, B, R) _mm256_fcmul_round_pch ((A), (B), (R))
6417 #define _mm256_mask_cmul_round_pch(W, U, A, B, R) \
6418 _mm256_mask_fcmul_round_pch ((W), (U), (A), (B), (R))
6419 #define _mm256_maskz_cmul_round_pch(U, A, B, R) \
6420 _mm256_maskz_fcmul_round_pch ((U), (A), (B), (R))
6422 #define _mm256_mul_round_pch(A, B, R) _mm256_fmul_round_pch ((A), (B), (R))
6423 #define _mm256_mask_mul_round_pch(W, U, A, B, R) \
6424 _mm256_mask_fmul_round_pch ((W), (U), (A), (B), (R))
6425 #define _mm256_maskz_mul_round_pch(U, A, B, R) \
6426 _mm256_maskz_fmul_round_pch ((U), (A), (B), (R))
6428 #ifdef __DISABLE_AVX10_2_256__
6429 #undef __DISABLE_AVX10_2_256__
6430 #pragma GCC pop_options