gcc/config/i386/zn4zn5.md

   1 ;; Copyright (C) 2012-2024 Free Software Foundation, Inc.
   2 ;;
   3 ;; This file is part of GCC.
   4 ;;
   5 ;; GCC is free software; you can redistribute it and/or modify
   6 ;; it under the terms of the GNU General Public License as published by
   7 ;; the Free Software Foundation; either version 3, or (at your option)
   8 ;; any later version.
   9 ;;
  10 ;; GCC is distributed in the hope that it will be useful,
  11 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ;; GNU General Public License for more details.
  14 ;;
  15 ;; You should have received a copy of the GNU General Public License
  16 ;; along with GCC; see the file COPYING3.  If not see
  17 ;; <http://www.gnu.org/licenses/>.
  18 ;;
  19
  20
  21 (define_attr "znver4_decode" "direct,vector,double"
  22   (const_string "direct"))
  23
  24 ;; AMD znver4 and znver5 Scheduling
  25 ;; Modeling automatons for zen decoders, integer execution pipes,
  26 ;; AGU pipes, branch, floating point execution and fp store units.
  27 (define_automaton "znver4, znver4_ieu, znver4_idiv, znver4_fdiv, znver4_agu, znver4_fpu, znver4_fp_store")
  28
  29 ;; Decoders unit has 4 decoders and all of them can decode fast path
  30 ;; and vector type instructions.
  31 (define_cpu_unit "znver4-decode0" "znver4")
  32 (define_cpu_unit "znver4-decode1" "znver4")
  33 (define_cpu_unit "znver4-decode2" "znver4")
  34 (define_cpu_unit "znver4-decode3" "znver4")
  35
  36 ;; Currently blocking all decoders for vector path instructions as
  37 ;; they are dispatched separetely as microcode sequence.
  38 (define_reservation "znver4-vector" "znver4-decode0+znver4-decode1+znver4-decode2+znver4-decode3")
  39
  40 ;; Direct instructions can be issued to any of the four decoders.
  41 (define_reservation "znver4-direct" "znver4-decode0|znver4-decode1|znver4-decode2|znver4-decode3")
  42
  43 ;; Fix me: Need to revisit this later to simulate fast path double behavior.
  44 (define_reservation "znver4-double" "znver4-direct")
  45
  46
  47 ;; Integer unit 4 ALU pipes in znver4 6 ALU pipes in znver5.
  48 (define_cpu_unit "znver4-ieu0" "znver4_ieu")
  49 (define_cpu_unit "znver4-ieu1" "znver4_ieu")
  50 (define_cpu_unit "znver4-ieu2" "znver4_ieu")
  51 (define_cpu_unit "znver4-ieu3" "znver4_ieu")
  52 (define_cpu_unit "znver5-ieu4" "znver4_ieu")
  53 (define_cpu_unit "znver5-ieu5" "znver4_ieu")
  54
  55 ;; Znver4 has an additional branch unit.
  56 (define_cpu_unit "znver4-bru0" "znver4_ieu")
  57
  58 (define_reservation "znver4-ieu" "znver4-ieu0|znver4-ieu1|znver4-ieu2|znver4-ieu3")
  59 (define_reservation "znver5-ieu" "znver4-ieu0|znver4-ieu1|znver4-ieu2|znver4-ieu3|znver5-ieu4|znver5-ieu5")
  60
  61 ;; 3 AGU pipes in znver4 and 4 AGU pipes in znver5
  62 (define_cpu_unit "znver4-agu0" "znver4_agu")
  63 (define_cpu_unit "znver4-agu1" "znver4_agu")
  64 (define_cpu_unit "znver4-agu2" "znver4_agu")
  65 (define_cpu_unit "znver5-agu3" "znver4_agu")
  66
  67 (define_reservation "znver4-agu-reserve" "znver4-agu0|znver4-agu1|znver4-agu2")
  68 (define_reservation "znver5-agu-reserve" "znver4-agu0|znver4-agu1|znver4-agu2|znver5-agu3")
  69
  70 ;; Load is 4 cycles. We do not model reservation of load unit.
  71 (define_reservation "znver4-load" "znver4-agu-reserve")
  72 (define_reservation "znver4-store" "znver4-agu-reserve")
  73 (define_reservation "znver5-load" "znver5-agu-reserve")
  74 (define_reservation "znver5-store" "znver5-agu-reserve")
  75
  76 ;; vectorpath (microcoded) instructions are single issue instructions.
  77 ;; So, they occupy all the integer units.
  78 ;; This is used for both Znver4 and Znver5, since reserving extra units not used otherwise
  79 ;; is harmless.
  80 (define_reservation "znver4-ivector" "znver4-ieu0+znver4-ieu1
  81                                       +znver4-ieu2+znver4-ieu3+znver5-ieu4+znver5-ieu5+znver4-bru0
  82                                       +znver4-agu0+znver4-agu1+znver4-agu2+znver5-agu3")
  83
  84 ;; Floating point unit 4 FP pipes in znver4 and znver5.
  85 (define_cpu_unit "znver4-fpu0" "znver4_fpu")
  86 (define_cpu_unit "znver4-fpu1" "znver4_fpu")
  87 (define_cpu_unit "znver4-fpu2" "znver4_fpu")
  88 (define_cpu_unit "znver4-fpu3" "znver4_fpu")
  89
  90 (define_reservation "znver4-fpu" "znver4-fpu0|znver4-fpu1|znver4-fpu2|znver4-fpu3")
  91
  92 ;; DIV units
  93 (define_cpu_unit "znver4-idiv" "znver4_idiv")
  94 (define_cpu_unit "znver4-fdiv" "znver4_fdiv")
  95
  96 ;; Separate fp store and fp-to-int store. Although there are 2 store pipes, the
  97 ;; throughput is limited to only one per cycle.
  98 (define_cpu_unit "znver4-fp-store" "znver4_fp_store")
  99
 100 ;; Floating point store unit 2 FP pipes in znver5.
 101 (define_cpu_unit "znver5-fp-store0" "znver4_fp_store")
 102 (define_cpu_unit "znver5-fp-store1" "znver4_fp_store")
 103
 104 ;; This is used for both Znver4 and Znver5, since reserving extra units not used otherwise
 105 ;; is harmless.
 106 (define_reservation "znver4-fvector" "znver4-fpu0+znver4-fpu1
 107                                       +znver4-fpu2+znver4-fpu3+znver5-fp-store0+znver5-fp-store1
 108                                       +znver4-agu0+znver4-agu1+znver4-agu2+znver5-agu3")
 109
 110 (define_reservation "znver5-fp-store256" "znver5-fp-store0|znver5-fp-store1")
 111 (define_reservation "znver5-fp-store-512" "znver5-fp-store0+znver5-fp-store1")
 112
 113
 114 ;; Integer Instructions
 115 ;; Move instructions
 116 ;; XCHG
 117 (define_insn_reservation "znver4_imov_double" 1
 118                         (and (eq_attr "cpu" "znver4")
 119                                  (and (eq_attr "znver1_decode" "double")
 120                                   (and (eq_attr "type" "imov")
 121                                    (eq_attr "memory" "none"))))
 122                          "znver4-double,znver4-ieu")
 123
 124 (define_insn_reservation "znver5_imov_double" 1
 125                         (and (eq_attr "cpu" "znver5")
 126                                  (and (eq_attr "znver1_decode" "double")
 127                                   (and (eq_attr "type" "imov")
 128                                    (eq_attr "memory" "none"))))
 129                          "znver4-double,znver5-ieu")
 130
 131 (define_insn_reservation "znver4_imov_double_load" 5
 132                         (and (eq_attr "cpu" "znver4")
 133                                  (and (eq_attr "znver1_decode" "double")
 134                                   (and (eq_attr "type" "imov")
 135                                    (eq_attr "memory" "load"))))
 136                          "znver4-double,znver4-load,znver4-ieu")
 137
 138 (define_insn_reservation "znver5_imov_double_load" 5
 139                         (and (eq_attr "cpu" "znver5")
 140                                  (and (eq_attr "znver1_decode" "double")
 141                                   (and (eq_attr "type" "imov")
 142                                    (eq_attr "memory" "load"))))
 143                          "znver4-double,znver5-load,znver5-ieu")
 144
 145 ;; imov, imovx
 146 (define_insn_reservation "znver4_imov" 1
 147             (and (eq_attr "cpu" "znver4")
 148                                  (and (eq_attr "type" "imov,imovx")
 149                                   (eq_attr "memory" "none")))
 150              "znver4-direct,znver4-ieu")
 151
 152 (define_insn_reservation "znver5_imov" 1
 153             (and (eq_attr "cpu" "znver5")
 154                                  (and (eq_attr "type" "imov,imovx")
 155                                   (eq_attr "memory" "none")))
 156              "znver4-direct,znver5-ieu")
 157
 158 (define_insn_reservation "znver4_imov_load" 5
 159                         (and (eq_attr "cpu" "znver4")
 160                                  (and (eq_attr "type" "imov,imovx")
 161                                   (eq_attr "memory" "load")))
 162                          "znver4-direct,znver4-load,znver4-ieu")
 163
 164 (define_insn_reservation "znver5_imov_load" 5
 165                         (and (eq_attr "cpu" "znver5")
 166                                  (and (eq_attr "type" "imov,imovx")
 167                                   (eq_attr "memory" "load")))
 168                          "znver4-direct,znver5-load,znver5-ieu")
 169
 170 ;; Push Instruction
 171 (define_insn_reservation "znver4_push" 1
 172                         (and (eq_attr "cpu" "znver4")
 173                              (and (eq_attr "type" "push")
 174                                   (eq_attr "memory" "store")))
 175                          "znver4-direct,znver4-store")
 176
 177 (define_insn_reservation "znver5_push" 1
 178                         (and (eq_attr "cpu" "znver5")
 179                              (and (eq_attr "type" "push")
 180                                   (eq_attr "memory" "store")))
 181                          "znver4-direct,znver5-store")
 182
 183 (define_insn_reservation "znver4_push_mem" 5
 184                         (and (eq_attr "cpu" "znver4")
 185                                  (and (eq_attr "type" "push")
 186                                   (eq_attr "memory" "both")))
 187                          "znver4-direct,znver4-load,znver4-store")
 188
 189 (define_insn_reservation "znver5_push_mem" 5
 190                         (and (eq_attr "cpu" "znver5")
 191                                  (and (eq_attr "type" "push")
 192                                   (eq_attr "memory" "both")))
 193                          "znver4-direct,znver5-load,znver5-store")
 194
 195 ;; Pop instruction
 196 (define_insn_reservation "znver4_pop" 4
 197                         (and (eq_attr "cpu" "znver4")
 198                              (and (eq_attr "type" "pop")
 199                                   (eq_attr "memory" "load")))
 200                          "znver4-direct,znver4-load")
 201
 202 (define_insn_reservation "znver5_pop" 4
 203                         (and (eq_attr "cpu" "znver5")
 204                              (and (eq_attr "type" "pop")
 205                                   (eq_attr "memory" "load")))
 206                          "znver4-direct,znver5-load")
 207
 208 (define_insn_reservation "znver4_pop_mem" 5
 209             (and (eq_attr "cpu" "znver4")
 210                  (and (eq_attr "type" "pop")
 211                   (eq_attr "memory" "both")))
 212              "znver4-direct,znver4-load,znver4-store")
 213
 214 (define_insn_reservation "znver5_pop_mem" 5
 215             (and (eq_attr "cpu" "znver5")
 216                  (and (eq_attr "type" "pop")
 217                   (eq_attr "memory" "both")))
 218              "znver4-direct,znver5-load,znver5-store")
 219
 220 ;; Integer Instructions or General instructions
 221 ;; Multiplications
 222 (define_insn_reservation "znver4_imul" 3
 223                         (and (eq_attr "cpu" "znver4,znver5")
 224                              (and (eq_attr "type" "imul")
 225                                   (eq_attr "memory" "none")))
 226                          "znver4-direct,znver4-ieu1")
 227
 228 (define_insn_reservation "znver4_imul_load" 7
 229                         (and (eq_attr "cpu" "znver4")
 230                              (and (eq_attr "type" "imul")
 231                                   (eq_attr "memory" "load")))
 232                          "znver4-direct,znver4-load,znver4-ieu1")
 233
 234 (define_insn_reservation "znver5_imul_load" 7
 235                         (and (eq_attr "cpu" "znver5")
 236                              (and (eq_attr "type" "imul")
 237                                   (eq_attr "memory" "load")))
 238                          "znver4-direct,znver5-load,znver4-ieu1")
 239
 240 ;; Divisions
 241 (define_insn_reservation "znver4_idiv_DI" 18
 242                          (and (eq_attr "cpu" "znver4,znver5")
 243                               (and (eq_attr "type" "idiv")
 244                                    (and (eq_attr "mode" "DI")
 245                                         (eq_attr "memory" "none"))))
 246                          "znver4-double,znver4-idiv*10")
 247
 248 (define_insn_reservation "znver4_idiv_SI" 12
 249                          (and (eq_attr "cpu" "znver4,znver5")
 250                               (and (eq_attr "type" "idiv")
 251                                    (and (eq_attr "mode" "SI")
 252                                         (eq_attr "memory" "none"))))
 253                          "znver4-double,znver4-idiv*6")
 254
 255 (define_insn_reservation "znver4_idiv_HI" 10
 256                          (and (eq_attr "cpu" "znver4,znver5")
 257                               (and (eq_attr "type" "idiv")
 258                                    (and (eq_attr "mode" "HI")
 259                                         (eq_attr "memory" "none"))))
 260                          "znver4-double,znver4-idiv*4")
 261
 262 (define_insn_reservation "znver4_idiv_QI" 9
 263                          (and (eq_attr "cpu" "znver4,znver5")
 264                               (and (eq_attr "type" "idiv")
 265                                    (and (eq_attr "mode" "QI")
 266                                         (eq_attr "memory" "none"))))
 267                          "znver4-double,znver4-idiv*4")
 268
 269 (define_insn_reservation "znver4_idiv_DI_load" 22
 270                          (and (eq_attr "cpu" "znver4")
 271                               (and (eq_attr "type" "idiv")
 272                                    (and (eq_attr "mode" "DI")
 273                                         (eq_attr "memory" "load"))))
 274                          "znver4-double,znver4-load,znver4-idiv*10")
 275
 276 (define_insn_reservation "znver5_idiv_DI_load" 22
 277                          (and (eq_attr "cpu" "znver5")
 278                               (and (eq_attr "type" "idiv")
 279                                    (and (eq_attr "mode" "DI")
 280                                         (eq_attr "memory" "load"))))
 281                          "znver4-double,znver5-load,znver4-idiv*10")
 282
 283 (define_insn_reservation "znver4_idiv_SI_load" 16
 284                          (and (eq_attr "cpu" "znver4")
 285                               (and (eq_attr "type" "idiv")
 286                                    (and (eq_attr "mode" "SI")
 287                                         (eq_attr "memory" "load"))))
 288                          "znver4-double,znver4-load,znver4-idiv*6")
 289
 290 (define_insn_reservation "znver5_idiv_SI_load" 16
 291                          (and (eq_attr "cpu" "znver5")
 292                               (and (eq_attr "type" "idiv")
 293                                    (and (eq_attr "mode" "SI")
 294                                         (eq_attr "memory" "load"))))
 295                          "znver4-double,znver5-load,znver4-idiv*6")
 296
 297 (define_insn_reservation "znver4_idiv_HI_load" 14
 298                          (and (eq_attr "cpu" "znver4")
 299                               (and (eq_attr "type" "idiv")
 300                                    (and (eq_attr "mode" "HI")
 301                                         (eq_attr "memory" "load"))))
 302                          "znver4-double,znver4-load,znver4-idiv*4")
 303
 304 (define_insn_reservation "znver5_idiv_HI_load" 14
 305                          (and (eq_attr "cpu" "znver5")
 306                               (and (eq_attr "type" "idiv")
 307                                    (and (eq_attr "mode" "HI")
 308                                         (eq_attr "memory" "load"))))
 309                          "znver4-double,znver5-load,znver4-idiv*4")
 310
 311 (define_insn_reservation "znver4_idiv_QI_load" 13
 312                          (and (eq_attr "cpu" "znver4")
 313                               (and (eq_attr "type" "idiv")
 314                                    (and (eq_attr "mode" "QI")
 315                                         (eq_attr "memory" "load"))))
 316                          "znver4-double,znver4-load,znver4-idiv*4")
 317
 318 (define_insn_reservation "znver5_idiv_QI_load" 13
 319                          (and (eq_attr "cpu" "znver5")
 320                               (and (eq_attr "type" "idiv")
 321                                    (and (eq_attr "mode" "QI")
 322                                         (eq_attr "memory" "load"))))
 323                          "znver4-double,znver5-load,znver4-idiv*4")
 324
 325 ;; INTEGER/GENERAL Instructions
 326 (define_insn_reservation "znver4_insn" 1
 327                          (and (eq_attr "cpu" "znver4")
 328                               (and (eq_attr "type" "alu,alu1,negnot,rotate1,ishift1,test,incdec,icmp")
 329                                    (eq_attr "memory" "none,unknown")))
 330                          "znver4-direct,znver4-ieu")
 331
 332 (define_insn_reservation "znver5_insn" 1
 333                          (and (eq_attr "cpu" "znver5")
 334                               (and (eq_attr "type" "alu,alu1,negnot,rotate1,ishift1,test,incdec,icmp")
 335                                    (eq_attr "memory" "none,unknown")))
 336                          "znver4-direct,znver5-ieu")
 337
 338 (define_insn_reservation "znver4_insn_load" 5
 339                          (and (eq_attr "cpu" "znver4")
 340                               (and (eq_attr "type" "alu,alu1,negnot,rotate1,ishift1,test,incdec,icmp")
 341                                    (eq_attr "memory" "load")))
 342                          "znver4-direct,znver4-load,znver4-ieu")
 343
 344 (define_insn_reservation "znver5_insn_load" 5
 345                          (and (eq_attr "cpu" "znver5")
 346                               (and (eq_attr "type" "alu,alu1,negnot,rotate1,ishift1,test,incdec,icmp")
 347                                    (eq_attr "memory" "load")))
 348                          "znver4-direct,znver5-load,znver5-ieu")
 349
 350 (define_insn_reservation "znver4_insn2" 1
 351                          (and (eq_attr "cpu" "znver4,znver5")
 352                               (and (eq_attr "type" "icmov,setcc")
 353                                    (eq_attr "memory" "none,unknown")))
 354                          "znver4-direct,znver4-ieu0|znver4-ieu3")
 355
 356 (define_insn_reservation "znver4_insn2_load" 5
 357                          (and (eq_attr "cpu" "znver4")
 358                               (and (eq_attr "type" "icmov,setcc")
 359                                    (eq_attr "memory" "load")))
 360                          "znver4-direct,znver4-load,znver4-ieu0|znver4-ieu3")
 361
 362 (define_insn_reservation "znver5_insn2_load" 5
 363                          (and (eq_attr "cpu" "znver5")
 364                               (and (eq_attr "type" "icmov,setcc")
 365                                    (eq_attr "memory" "load")))
 366                          "znver4-direct,znver5-load,znver4-ieu0|znver4-ieu3")
 367
 368 (define_insn_reservation "znver4_rotate" 1
 369                          (and (eq_attr "cpu" "znver4,znver5")
 370                               (and (eq_attr "type" "rotate")
 371                                    (eq_attr "memory" "none,unknown")))
 372                          "znver4-direct,znver4-ieu1|znver4-ieu2")
 373
 374 (define_insn_reservation "znver4_rotate_load" 5
 375                          (and (eq_attr "cpu" "znver4")
 376                               (and (eq_attr "type" "rotate")
 377                                    (eq_attr "memory" "load")))
 378                          "znver4-direct,znver4-load,znver4-ieu1|znver4-ieu2")
 379
 380 (define_insn_reservation "znver5_rotate_load" 5
 381                          (and (eq_attr "cpu" "znver5")
 382                               (and (eq_attr "type" "rotate")
 383                                    (eq_attr "memory" "load")))
 384                          "znver4-direct,znver5-load,znver4-ieu1|znver4-ieu2")
 385
 386 (define_insn_reservation "znver4_insn_store" 1
 387                          (and (eq_attr "cpu" "znver4")
 388                               (and (eq_attr "type" "alu,alu1,negnot,rotate1,ishift1,test,incdec,icmp")
 389                                    (eq_attr "memory" "store")))
 390                          "znver4-direct,znver4-ieu,znver4-store")
 391
 392 (define_insn_reservation "znver5_insn_store" 1
 393                          (and (eq_attr "cpu" "znver5")
 394                               (and (eq_attr "type" "alu,alu1,negnot,rotate1,ishift1,test,incdec,icmp")
 395                                    (eq_attr "memory" "store")))
 396                          "znver4-direct,znver4-ieu,znver5-store")
 397
 398 (define_insn_reservation "znver4_insn2_store" 1
 399                          (and (eq_attr "cpu" "znver4")
 400                               (and (eq_attr "type" "icmov,setcc")
 401                                    (eq_attr "memory" "store")))
 402                          "znver4-direct,znver4-ieu0|znver4-ieu3,znver4-store")
 403
 404 (define_insn_reservation "znver5_insn2_store" 1
 405                          (and (eq_attr "cpu" "znver5")
 406                               (and (eq_attr "type" "icmov,setcc")
 407                                    (eq_attr "memory" "store")))
 408                          "znver4-direct,znver4-ieu0|znver4-ieu3,znver5-store")
 409
 410 (define_insn_reservation "znver4_rotate_store" 1
 411                          (and (eq_attr "cpu" "znver4")
 412                               (and (eq_attr "type" "rotate")
 413                                    (eq_attr "memory" "store")))
 414                          "znver4-direct,znver4-ieu1|znver4-ieu2,znver4-store")
 415
 416 (define_insn_reservation "znver5_rotate_store" 1
 417                          (and (eq_attr "cpu" "znver5")
 418                               (and (eq_attr "type" "rotate")
 419                                    (eq_attr "memory" "store")))
 420                          "znver4-direct,znver4-ieu1|znver4-ieu2,znver5-store")
 421
 422 ;; alu1 instructions
 423 (define_insn_reservation "znver4_alu1_vector" 3
 424                          (and (eq_attr "cpu" "znver4,znver5")
 425                               (and (eq_attr "znver1_decode" "vector")
 426                                    (and (eq_attr "type" "alu1")
 427                                         (eq_attr "memory" "none,unknown"))))
 428                          "znver4-vector,znver4-ivector*3")
 429
 430 (define_insn_reservation "znver4_alu1_vector_load" 7
 431                          (and (eq_attr "cpu" "znver4")
 432                               (and (eq_attr "znver1_decode" "vector")
 433                                    (and (eq_attr "type" "alu1")
 434                                         (eq_attr "memory" "load"))))
 435                          "znver4-vector,znver4-load,znver4-ivector*3")
 436
 437 (define_insn_reservation "znver5_alu1_vector_load" 7
 438                          (and (eq_attr "cpu" "znver5")
 439                               (and (eq_attr "znver1_decode" "vector")
 440                                    (and (eq_attr "type" "alu1")
 441                                         (eq_attr "memory" "load"))))
 442                          "znver4-vector,znver5-load,znver4-ivector*3")
 443
 444 ;; Call Instruction
 445 (define_insn_reservation "znver4_call" 1
 446                          (and (eq_attr "cpu" "znver4")
 447                               (eq_attr "type" "call,callv"))
 448                          "znver4-double,znver4-ieu0|znver4-bru0,znver4-store")
 449
 450 (define_insn_reservation "znver5_call" 1
 451                          (and (eq_attr "cpu" "znver5")
 452                               (eq_attr "type" "call,callv"))
 453                          "znver4-double,znver4-ieu0|znver4-bru0,znver5-store")
 454
 455 ;; Branches
 456 (define_insn_reservation "znver4_branch" 1
 457                          (and (eq_attr "cpu" "znver4,znver5")
 458                               (and (eq_attr "type" "ibr")
 459                                         (eq_attr "memory" "none")))
 460                           "znver4-direct,znver4-ieu0|znver4-bru0")
 461
 462 (define_insn_reservation "znver4_branch_load" 5
 463                          (and (eq_attr "cpu" "znver4")
 464                               (and (eq_attr "type" "ibr")
 465                                         (eq_attr "memory" "load")))
 466                           "znver4-direct,znver4-load,znver4-ieu0|znver4-bru0")
 467
 468 (define_insn_reservation "znver5_branch_load" 5
 469                          (and (eq_attr "cpu" "znver5")
 470                               (and (eq_attr "type" "ibr")
 471                                         (eq_attr "memory" "load")))
 472                           "znver4-direct,znver5-load,znver4-ieu0|znver4-bru0")
 473
 474 (define_insn_reservation "znver4_branch_vector" 2
 475                          (and (eq_attr "cpu" "znver4,znver5")
 476                               (and (eq_attr "type" "ibr")
 477                                         (eq_attr "memory" "none,unknown")))
 478                           "znver4-vector,znver4-ivector*2")
 479
 480 (define_insn_reservation "znver4_branch_vector_load" 6
 481                          (and (eq_attr "cpu" "znver4")
 482                               (and (eq_attr "type" "ibr")
 483                                         (eq_attr "memory" "load")))
 484                           "znver4-vector,znver4-load,znver4-ivector*2")
 485
 486 (define_insn_reservation "znver5_branch_vector_load" 6
 487                          (and (eq_attr "cpu" "znver5")
 488                               (and (eq_attr "type" "ibr")
 489                                         (eq_attr "memory" "load")))
 490                           "znver4-vector,znver5-load,znver4-ivector*2")
 491
 492 ;; LEA instruction with simple addressing
 493 (define_insn_reservation "znver4_lea" 1
 494                          (and (eq_attr "cpu" "znver4")
 495                               (eq_attr "type" "lea"))
 496                          "znver4-direct,znver4-ieu")
 497
 498 (define_insn_reservation "znver5_lea" 1
 499                          (and (eq_attr "cpu" "znver5")
 500                               (eq_attr "type" "lea"))
 501                          "znver4-direct,znver5-ieu")
 502 ;; Leave
 503 (define_insn_reservation "znver4_leave" 1
 504                          (and (eq_attr "cpu" "znver4")
 505                               (eq_attr "type" "leave"))
 506                          "znver4-double,znver4-ieu,znver4-store")
 507
 508 (define_insn_reservation "znver5_leave" 1
 509                          (and (eq_attr "cpu" "znver5")
 510                               (eq_attr "type" "leave"))
 511                          "znver4-double,znver5-ieu,znver5-store")
 512
 513 ;; STR and ISHIFT are microcoded.
 514 (define_insn_reservation "znver4_str" 3
 515                          (and (eq_attr "cpu" "znver4,znver5")
 516                               (and (eq_attr "type" "str")
 517                                    (eq_attr "memory" "none")))
 518                          "znver4-vector,znver4-ivector*3")
 519
 520 (define_insn_reservation "znver4_str_load" 7
 521                          (and (eq_attr "cpu" "znver4")
 522                               (and (eq_attr "type" "str")
 523                                    (eq_attr "memory" "load")))
 524                          "znver4-vector,znver4-load,znver4-ivector*3")
 525
 526 (define_insn_reservation "znver5_str_load" 7
 527                          (and (eq_attr "cpu" "znver5")
 528                               (and (eq_attr "type" "str")
 529                                    (eq_attr "memory" "load")))
 530                          "znver4-vector,znver5-load,znver4-ivector*3")
 531
 532 (define_insn_reservation "znver4_ishift" 2
 533                          (and (eq_attr "cpu" "znver4,znver5")
 534                               (and (eq_attr "type" "ishift")
 535                                    (eq_attr "memory" "none")))
 536                          "znver4-vector,znver4-ivector*2")
 537
 538 (define_insn_reservation "znver4_ishift_load" 6
 539                          (and (eq_attr "cpu" "znver4")
 540                               (and (eq_attr "type" "ishift")
 541                                    (eq_attr "memory" "load")))
 542                          "znver4-vector,znver4-load,znver4-ivector*2")
 543
 544 (define_insn_reservation "znver5_ishift_load" 6
 545                          (and (eq_attr "cpu" "znver5")
 546                               (and (eq_attr "type" "ishift")
 547                                    (eq_attr "memory" "load")))
 548                          "znver4-vector,znver5-load,znver4-ivector*2")
 549
 550 ;; Other vector type
 551 (define_insn_reservation "znver4_ieu_vector" 5
 552                          (and (eq_attr "cpu" "znver4,znver5")
 553                               (and (eq_attr "type" "other,multi")
 554                                    (eq_attr "memory" "none,unknown")))
 555                          "znver4-vector,znver4-ivector*5")
 556
 557 (define_insn_reservation "znver4_ieu_vector_load" 9
 558                          (and (eq_attr "cpu" "znver4")
 559                               (and (eq_attr "type" "other,multi")
 560                                    (eq_attr "memory" "load")))
 561                          "znver4-vector,znver4-load,znver4-ivector*5")
 562
 563 (define_insn_reservation "znver5_ieu_vector_load" 9
 564                          (and (eq_attr "cpu" "znver5")
 565                               (and (eq_attr "type" "other,multi")
 566                                    (eq_attr "memory" "load")))
 567                          "znver4-vector,znver5-load,znver4-ivector*5")
 568
 569 ;; Floating Point
 570 ;; FP movs
 571 (define_insn_reservation "znver4_fp_cmov" 4
 572                          (and (eq_attr "cpu" "znver4,znver5")
 573                               (eq_attr "type" "fcmov"))
 574                          "znver4-vector,znver4-fvector*3")
 575
 576 (define_insn_reservation "znver4_fp_mov_direct" 1
 577                          (and (eq_attr "cpu" "znver4,znver5")
 578                               (eq_attr "type" "fmov"))
 579                          "znver4-direct,znver4-fpu0|znver4-fpu1")
 580
 581 ;;FLD
 582 (define_insn_reservation "znver4_fp_mov_direct_load" 6
 583                          (and (eq_attr "cpu" "znver4")
 584                               (and (eq_attr "znver1_decode" "direct")
 585                                    (and (eq_attr "type" "fmov")
 586                                         (eq_attr "memory" "load"))))
 587                          "znver4-direct,znver4-load,znver4-fpu0|znver4-fpu1")
 588
 589 (define_insn_reservation "znver5_fp_mov_direct_load" 6
 590                          (and (eq_attr "cpu" "znver5")
 591                               (and (eq_attr "znver1_decode" "direct")
 592                                    (and (eq_attr "type" "fmov")
 593                                         (eq_attr "memory" "load"))))
 594                          "znver4-direct,znver5-load,znver4-fpu0|znver4-fpu1")
 595
 596 ;;FST
 597 (define_insn_reservation "znver4_fp_mov_direct_store" 6
 598                          (and (eq_attr "cpu" "znver4")
 599                               (and (eq_attr "znver1_decode" "direct")
 600                                    (and (eq_attr "type" "fmov")
 601                                         (eq_attr "memory" "store"))))
 602                          "znver4-direct,znver4-fpu0|znver4-fpu1,znver4-fp-store")
 603
 604 (define_insn_reservation "znver5_fp_mov_direct_store" 6
 605                          (and (eq_attr "cpu" "znver5")
 606                               (and (eq_attr "znver1_decode" "direct")
 607                                    (and (eq_attr "type" "fmov")
 608                                         (eq_attr "memory" "store"))))
 609                          "znver4-direct,znver4-fpu0|znver4-fpu1,znver5-fp-store256")
 610
 611 ;;FILD
 612 (define_insn_reservation "znver4_fp_mov_double_load" 13
 613                          (and (eq_attr "cpu" "znver4")
 614                               (and (eq_attr "znver1_decode" "double")
 615                                    (and (eq_attr "type" "fmov")
 616                                         (eq_attr "memory" "load"))))
 617                          "znver4-direct,znver4-load,znver4-fpu1")
 618
 619 (define_insn_reservation "znver5_fp_mov_double_load" 13
 620                          (and (eq_attr "cpu" "znver5")
 621                               (and (eq_attr "znver1_decode" "double")
 622                                    (and (eq_attr "type" "fmov")
 623                                         (eq_attr "memory" "load"))))
 624                          "znver4-direct,znver5-load,znver4-fpu1")
 625
 626 ;;FIST
 627 (define_insn_reservation "znver4_fp_mov_double_store" 7
 628                          (and (eq_attr "cpu" "znver4")
 629                               (and (eq_attr "znver1_decode" "double")
 630                                    (and (eq_attr "type" "fmov")
 631                                         (eq_attr "memory" "store"))))
 632                          "znver4-double,znver4-fpu1,znver4-fp-store")
 633
 634 (define_insn_reservation "znver5_fp_mov_double_store" 7
 635                          (and (eq_attr "cpu" "znver5")
 636                               (and (eq_attr "znver1_decode" "double")
 637                                    (and (eq_attr "type" "fmov")
 638                                         (eq_attr "memory" "store"))))
 639                          "znver4-double,znver4-fpu1,znver5-fp-store256")
 640
 641 ;; FSQRT
 642 (define_insn_reservation "znver4_fsqrt" 22
 643                          (and (eq_attr "cpu" "znver4,znver5")
 644                               (and (eq_attr "type" "fpspc")
 645                                    (and (eq_attr "mode" "XF")
 646                                         (eq_attr "memory" "none"))))
 647                          "znver4-direct,znver4-fdiv*10")
 648
 649 ;; FPSPC instructions
 650 (define_insn_reservation "znver4_fp_spc" 6
 651                          (and (eq_attr "cpu" "znver4,znver5")
 652                               (and (eq_attr "type" "fpspc")
 653                                    (eq_attr "memory" "none")))
 654                          "znver4-vector,znver4-fvector*6")
 655
 656 (define_insn_reservation "znver4_fp_insn_vector" 6
 657                          (and (eq_attr "cpu" "znver4,znver5")
 658                               (and (eq_attr "znver1_decode" "vector")
 659                                    (eq_attr "type" "mmxcvt,sselog1,ssemov")))
 660                          "znver4-vector,znver4-fvector*6")
 661
 662 ;; FADD, FSUB, FMUL
 663 (define_insn_reservation "znver4_fp_op_mul" 7
 664                          (and (eq_attr "cpu" "znver4,znver5")
 665                               (and (eq_attr "type" "fop,fmul")
 666                                    (eq_attr "memory" "none")))
 667                          "znver4-direct,znver4-fpu0")
 668
 669 (define_insn_reservation "znver4_fp_op_mul_load" 12
 670                          (and (eq_attr "cpu" "znver4")
 671                               (and (eq_attr "type" "fop,fmul")
 672                                    (eq_attr "memory" "load")))
 673                          "znver4-direct,znver4-load,znver4-fpu0")
 674
 675 (define_insn_reservation "znver5_fp_op_mul_load" 12
 676                          (and (eq_attr "cpu" "znver5")
 677                               (and (eq_attr "type" "fop,fmul")
 678                                    (eq_attr "memory" "load")))
 679                          "znver4-direct,znver5-load,znver4-fpu0")
 680 ;; FDIV
 681 (define_insn_reservation "znver4_fp_div" 15
 682                          (and (eq_attr "cpu" "znver4,znver5")
 683                               (and (eq_attr "type" "fdiv")
 684                                    (eq_attr "memory" "none")))
 685                          "znver4-direct,znver4-fdiv*6")
 686
 687 (define_insn_reservation "znver4_fp_div_load" 20
 688                          (and (eq_attr "cpu" "znver4")
 689                               (and (eq_attr "type" "fdiv")
 690                                    (eq_attr "memory" "load")))
 691                          "znver4-direct,znver4-load,znver4-fdiv*6")
 692
 693 (define_insn_reservation "znver5_fp_div_load" 20
 694                          (and (eq_attr "cpu" "znver5")
 695                               (and (eq_attr "type" "fdiv")
 696                                    (eq_attr "memory" "load")))
 697                          "znver4-direct,znver5-load,znver4-fdiv*6")
 698
 699 (define_insn_reservation "znver4_fp_idiv_load" 24
 700                          (and (eq_attr "cpu" "znver4")
 701                               (and (eq_attr "type" "fdiv")
 702                                    (and (eq_attr "fp_int_src" "true")
 703                                         (eq_attr "memory" "load"))))
 704                          "znver4-double,znver4-load,znver4-fdiv*6")
 705
 706 (define_insn_reservation "znver5_fp_idiv_load" 24
 707                          (and (eq_attr "cpu" "znver5")
 708                               (and (eq_attr "type" "fdiv")
 709                                    (and (eq_attr "fp_int_src" "true")
 710                                         (eq_attr "memory" "load"))))
 711                          "znver4-double,znver5-load,znver4-fdiv*6")
 712
 713 ;; FABS, FCHS
 714 (define_insn_reservation "znver4_fp_fsgn" 1
 715                          (and (eq_attr "cpu" "znver4")
 716                               (eq_attr "type" "fsgn"))
 717                          "znver4-direct,znver4-fpu0|znver4-fpu1")
 718
 719 (define_insn_reservation "znver5_fp_fsgn" 1
 720                          (and (eq_attr "cpu" "znver5")
 721                               (eq_attr "type" "fsgn"))
 722                          "znver4-direct,znver4-fpu1|znver4-fpu2")
 723
 724 ;; FCMP
 725 (define_insn_reservation "znver4_fp_fcmp" 3
 726                          (and (eq_attr "cpu" "znver4,znver5")
 727                               (and (eq_attr "type" "fcmp")
 728                                    (eq_attr "memory" "none")))
 729                          "znver4-direct,znver4-fpu1")
 730
 731 (define_insn_reservation "znver4_fp_fcmp_double" 4
 732                          (and (eq_attr "cpu" "znver4")
 733                               (and (eq_attr "type" "fcmp")
 734                                    (and (eq_attr "znver1_decode" "double")
 735                                         (eq_attr "memory" "none"))))
 736                          "znver4-double,znver4-fpu1,znver4-fpu2")
 737
 738 (define_insn_reservation "znver5_fp_fcmp_double" 4
 739                          (and (eq_attr "cpu" "znver5")
 740                               (and (eq_attr "type" "fcmp")
 741                                    (and (eq_attr "znver1_decode" "double")
 742                                         (eq_attr "memory" "none"))))
 743                          "znver4-double,znver4-fpu1,znver5-fp-store256")
 744
 745 ;; MMX, SSE, SSEn.n instructions
 746 (define_insn_reservation "znver4_fp_mmx " 1
 747                          (and (eq_attr "cpu" "znver4,znver5")
 748                               (eq_attr "type" "mmx"))
 749                          "znver4-direct,znver4-fpu1|znver4-fpu2")
 750
 751 (define_insn_reservation "znver4_mmx_add_cmp" 1
 752                          (and (eq_attr "cpu" "znver4,znver5")
 753                               (and (eq_attr "type" "mmxadd,mmxcmp")
 754                                    (eq_attr "memory" "none")))
 755                          "znver4-direct,znver4-fpu")
 756
 757 (define_insn_reservation "znver4_mmx_add_cmp_load" 6
 758                          (and (eq_attr "cpu" "znver4")
 759                               (and (eq_attr "type" "mmxadd,mmxcmp")
 760                                    (eq_attr "memory" "load")))
 761                          "znver4-direct,znver4-load,znver4-fpu")
 762
 763 (define_insn_reservation "znver5_mmx_add_cmp_load" 6
 764                          (and (eq_attr "cpu" "znver5")
 765                               (and (eq_attr "type" "mmxadd,mmxcmp")
 766                                    (eq_attr "memory" "load")))
 767                          "znver4-direct,znver5-load,znver4-fpu")
 768
 769 (define_insn_reservation "znver4_mmx_insn" 1
 770                          (and (eq_attr "cpu" "znver4")
 771                               (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1,mmxshft")
 772                                    (eq_attr "memory" "none")))
 773                          "znver4-direct,znver4-fpu1|znver4-fpu2")
 774
 775 (define_insn_reservation "znver5_mmx_insn" 1
 776                          (and (eq_attr "cpu" "znver5")
 777                               (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1,mmxshft")
 778                                    (eq_attr "memory" "none")))
 779                          "znver4-direct,znver4-fpu0|znver4-fpu1|znver4-fpu2|znver4-fpu3")
 780
 781 (define_insn_reservation "znver4_mmx_insn_load" 6
 782                          (and (eq_attr "cpu" "znver4")
 783                               (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1,mmxshft")
 784                                    (eq_attr "memory" "load")))
 785                          "znver4-direct,znver4-load,znver4-fpu1|znver4-fpu2")
 786
 787 (define_insn_reservation "znver5_mmx_insn_load" 6
 788                          (and (eq_attr "cpu" "znver5")
 789                               (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1,mmxshft")
 790                                    (eq_attr "memory" "load")))
 791                          "znver4-direct,znver5-load,znver4-fpu0|znver4-fpu1|znver4-fpu2|znver4-fpu3")
 792
 793 (define_insn_reservation "znver4_mmx_mov" 1
 794                          (and (eq_attr "cpu" "znver4")
 795                               (and (eq_attr "type" "mmxmov")
 796                                    (eq_attr "memory" "store")))
 797                          "znver4-direct,znver4-fp-store")
 798
 799 (define_insn_reservation "znver5_mmx_mov" 1
 800                          (and (eq_attr "cpu" "znver5")
 801                               (and (eq_attr "type" "mmxmov")
 802                                    (eq_attr "memory" "store")))
 803                          "znver4-direct,znver5-fp-store256")
 804
 805 (define_insn_reservation "znver4_mmx_mov_load" 6
 806                          (and (eq_attr "cpu" "znver4")
 807                               (and (eq_attr "type" "mmxmov")
 808                                    (eq_attr "memory" "both")))
 809                          "znver4-direct,znver4-load,znver4-fp-store")
 810
 811 (define_insn_reservation "znver5_mmx_mov_load" 6
 812                          (and (eq_attr "cpu" "znver5")
 813                               (and (eq_attr "type" "mmxmov")
 814                                    (eq_attr "memory" "both")))
 815                          "znver4-direct,znver5-load,znver5-fp-store256")
 816
 817 (define_insn_reservation "znver4_mmx_mul" 3
 818                          (and (eq_attr "cpu" "znver4,znver5")
 819                               (and (eq_attr "type" "mmxmul")
 820                                    (eq_attr "memory" "none")))
 821                           "znver4-direct,znver4-fpu0|znver4-fpu3")
 822
 823 (define_insn_reservation "znver4_mmx_mul_load" 8
 824                          (and (eq_attr "cpu" "znver4")
 825                               (and (eq_attr "type" "mmxmul")
 826                                    (eq_attr "memory" "load")))
 827                           "znver4-direct,znver4-load,znver4-fpu0|znver4-fpu3")
 828
 829 (define_insn_reservation "znver5_mmx_mul_load" 8
 830                          (and (eq_attr "cpu" "znver5")
 831                               (and (eq_attr "type" "mmxmul")
 832                                    (eq_attr "memory" "load")))
 833                           "znver4-direct,znver5-load,znver4-fpu0|znver4-fpu3")
 834
 835 ;; AVX instructions
 836 (define_insn_reservation "znver4_sse_log" 1
 837                          (and (eq_attr "cpu" "znver4,znver5")
 838                               (and (eq_attr "type" "sselog")
 839                                    (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF,QI,HI,SI,DI,TI,OI")
 840                                     (eq_attr "memory" "none"))))
 841                          "znver4-direct,znver4-fpu")
 842
 843 (define_insn_reservation "znver4_sse_log_load" 6
 844                          (and (eq_attr "cpu" "znver4")
 845                               (and (eq_attr "type" "sselog")
 846                                    (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF,QI,HI,SI,DI,TI,OI")
 847                                     (eq_attr "memory" "load"))))
 848                          "znver4-direct,znver4-load,znver4-fpu")
 849
 850 (define_insn_reservation "znver5_sse_log_load" 6
 851                          (and (eq_attr "cpu" "znver5")
 852                               (and (eq_attr "type" "sselog")
 853                                    (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF,QI,HI,SI,DI,TI,OI")
 854                                     (eq_attr "memory" "load"))))
 855                          "znver4-direct,znver5-load,znver4-fpu")
 856
 857 (define_insn_reservation "znver4_sse_log1" 1
 858                          (and (eq_attr "cpu" "znver4")
 859                               (and (eq_attr "type" "sselog1")
 860                                    (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF,QI,HI,SI,DI,TI,OI")
 861                                     (eq_attr "memory" "store"))))
 862                          "znver4-direct,znver4-fpu1|znver4-fpu2,znver4-fp-store")
 863
 864 (define_insn_reservation "znver5_sse_log1" 1
 865                          (and (eq_attr "cpu" "znver5")
 866                               (and (eq_attr "type" "sselog1")
 867                                    (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF,QI,HI,SI,DI,TI,OI")
 868                                     (eq_attr "memory" "store"))))
 869                          "znver4-direct,znver4-fpu1|znver4-fpu2,znver5-fp-store256")
 870
 871 (define_insn_reservation "znver4_sse_log1_load" 6
 872                          (and (eq_attr "cpu" "znver4")
 873                               (and (eq_attr "type" "sselog1")
 874                                    (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF,QI,HI,SI,DI,TI,OI")
 875                                     (eq_attr "memory" "both"))))
 876                          "znver4-direct,znver4-load,znver4-fpu1|znver4-fpu2,znver4-fp-store")
 877
 878 (define_insn_reservation "znver5_sse_log1_load" 6
 879                          (and (eq_attr "cpu" "znver5")
 880                               (and (eq_attr "type" "sselog1")
 881                                    (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF,QI,HI,SI,DI,TI,OI")
 882                                     (eq_attr "memory" "both"))))
 883                          "znver4-direct,znver5-load,znver4-fpu1|znver4-fpu2,znver5-fp-store256")
 884
 885 (define_insn_reservation "znver4_sse_comi" 1
 886                          (and (eq_attr "cpu" "znver4")
 887                               (and (eq_attr "type" "ssecomi")
 888                                    (eq_attr "memory" "store")))
 889                          "znver4-double,znver4-fpu2|znver4-fpu3,znver4-fp-store")
 890
 891 (define_insn_reservation "znver5_sse_comi" 1
 892                          (and (eq_attr "cpu" "znver5")
 893                               (and (eq_attr "type" "ssecomi")
 894                                    (eq_attr "memory" "store")))
 895                          "znver4-double,znver4-fpu2|znver4-fpu3,znver5-fp-store256")
 896
 897 (define_insn_reservation "znver4_sse_comi_load" 6
 898                          (and (eq_attr "cpu" "znver4")
 899                               (and (eq_attr "type" "ssecomi")
 900                                    (eq_attr "memory" "both")))
 901                          "znver4-double,znver4-load,znver4-fpu2|znver4-fpu3,znver4-fp-store")
 902
 903 (define_insn_reservation "znver5_sse_comi_load" 6
 904                          (and (eq_attr "cpu" "znver5")
 905                               (and (eq_attr "type" "ssecomi")
 906                                    (eq_attr "memory" "both")))
 907                          "znver4-double,znver5-load,znver4-fpu2|znver4-fpu3,znver5-fp-store256")
 908
 909 (define_insn_reservation "znver4_sse_test" 1
 910                          (and (eq_attr "cpu" "znver4,znver5")
 911                               (and (eq_attr "prefix_extra" "1")
 912                                    (and (eq_attr "type" "ssecomi")
 913                                         (eq_attr "memory" "none"))))
 914                          "znver4-direct,znver4-fpu1|znver4-fpu2")
 915
 916 (define_insn_reservation "znver4_sse_test_load" 6
 917                          (and (eq_attr "cpu" "znver4")
 918                               (and (eq_attr "prefix_extra" "1")
 919                                    (and (eq_attr "type" "ssecomi")
 920                                         (eq_attr "memory" "load"))))
 921                          "znver4-direct,znver4-load,znver4-fpu1|znver4-fpu2")
 922
 923 (define_insn_reservation "znver5_sse_test_load" 6
 924                          (and (eq_attr "cpu" "znver5")
 925                               (and (eq_attr "prefix_extra" "1")
 926                                    (and (eq_attr "type" "ssecomi")
 927                                         (eq_attr "memory" "load"))))
 928                          "znver4-direct,znver5-load,znver4-fpu1|znver4-fpu2")
 929
 930 (define_insn_reservation "znver4_sse_imul" 3
 931                          (and (eq_attr "cpu" "znver4,znver5")
 932                               (and (eq_attr "type" "sseimul")
 933                                    (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI")
 934                                     (eq_attr "memory" "none"))))
 935                          "znver4-direct,znver4-fpu0|znver4-fpu3")
 936
 937 (define_insn_reservation "znver4_sse_imul_load" 8
 938                          (and (eq_attr "cpu" "znver4")
 939                               (and (eq_attr "type" "sseimul")
 940                                    (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI")
 941                                     (eq_attr "memory" "load"))))
 942                          "znver4-direct,znver4-load,znver4-fpu0|znver4-fpu1")
 943
 944 (define_insn_reservation "znver5_sse_imul_load" 8
 945                          (and (eq_attr "cpu" "znver5")
 946                               (and (eq_attr "type" "sseimul")
 947                                    (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI")
 948                                     (eq_attr "memory" "load"))))
 949                          "znver4-direct,znver5-load,znver4-fpu0|znver4-fpu1")
 950
 951 (define_insn_reservation "znver4_sse_mov" 1
 952                          (and (eq_attr "cpu" "znver4,znver5")
 953                               (and (eq_attr "type" "ssemov")
 954                                    (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI")
 955                                     (eq_attr "memory" "none"))))
 956                          "znver4-direct,znver4-fpu1|znver4-fpu2")
 957
 958 (define_insn_reservation "znver4_sse_mov_load" 6
 959                          (and (eq_attr "cpu" "znver4")
 960                               (and (eq_attr "type" "ssemov")
 961                                    (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI")
 962                                     (eq_attr "memory" "load"))))
 963                          "znver4-direct,znver4-load,znver4-fpu1|znver4-fpu2")
 964
 965 (define_insn_reservation "znver5_sse_mov_load" 6
 966                          (and (eq_attr "cpu" "znver5")
 967                               (and (eq_attr "type" "ssemov")
 968                                    (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI")
 969                                     (eq_attr "memory" "load"))))
 970                          "znver4-direct,znver5-load,znver4-fpu1|znver4-fpu2")
 971
 972 (define_insn_reservation "znver4_sse_mov_store" 1
 973                          (and (eq_attr "cpu" "znver4")
 974                               (and (eq_attr "type" "ssemov")
 975                                    (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI")
 976                                     (eq_attr "memory" "store"))))
 977                          "znver4-direct,znver4-fpu1|znver4-fpu2,znver4-fp-store")
 978
 979 (define_insn_reservation "znver5_sse_mov_store" 1
 980                          (and (eq_attr "cpu" "znver5")
 981                               (and (eq_attr "type" "ssemov")
 982                                    (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI")
 983                                     (eq_attr "memory" "store"))))
 984                          "znver4-direct,znver4-fpu1|znver4-fpu2,znver5-fp-store256")
 985
 986 (define_insn_reservation "znver4_sse_mov_fp" 1
 987                          (and (eq_attr "cpu" "znver4,znver5")
 988                               (and (eq_attr "type" "ssemov")
 989                                    (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
 990                                     (eq_attr "memory" "none"))))
 991                          "znver4-direct,znver4-fpu")
 992
 993 (define_insn_reservation "znver4_sse_mov_fp_load" 6
 994                          (and (eq_attr "cpu" "znver4")
 995                               (and (eq_attr "type" "ssemov")
 996                                    (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
 997                                     (eq_attr "memory" "load"))))
 998                          "znver4-direct,znver4-load,znver4-fpu")
 999
1000 (define_insn_reservation "znver5_sse_mov_fp_load" 6
1001                          (and (eq_attr "cpu" "znver5")
1002                               (and (eq_attr "type" "ssemov")
1003                                    (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1004                                     (eq_attr "memory" "load"))))
1005                          "znver4-direct,znver5-load,znver4-fpu")
1006
1007 (define_insn_reservation "znver4_sse_mov_fp_store" 1
1008                          (and (eq_attr "cpu" "znver4")
1009                               (and (eq_attr "type" "ssemov")
1010                                    (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1011                                     (eq_attr "memory" "store"))))
1012                          "znver4-direct,znver4-fp-store")
1013
1014 (define_insn_reservation "znver5_sse_mov_fp_store" 1
1015                          (and (eq_attr "cpu" "znver5")
1016                               (and (eq_attr "type" "ssemov")
1017                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1018                                     (eq_attr "memory" "store"))))
1019                          "znver4-direct,znver5-fp-store256")
1020
1021 (define_insn_reservation "znver5_sse_mov_fp_store_512" 1
1022                          (and (eq_attr "cpu" "znver5")
1023                               (and (eq_attr "type" "ssemov")
1024                                    (and (eq_attr "mode" "V16SF,V8DF")
1025                                     (eq_attr "memory" "store"))))
1026                          "znver4-direct,znver5-fp-store-512")
1027
1028 (define_insn_reservation "znver4_sse_add" 3
1029                          (and (eq_attr "cpu" "znver4,znver5")
1030                               (and (eq_attr "type" "sseadd")
1031                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1032                                     (eq_attr "memory" "none"))))
1033                          "znver4-direct,znver4-fpu2|znver4-fpu3")
1034
1035 (define_insn_reservation "znver4_sse_add_load" 8
1036                          (and (eq_attr "cpu" "znver4")
1037                               (and (eq_attr "type" "sseadd")
1038                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1039                                     (eq_attr "memory" "load"))))
1040                          "znver4-direct,znver4-load,znver4-fpu2|znver4-fpu3")
1041
1042 (define_insn_reservation "znver5_sse_add_load" 8
1043                          (and (eq_attr "cpu" "znver5")
1044                               (and (eq_attr "type" "sseadd")
1045                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1046                                     (eq_attr "memory" "load"))))
1047                          "znver4-direct,znver5-load,znver4-fpu2|znver4-fpu3")
1048
1049 (define_insn_reservation "znver4_sse_add1" 4
1050                          (and (eq_attr "cpu" "znver4,znver5")
1051                               (and (eq_attr "type" "sseadd1")
1052                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1053                                     (eq_attr "memory" "none"))))
1054                          "znver4-vector,znver4-fvector*2")
1055
1056 (define_insn_reservation "znver4_sse_add1_load" 9
1057                          (and (eq_attr "cpu" "znver4")
1058                               (and (eq_attr "type" "sseadd1")
1059                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1060                                     (eq_attr "memory" "load"))))
1061                          "znver4-vector,znver4-load,znver4-fvector*2")
1062
1063 (define_insn_reservation "znver5_sse_add1_load" 9
1064                          (and (eq_attr "cpu" "znver5")
1065                               (and (eq_attr "type" "sseadd1")
1066                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1067                                     (eq_attr "memory" "load"))))
1068                          "znver4-vector,znver5-load,znver4-fvector*2")
1069
1070 (define_insn_reservation "znver4_sse_iadd" 1
1071                          (and (eq_attr "cpu" "znver4,znver5")
1072                               (and (eq_attr "type" "sseiadd")
1073                                    (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI")
1074                                     (eq_attr "memory" "none"))))
1075                          "znver4-direct,znver4-fpu")
1076
1077 (define_insn_reservation "znver4_sse_iadd_load" 6
1078                          (and (eq_attr "cpu" "znver4")
1079                               (and (eq_attr "type" "sseiadd")
1080                                    (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI")
1081                                     (eq_attr "memory" "load"))))
1082                          "znver4-direct,znver4-load,znver4-fpu")
1083
1084 (define_insn_reservation "znver5_sse_iadd_load" 6
1085                          (and (eq_attr "cpu" "znver5")
1086                               (and (eq_attr "type" "sseiadd")
1087                                    (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI")
1088                                     (eq_attr "memory" "load"))))
1089                          "znver4-direct,znver5-load,znver4-fpu")
1090
1091 (define_insn_reservation "znver4_sse_mul" 3
1092                          (and (eq_attr "cpu" "znver4,znver5")
1093                               (and (eq_attr "type" "ssemul")
1094                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1095                                     (eq_attr "memory" "none"))))
1096                          "znver4-direct,znver4-fpu0|znver4-fpu1")
1097
1098 (define_insn_reservation "znver4_sse_mul_load" 8
1099                          (and (eq_attr "cpu" "znver4")
1100                               (and (eq_attr "type" "ssemul")
1101                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1102                                     (eq_attr "memory" "load"))))
1103                          "znver4-direct,znver4-load,znver4-fpu0|znver4-fpu1")
1104
1105 (define_insn_reservation "znver5_sse_mul_load" 8
1106                          (and (eq_attr "cpu" "znver5")
1107                               (and (eq_attr "type" "ssemul")
1108                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1109                                     (eq_attr "memory" "load"))))
1110                          "znver4-direct,znver5-load,znver4-fpu0|znver4-fpu1")
1111
1112 (define_insn_reservation "znver4_sse_div_pd" 13
1113                          (and (eq_attr "cpu" "znver4,znver5")
1114                               (and (eq_attr "type" "ssediv")
1115                                    (and (eq_attr "mode" "V4DF,V2DF,V1DF")
1116                                     (eq_attr "memory" "none"))))
1117                          "znver4-direct,znver4-fdiv*5")
1118
1119 (define_insn_reservation "znver4_sse_div_ps" 10
1120                          (and (eq_attr "cpu" "znver4,znver5")
1121                               (and (eq_attr "type" "ssediv")
1122                                    (and (eq_attr "mode" "V8SF,V4SF,V2SF,SF")
1123                                     (eq_attr "memory" "none"))))
1124                          "znver4-direct,znver4-fdiv*3")
1125
1126 (define_insn_reservation "znver4_sse_div_pd_load" 18
1127                          (and (eq_attr "cpu" "znver4")
1128                               (and (eq_attr "type" "ssediv")
1129                                    (and (eq_attr "mode" "V4DF,V2DF,V1DF")
1130                                     (eq_attr "memory" "load"))))
1131                          "znver4-direct,znver4-load,znver4-fdiv*5")
1132
1133 (define_insn_reservation "znver5_sse_div_pd_load" 18
1134                          (and (eq_attr "cpu" "znver5")
1135                               (and (eq_attr "type" "ssediv")
1136                                    (and (eq_attr "mode" "V4DF,V2DF,V1DF")
1137                                     (eq_attr "memory" "load"))))
1138                          "znver4-direct,znver5-load,znver4-fdiv*5")
1139
1140 (define_insn_reservation "znver4_sse_div_ps_load" 15
1141                          (and (eq_attr "cpu" "znver4")
1142                               (and (eq_attr "type" "ssediv")
1143                                    (and (eq_attr "mode" "V8SF,V4SF,V2SF,SF")
1144                                     (eq_attr "memory" "load"))))
1145                          "znver4-direct,znver4-load,znver4-fdiv*3")
1146
1147 (define_insn_reservation "znver5_sse_div_ps_load" 15
1148                          (and (eq_attr "cpu" "znver5")
1149                               (and (eq_attr "type" "ssediv")
1150                                    (and (eq_attr "mode" "V8SF,V4SF,V2SF,SF")
1151                                     (eq_attr "memory" "load"))))
1152                          "znver4-direct,znver5-load,znver4-fdiv*3")
1153
1154 (define_insn_reservation "znver4_sse_cmp_avx" 1
1155                          (and (eq_attr "cpu" "znver4,znver5")
1156                               (and (eq_attr "type" "ssecmp")
1157                                    (and (eq_attr "prefix" "vex")
1158                                     (eq_attr "memory" "none"))))
1159                          "znver4-direct,znver4-fpu0|znver4-fpu1")
1160
1161 (define_insn_reservation "znver4_sse_cmp_avx_load" 6
1162                          (and (eq_attr "cpu" "znver4")
1163                               (and (eq_attr "type" "ssecmp")
1164                                    (and (eq_attr "prefix" "vex")
1165                                     (eq_attr "memory" "load"))))
1166                          "znver4-direct,znver4-load,znver4-fpu0|znver4-fpu1")
1167
1168 (define_insn_reservation "znver5_sse_cmp_avx_load" 6
1169                          (and (eq_attr "cpu" "znver5")
1170                               (and (eq_attr "type" "ssecmp")
1171                                    (and (eq_attr "prefix" "vex")
1172                                     (eq_attr "memory" "load"))))
1173                          "znver4-direct,znver5-load,znver4-fpu0|znver4-fpu1")
1174
1175 (define_insn_reservation "znver4_sse_comi_avx" 1
1176                          (and (eq_attr "cpu" "znver4")
1177                               (and (eq_attr "type" "ssecomi")
1178                                    (eq_attr "memory" "store")))
1179                          "znver4-direct,znver4-fpu2+znver4-fpu3,znver4-fp-store")
1180
1181 (define_insn_reservation "znver5_sse_comi_avx" 1
1182                          (and (eq_attr "cpu" "znver5")
1183                               (and (eq_attr "type" "ssecomi")
1184                                    (eq_attr "memory" "store")))
1185                          "znver4-direct,znver4-fpu2+znver4-fpu3,znver5-fp-store256")
1186
1187 (define_insn_reservation "znver4_sse_comi_avx_load" 6
1188                          (and (eq_attr "cpu" "znver4")
1189                               (and (eq_attr "type" "ssecomi")
1190                                    (eq_attr "memory" "both")))
1191                          "znver4-direct,znver4-load,znver4-fpu2+znver4-fpu3,znver4-fp-store")
1192
1193 (define_insn_reservation "znver5_sse_comi_avx_load" 6
1194                          (and (eq_attr "cpu" "znver5")
1195                               (and (eq_attr "type" "ssecomi")
1196                                    (eq_attr "memory" "both")))
1197                          "znver4-direct,znver5-load,znver4-fpu2+znver4-fpu3,znver5-fp-store256")
1198
1199 (define_insn_reservation "znver4_sse_cvt" 3
1200                          (and (eq_attr "cpu" "znver4,znver5")
1201                               (and (eq_attr "type" "ssecvt")
1202                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1203                                     (eq_attr "memory" "none"))))
1204                          "znver4-direct,znver4-fpu2|znver4-fpu3")
1205
1206 (define_insn_reservation "znver4_sse_cvt_load" 8
1207                          (and (eq_attr "cpu" "znver4")
1208                               (and (eq_attr "type" "ssecvt")
1209                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1210                                     (eq_attr "memory" "load"))))
1211                          "znver4-direct,znver4-load,znver4-fpu2|znver4-fpu3")
1212
1213 (define_insn_reservation "znver5_sse_cvt_load" 8
1214                          (and (eq_attr "cpu" "znver5")
1215                               (and (eq_attr "type" "ssecvt")
1216                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1217                                     (eq_attr "memory" "load"))))
1218                          "znver4-direct,znver5-load,znver4-fpu2|znver4-fpu3")
1219
1220 (define_insn_reservation "znver4_sse_icvt" 3
1221                          (and (eq_attr "cpu" "znver4,znver5")
1222                               (and (eq_attr "type" "ssecvt")
1223                                    (and (eq_attr "mode" "SI")
1224                                     (eq_attr "memory" "none"))))
1225                          "znver4-direct,znver4-fpu2|znver4-fpu3")
1226
1227 (define_insn_reservation "znver4_sse_icvt_store" 4
1228                          (and (eq_attr "cpu" "znver4")
1229                               (and (eq_attr "type" "ssecvt")
1230                                    (and (eq_attr "mode" "SI")
1231                                     (eq_attr "memory" "store"))))
1232                          "znver4-double,znver4-fpu2|znver4-fpu3,znver4-fp-store")
1233
1234 (define_insn_reservation "znver5_sse_icvt_store" 4
1235                          (and (eq_attr "cpu" "znver5")
1236                               (and (eq_attr "type" "ssecvt")
1237                                    (and (eq_attr "mode" "SI")
1238                                     (eq_attr "memory" "store"))))
1239                          "znver4-double,znver4-fpu2|znver4-fpu3,znver5-fp-store256")
1240
1241 (define_insn_reservation "znver4_sse_shuf" 1
1242                          (and (eq_attr "cpu" "znver4")
1243                               (and (eq_attr "type" "sseshuf")
1244                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1245                                     (eq_attr "memory" "none"))))
1246                          "znver4-direct,znver4-fpu1|znver4-fpu2")
1247
1248 (define_insn_reservation "znver5_sse_shuf" 1
1249                          (and (eq_attr "cpu" "znver5")
1250                               (and (eq_attr "type" "sseshuf")
1251                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1252                                     (eq_attr "memory" "none"))))
1253                          "znver4-direct,znver4-fpu1|znver4-fpu2|znver4-fpu3")
1254
1255 (define_insn_reservation "znver4_sse_shuf_load" 6
1256                          (and (eq_attr "cpu" "znver4")
1257                               (and (eq_attr "type" "sseshuf")
1258                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1259                                     (eq_attr "memory" "load"))))
1260                          "znver4-direct,znver4-load,znver4-fpu")
1261
1262 (define_insn_reservation "znver5_sse_shuf_load" 6
1263                          (and (eq_attr "cpu" "znver5")
1264                               (and (eq_attr "type" "sseshuf")
1265                                    (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF")
1266                                     (eq_attr "memory" "load"))))
1267                          "znver4-direct,znver5-load,znver4-fpu")
1268
1269 (define_insn_reservation "znver4_sse_ishuf" 3
1270                          (and (eq_attr "cpu" "znver4,znver5")
1271                               (and (eq_attr "type" "sseshuf")
1272                                    (and (eq_attr "mode" "OI")
1273                                     (eq_attr "memory" "none"))))
1274                          "znver4-direct,znver4-fpu1|znver4-fpu2")
1275
1276 (define_insn_reservation "znver4_sse_ishuf_load" 8
1277                          (and (eq_attr "cpu" "znver4")
1278                               (and (eq_attr "type" "sseshuf")
1279                                    (and (eq_attr "mode" "OI")
1280                                     (eq_attr "memory" "load"))))
1281                          "znver4-direct,znver4-load,znver4-fpu1|znver4-fpu2")
1282
1283 (define_insn_reservation "znver5_sse_ishuf_load" 8
1284                          (and (eq_attr "cpu" "znver5")
1285                               (and (eq_attr "type" "sseshuf")
1286                                    (and (eq_attr "mode" "OI")
1287                                     (eq_attr "memory" "load"))))
1288                          "znver4-direct,znver5-load,znver4-fpu1|znver4-fpu2")
1289
1290 ;; AVX512 instructions
1291 (define_insn_reservation "znver4_sse_log_evex" 1
1292                          (and (eq_attr "cpu" "znver4")
1293                               (and (eq_attr "type" "sselog")
1294                                    (and (eq_attr "mode" "V16SF,V8DF,XI")
1295                                     (eq_attr "memory" "none"))))
1296                          "znver4-direct,znver4-fpu0*2|znver4-fpu1*2|znver4-fpu2*2|znver4-fpu3*2")
1297
1298 (define_insn_reservation "znver5_sse_log_evex" 1
1299                          (and (eq_attr "cpu" "znver5")
1300                               (and (eq_attr "type" "sselog")
1301                                    (and (eq_attr "mode" "V16SF,V8DF,XI")
1302                                     (eq_attr "memory" "none"))))
1303                          "znver4-direct,znver4-fpu0|znver4-fpu1|znver4-fpu2|znver4-fpu3")
1304
1305 (define_insn_reservation "znver4_sse_log_evex_load" 7
1306                          (and (eq_attr "cpu" "znver4")
1307                               (and (eq_attr "type" "sselog")
1308                                    (and (eq_attr "mode" "V16SF,V8DF,XI")
1309                                     (eq_attr "memory" "load"))))
1310                          "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2|znver4-fpu2*2|znver4-fpu3*2")
1311
1312 (define_insn_reservation "znver5_sse_log_evex_load" 7
1313                          (and (eq_attr "cpu" "znver5")
1314                               (and (eq_attr "type" "sselog")
1315                                    (and (eq_attr "mode" "V16SF,V8DF,XI")
1316                                     (eq_attr "memory" "load"))))
1317                          "znver4-direct,znver5-load,znver4-fpu0|znver4-fpu1|znver4-fpu2|znver4-fpu3")
1318
1319 (define_insn_reservation "znver4_sse_log1_evex" 1
1320                          (and (eq_attr "cpu" "znver4")
1321                               (and (eq_attr "type" "sselog1")
1322                                    (and (eq_attr "mode" "V16SF,V8DF,XI")
1323                                     (eq_attr "memory" "none"))))
1324                          "znver4-direct,znver4-fpu1*2|znver4-fpu2*2,znver4-fp-store")
1325
1326 (define_insn_reservation "znver5_sse_log1_evex" 1
1327                          (and (eq_attr "cpu" "znver5")
1328                               (and (eq_attr "type" "sselog1")
1329                                    (and (eq_attr "mode" "V16SF,V8DF,XI")
1330                                     (eq_attr "memory" "none"))))
1331                          "znver4-direct,znver4-fpu1|znver4-fpu2,znver5-fp-store-512")
1332
1333 (define_insn_reservation "znver4_sse_log1_evex_load" 7
1334                          (and (eq_attr "cpu" "znver4")
1335                               (and (eq_attr "type" "sselog1")
1336                                    (and (eq_attr "mode" "V16SF,V8DF,XI")
1337                                     (eq_attr "memory" "load"))))
1338                          "znver4-direct,znver4-load,znver4-fpu1*2|znver4-fpu2*2,znver4-fp-store")
1339
1340 (define_insn_reservation "znver5_sse_log1_evex_load" 7
1341                          (and (eq_attr "cpu" "znver5")
1342                               (and (eq_attr "type" "sselog1")
1343                                    (and (eq_attr "mode" "V16SF,V8DF,XI")
1344                                     (eq_attr "memory" "load"))))
1345                          "znver4-direct,znver5-load,znver4-fpu1|znver4-fpu2,znver5-fp-store-512")
1346
1347 (define_insn_reservation "znver4_sse_mul_evex" 3
1348                          (and (eq_attr "cpu" "znver4")
1349                               (and (eq_attr "type" "ssemul")
1350                                    (and (eq_attr "mode" "V16SF,V8DF")
1351                                     (eq_attr "memory" "none"))))
1352                          "znver4-direct,znver4-fpu0*2|znver4-fpu1*2")
1353
1354 (define_insn_reservation "znver5_sse_mul_evex" 3
1355                          (and (eq_attr "cpu" "znver5")
1356                               (and (eq_attr "type" "ssemul")
1357                                    (and (eq_attr "mode" "V16SF,V8DF")
1358                                     (eq_attr "memory" "none"))))
1359                          "znver4-direct,znver4-fpu0|znver4-fpu1")
1360
1361 (define_insn_reservation "znver4_sse_mul_evex_load" 9
1362                          (and (eq_attr "cpu" "znver4")
1363                               (and (eq_attr "type" "ssemul")
1364                                    (and (eq_attr "mode" "V16SF,V8DF")
1365                                     (eq_attr "memory" "load"))))
1366                          "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2")
1367
1368 (define_insn_reservation "znver5_sse_mul_evex_load" 9
1369                          (and (eq_attr "cpu" "znver5")
1370                               (and (eq_attr "type" "ssemul")
1371                                    (and (eq_attr "mode" "V16SF,V8DF")
1372                                     (eq_attr "memory" "load"))))
1373                          "znver4-direct,znver4-load,znver4-fpu0|znver4-fpu1")
1374
1375 (define_insn_reservation "znver4_sse_imul_evex" 3
1376                          (and (eq_attr "cpu" "znver4")
1377                               (and (eq_attr "type" "sseimul")
1378                                    (and (eq_attr "mode" "XI")
1379                                     (eq_attr "memory" "none"))))
1380                          "znver4-direct,znver4-fpu0*2|znver4-fpu3*2")
1381
1382 (define_insn_reservation "znver5_sse_imul_evex" 3
1383                          (and (eq_attr "cpu" "znver5")
1384                               (and (eq_attr "type" "sseimul")
1385                                    (and (eq_attr "mode" "XI")
1386                                     (eq_attr "memory" "none"))))
1387                          "znver4-direct,znver4-fpu0|znver4-fpu3")
1388
1389 (define_insn_reservation "znver4_sse_imul_evex_load" 9
1390                          (and (eq_attr "cpu" "znver4")
1391                               (and (eq_attr "type" "sseimul")
1392                                    (and (eq_attr "mode" "XI")
1393                                     (eq_attr "memory" "load"))))
1394                          "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2")
1395
1396 (define_insn_reservation "znver5_sse_imul_evex_load" 9
1397                          (and (eq_attr "cpu" "znver5")
1398                               (and (eq_attr "type" "sseimul")
1399                                    (and (eq_attr "mode" "XI")
1400                                     (eq_attr "memory" "load"))))
1401                          "znver4-direct,znver4-load,znver4-fpu0|znver4-fpu1")
1402
1403 (define_insn_reservation "znver4_sse_mov_evex" 4
1404                          (and (eq_attr "cpu" "znver4")
1405                               (and (eq_attr "type" "ssemov")
1406                                    (and (eq_attr "mode" "XI")
1407                                     (eq_attr "memory" "none"))))
1408                          "znver4-direct,znver4-fpu1*2|znver4-fpu2*2")
1409
1410 (define_insn_reservation "znver5_sse_mov_evex" 2
1411                          (and (eq_attr "cpu" "znver5")
1412                               (and (eq_attr "type" "ssemov")
1413                                    (and (eq_attr "mode" "XI")
1414                                     (eq_attr "memory" "none"))))
1415                          "znver4-direct,znver4-fpu1|znver4-fpu2")
1416
1417 (define_insn_reservation "znver4_sse_mov_evex_load" 10
1418                          (and (eq_attr "cpu" "znver4")
1419                               (and (eq_attr "type" "ssemov")
1420                                    (and (eq_attr "mode" "XI")
1421                                     (eq_attr "memory" "load"))))
1422                          "znver4-direct,znver4-load,znver4-fpu1*2|znver4-fpu2*2")
1423
1424 (define_insn_reservation "znver5_sse_mov_evex_load" 8
1425                          (and (eq_attr "cpu" "znver5")
1426                               (and (eq_attr "type" "ssemov")
1427                                    (and (eq_attr "mode" "XI")
1428                                     (eq_attr "memory" "load"))))
1429                          "znver4-direct,znver4-load,znver4-fpu1|znver4-fpu2")
1430
1431 (define_insn_reservation "znver4_sse_mov_evex_store" 5
1432                          (and (eq_attr "cpu" "znver4")
1433                               (and (eq_attr "type" "ssemov")
1434                                    (and (eq_attr "mode" "XI")
1435                                     (eq_attr "memory" "store"))))
1436                          "znver4-direct,znver4-fpu1*2|znver4-fpu2*2,znver4-fp-store")
1437
1438 (define_insn_reservation "znver5_sse_mov_evex_store" 3
1439                          (and (eq_attr "cpu" "znver5")
1440                               (and (eq_attr "type" "ssemov")
1441                                    (and (eq_attr "mode" "XI")
1442                                     (eq_attr "memory" "store"))))
1443                          "znver4-direct,znver4-fpu1|znver4-fpu2,znver5-fp-store-512")
1444
1445 (define_insn_reservation "znver4_sse_add_evex" 3
1446                          (and (eq_attr "cpu" "znver4")
1447                               (and (eq_attr "type" "sseadd")
1448                                    (and (eq_attr "mode" "V16SF,V8DF")
1449                                     (eq_attr "memory" "none"))))
1450                          "znver4-direct,znver4-fpu2*2|znver4-fpu3*2")
1451
1452 (define_insn_reservation "znver5_sse_add_evex" 2
1453                          (and (eq_attr "cpu" "znver5")
1454                               (and (eq_attr "type" "sseadd")
1455                                    (and (eq_attr "mode" "V16SF,V8DF")
1456                                     (eq_attr "memory" "none"))))
1457                          "znver4-direct,znver4-fpu2|znver4-fpu3")
1458
1459 (define_insn_reservation "znver4_sse_add_evex_load" 9
1460                          (and (eq_attr "cpu" "znver4")
1461                               (and (eq_attr "type" "sseadd")
1462                                    (and (eq_attr "mode" "V16SF,V8DF")
1463                                     (eq_attr "memory" "load"))))
1464                          "znver4-direct,znver4-load,znver4-fpu2*2|znver4-fpu3*2")
1465
1466 (define_insn_reservation "znver5_sse_add_evex_load" 8
1467                          (and (eq_attr "cpu" "znver5")
1468                               (and (eq_attr "type" "sseadd")
1469                                    (and (eq_attr "mode" "V16SF,V8DF")
1470                                     (eq_attr "memory" "load"))))
1471                          "znver4-direct,znver4-load,znver4-fpu2|znver4-fpu3")
1472
1473 (define_insn_reservation "znver4_sse_iadd_evex" 1
1474                          (and (eq_attr "cpu" "znver4")
1475                               (and (eq_attr "type" "sseiadd")
1476                                    (and (eq_attr "mode" "XI")
1477                                     (eq_attr "memory" "none"))))
1478                          "znver4-direct,znver4-fpu0*2|znver4-fpu1*2|znver4-fpu2*2|znver4-fpu3*2")
1479
1480 (define_insn_reservation "znver5_sse_iadd_evex" 1
1481                          (and (eq_attr "cpu" "znver5")
1482                               (and (eq_attr "type" "sseiadd")
1483                                    (and (eq_attr "mode" "XI")
1484                                     (eq_attr "memory" "none"))))
1485                          "znver4-direct,znver4-fpu0|znver4-fpu1|znver4-fpu2|znver4-fpu3")
1486
1487 (define_insn_reservation "znver4_sse_iadd_evex_load" 7
1488                          (and (eq_attr "cpu" "znver4")
1489                               (and (eq_attr "type" "sseiadd")
1490                                    (and (eq_attr "mode" "XI")
1491                                     (eq_attr "memory" "load"))))
1492                          "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2|znver4-fpu2*2|znver4-fpu3*2")
1493
1494 (define_insn_reservation "znver5_sse_iadd_evex_load" 7
1495                          (and (eq_attr "cpu" "znver5")
1496                               (and (eq_attr "type" "sseiadd")
1497                                    (and (eq_attr "mode" "XI")
1498                                     (eq_attr "memory" "load"))))
1499                          "znver4-direct,znver4-load,znver4-fpu0|znver4-fpu1|znver4-fpu2|znver4-fpu3")
1500
1501 (define_insn_reservation "znver4_sse_div_pd_evex" 13
1502                          (and (eq_attr "cpu" "znver4")
1503                               (and (eq_attr "type" "ssediv")
1504                                    (and (eq_attr "mode" "V8DF")
1505                                     (eq_attr "memory" "none"))))
1506                          "znver4-direct,znver4-fdiv*9")
1507
1508 (define_insn_reservation "znver5_sse_div_pd_evex" 13
1509                          (and (eq_attr "cpu" "znver5")
1510                               (and (eq_attr "type" "ssediv")
1511                                    (and (eq_attr "mode" "V8DF")
1512                                     (eq_attr "memory" "none"))))
1513                          "znver4-direct,znver4-fdiv*9")
1514
1515 (define_insn_reservation "znver4_sse_div_ps_evex" 10
1516                          (and (eq_attr "cpu" "znver4")
1517                               (and (eq_attr "type" "ssediv")
1518                                    (and (eq_attr "mode" "V16SF")
1519                                     (eq_attr "memory" "none"))))
1520                          "znver4-direct,znver4-fdiv*6")
1521
1522 (define_insn_reservation "znver5_sse_div_ps_evex" 10
1523                          (and (eq_attr "cpu" "znver5")
1524                               (and (eq_attr "type" "ssediv")
1525                                    (and (eq_attr "mode" "V16SF")
1526                                     (eq_attr "memory" "none"))))
1527                          "znver4-direct,znver4-fdiv*6")
1528
1529 (define_insn_reservation "znver4_sse_div_pd_evex_load" 19
1530                          (and (eq_attr "cpu" "znver4")
1531                               (and (eq_attr "type" "ssediv")
1532                                    (and (eq_attr "mode" "V8DF")
1533                                     (eq_attr "memory" "load"))))
1534                          "znver4-direct,znver4-load,znver4-fdiv*9")
1535
1536 (define_insn_reservation "znver5_sse_div_pd_evex_load" 19
1537                          (and (eq_attr "cpu" "znver5")
1538                               (and (eq_attr "type" "ssediv")
1539                                    (and (eq_attr "mode" "V8DF")
1540                                     (eq_attr "memory" "load"))))
1541                          "znver4-direct,znver5-load,znver4-fdiv*9")
1542
1543 (define_insn_reservation "znver4_sse_div_ps_evex_load" 16
1544                          (and (eq_attr "cpu" "znver4")
1545                               (and (eq_attr "type" "ssediv")
1546                                    (and (eq_attr "mode" "V16SF")
1547                                     (eq_attr "memory" "load"))))
1548                          "znver4-direct,znver4-load,znver4-fdiv*6")
1549
1550 (define_insn_reservation "znver5_sse_div_ps_evex_load" 16
1551                          (and (eq_attr "cpu" "znver5")
1552                               (and (eq_attr "type" "ssediv")
1553                                    (and (eq_attr "mode" "V16SF")
1554                                     (eq_attr "memory" "load"))))
1555                          "znver4-direct,znver5-load,znver4-fdiv*6")
1556
1557 (define_insn_reservation "znver4_sse_cmp_avx128" 3
1558                          (and (eq_attr "cpu" "znver4")
1559                               (and (eq_attr "type" "ssecmp")
1560                                    (and (eq_attr "mode" "V4SF,V2DF,V2SF,V1DF,SF")
1561                                     (and (eq_attr "prefix" "evex")
1562                                          (eq_attr "memory" "none")))))
1563                          "znver4-direct,znver4-fpu0*2|znver4-fpu1*2")
1564
1565 (define_insn_reservation "znver5_sse_cmp_avx128" 3
1566                          (and (eq_attr "cpu" "znver5")
1567                               (and (eq_attr "type" "ssecmp")
1568                                    (and (eq_attr "mode" "V4SF,V2DF,V2SF,V1DF,SF")
1569                                     (and (eq_attr "prefix" "evex")
1570                                          (eq_attr "memory" "none")))))
1571                          "znver4-direct,znver4-fpu1|znver4-fpu2")
1572
1573 (define_insn_reservation "znver4_sse_cmp_avx128_load" 9
1574                          (and (eq_attr "cpu" "znver4")
1575                               (and (eq_attr "type" "ssecmp")
1576                                    (and (eq_attr "mode" "V4SF,V2DF,V2SF,V1DF,SF")
1577                                     (and (eq_attr "prefix" "evex")
1578                                          (eq_attr "memory" "load")))))
1579                          "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2")
1580
1581 (define_insn_reservation "znver5_sse_cmp_avx128_load" 9
1582                          (and (eq_attr "cpu" "znver5")
1583                               (and (eq_attr "type" "ssecmp")
1584                                    (and (eq_attr "mode" "V4SF,V2DF,V2SF,V1DF,SF")
1585                                     (and (eq_attr "prefix" "evex")
1586                                          (eq_attr "memory" "load")))))
1587                          "znver4-direct,znver5-load,znver4-fpu1|znver4-fpu2")
1588
1589 (define_insn_reservation "znver4_sse_cmp_avx256" 4
1590                          (and (eq_attr "cpu" "znver4")
1591                               (and (eq_attr "type" "ssecmp")
1592                                    (and (eq_attr "mode" "V8SF,V4DF")
1593                                     (and (eq_attr "prefix" "evex")
1594                                          (eq_attr "memory" "none")))))
1595                          "znver4-direct,znver4-fpu0*2|znver4-fpu1*2")
1596
1597 (define_insn_reservation "znver5_sse_cmp_avx256" 4
1598                          (and (eq_attr "cpu" "znver5")
1599                               (and (eq_attr "type" "ssecmp")
1600                                    (and (eq_attr "mode" "V8SF,V4DF")
1601                                     (and (eq_attr "prefix" "evex")
1602                                          (eq_attr "memory" "none")))))
1603                          "znver4-direct,znver4-fpu1|znver4-fpu2")
1604
1605 (define_insn_reservation "znver4_sse_cmp_avx256_load" 10
1606                          (and (eq_attr "cpu" "znver4")
1607                               (and (eq_attr "type" "ssecmp")
1608                                    (and (eq_attr "mode" "V8SF,V4DF")
1609                                     (and (eq_attr "prefix" "evex")
1610                                          (eq_attr "memory" "load")))))
1611                          "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2")
1612
1613 (define_insn_reservation "znver5_sse_cmp_avx256_load" 10
1614                          (and (eq_attr "cpu" "znver5")
1615                               (and (eq_attr "type" "ssecmp")
1616                                    (and (eq_attr "mode" "V8SF,V4DF")
1617                                     (and (eq_attr "prefix" "evex")
1618                                          (eq_attr "memory" "load")))))
1619                          "znver4-direct,znver5-load,znver4-fpu1|znver4-fpu2")
1620
1621 (define_insn_reservation "znver4_sse_cmp_avx512" 5
1622                          (and (eq_attr "cpu" "znver4")
1623                               (and (eq_attr "type" "ssecmp")
1624                                    (and (eq_attr "mode" "V16SF,V8DF")
1625                                     (and (eq_attr "prefix" "evex")
1626                                          (eq_attr "memory" "none")))))
1627                          "znver4-direct,znver4-fpu0*2|znver4-fpu1*2")
1628
1629 (define_insn_reservation "znver5_sse_cmp_avx512" 5
1630                          (and (eq_attr "cpu" "znver5")
1631                               (and (eq_attr "type" "ssecmp")
1632                                    (and (eq_attr "mode" "V16SF,V8DF")
1633                                     (and (eq_attr "prefix" "evex")
1634                                          (eq_attr "memory" "none")))))
1635                          "znver4-direct,znver4-fpu1|znver4-fpu2")
1636
1637 (define_insn_reservation "znver4_sse_cmp_avx512_load" 11
1638                          (and (eq_attr "cpu" "znver4")
1639                               (and (eq_attr "type" "ssecmp")
1640                                    (and (eq_attr "mode" "V16SF,V8DF")
1641                                     (and (eq_attr "prefix" "evex")
1642                                          (eq_attr "memory" "load")))))
1643                          "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2")
1644
1645 (define_insn_reservation "znver5_sse_cmp_avx512_load" 11
1646                          (and (eq_attr "cpu" "znver5")
1647                               (and (eq_attr "type" "ssecmp")
1648                                    (and (eq_attr "mode" "V16SF,V8DF")
1649                                     (and (eq_attr "prefix" "evex")
1650                                          (eq_attr "memory" "load")))))
1651                          "znver4-direct,znver5-load,znver4-fpu1|znver4-fpu2")
1652
1653 (define_insn_reservation "znver4_sse_cvt_evex" 6
1654                          (and (eq_attr "cpu" "znver4")
1655                               (and (eq_attr "type" "ssecvt")
1656                                    (and (eq_attr "mode" "V16SF,V8DF")
1657                                     (eq_attr "memory" "none"))))
1658                          "znver4-direct,znver4-fpu1*2|znver4-fpu2*2,znver4-fpu2*2|znver4-fpu3*2")
1659
1660 (define_insn_reservation "znver5_sse_cvt_evex" 6
1661                          (and (eq_attr "cpu" "znver5")
1662                               (and (eq_attr "type" "ssecvt")
1663                                    (and (eq_attr "mode" "V16SF,V8DF")
1664                                     (eq_attr "memory" "none"))))
1665                          "znver4-direct,znver4-fpu1|znver4-fpu2,znver4-fpu2|znver4-fpu3")
1666
1667 (define_insn_reservation "znver4_sse_cvt_evex_load" 12
1668                          (and (eq_attr "cpu" "znver4")
1669                               (and (eq_attr "type" "ssecvt")
1670                                    (and (eq_attr "mode" "V16SF,V8DF")
1671                                     (eq_attr "memory" "load"))))
1672                          "znver4-direct,znver4-load,znver4-fpu1*2|znver4-fpu2*2,znver4-fpu2*2|znver4-fpu3*2")
1673
1674 (define_insn_reservation "znver5_sse_cvt_evex_load" 12
1675                          (and (eq_attr "cpu" "znver5")
1676                               (and (eq_attr "type" "ssecvt")
1677                                    (and (eq_attr "mode" "V16SF,V8DF")
1678                                     (eq_attr "memory" "load"))))
1679                          "znver4-direct,znver5-load,znver4-fpu1|znver4-fpu2,znver4-fpu2|znver4-fpu3")
1680
1681 (define_insn_reservation "znver4_sse_shuf_evex" 1
1682                          (and (eq_attr "cpu" "znver4")
1683                               (and (eq_attr "type" "sseshuf")
1684                                    (and (eq_attr "mode" "V16SF,V8DF")
1685                                     (eq_attr "memory" "none"))))
1686                          "znver4-direct,znver4-fpu0*2|znver4-fpu1*2|znver4-fpu2*2|znver4-fpu3*2")
1687
1688 (define_insn_reservation "znver5_sse_shuf_evex" 1
1689                          (and (eq_attr "cpu" "znver5")
1690                               (and (eq_attr "type" "sseshuf")
1691                                    (and (eq_attr "mode" "V16SF,V8DF")
1692                                     (eq_attr "memory" "none"))))
1693                          "znver4-direct,znver4-fpu0|znver4-fpu1|znver4-fpu2|znver4-fpu3")
1694
1695 (define_insn_reservation "znver4_sse_shuf_evex_load" 7
1696                          (and (eq_attr "cpu" "znver4")
1697                               (and (eq_attr "type" "sseshuf")
1698                                    (and (eq_attr "mode" "V16SF,V8DF")
1699                                     (eq_attr "memory" "load"))))
1700                          "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2|znver4-fpu2*2|znver4-fpu3*2")
1701
1702 (define_insn_reservation "znver5_sse_shuf_evex_load" 7
1703                          (and (eq_attr "cpu" "znver5")
1704                               (and (eq_attr "type" "sseshuf")
1705                                    (and (eq_attr "mode" "V16SF,V8DF")
1706                                     (eq_attr "memory" "load"))))
1707                          "znver4-direct,znver5-load,znver4-fpu0|znver4-fpu1|znver4-fpu2|znver4-fpu3")
1708
1709 (define_insn_reservation "znver4_sse_ishuf_evex" 4
1710                          (and (eq_attr "cpu" "znver4")
1711                               (and (eq_attr "type" "sseshuf")
1712                                    (and (eq_attr "mode" "XI")
1713                                     (eq_attr "memory" "none"))))
1714                          "znver4-direct,znver4-fpu1*2|znver4-fpu2*2")
1715
1716 (define_insn_reservation "znver5_sse_ishuf_evex" 5
1717                          (and (eq_attr "cpu" "znver5")
1718                               (and (eq_attr "type" "sseshuf")
1719                                    (and (eq_attr "mode" "XI")
1720                                     (eq_attr "memory" "none"))))
1721                          "znver4-direct,znver4-fpu1|znver4-fpu2")
1722
1723 (define_insn_reservation "znver4_sse_ishuf_evex_load" 10
1724                          (and (eq_attr "cpu" "znver4")
1725                               (and (eq_attr "type" "sseshuf")
1726                                    (and (eq_attr "mode" "XI")
1727                                     (eq_attr "memory" "load"))))
1728                          "znver4-direct,znver4-load,znver4-fpu1*2|znver4-fpu2*2")
1729
1730 (define_insn_reservation "znver5_sse_ishuf_evex_load" 10
1731                          (and (eq_attr "cpu" "znver5")
1732                               (and (eq_attr "type" "sseshuf")
1733                                    (and (eq_attr "mode" "XI")
1734                                     (eq_attr "memory" "load"))))
1735                          "znver4-direct,znver5-load,znver4-fpu1|znver4-fpu2")
1736
1737 (define_insn_reservation "znver4_sse_muladd" 4
1738                          (and (eq_attr "cpu" "znver4")
1739                               (and (eq_attr "type" "ssemuladd")
1740                                    (eq_attr "memory" "none")))
1741                          "znver4-direct,znver4-fpu0*2|znver4-fpu1*2")
1742
1743 (define_insn_reservation "znver5_sse_muladd" 4
1744                          (and (eq_attr "cpu" "znver5")
1745                               (and (eq_attr "type" "ssemuladd")
1746                                    (eq_attr "memory" "none")))
1747                          "znver4-direct,znver4-fpu0|znver4-fpu1")
1748
1749 (define_insn_reservation "znver4_sse_muladd_load" 10
1750                          (and (eq_attr "cpu" "znver4")
1751                               (and (eq_attr "type" "sseshuf")
1752                                    (eq_attr "memory" "load")))
1753                          "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2")
1754
1755 (define_insn_reservation "znver5_sse_muladd_load" 10
1756                          (and (eq_attr "cpu" "znver5")
1757                               (and (eq_attr "type" "sseshuf")
1758                                    (eq_attr "memory" "load")))
1759                          "znver4-direct,znver5-load,znver4-fpu1|znver4-fpu2")
1760
1761 ;; AVX512 mask instructions
1762
1763 (define_insn_reservation "znver4_sse_mskmov" 2
1764                          (and (eq_attr "cpu" "znver4")
1765                               (and (eq_attr "type" "mskmov")
1766                                    (eq_attr "memory" "none")))
1767                          "znver4-direct,znver4-fpu0*2|znver4-fpu1*2")
1768
1769 (define_insn_reservation "znver5_sse_mskmov" 2
1770                          (and (eq_attr "cpu" "znver5")
1771                               (and (eq_attr "type" "mskmov")
1772                                    (eq_attr "memory" "none")))
1773                          "znver4-direct,znver4-fpu0|znver4-fpu1")
1774
1775 (define_insn_reservation "znver4_sse_msklog" 1
1776                          (and (eq_attr "cpu" "znver4")
1777                               (and (eq_attr "type" "msklog")
1778                                    (eq_attr "memory" "none")))
1779                          "znver4-direct,znver4-fpu2*2|znver4-fpu3*2")
1780
1781 (define_insn_reservation "znver5_sse_msklog" 1
1782                          (and (eq_attr "cpu" "znver5")
1783                               (and (eq_attr "type" "msklog")
1784                                    (eq_attr "memory" "none")))
1785                          "znver4-direct,znver4-fpu0|znver4-fpu3")