| blob | 432b89520d723a16edf8ede81ec6770825f83a72 |
1 ;; Machine description the Motorola MCore
2 ;; Copyright (C) 1993-2024 Free Software Foundation, Inc.
3 ;; Contributed by Motorola.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; -------------------------------------------------------------------------
26 ;; Attributes
27 ;; -------------------------------------------------------------------------
29 ; Target CPU.
31 (define_attr "type" "brcond,branch,jmp,load,store,move,alu,shift"
32 (const_string "alu"))
34 ;; If a branch destination is within -2048..2047 bytes away from the
35 ;; instruction it can be 2 bytes long. All other conditional branches
36 ;; are 10 bytes long, and all other unconditional branches are 8 bytes.
37 ;;
38 ;; the assembler handles the long-branch span case for us if we use
39 ;; the "jb*" mnemonics for jumps/branches. This pushes the span
40 ;; calculations and the literal table placement into the assembler,
41 ;; where their interactions can be managed in a single place.
43 ;; All MCORE instructions are two bytes long.
45 (define_attr "length" "" (const_int 2))
47 ;; Scheduling. We only model a simple load latency.
48 (define_insn_reservation "any_insn" 1
49 (eq_attr "type" "!load")
50 "nothing")
51 (define_insn_reservation "memory" 2
52 (eq_attr "type" "load")
53 "nothing")
55 (include "predicates.md")
56 (include "constraints.md")
58 ;; -------------------------------------------------------------------------
59 ;; Test and bit test
60 ;; -------------------------------------------------------------------------
62 (define_insn ""
63 [(set (reg:SI 17)
64 (sign_extract:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
65 (const_int 1)
66 (match_operand:SI 1 "mcore_literal_K_operand" "K")))]
67 ""
68 "btsti %0,%1"
69 [(set_attr "type" "shift")])
71 (define_insn ""
72 [(set (reg:SI 17)
73 (zero_extract:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
74 (const_int 1)
75 (match_operand:SI 1 "mcore_literal_K_operand" "K")))]
76 ""
77 "btsti %0,%1"
78 [(set_attr "type" "shift")])
80 ;;; This is created by combine.
81 (define_insn ""
82 [(set (reg:CC 17)
83 (ne:CC (zero_extract:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
84 (const_int 1)
85 (match_operand:SI 1 "mcore_literal_K_operand" "K"))
86 (const_int 0)))]
87 ""
88 "btsti %0,%1"
89 [(set_attr "type" "shift")])
92 ;; Created by combine from conditional patterns below (see sextb/btsti rx,31)
94 (define_insn ""
95 [(set (reg:CC 17)
96 (ne:CC (lshiftrt:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
97 (const_int 7))
98 (const_int 0)))]
99 "GET_CODE(operands[0]) == SUBREG &&
100 GET_MODE(SUBREG_REG(operands[0])) == QImode"
101 "btsti %0,7"
102 [(set_attr "type" "shift")])
104 (define_insn ""
105 [(set (reg:CC 17)
106 (ne:CC (lshiftrt:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
107 (const_int 15))
108 (const_int 0)))]
109 "GET_CODE(operands[0]) == SUBREG &&
110 GET_MODE(SUBREG_REG(operands[0])) == HImode"
111 "btsti %0,15"
112 [(set_attr "type" "shift")])
114 (define_split
115 [(set (pc)
116 (if_then_else (ne (eq:CC (zero_extract:SI
117 (match_operand:SI 0 "mcore_arith_reg_operand" "")
118 (const_int 1)
119 (match_operand:SI 1 "mcore_literal_K_operand" ""))
120 (const_int 0))
121 (const_int 0))
122 (label_ref (match_operand 2 "" ""))
123 (pc)))]
124 ""
125 [(set (reg:CC 17)
126 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))
127 (set (pc) (if_then_else (eq (reg:CC 17) (const_int 0))
128 (label_ref (match_dup 2))
129 (pc)))]
130 "")
132 (define_split
133 [(set (pc)
134 (if_then_else (eq (ne:CC (zero_extract:SI
135 (match_operand:SI 0 "mcore_arith_reg_operand" "")
136 (const_int 1)
137 (match_operand:SI 1 "mcore_literal_K_operand" ""))
138 (const_int 0))
139 (const_int 0))
140 (label_ref (match_operand 2 "" ""))
141 (pc)))]
142 ""
143 [(set (reg:CC 17)
144 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))
145 (set (pc) (if_then_else (eq (reg:CC 17) (const_int 0))
146 (label_ref (match_dup 2))
147 (pc)))]
148 "")
150 ;; XXX - disabled by nickc because it fails on libiberty/fnmatch.c
151 ;;
152 ;; ; Experimental - relax immediates for and, andn, or, and tst to allow
153 ;; ; any immediate value (or an immediate at all -- or, andn, & tst).
154 ;; ; This is done to allow bit field masks to fold together in combine.
155 ;; ; The reload phase will force the immediate into a register at the
156 ;; ; very end. This helps in some cases, but hurts in others: we'd
157 ;; ; really like to cse these immediates. However, there is a phase
158 ;; ; ordering problem here. cse picks up individual masks and cse's
159 ;; ; those, but not folded masks (cse happens before combine). It's
160 ;; ; not clear what the best solution is because we really want cse
161 ;; ; before combine (leaving the bit field masks alone). To pick up
162 ;; ; relaxed immediates use -mrelax-immediates. It might take some
163 ;; ; experimenting to see which does better (i.e. regular imms vs.
164 ;; ; arbitrary imms) for a particular code. BRC
165 ;;
166 ;; (define_insn ""
167 ;; [(set (reg:CC 17)
168 ;; (ne:CC (and:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
169 ;; (match_operand:SI 1 "mcore_arith_any_imm_operand" "rI"))
170 ;; (const_int 0)))]
171 ;; "TARGET_RELAX_IMM"
172 ;; "tst %0,%1")
173 ;;
174 ;; (define_insn ""
175 ;; [(set (reg:CC 17)
176 ;; (ne:CC (and:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
177 ;; (match_operand:SI 1 "mcore_arith_M_operand" "r"))
178 ;; (const_int 0)))]
179 ;; "!TARGET_RELAX_IMM"
180 ;; "tst %0,%1")
182 (define_insn ""
183 [(set (reg:CC 17)
184 (ne:CC (and:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
185 (match_operand:SI 1 "mcore_arith_M_operand" "r"))
186 (const_int 0)))]
187 ""
188 "tst %0,%1")
191 (define_split
192 [(parallel[
193 (set (reg:CC 17)
194 (ne:CC (ne:SI (leu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "")
195 (match_operand:SI 1 "mcore_arith_reg_operand" ""))
196 (const_int 0))
197 (const_int 0)))
198 (clobber (match_operand:CC 2 "mcore_arith_reg_operand" ""))])]
199 ""
200 [(set (reg:CC 17) (ne:SI (match_dup 0) (const_int 0)))
201 (set (reg:CC 17) (leu:CC (match_dup 0) (match_dup 1)))])
203 ;; -------------------------------------------------------------------------
204 ;; SImode signed integer comparisons
205 ;; -------------------------------------------------------------------------
207 (define_insn "decne_t"
208 [(set (reg:CC 17) (ne:CC (plus:SI (match_operand:SI 0 "mcore_arith_reg_operand" "+r")
209 (const_int -1))
210 (const_int 0)))
211 (set (match_dup 0)
212 (plus:SI (match_dup 0)
213 (const_int -1)))]
214 ""
215 "decne %0")
217 ;; The combiner seems to prefer the following to the former.
218 ;;
219 (define_insn ""
220 [(set (reg:CC 17) (ne:CC (match_operand:SI 0 "mcore_arith_reg_operand" "+r")
221 (const_int 1)))
222 (set (match_dup 0)
223 (plus:SI (match_dup 0)
224 (const_int -1)))]
225 ""
226 "decne %0")
228 (define_insn "cmpnesi_t"
229 [(set (reg:CC 17) (ne:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
230 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
231 ""
232 "cmpne %0,%1")
234 (define_insn "cmpneisi_t"
235 [(set (reg:CC 17) (ne:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
236 (match_operand:SI 1 "mcore_arith_K_operand" "K")))]
237 ""
238 "cmpnei %0,%1")
240 (define_insn "cmpgtsi_t"
241 [(set (reg:CC 17) (gt:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
242 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
243 ""
244 "cmplt %1,%0")
246 (define_insn ""
247 [(set (reg:CC 17) (gt:CC (plus:SI
248 (match_operand:SI 0 "mcore_arith_reg_operand" "+r")
249 (const_int -1))
250 (const_int 0)))
251 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
252 ""
253 "decgt %0")
255 (define_insn "cmpltsi_t"
256 [(set (reg:CC 17) (lt:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
257 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
258 ""
259 "cmplt %0,%1")
261 ; cmplti is 1-32
262 (define_insn "cmpltisi_t"
263 [(set (reg:CC 17) (lt:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
264 (match_operand:SI 1 "mcore_arith_J_operand" "J")))]
265 ""
266 "cmplti %0,%1")
268 ; covers cmplti x,0
269 (define_insn ""
270 [(set (reg:CC 17) (lt:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
271 (const_int 0)))]
272 ""
273 "btsti %0,31")
275 (define_insn ""
276 [(set (reg:CC 17) (lt:CC (plus:SI
277 (match_operand:SI 0 "mcore_arith_reg_operand" "+r")
278 (const_int -1))
279 (const_int 0)))
280 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
281 ""
282 "declt %0")
284 ;; -------------------------------------------------------------------------
285 ;; SImode unsigned integer comparisons
286 ;; -------------------------------------------------------------------------
288 (define_insn "cmpgeusi_t"
289 [(set (reg:CC 17) (geu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
290 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
291 ""
292 "cmphs %0,%1")
294 (define_insn "cmpgeusi_0"
295 [(set (reg:CC 17) (geu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
296 (const_int 0)))]
297 ""
298 "cmpnei %0, 0")
300 (define_insn "cmpleusi_t"
301 [(set (reg:CC 17) (leu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
302 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
303 ""
304 "cmphs %1,%0")
306 ;; -------------------------------------------------------------------------
307 ;; Logical operations
308 ;; -------------------------------------------------------------------------
310 ;; Logical AND clearing a single bit. andsi3 knows that we have this
311 ;; pattern and allows the constant literal pass through.
312 ;;
314 ;; RBE 2/97: don't need this pattern any longer...
315 ;; RBE: I don't think we need both "S" and exact_log2() clauses.
316 ;;(define_insn ""
317 ;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
318 ;; (and:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
319 ;; (match_operand:SI 2 "const_int_operand" "S")))]
320 ;; "mcore_arith_S_operand (operands[2])"
321 ;; "bclri %0,%Q2")
322 ;;
324 (define_insn "andnsi3"
325 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
326 (and:SI (not:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))
327 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
328 ""
329 "andn %0,%1")
331 (define_expand "andsi3"
332 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
333 (and:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
334 (match_operand:SI 2 "nonmemory_operand" "")))]
335 ""
336 "
337 {
338 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0
339 && ! mcore_arith_S_operand (operands[2]))
340 {
341 HOST_WIDE_INT not_value = ~ INTVAL (operands[2]);
343 if ( CONST_OK_FOR_I (not_value)
344 || CONST_OK_FOR_M (not_value)
345 || CONST_OK_FOR_N (not_value))
346 {
347 operands[2] = copy_to_mode_reg (SImode, GEN_INT (not_value));
348 emit_insn (gen_andnsi3 (operands[0], operands[2], operands[1]));
349 DONE;
350 }
351 }
353 if (! mcore_arith_K_S_operand (operands[2], SImode))
354 operands[2] = copy_to_mode_reg (SImode, operands[2]);
355 }")
357 (define_insn ""
358 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
359 (and:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0,r,0")
360 (match_operand:SI 2 "mcore_arith_any_imm_operand" "r,K,0,S")))]
361 "TARGET_RELAX_IMM"
362 "*
363 {
364 switch (which_alternative)
365 {
366 case 0: return \"and %0,%2\";
367 case 1: return \"andi %0,%2\";
368 case 2: return \"and %0,%1\";
369 /* case -1: return \"bclri %0,%Q2\"; will not happen */
370 case 3: return mcore_output_bclri (operands[0], INTVAL (operands[2]));
371 default: gcc_unreachable ();
372 }
373 }")
375 ;; This was the old "S" which was "!(2^n)" */
376 ;; case -1: return \"bclri %0,%Q2\"; will not happen */
378 (define_insn ""
379 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
380 (and:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0,r,0")
381 (match_operand:SI 2 "mcore_arith_K_S_operand" "r,K,0,S")))]
382 "!TARGET_RELAX_IMM"
383 "*
384 {
385 switch (which_alternative)
386 {
387 case 0: return \"and %0,%2\";
388 case 1: return \"andi %0,%2\";
389 case 2: return \"and %0,%1\";
390 case 3: return mcore_output_bclri (operands[0], INTVAL (operands[2]));
391 default: gcc_unreachable ();
392 }
393 }")
395 ;(define_insn "iorsi3"
396 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
397 ; (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
398 ; (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
399 ; ""
400 ; "or %0,%2")
402 ; need an expand to resolve ambiguity betw. the two iors below.
403 (define_expand "iorsi3"
404 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
405 (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
406 (match_operand:SI 2 "nonmemory_operand" "")))]
407 ""
408 "
409 {
410 if (! mcore_arith_M_operand (operands[2], SImode))
411 operands[2] = copy_to_mode_reg (SImode, operands[2]);
412 }")
414 (define_insn ""
415 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
416 (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0,0,0")
417 (match_operand:SI 2 "mcore_arith_any_imm_operand" "r,M,T")))]
418 "TARGET_RELAX_IMM"
419 "*
420 {
421 switch (which_alternative)
422 {
423 case 0: return \"or %0,%2\";
424 case 1: return \"bseti %0,%P2\";
425 case 2: return mcore_output_bseti (operands[0], INTVAL (operands[2]));
426 default: gcc_unreachable ();
427 }
428 }")
430 (define_insn ""
431 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
432 (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0,0,0")
433 (match_operand:SI 2 "mcore_arith_M_operand" "r,M,T")))]
434 "!TARGET_RELAX_IMM"
435 "*
436 {
437 switch (which_alternative)
438 {
439 case 0: return \"or %0,%2\";
440 case 1: return \"bseti %0,%P2\";
441 case 2: return mcore_output_bseti (operands[0], INTVAL (operands[2]));
442 default: gcc_unreachable ();
443 }
444 }")
446 ;(define_insn ""
447 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
448 ; (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
449 ; (match_operand:SI 2 "const_int_operand" "M")))]
450 ; "exact_log2 (INTVAL (operands[2])) >= 0"
451 ; "bseti %0,%P2")
453 ;(define_insn ""
454 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
455 ; (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
456 ; (match_operand:SI 2 "const_int_operand" "i")))]
457 ; "mcore_num_ones (INTVAL (operands[2])) < 3"
458 ; "* return mcore_output_bseti (operands[0], INTVAL (operands[2]));")
460 (define_insn "xorsi3"
461 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
462 (xor:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
463 (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
464 ""
465 "xor %0,%2")
467 ;; -------------------------------------------------------------------------
468 ;; Shifts and rotates
469 ;; -------------------------------------------------------------------------
471 ;; Only allow these if the shift count is a convenient constant.
472 (define_expand "rotlsi3"
473 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
474 (rotate:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
475 (match_operand:SI 2 "nonmemory_operand" "")))]
476 ""
477 "if (! mcore_literal_K_operand (operands[2], SImode))
478 FAIL;
479 ")
481 ;; We can only do constant rotates, which is what this pattern provides.
482 ;; The combiner will put it together for us when we do:
483 ;; (x << N) | (x >> (32 - N))
484 (define_insn ""
485 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
486 (rotate:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
487 (match_operand:SI 2 "mcore_literal_K_operand" "K")))]
488 ""
489 "rotli %0,%2"
490 [(set_attr "type" "shift")])
492 (define_insn "ashlsi3"
493 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
494 (ashift:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0")
495 (match_operand:SI 2 "mcore_arith_K_operand_not_0" "r,K")))]
496 ""
497 "@
498 lsl %0,%2
499 lsli %0,%2"
500 [(set_attr "type" "shift")])
502 (define_insn ""
503 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
504 (ashift:SI (const_int 1)
505 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
506 ""
507 "bgenr %0,%1"
508 [(set_attr "type" "shift")])
510 (define_insn "ashrsi3"
511 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
512 (ashiftrt:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0")
513 (match_operand:SI 2 "mcore_arith_K_operand_not_0" "r,K")))]
514 ""
515 "@
516 asr %0,%2
517 asri %0,%2"
518 [(set_attr "type" "shift")])
520 (define_insn "lshrsi3"
521 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
522 (lshiftrt:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0")
523 (match_operand:SI 2 "mcore_arith_K_operand_not_0" "r,K")))]
524 ""
525 "@
526 lsr %0,%2
527 lsri %0,%2"
528 [(set_attr "type" "shift")])
530 ;(define_expand "ashldi3"
531 ; [(parallel[(set (match_operand:DI 0 "mcore_arith_reg_operand" "")
532 ; (ashift:DI (match_operand:DI 1 "mcore_arith_reg_operand" "")
533 ; (match_operand:DI 2 "immediate_operand" "")))
534 ;
535 ; (clobber (reg:CC 17))])]
536 ;
537 ; ""
538 ; "
539 ;{
540 ; if (GET_CODE (operands[2]) != CONST_INT
541 ; || INTVAL (operands[2]) != 1)
542 ; FAIL;
543 ;}")
544 ;
545 ;(define_insn ""
546 ; [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=r")
547 ; (ashift:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
548 ; (const_int 1)))
549 ; (clobber (reg:CC 17))]
550 ; ""
551 ; "lsli %R0,0\;rotli %0,0"
552 ; [(set_attr "length" "4") (set_attr "type" "shift")])
554 ;; -------------------------------------------------------------------------
555 ;; Index instructions
556 ;; -------------------------------------------------------------------------
557 ;; The second of each set of patterns is borrowed from the alpha.md file.
558 ;; These variants of the above insns can occur if the second operand
559 ;; is the frame pointer. This is a kludge, but there doesn't
560 ;; seem to be a way around it. Only recognize them while reloading.
562 ;; We must use reload_operand for some operands in case frame pointer
563 ;; elimination put a MEM with invalid address there. Otherwise,
564 ;; the result of the substitution will not match this pattern, and reload
565 ;; will not be able to correctly fix the result.
567 ;; indexing longlongs or doubles (8 bytes)
569 (define_insn "indexdi_t"
570 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
571 (plus:SI (mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
572 (const_int 8))
573 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
574 ""
575 "*
576 if (! mcore_is_same_reg (operands[1], operands[2]))
577 {
578 output_asm_insn (\"ixw\\t%0,%1\", operands);
579 output_asm_insn (\"ixw\\t%0,%1\", operands);
580 }
581 else
582 {
583 output_asm_insn (\"ixh\\t%0,%1\", operands);
584 output_asm_insn (\"ixh\\t%0,%1\", operands);
585 }
586 return \"\";
587 "
588 ;; if operands[1] == operands[2], the first option above is wrong! -- dac
589 ;; was this... -- dac
590 ;; ixw %0,%1\;ixw %0,%1"
592 [(set_attr "length" "4")])
594 (define_insn ""
595 [(set (match_operand:SI 0 "mcore_reload_operand" "=r,r,r")
596 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "mcore_reload_operand" "r,r,r")
597 (const_int 8))
598 (match_operand:SI 2 "mcore_arith_reg_operand" "0,0,0"))
599 (match_operand:SI 3 "mcore_addsub_operand" "r,J,L")))]
600 "reload_in_progress"
601 "@
602 ixw %0,%1\;ixw %0,%1\;addu %0,%3
603 ixw %0,%1\;ixw %0,%1\;addi %0,%3
604 ixw %0,%1\;ixw %0,%1\;subi %0,%M3"
605 [(set_attr "length" "6")])
607 ;; indexing longs (4 bytes)
609 (define_insn "indexsi_t"
610 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
611 (plus:SI (mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
612 (const_int 4))
613 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
614 ""
615 "ixw %0,%1")
617 (define_insn ""
618 [(set (match_operand:SI 0 "mcore_reload_operand" "=r,r,r")
619 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "mcore_reload_operand" "r,r,r")
620 (const_int 4))
621 (match_operand:SI 2 "mcore_arith_reg_operand" "0,0,0"))
622 (match_operand:SI 3 "mcore_addsub_operand" "r,J,L")))]
623 "reload_in_progress"
624 "@
625 ixw %0,%1\;addu %0,%3
626 ixw %0,%1\;addi %0,%3
627 ixw %0,%1\;subi %0,%M3"
628 [(set_attr "length" "4")])
630 ;; indexing shorts (2 bytes)
632 (define_insn "indexhi_t"
633 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
634 (plus:SI (mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
635 (const_int 2))
636 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
637 ""
638 "ixh %0,%1")
640 (define_insn ""
641 [(set (match_operand:SI 0 "mcore_reload_operand" "=r,r,r")
642 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "mcore_reload_operand" "r,r,r")
643 (const_int 2))
644 (match_operand:SI 2 "mcore_arith_reg_operand" "0,0,0"))
645 (match_operand:SI 3 "mcore_addsub_operand" "r,J,L")))]
646 "reload_in_progress"
647 "@
648 ixh %0,%1\;addu %0,%3
649 ixh %0,%1\;addi %0,%3
650 ixh %0,%1\;subi %0,%M3"
651 [(set_attr "length" "4")])
653 ;;
654 ;; Other sizes may be handy for indexing.
655 ;; the tradeoffs to consider when adding these are
656 ;; code size, execution time [vs. mul it is easy to win],
657 ;; and register pressure -- these patterns don't use an extra
658 ;; register to build the offset from the base
659 ;; and whether the compiler will not come up with some other idiom.
660 ;;
662 ;; -------------------------------------------------------------------------
663 ;; Addition, Subtraction instructions
664 ;; -------------------------------------------------------------------------
666 (define_expand "addsi3"
667 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
668 (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
669 (match_operand:SI 2 "nonmemory_operand" "")))]
670 ""
671 "
672 {
673 /* If this is an add to the frame pointer, then accept it as is so
674 that we can later fold in the fp/sp offset from frame pointer
675 elimination. */
676 if (flag_omit_frame_pointer
677 && GET_CODE (operands[1]) == REG
678 && (REGNO (operands[1]) == VIRTUAL_STACK_VARS_REGNUM
679 || REGNO (operands[1]) == FRAME_POINTER_REGNUM))
680 {
681 emit_insn (gen_addsi3_fp (operands[0], operands[1], operands[2]));
682 DONE;
683 }
685 /* Convert adds to subtracts if this makes loading the constant cheaper.
686 But only if we are allowed to generate new pseudos. */
687 if (! (reload_in_progress || reload_completed)
688 && GET_CODE (operands[2]) == CONST_INT
689 && INTVAL (operands[2]) < -32)
690 {
691 HOST_WIDE_INT neg_value = - INTVAL (operands[2]);
693 if ( CONST_OK_FOR_I (neg_value)
694 || CONST_OK_FOR_M (neg_value)
695 || CONST_OK_FOR_N (neg_value))
696 {
697 operands[2] = copy_to_mode_reg (SImode, GEN_INT (neg_value));
698 emit_insn (gen_subsi3 (operands[0], operands[1], operands[2]));
699 DONE;
700 }
701 }
703 if (! mcore_addsub_operand (operands[2], SImode))
704 operands[2] = copy_to_mode_reg (SImode, operands[2]);
705 }")
707 ;; RBE: for some constants which are not in the range which allows
708 ;; us to do a single operation, we will try a paired addi/addi instead
709 ;; of a movi/addi. This relieves some register pressure at the expense
710 ;; of giving away some potential constant reuse.
711 ;;
712 ;; RBE 6/17/97: this didn't buy us anything, but I keep the pattern
713 ;; for later reference
714 ;;
715 ;; (define_insn "addsi3_i2"
716 ;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
717 ;; (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
718 ;; (match_operand:SI 2 "const_int_operand" "g")))]
719 ;; "GET_CODE(operands[2]) == CONST_INT
720 ;; && ((INTVAL (operands[2]) > 32 && INTVAL(operands[2]) <= 64)
721 ;; || (INTVAL (operands[2]) < -32 && INTVAL(operands[2]) >= -64))"
722 ;; "*
723 ;; {
724 ;; HOST_WIDE_INT n = INTVAL(operands[2]);
725 ;; if (n > 0)
726 ;; {
727 ;; operands[2] = GEN_INT(n - 32);
728 ;; return \"addi\\t%0,32\;addi\\t%0,%2\";
729 ;; }
730 ;; else
731 ;; {
732 ;; n = (-n);
733 ;; operands[2] = GEN_INT(n - 32);
734 ;; return \"subi\\t%0,32\;subi\\t%0,%2\";
735 ;; }
736 ;; }"
737 ;; [(set_attr "length" "4")])
739 (define_insn "addsi3_i"
740 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
741 (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0,0,0")
742 (match_operand:SI 2 "mcore_addsub_operand" "r,J,L")))]
743 ""
744 "@
745 addu %0,%2
746 addi %0,%2
747 subi %0,%M2")
749 ;; This exists so that address computations based on the frame pointer
750 ;; can be folded in when frame pointer elimination occurs. Ordinarily
751 ;; this would be bad because it allows insns which would require reloading,
752 ;; but without it, we get multiple adds where one would do.
754 (define_insn "addsi3_fp"
755 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
756 (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0,0,0")
757 (match_operand:SI 2 "immediate_operand" "r,J,L")))]
758 "flag_omit_frame_pointer
759 && (reload_in_progress || reload_completed || REGNO (operands[1]) == FRAME_POINTER_REGNUM)"
760 "@
761 addu %0,%2
762 addi %0,%2
763 subi %0,%M2")
765 ;; RBE: for some constants which are not in the range which allows
766 ;; us to do a single operation, we will try a paired addi/addi instead
767 ;; of a movi/addi. This relieves some register pressure at the expense
768 ;; of giving away some potential constant reuse.
769 ;;
770 ;; RBE 6/17/97: this didn't buy us anything, but I keep the pattern
771 ;; for later reference
772 ;;
773 ;; (define_insn "subsi3_i2"
774 ;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
775 ;; (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
776 ;; (match_operand:SI 2 "const_int_operand" "g")))]
777 ;; "TARGET_RBETEST && GET_CODE(operands[2]) == CONST_INT
778 ;; && ((INTVAL (operands[2]) > 32 && INTVAL(operands[2]) <= 64)
779 ;; || (INTVAL (operands[2]) < -32 && INTVAL(operands[2]) >= -64))"
780 ;; "*
781 ;; {
782 ;; HOST_WIDE_INT n = INTVAL(operands[2]);
783 ;; if ( n > 0)
784 ;; {
785 ;; operands[2] = GEN_INT( n - 32);
786 ;; return \"subi\\t%0,32\;subi\\t%0,%2\";
787 ;; }
788 ;; else
789 ;; {
790 ;; n = (-n);
791 ;; operands[2] = GEN_INT(n - 32);
792 ;; return \"addi\\t%0,32\;addi\\t%0,%2\";
793 ;; }
794 ;; }"
795 ;; [(set_attr "length" "4")])
797 ;(define_insn "subsi3"
798 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
799 ; (minus:SI (match_operand:SI 1 "mcore_arith_K_operand" "0,0,r,K")
800 ; (match_operand:SI 2 "mcore_arith_J_operand" "r,J,0,0")))]
801 ; ""
802 ; "@
803 ; sub %0,%2
804 ; subi %0,%2
805 ; rsub %0,%1
806 ; rsubi %0,%1")
808 (define_insn "subsi3"
809 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
810 (minus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0,r")
811 (match_operand:SI 2 "mcore_arith_J_operand" "r,J,0")))]
812 ""
813 "@
814 subu %0,%2
815 subi %0,%2
816 rsub %0,%1")
818 (define_insn ""
819 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
820 (minus:SI (match_operand:SI 1 "mcore_literal_K_operand" "K")
821 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
822 ""
823 "rsubi %0,%1")
825 (define_insn "adddi3"
826 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
827 (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
828 (match_operand:DI 2 "mcore_arith_reg_operand" "r")))
829 (clobber (reg:CC 17))]
830 ""
831 "*
832 {
833 if (TARGET_LITTLE_END)
834 return \"cmplt %0,%0\;addc %0,%2\;addc %R0,%R2\";
835 return \"cmplt %R0,%R0\;addc %R0,%R2\;addc %0,%2\";
836 }"
837 [(set_attr "length" "6")])
839 ;; special case for "longlong += 1"
840 (define_insn ""
841 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
842 (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
843 (const_int 1)))
844 (clobber (reg:CC 17))]
845 ""
846 "*
847 {
848 if (TARGET_LITTLE_END)
849 return \"addi %0,1\;cmpnei %0,0\;incf %R0\";
850 return \"addi %R0,1\;cmpnei %R0,0\;incf %0\";
851 }"
852 [(set_attr "length" "6")])
854 ;; special case for "longlong -= 1"
855 (define_insn ""
856 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
857 (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
858 (const_int -1)))
859 (clobber (reg:CC 17))]
860 ""
861 "*
862 {
863 if (TARGET_LITTLE_END)
864 return \"cmpnei %0,0\;decf %R0\;subi %0,1\";
865 return \"cmpnei %R0,0\;decf %0\;subi %R0,1\";
866 }"
867 [(set_attr "length" "6")])
869 ;; special case for "longlong += const_int"
870 ;; we have to use a register for the const_int because we don't
871 ;; have an unsigned compare immediate... only +/- 1 get to
872 ;; play the no-extra register game because they compare with 0.
873 ;; This winds up working out for any literal that is synthesized
874 ;; with a single instruction. The more complicated ones look
875 ;; like the get broken into subreg's to get initialized too soon
876 ;; for us to catch here. -- RBE 4/25/96
877 ;; only allow for-sure positive values.
879 (define_insn ""
880 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
881 (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
882 (match_operand:SI 2 "const_int_operand" "r")))
883 (clobber (reg:CC 17))]
884 "GET_CODE (operands[2]) == CONST_INT
885 && INTVAL (operands[2]) > 0 && ! (INTVAL (operands[2]) & 0x80000000)"
886 "*
887 {
888 gcc_assert (GET_MODE (operands[2]) == SImode);
889 if (TARGET_LITTLE_END)
890 return \"addu %0,%2\;cmphs %0,%2\;incf %R0\";
891 return \"addu %R0,%2\;cmphs %R0,%2\;incf %0\";
892 }"
893 [(set_attr "length" "6")])
895 ;; optimize "long long" + "unsigned long"
896 ;; won't trigger because of how the extension is expanded upstream.
897 ;; (define_insn ""
898 ;; [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
899 ;; (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
900 ;; (zero_extend:DI (match_operand:SI 2 "mcore_arith_reg_operand" "r"))))
901 ;; (clobber (reg:CC 17))]
902 ;; "0"
903 ;; "cmplt %R0,%R0\;addc %R0,%2\;inct %0"
904 ;; [(set_attr "length" "6")])
906 ;; optimize "long long" + "signed long"
907 ;; won't trigger because of how the extension is expanded upstream.
908 ;; (define_insn ""
909 ;; [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
910 ;; (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
911 ;; (sign_extend:DI (match_operand:SI 2 "mcore_arith_reg_operand" "r"))))
912 ;; (clobber (reg:CC 17))]
913 ;; "0"
914 ;; "cmplt %R0,%R0\;addc %R0,%2\;inct %0\;btsti %2,31\;dect %0"
915 ;; [(set_attr "length" "6")])
917 (define_insn "subdi3"
918 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
919 (minus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
920 (match_operand:DI 2 "mcore_arith_reg_operand" "r")))
921 (clobber (reg:CC 17))]
922 ""
923 "*
924 {
925 if (TARGET_LITTLE_END)
926 return \"cmphs %0,%0\;subc %0,%2\;subc %R0,%R2\";
927 return \"cmphs %R0,%R0\;subc %R0,%R2\;subc %0,%2\";
928 }"
929 [(set_attr "length" "6")])
931 ;; -------------------------------------------------------------------------
932 ;; Multiplication instructions
933 ;; -------------------------------------------------------------------------
935 (define_insn "mulsi3"
936 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
937 (mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
938 (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
939 ""
940 "mult %0,%2")
942 ;;
943 ;; 32/32 signed division -- added to the MCORE instruction set spring 1997
944 ;;
945 ;; Different constraints based on the architecture revision...
946 ;;
947 (define_expand "divsi3"
948 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
949 (div:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
950 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
951 "TARGET_DIV"
952 "")
954 ;; MCORE Revision 1.50: restricts the divisor to be in r1. (6/97)
955 ;;
956 (define_insn ""
957 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
958 (div:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
959 (match_operand:SI 2 "mcore_arith_reg_operand" "b")))]
960 "TARGET_DIV"
961 "divs %0,%2")
963 ;;
964 ;; 32/32 signed division -- added to the MCORE instruction set spring 1997
965 ;;
966 ;; Different constraints based on the architecture revision...
967 ;;
968 (define_expand "udivsi3"
969 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
970 (udiv:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
971 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
972 "TARGET_DIV"
973 "")
975 ;; MCORE Revision 1.50: restricts the divisor to be in r1. (6/97)
976 (define_insn ""
977 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
978 (udiv:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
979 (match_operand:SI 2 "mcore_arith_reg_operand" "b")))]
980 "TARGET_DIV"
981 "divu %0,%2")
983 ;; -------------------------------------------------------------------------
984 ;; Unary arithmetic
985 ;; -------------------------------------------------------------------------
987 (define_insn "negsi2"
988 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
989 (neg:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
990 ""
991 "*
992 {
993 return \"rsubi %0,0\";
994 }")
997 (define_insn "abssi2"
998 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
999 (abs:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
1000 ""
1001 "abs %0")
1003 (define_insn "negdi2"
1004 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
1005 (neg:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")))
1006 (clobber (reg:CC 17))]
1007 ""
1008 "*
1009 {
1010 if (TARGET_LITTLE_END)
1011 return \"cmpnei %0,0\\n\\trsubi %0,0\\n\\tnot %R0\\n\\tincf %R0\";
1012 return \"cmpnei %R0,0\\n\\trsubi %R0,0\\n\\tnot %0\\n\\tincf %0\";
1013 }"
1014 [(set_attr "length" "8")])
1016 (define_insn "one_cmplsi2"
1017 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1018 (not:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
1019 ""
1020 "not %0")
1022 ;; -------------------------------------------------------------------------
1023 ;; Zero extension instructions
1024 ;; -------------------------------------------------------------------------
1026 (define_expand "zero_extendhisi2"
1027 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1028 (zero_extend:SI (match_operand:HI 1 "mcore_arith_reg_operand" "")))]
1029 ""
1030 "")
1032 (define_insn ""
1033 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
1034 (zero_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
1035 ""
1036 "@
1037 zexth %0
1038 ld.h %0,%1"
1039 [(set_attr "type" "shift,load")])
1041 ;; ldh gives us a free zero-extension. The combiner picks up on this.
1042 (define_insn ""
1043 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1044 (zero_extend:SI (mem:HI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))))]
1045 ""
1046 "ld.h %0,(%1)"
1047 [(set_attr "type" "load")])
1049 (define_insn ""
1050 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1051 (zero_extend:SI (mem:HI (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
1052 (match_operand:SI 2 "const_int_operand" "")))))]
1053 "(INTVAL (operands[2]) >= 0) &&
1054 (INTVAL (operands[2]) < 32) &&
1055 ((INTVAL (operands[2])&1) == 0)"
1056 "ld.h %0,(%1,%2)"
1057 [(set_attr "type" "load")])
1059 (define_expand "zero_extendqisi2"
1060 [(parallel [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1061 (zero_extend:SI (match_operand:QI 1 "general_operand" "")))
1062 (clobber (reg:CC 17))])]
1063 ""
1064 "")
1066 ;; RBE: XXX: we don't recognize that the xtrb3 kills the CC register.
1067 (define_insn ""
1068 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b,r")
1069 (zero_extend:SI (match_operand:QI 1 "general_operand" "0,r,m")))
1070 (clobber (reg:CC 17))]
1071 ""
1072 "@
1073 zextb %0
1074 xtrb3 %0,%1
1075 ld.b %0,%1"
1076 [(set_attr "type" "shift,shift,load")])
1078 ;; ldb gives us a free zero-extension. The combiner picks up on this.
1079 (define_insn ""
1080 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1081 (zero_extend:SI (mem:QI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))))]
1082 ""
1083 "ld.b %0,(%1)"
1084 [(set_attr "type" "load")])
1086 (define_insn ""
1087 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1088 (zero_extend:SI (mem:QI (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
1089 (match_operand:SI 2 "const_int_operand" "")))))]
1090 "(INTVAL (operands[2]) >= 0) &&
1091 (INTVAL (operands[2]) < 16)"
1092 "ld.b %0,(%1,%2)"
1093 [(set_attr "type" "load")])
1095 (define_expand "zero_extendqihi2"
1096 [(parallel [(set (match_operand:HI 0 "mcore_arith_reg_operand" "")
1097 (zero_extend:HI (match_operand:QI 1 "general_operand" "")))
1098 (clobber (reg:CC 17))])]
1099 ""
1100 "")
1102 ;; RBE: XXX: we don't recognize that the xtrb3 kills the CC register.
1103 (define_insn ""
1104 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r,b,r")
1105 (zero_extend:HI (match_operand:QI 1 "general_operand" "0,r,m")))
1106 (clobber (reg:CC 17))]
1107 ""
1108 "@
1109 zextb %0
1110 xtrb3 %0,%1
1111 ld.b %0,%1"
1112 [(set_attr "type" "shift,shift,load")])
1114 ;; ldb gives us a free zero-extension. The combiner picks up on this.
1115 ;; this doesn't catch references that are into a structure.
1116 ;; note that normally the compiler uses the above insn, unless it turns
1117 ;; out that we're dealing with a volatile...
1118 (define_insn ""
1119 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
1120 (zero_extend:HI (mem:QI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))))]
1121 ""
1122 "ld.b %0,(%1)"
1123 [(set_attr "type" "load")])
1125 (define_insn ""
1126 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
1127 (zero_extend:HI (mem:QI (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
1128 (match_operand:SI 2 "const_int_operand" "")))))]
1129 "(INTVAL (operands[2]) >= 0) &&
1130 (INTVAL (operands[2]) < 16)"
1131 "ld.b %0,(%1,%2)"
1132 [(set_attr "type" "load")])
1135 ;; -------------------------------------------------------------------------
1136 ;; Sign extension instructions
1137 ;; -------------------------------------------------------------------------
1139 (define_expand "extendsidi2"
1140 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=r")
1141 (match_operand:SI 1 "mcore_arith_reg_operand" "r"))]
1142 ""
1143 "
1144 {
1145 int low, high;
1147 if (TARGET_LITTLE_END)
1148 low = 0, high = 4;
1149 else
1150 low = 4, high = 0;
1152 emit_insn (gen_rtx_SET (gen_rtx_SUBREG (SImode, operands[0], low),
1153 operands[1]));
1154 emit_insn (gen_rtx_SET (gen_rtx_SUBREG (SImode, operands[0], high),
1155 gen_rtx_ASHIFTRT (SImode,
1156 gen_rtx_SUBREG (SImode, operands[0], low),
1157 GEN_INT (31))));
1158 DONE;
1159 }"
1160 )
1162 (define_insn "extendhisi2"
1163 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1164 (sign_extend:SI (match_operand:HI 1 "mcore_arith_reg_operand" "0")))]
1165 ""
1166 "sexth %0")
1168 (define_insn "extendqisi2"
1169 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1170 (sign_extend:SI (match_operand:QI 1 "mcore_arith_reg_operand" "0")))]
1171 ""
1172 "sextb %0")
1174 (define_insn "extendqihi2"
1175 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
1176 (sign_extend:HI (match_operand:QI 1 "mcore_arith_reg_operand" "0")))]
1177 ""
1178 "sextb %0")
1180 ;; -------------------------------------------------------------------------
1181 ;; Move instructions
1182 ;; -------------------------------------------------------------------------
1184 ;; SImode
1186 (define_expand "movsi"
1187 [(set (match_operand:SI 0 "general_operand" "")
1188 (match_operand:SI 1 "general_operand" ""))]
1189 ""
1190 "
1191 {
1192 if (GET_CODE (operands[0]) == MEM)
1193 operands[1] = force_reg (SImode, operands[1]);
1194 }")
1196 (define_insn ""
1197 [(set (match_operand:SI 0 "mcore_general_movdst_operand" "=r,r,a,r,a,r,m")
1198 (match_operand:SI 1 "mcore_general_movsrc_operand" "r,P,i,c,R,m,r"))]
1199 "(register_operand (operands[0], SImode)
1200 || register_operand (operands[1], SImode))"
1201 "* return mcore_output_move (insn, operands, SImode);"
1202 [(set_attr "type" "move,move,move,move,load,load,store")])
1204 ;;
1205 ;; HImode
1206 ;;
1208 (define_expand "movhi"
1209 [(set (match_operand:HI 0 "general_operand" "")
1210 (match_operand:HI 1 "general_operand" ""))]
1211 ""
1212 "
1213 {
1214 if (GET_CODE (operands[0]) == MEM)
1215 operands[1] = force_reg (HImode, operands[1]);
1216 else if (CONSTANT_P (operands[1])
1217 && (GET_CODE (operands[1]) != CONST_INT
1218 || (! CONST_OK_FOR_I (INTVAL (operands[1]))
1219 && ! CONST_OK_FOR_M (INTVAL (operands[1]))
1220 && ! CONST_OK_FOR_N (INTVAL (operands[1]))))
1221 && ! reload_completed && ! reload_in_progress)
1222 {
1223 rtx reg = gen_reg_rtx (SImode);
1224 emit_insn (gen_movsi (reg, operands[1]));
1225 operands[1] = gen_lowpart (HImode, reg);
1226 }
1227 }")
1229 (define_insn ""
1230 [(set (match_operand:HI 0 "mcore_general_movdst_operand" "=r,r,a,r,r,m")
1231 (match_operand:HI 1 "mcore_general_movsrc_operand" "r,P,i,c,m,r"))]
1232 "(register_operand (operands[0], HImode)
1233 || register_operand (operands[1], HImode))"
1234 "* return mcore_output_move (insn, operands, HImode);"
1235 [(set_attr "type" "move,move,move,move,load,store")])
1237 ;;
1238 ;; QImode
1239 ;;
1241 (define_expand "movqi"
1242 [(set (match_operand:QI 0 "general_operand" "")
1243 (match_operand:QI 1 "general_operand" ""))]
1244 ""
1245 "
1246 {
1247 if (GET_CODE (operands[0]) == MEM)
1248 operands[1] = force_reg (QImode, operands[1]);
1249 else if (CONSTANT_P (operands[1])
1250 && (GET_CODE (operands[1]) != CONST_INT
1251 || (! CONST_OK_FOR_I (INTVAL (operands[1]))
1252 && ! CONST_OK_FOR_M (INTVAL (operands[1]))
1253 && ! CONST_OK_FOR_N (INTVAL (operands[1]))))
1254 && ! reload_completed && ! reload_in_progress)
1255 {
1256 rtx reg = gen_reg_rtx (SImode);
1257 emit_insn (gen_movsi (reg, operands[1]));
1258 operands[1] = gen_lowpart (QImode, reg);
1259 }
1260 }")
1262 (define_insn ""
1263 [(set (match_operand:QI 0 "mcore_general_movdst_operand" "=r,r,a,r,r,m")
1264 (match_operand:QI 1 "mcore_general_movsrc_operand" "r,P,i,c,m,r"))]
1265 "(register_operand (operands[0], QImode)
1266 || register_operand (operands[1], QImode))"
1267 "* return mcore_output_move (insn, operands, QImode);"
1268 [(set_attr "type" "move,move,move,move,load,store")])
1271 ;; DImode
1273 (define_expand "movdi"
1274 [(set (match_operand:DI 0 "general_operand" "")
1275 (match_operand:DI 1 "general_operand" ""))]
1276 ""
1277 "
1278 {
1279 if (GET_CODE (operands[0]) == MEM)
1280 operands[1] = force_reg (DImode, operands[1]);
1281 else if (GET_CODE (operands[1]) == CONST_INT
1282 && ! CONST_OK_FOR_I (INTVAL (operands[1]))
1283 && ! CONST_OK_FOR_M (INTVAL (operands[1]))
1284 && ! CONST_OK_FOR_N (INTVAL (operands[1])))
1285 {
1286 int i;
1287 for (i = 0; i < UNITS_PER_WORD * 2; i += UNITS_PER_WORD)
1288 emit_move_insn (simplify_gen_subreg (SImode, operands[0], DImode, i),
1289 simplify_gen_subreg (SImode, operands[1], DImode, i));
1290 DONE;
1291 }
1292 }")
1294 (define_insn "movdi_i"
1295 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,a,r,m")
1296 (match_operand:DI 1 "mcore_general_movsrc_operand" "I,M,N,r,R,m,r"))]
1297 ""
1298 "* return mcore_output_movedouble (operands, DImode);"
1299 [(set_attr "length" "4") (set_attr "type" "move,move,move,move,load,load,store")])
1301 ;; SFmode
1303 (define_expand "movsf"
1304 [(set (match_operand:SF 0 "general_operand" "")
1305 (match_operand:SF 1 "general_operand" ""))]
1306 ""
1307 "
1308 {
1309 if (GET_CODE (operands[0]) == MEM)
1310 operands[1] = force_reg (SFmode, operands[1]);
1311 }")
1313 (define_insn "movsf_i"
1314 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
1315 (match_operand:SF 1 "general_operand" "r,m,r"))]
1316 ""
1317 "@
1318 mov %0,%1
1319 ld.w %0,%1
1320 st.w %1,%0"
1321 [(set_attr "type" "move,load,store")])
1323 ;; DFmode
1325 (define_expand "movdf"
1326 [(set (match_operand:DF 0 "general_operand" "")
1327 (match_operand:DF 1 "general_operand" ""))]
1328 ""
1329 "
1330 {
1331 if (GET_CODE (operands[0]) == MEM)
1332 operands[1] = force_reg (DFmode, operands[1]);
1333 }")
1335 (define_insn "movdf_k"
1336 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
1337 (match_operand:DF 1 "general_operand" "r,m,r"))]
1338 ""
1339 "* return mcore_output_movedouble (operands, DFmode);"
1340 [(set_attr "length" "4") (set_attr "type" "move,load,store")])
1343 ;; Load/store multiple
1345 ;; ??? This is not currently used.
1346 (define_insn "ldm"
1347 [(set (match_operand:TI 0 "mcore_arith_reg_operand" "=r")
1348 (mem:TI (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
1349 ""
1350 "ldq %U0,(%1)")
1352 ;; ??? This is not currently used.
1353 (define_insn "stm"
1354 [(set (mem:TI (match_operand:SI 0 "mcore_arith_reg_operand" "r"))
1355 (match_operand:TI 1 "mcore_arith_reg_operand" "r"))]
1356 ""
1357 "stq %U1,(%0)")
1359 (define_expand "load_multiple"
1360 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
1361 (match_operand:SI 1 "" ""))
1362 (use (match_operand:SI 2 "" ""))])]
1363 ""
1364 "
1365 {
1366 int regno, count, i;
1368 /* Support only loading a constant number of registers from memory and
1369 only if at least two registers. The last register must be r15. */
1370 if (GET_CODE (operands[2]) != CONST_INT
1371 || INTVAL (operands[2]) < 2
1372 || GET_CODE (operands[1]) != MEM
1373 || XEXP (operands[1], 0) != stack_pointer_rtx
1374 || GET_CODE (operands[0]) != REG
1375 || REGNO (operands[0]) + INTVAL (operands[2]) != 16)
1376 FAIL;
1378 count = INTVAL (operands[2]);
1379 regno = REGNO (operands[0]);
1381 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1383 for (i = 0; i < count; i++)
1384 XVECEXP (operands[3], 0, i)
1385 = gen_rtx_SET (gen_rtx_REG (SImode, regno + i),
1386 gen_rtx_MEM (SImode, plus_constant (Pmode, stack_pointer_rtx,
1387 i * 4)));
1388 }")
1390 (define_insn ""
1391 [(match_parallel 0 "mcore_load_multiple_operation"
1392 [(set (match_operand:SI 1 "mcore_arith_reg_operand" "=r")
1393 (mem:SI (match_operand:SI 2 "register_operand" "r")))])]
1394 "GET_CODE (operands[2]) == REG && REGNO (operands[2]) == STACK_POINTER_REGNUM"
1395 "ldm %1-r15,(%2)")
1397 (define_expand "store_multiple"
1398 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
1399 (match_operand:SI 1 "" ""))
1400 (use (match_operand:SI 2 "" ""))])]
1401 ""
1402 "
1403 {
1404 int regno, count, i;
1406 /* Support only storing a constant number of registers to memory and
1407 only if at least two registers. The last register must be r15. */
1408 if (GET_CODE (operands[2]) != CONST_INT
1409 || INTVAL (operands[2]) < 2
1410 || GET_CODE (operands[0]) != MEM
1411 || XEXP (operands[0], 0) != stack_pointer_rtx
1412 || GET_CODE (operands[1]) != REG
1413 || REGNO (operands[1]) + INTVAL (operands[2]) != 16)
1414 FAIL;
1416 count = INTVAL (operands[2]);
1417 regno = REGNO (operands[1]);
1419 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1421 for (i = 0; i < count; i++)
1422 XVECEXP (operands[3], 0, i)
1423 = gen_rtx_SET (
1424 gen_rtx_MEM (SImode, plus_constant (Pmode, stack_pointer_rtx,
1425 i * 4)),
1426 gen_rtx_REG (SImode, regno + i));
1427 }")
1429 (define_insn ""
1430 [(match_parallel 0 "mcore_store_multiple_operation"
1431 [(set (mem:SI (match_operand:SI 2 "register_operand" "r"))
1432 (match_operand:SI 1 "mcore_arith_reg_operand" "r"))])]
1433 "GET_CODE (operands[2]) == REG && REGNO (operands[2]) == STACK_POINTER_REGNUM"
1434 "stm %1-r15,(%2)")
1436 ;; ------------------------------------------------------------------------
1437 ;; Define the real conditional branch instructions.
1438 ;; ------------------------------------------------------------------------
1440 ;; At top-level, condition test are eq/ne, because we
1441 ;; are comparing against the condition register (which
1442 ;; has the result of the true relational test
1444 (define_insn "branch_true"
1445 [(set (pc) (if_then_else (ne (reg:CC 17) (const_int 0))
1446 (label_ref (match_operand 0 "" ""))
1447 (pc)))]
1448 ""
1449 "jbt %l0"
1450 [(set_attr "type" "brcond")])
1452 (define_insn "branch_false"
1453 [(set (pc) (if_then_else (eq (reg:CC 17) (const_int 0))
1454 (label_ref (match_operand 0 "" ""))
1455 (pc)))]
1456 ""
1457 "jbf %l0"
1458 [(set_attr "type" "brcond")])
1460 (define_insn "inverse_branch_true"
1461 [(set (pc) (if_then_else (ne (reg:CC 17) (const_int 0))
1462 (pc)
1463 (label_ref (match_operand 0 "" ""))))]
1464 ""
1465 "jbf %l0"
1466 [(set_attr "type" "brcond")])
1468 (define_insn "inverse_branch_false"
1469 [(set (pc) (if_then_else (eq (reg:CC 17) (const_int 0))
1470 (pc)
1471 (label_ref (match_operand 0 "" ""))))]
1472 ""
1473 "jbt %l0"
1474 [(set_attr "type" "brcond")])
1476 ;; Conditional branch insns
1478 (define_expand "cbranchsi4"
1479 [(set (pc)
1480 (if_then_else (match_operator 0 "ordered_comparison_operator"
1481 [(match_operand:SI 1 "mcore_compare_operand")
1482 (match_operand:SI 2 "nonmemory_operand")])
1483 (label_ref (match_operand 3 ""))
1484 (pc)))]
1485 ""
1486 "
1487 {
1488 bool invert;
1489 invert = mcore_gen_compare (GET_CODE (operands[0]),
1490 operands[1], operands[2]);
1492 if (invert)
1493 emit_jump_insn (gen_branch_false (operands[3]));
1494 else
1495 emit_jump_insn (gen_branch_true (operands[3]));
1496 DONE;
1497 }")
1501 ;; ------------------------------------------------------------------------
1502 ;; Jump and linkage insns
1503 ;; ------------------------------------------------------------------------
1505 (define_insn "jump_real"
1506 [(set (pc)
1507 (label_ref (match_operand 0 "" "")))]
1508 ""
1509 "jbr %l0"
1510 [(set_attr "type" "branch")])
1512 (define_expand "jump"
1513 [(set (pc) (label_ref (match_operand 0 "" "")))]
1514 ""
1515 "
1516 {
1517 emit_jump_insn (gen_jump_real (operand0));
1518 DONE;
1519 }
1520 ")
1522 (define_insn "indirect_jump"
1523 [(set (pc)
1524 (match_operand:SI 0 "mcore_arith_reg_operand" "r"))]
1525 ""
1526 "jmp %0"
1527 [(set_attr "type" "jmp")])
1529 (define_expand "call"
1530 [(parallel[(call (match_operand:SI 0 "" "")
1531 (match_operand 1 "" ""))
1532 (clobber (reg:SI 15))])]
1533 ""
1534 "
1535 {
1536 if (GET_CODE (operands[0]) == MEM
1537 && ! register_operand (XEXP (operands[0], 0), SImode)
1538 && ! mcore_symbolic_address_p (XEXP (operands[0], 0)))
1539 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1540 force_reg (Pmode, XEXP (operands[0], 0)));
1541 }")
1543 (define_insn "call_internal"
1544 [(call (mem:SI (match_operand:SI 0 "mcore_call_address_operand" "riR"))
1545 (match_operand 1 "" ""))
1546 (clobber (reg:SI 15))]
1547 ""
1548 "* return mcore_output_call (operands, 0);")
1550 (define_expand "call_value"
1551 [(parallel[(set (match_operand 0 "register_operand" "")
1552 (call (match_operand:SI 1 "" "")
1553 (match_operand 2 "" "")))
1554 (clobber (reg:SI 15))])]
1555 ""
1556 "
1557 {
1558 if (GET_CODE (operands[0]) == MEM
1559 && ! register_operand (XEXP (operands[0], 0), SImode)
1560 && ! mcore_symbolic_address_p (XEXP (operands[0], 0)))
1561 operands[1] = gen_rtx_MEM (GET_MODE (operands[1]),
1562 force_reg (Pmode, XEXP (operands[1], 0)));
1563 }")
1565 (define_insn "call_value_internal"
1566 [(set (match_operand 0 "register_operand" "=r")
1567 (call (mem:SI (match_operand:SI 1 "mcore_call_address_operand" "riR"))
1568 (match_operand 2 "" "")))
1569 (clobber (reg:SI 15))]
1570 ""
1571 "* return mcore_output_call (operands, 1);")
1573 (define_insn "call_value_struct"
1574 [(parallel [(set (match_parallel 0 ""
1575 [(expr_list (match_operand 3 "register_operand" "") (match_operand 4 "immediate_operand" ""))
1576 (expr_list (match_operand 5 "register_operand" "") (match_operand 6 "immediate_operand" ""))])
1577 (call (match_operand:SI 1 "" "")
1578 (match_operand 2 "" "")))
1579 (clobber (reg:SI 15))])]
1580 ""
1581 "* return mcore_output_call (operands, 1);"
1582 )
1585 ;; ------------------------------------------------------------------------
1586 ;; Misc insns
1587 ;; ------------------------------------------------------------------------
1589 (define_insn "nop"
1590 [(const_int 0)]
1591 ""
1592 "or r0,r0")
1594 (define_insn "tablejump"
1595 [(set (pc)
1596 (match_operand:SI 0 "mcore_arith_reg_operand" "r"))
1597 (use (label_ref (match_operand 1 "" "")))]
1598 ""
1599 "jmp %0"
1600 [(set_attr "type" "jmp")])
1602 (define_insn "*return"
1603 [(return)]
1604 "reload_completed && ! mcore_naked_function_p ()"
1605 "jmp r15"
1606 [(set_attr "type" "jmp")])
1608 (define_insn "*no_return"
1609 [(return)]
1610 "reload_completed && mcore_naked_function_p ()"
1611 ""
1612 [(set_attr "length" "0")]
1613 )
1615 (define_expand "prologue"
1616 [(const_int 0)]
1617 ""
1618 "mcore_expand_prolog (); DONE;")
1620 (define_expand "epilogue"
1621 [(return)]
1622 ""
1623 "mcore_expand_epilog ();")
1625 ;; ------------------------------------------------------------------------
1626 ;; Scc instructions
1627 ;; ------------------------------------------------------------------------
1629 (define_insn "mvc"
1630 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1631 (ne:SI (reg:CC 17) (const_int 0)))]
1632 ""
1633 "mvc %0"
1634 [(set_attr "type" "move")])
1636 (define_insn "mvcv"
1637 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1638 (eq:SI (reg:CC 17) (const_int 0)))]
1639 ""
1640 "mvcv %0"
1641 [(set_attr "type" "move")])
1643 ; in 0.97 use (LE 0) with (LT 1) and complement c. BRC
1644 (define_split
1645 [(parallel[
1646 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1647 (ne:SI (gt:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
1648 (const_int 0))
1649 (const_int 0)))
1650 (clobber (reg:SI 17))])]
1651 ""
1652 [(set (reg:CC 17)
1653 (lt:CC (match_dup 1) (const_int 1)))
1654 (set (match_dup 0) (eq:SI (reg:CC 17) (const_int 0)))])
1657 (define_expand "cstoresi4"
1658 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1659 (match_operator:SI 1 "ordered_comparison_operator"
1660 [(match_operand:SI 2 "mcore_compare_operand" "")
1661 (match_operand:SI 3 "nonmemory_operand" "")]))]
1662 ""
1663 "
1664 {
1665 bool invert;
1666 invert = mcore_gen_compare (GET_CODE (operands[1]),
1667 operands[2], operands[3]);
1669 if (invert)
1670 emit_insn (gen_mvcv (operands[0]));
1671 else
1672 emit_insn (gen_mvc (operands[0]));
1673 DONE;
1674 }")
1676 (define_insn "incscc"
1677 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1678 (plus:SI (ne (reg:CC 17) (const_int 0))
1679 (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
1680 ""
1681 "inct %0")
1683 (define_insn "incscc_false"
1684 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1685 (plus:SI (eq (reg:CC 17) (const_int 0))
1686 (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
1687 ""
1688 "incf %0")
1690 (define_insn "decscc"
1691 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1692 (minus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
1693 (ne (reg:CC 17) (const_int 0))))]
1694 ""
1695 "dect %0")
1697 (define_insn "decscc_false"
1698 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1699 (minus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
1700 (eq (reg:CC 17) (const_int 0))))]
1701 ""
1702 "decf %0")
1704 ;; ------------------------------------------------------------------------
1705 ;; Conditional move patterns.
1706 ;; ------------------------------------------------------------------------
1708 (define_expand "smaxsi3"
1709 [(set (reg:CC 17)
1710 (lt:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
1711 (match_operand:SI 2 "mcore_arith_reg_operand" "")))
1712 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1713 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
1714 (match_dup 1) (match_dup 2)))]
1715 ""
1716 "")
1718 (define_split
1719 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1720 (smax:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
1721 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
1722 ""
1723 [(set (reg:CC 17)
1724 (lt:SI (match_dup 1) (match_dup 2)))
1725 (set (match_dup 0)
1726 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
1727 (match_dup 1) (match_dup 2)))]
1728 "")
1730 ; no tstgt in 0.97, so just use cmplti (btsti x,31) and reverse move
1731 ; condition BRC
1732 (define_split
1733 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1734 (smax:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
1735 (const_int 0)))]
1736 ""
1737 [(set (reg:CC 17)
1738 (lt:CC (match_dup 1) (const_int 0)))
1739 (set (match_dup 0)
1740 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
1741 (match_dup 1) (const_int 0)))]
1742 "")
1744 (define_expand "sminsi3"
1745 [(set (reg:CC 17)
1746 (lt:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
1747 (match_operand:SI 2 "mcore_arith_reg_operand" "")))
1748 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1749 (if_then_else:SI (ne (reg:CC 17) (const_int 0))
1750 (match_dup 1) (match_dup 2)))]
1751 ""
1752 "")
1754 (define_split
1755 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1756 (smin:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
1757 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
1758 ""
1759 [(set (reg:CC 17)
1760 (lt:SI (match_dup 1) (match_dup 2)))
1761 (set (match_dup 0)
1762 (if_then_else:SI (ne (reg:CC 17) (const_int 0))
1763 (match_dup 1) (match_dup 2)))]
1764 "")
1766 ;(define_split
1767 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1768 ; (smin:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
1769 ; (const_int 0)))]
1770 ; ""
1771 ; [(set (reg:CC 17)
1772 ; (gt:CC (match_dup 1) (const_int 0)))
1773 ; (set (match_dup 0)
1774 ; (if_then_else:SI (eq (reg:CC 17) (const_int 0))
1775 ; (match_dup 1) (const_int 0)))]
1776 ; "")
1778 ; changed these unsigned patterns to use geu instead of ltu. it appears
1779 ; that the c-torture & ssrl test suites didn't catch these! only showed
1780 ; up in friedman's clib work. BRC 7/7/95
1782 (define_expand "umaxsi3"
1783 [(set (reg:CC 17)
1784 (geu:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
1785 (match_operand:SI 2 "mcore_arith_reg_operand" "")))
1786 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1787 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
1788 (match_dup 2) (match_dup 1)))]
1789 ""
1790 "")
1792 (define_split
1793 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1794 (umax:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
1795 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
1796 ""
1797 [(set (reg:CC 17)
1798 (geu:SI (match_dup 1) (match_dup 2)))
1799 (set (match_dup 0)
1800 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
1801 (match_dup 2) (match_dup 1)))]
1802 "")
1804 (define_expand "uminsi3"
1805 [(set (reg:CC 17)
1806 (geu:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
1807 (match_operand:SI 2 "mcore_arith_reg_operand" "")))
1808 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1809 (if_then_else:SI (ne (reg:CC 17) (const_int 0))
1810 (match_dup 2) (match_dup 1)))]
1811 ""
1812 "")
1814 (define_split
1815 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1816 (umin:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
1817 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
1818 ""
1819 [(set (reg:CC 17)
1820 (geu:SI (match_dup 1) (match_dup 2)))
1821 (set (match_dup 0)
1822 (if_then_else:SI (ne (reg:CC 17) (const_int 0))
1823 (match_dup 2) (match_dup 1)))]
1824 "")
1826 ;; ------------------------------------------------------------------------
1827 ;; conditional move patterns really start here
1828 ;; ------------------------------------------------------------------------
1830 ;; the "movtK" patterns are experimental. they are intended to account for
1831 ;; gcc's mucking on code such as:
1832 ;;
1833 ;; free_ent = ((block_compress) ? 257 : 256 );
1834 ;;
1835 ;; these patterns help to get a tstne/bgeni/inct (or equivalent) sequence
1836 ;; when both arms have constants that are +/- 1 of each other.
1837 ;;
1838 ;; note in the following patterns that the "movtK" ones should be the first
1839 ;; one defined in each sequence. this is because the general pattern also
1840 ;; matches, so use ordering to determine priority (it's easier this way than
1841 ;; adding conditions to the general patterns). BRC
1842 ;;
1843 ;; the U and Q constraints are necessary to ensure that reload does the
1844 ;; 'right thing'. U constrains the operand to 0 and Q to 1 for use in the
1845 ;; clrt & clrf and clrt/inct & clrf/incf patterns. BRC 6/26
1846 ;;
1847 ;; ??? there appears to be some problems with these movtK patterns for ops
1848 ;; other than eq & ne. need to fix. 6/30 BRC
1850 ;; ------------------------------------------------------------------------
1851 ;; ne
1852 ;; ------------------------------------------------------------------------
1854 ; experimental conditional move with two constants +/- 1 BRC
1856 (define_insn "movtK_1"
1857 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1858 (if_then_else:SI
1859 (ne (reg:CC 17) (const_int 0))
1860 (match_operand:SI 1 "mcore_arith_O_operand" "O")
1861 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
1862 " GET_CODE (operands[1]) == CONST_INT
1863 && GET_CODE (operands[2]) == CONST_INT
1864 && ( (INTVAL (operands[1]) - INTVAL (operands[2]) == 1)
1865 || (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
1866 "* return mcore_output_cmov (operands, 1, NULL);"
1867 [(set_attr "length" "4")])
1869 (define_insn "movt0"
1870 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
1871 (if_then_else:SI
1872 (ne (reg:CC 17) (const_int 0))
1873 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
1874 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
1875 ""
1876 "@
1877 movt %0,%1
1878 movf %0,%2
1879 clrt %0
1880 clrf %0")
1882 ;; ------------------------------------------------------------------------
1883 ;; eq
1884 ;; ------------------------------------------------------------------------
1886 ; experimental conditional move with two constants +/- 1 BRC
1887 (define_insn "movtK_2"
1888 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1889 (if_then_else:SI
1890 (eq (reg:CC 17) (const_int 0))
1891 (match_operand:SI 1 "mcore_arith_O_operand" "O")
1892 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
1893 " GET_CODE (operands[1]) == CONST_INT
1894 && GET_CODE (operands[2]) == CONST_INT
1895 && ( (INTVAL (operands[1]) - INTVAL (operands[2]) == 1)
1896 || (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
1897 "* return mcore_output_cmov (operands, 0, NULL);"
1898 [(set_attr "length" "4")])
1900 (define_insn "movf0"
1901 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
1902 (if_then_else:SI
1903 (eq (reg:CC 17) (const_int 0))
1904 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
1905 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
1906 ""
1907 "@
1908 movf %0,%1
1909 movt %0,%2
1910 clrf %0
1911 clrt %0")
1913 ; turns lsli rx,imm/btsti rx,31 into btsti rx,imm. not done by a peephole
1914 ; because the instructions are not adjacent (peepholes are related by posn -
1915 ; not by dataflow). BRC
1917 (define_insn ""
1918 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
1919 (if_then_else:SI (eq (zero_extract:SI
1920 (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
1921 (const_int 1)
1922 (match_operand:SI 2 "mcore_literal_K_operand" "K,K,K,K"))
1923 (const_int 0))
1924 (match_operand:SI 3 "mcore_arith_imm_operand" "r,0,U,0")
1925 (match_operand:SI 4 "mcore_arith_imm_operand" "0,r,0,U")))]
1926 ""
1927 "@
1928 btsti %1,%2\;movf %0,%3
1929 btsti %1,%2\;movt %0,%4
1930 btsti %1,%2\;clrf %0
1931 btsti %1,%2\;clrt %0"
1932 [(set_attr "length" "4")])
1934 ; turns sextb rx/btsti rx,31 into btsti rx,7. must be QImode to be safe. BRC
1936 (define_insn ""
1937 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
1938 (if_then_else:SI (eq (lshiftrt:SI
1939 (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
1940 (const_int 7))
1941 (const_int 0))
1942 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
1943 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
1944 "GET_CODE (operands[1]) == SUBREG &&
1945 GET_MODE (SUBREG_REG (operands[1])) == QImode"
1946 "@
1947 btsti %1,7\;movf %0,%2
1948 btsti %1,7\;movt %0,%3
1949 btsti %1,7\;clrf %0
1950 btsti %1,7\;clrt %0"
1951 [(set_attr "length" "4")])
1954 ;; ------------------------------------------------------------------------
1955 ;; ne
1956 ;; ------------------------------------------------------------------------
1958 ;; Combine creates this from an andn instruction in a scc sequence.
1959 ;; We must recognize it to get conditional moves generated.
1961 ; experimental conditional move with two constants +/- 1 BRC
1962 (define_insn "movtK_3"
1963 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1964 (if_then_else:SI
1965 (ne (match_operand:SI 1 "mcore_arith_reg_operand" "r")
1966 (const_int 0))
1967 (match_operand:SI 2 "mcore_arith_O_operand" "O")
1968 (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
1969 " GET_CODE (operands[2]) == CONST_INT
1970 && GET_CODE (operands[3]) == CONST_INT
1971 && ( (INTVAL (operands[2]) - INTVAL (operands[3]) == 1)
1972 || (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
1973 "*
1974 {
1975 rtx out_operands[4];
1976 out_operands[0] = operands[0];
1977 out_operands[1] = operands[2];
1978 out_operands[2] = operands[3];
1979 out_operands[3] = operands[1];
1981 return mcore_output_cmov (out_operands, 1, \"cmpnei %3,0\");
1983 }"
1984 [(set_attr "length" "6")])
1986 (define_insn "movt2"
1987 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
1988 (if_then_else:SI (ne (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
1989 (const_int 0))
1990 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
1991 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
1992 ""
1993 "@
1994 cmpnei %1,0\;movt %0,%2
1995 cmpnei %1,0\;movf %0,%3
1996 cmpnei %1,0\;clrt %0
1997 cmpnei %1,0\;clrf %0"
1998 [(set_attr "length" "4")])
2000 ; turns lsli rx,imm/btsti rx,31 into btsti rx,imm. not done by a peephole
2001 ; because the instructions are not adjacent (peepholes are related by posn -
2002 ; not by dataflow). BRC
2004 (define_insn ""
2005 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2006 (if_then_else:SI (ne (zero_extract:SI
2007 (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2008 (const_int 1)
2009 (match_operand:SI 2 "mcore_literal_K_operand" "K,K,K,K"))
2010 (const_int 0))
2011 (match_operand:SI 3 "mcore_arith_imm_operand" "r,0,U,0")
2012 (match_operand:SI 4 "mcore_arith_imm_operand" "0,r,0,U")))]
2013 ""
2014 "@
2015 btsti %1,%2\;movt %0,%3
2016 btsti %1,%2\;movf %0,%4
2017 btsti %1,%2\;clrt %0
2018 btsti %1,%2\;clrf %0"
2019 [(set_attr "length" "4")])
2021 ; turns sextb rx/btsti rx,31 into btsti rx,7. must be QImode to be safe. BRC
2023 (define_insn ""
2024 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2025 (if_then_else:SI (ne (lshiftrt:SI
2026 (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2027 (const_int 7))
2028 (const_int 0))
2029 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2030 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2031 "GET_CODE (operands[1]) == SUBREG &&
2032 GET_MODE (SUBREG_REG (operands[1])) == QImode"
2033 "@
2034 btsti %1,7\;movt %0,%2
2035 btsti %1,7\;movf %0,%3
2036 btsti %1,7\;clrt %0
2037 btsti %1,7\;clrf %0"
2038 [(set_attr "length" "4")])
2040 ;; ------------------------------------------------------------------------
2041 ;; eq/eq
2042 ;; ------------------------------------------------------------------------
2044 ; experimental conditional move with two constants +/- 1 BRC
2045 (define_insn "movtK_4"
2046 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2047 (if_then_else:SI
2048 (eq (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
2049 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2050 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2051 "GET_CODE (operands[1]) == CONST_INT &&
2052 GET_CODE (operands[2]) == CONST_INT &&
2053 ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
2054 (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2055 "* return mcore_output_cmov(operands, 1, NULL);"
2056 [(set_attr "length" "4")])
2058 (define_insn "movt3"
2059 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2060 (if_then_else:SI
2061 (eq (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
2062 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2063 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2064 ""
2065 "@
2066 movt %0,%1
2067 movf %0,%2
2068 clrt %0
2069 clrf %0")
2071 ;; ------------------------------------------------------------------------
2072 ;; eq/ne
2073 ;; ------------------------------------------------------------------------
2075 ; experimental conditional move with two constants +/- 1 BRC
2076 (define_insn "movtK_5"
2077 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2078 (if_then_else:SI
2079 (eq (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
2080 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2081 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2082 "GET_CODE (operands[1]) == CONST_INT &&
2083 GET_CODE (operands[2]) == CONST_INT &&
2084 ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
2085 (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2086 "* return mcore_output_cmov (operands, 0, NULL);"
2087 [(set_attr "length" "4")])
2089 (define_insn "movf1"
2090 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2091 (if_then_else:SI
2092 (eq (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
2093 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2094 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2095 ""
2096 "@
2097 movf %0,%1
2098 movt %0,%2
2099 clrf %0
2100 clrt %0")
2102 ;; ------------------------------------------------------------------------
2103 ;; eq
2104 ;; ------------------------------------------------------------------------
2106 ;; Combine creates this from an andn instruction in a scc sequence.
2107 ;; We must recognize it to get conditional moves generated.
2109 ; experimental conditional move with two constants +/- 1 BRC
2111 (define_insn "movtK_6"
2112 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2113 (if_then_else:SI
2114 (eq (match_operand:SI 1 "mcore_arith_reg_operand" "r")
2115 (const_int 0))
2116 (match_operand:SI 2 "mcore_arith_O_operand" "O")
2117 (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
2118 "GET_CODE (operands[1]) == CONST_INT &&
2119 GET_CODE (operands[2]) == CONST_INT &&
2120 ((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
2121 (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
2122 "*
2123 {
2124 rtx out_operands[4];
2125 out_operands[0] = operands[0];
2126 out_operands[1] = operands[2];
2127 out_operands[2] = operands[3];
2128 out_operands[3] = operands[1];
2130 return mcore_output_cmov (out_operands, 0, \"cmpnei %3,0\");
2131 }"
2132 [(set_attr "length" "6")])
2134 (define_insn "movf3"
2135 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2136 (if_then_else:SI (eq (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2137 (const_int 0))
2138 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2139 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2140 ""
2141 "@
2142 cmpnei %1,0\;movf %0,%2
2143 cmpnei %1,0\;movt %0,%3
2144 cmpnei %1,0\;clrf %0
2145 cmpnei %1,0\;clrt %0"
2146 [(set_attr "length" "4")])
2148 ;; ------------------------------------------------------------------------
2149 ;; ne/eq
2150 ;; ------------------------------------------------------------------------
2152 ; experimental conditional move with two constants +/- 1 BRC
2153 (define_insn "movtK_7"
2154 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2155 (if_then_else:SI
2156 (ne (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
2157 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2158 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2159 "GET_CODE (operands[1]) == CONST_INT &&
2160 GET_CODE (operands[2]) == CONST_INT &&
2161 ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
2162 (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2163 "* return mcore_output_cmov (operands, 0, NULL);"
2164 [(set_attr "length" "4")])
2166 (define_insn "movf4"
2167 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2168 (if_then_else:SI
2169 (ne (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
2170 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2171 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2172 ""
2173 "@
2174 movf %0,%1
2175 movt %0,%2
2176 clrf %0
2177 clrt %0")
2179 ;; ------------------------------------------------------------------------
2180 ;; ne/ne
2181 ;; ------------------------------------------------------------------------
2183 ; experimental conditional move with two constants +/- 1 BRC
2184 (define_insn "movtK_8"
2185 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2186 (if_then_else:SI
2187 (ne (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
2188 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2189 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2190 "GET_CODE (operands[1]) == CONST_INT &&
2191 GET_CODE (operands[2]) == CONST_INT &&
2192 ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
2193 (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2194 "* return mcore_output_cmov (operands, 1, NULL);"
2195 [(set_attr "length" "4")])
2197 (define_insn "movt4"
2198 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2199 (if_then_else:SI
2200 (ne (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
2201 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2202 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2203 ""
2204 "@
2205 movt %0,%1
2206 movf %0,%2
2207 clrt %0
2208 clrf %0")
2210 ;; Also need patterns to recognize lt/ge, since otherwise the compiler will
2211 ;; try to output not/asri/tstne/movf.
2213 ;; ------------------------------------------------------------------------
2214 ;; lt
2215 ;; ------------------------------------------------------------------------
2217 ; experimental conditional move with two constants +/- 1 BRC
2218 (define_insn "movtK_9"
2219 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2220 (if_then_else:SI
2221 (lt (match_operand:SI 1 "mcore_arith_reg_operand" "r")
2222 (const_int 0))
2223 (match_operand:SI 2 "mcore_arith_O_operand" "O")
2224 (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
2225 "GET_CODE (operands[2]) == CONST_INT &&
2226 GET_CODE (operands[3]) == CONST_INT &&
2227 ((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
2228 (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
2229 "*
2230 {
2231 rtx out_operands[4];
2232 out_operands[0] = operands[0];
2233 out_operands[1] = operands[2];
2234 out_operands[2] = operands[3];
2235 out_operands[3] = operands[1];
2237 return mcore_output_cmov (out_operands, 1, \"btsti %3,31\");
2238 }"
2239 [(set_attr "length" "6")])
2241 (define_insn "movt5"
2242 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2243 (if_then_else:SI (lt (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2244 (const_int 0))
2245 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2246 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2247 ""
2248 "@
2249 btsti %1,31\;movt %0,%2
2250 btsti %1,31\;movf %0,%3
2251 btsti %1,31\;clrt %0
2252 btsti %1,31\;clrf %0"
2253 [(set_attr "length" "4")])
2256 ;; ------------------------------------------------------------------------
2257 ;; ge
2258 ;; ------------------------------------------------------------------------
2260 ; experimental conditional move with two constants +/- 1 BRC
2261 (define_insn "movtK_10"
2262 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2263 (if_then_else:SI
2264 (ge (match_operand:SI 1 "mcore_arith_reg_operand" "r")
2265 (const_int 0))
2266 (match_operand:SI 2 "mcore_arith_O_operand" "O")
2267 (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
2268 "GET_CODE (operands[2]) == CONST_INT &&
2269 GET_CODE (operands[3]) == CONST_INT &&
2270 ((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
2271 (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
2272 "*
2273 {
2274 rtx out_operands[4];
2275 out_operands[0] = operands[0];
2276 out_operands[1] = operands[2];
2277 out_operands[2] = operands[3];
2278 out_operands[3] = operands[1];
2280 return mcore_output_cmov (out_operands, 0, \"btsti %3,31\");
2281 }"
2282 [(set_attr "length" "6")])
2284 (define_insn "movf5"
2285 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2286 (if_then_else:SI (ge (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2287 (const_int 0))
2288 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2289 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2290 ""
2291 "@
2292 btsti %1,31\;movf %0,%2
2293 btsti %1,31\;movt %0,%3
2294 btsti %1,31\;clrf %0
2295 btsti %1,31\;clrt %0"
2296 [(set_attr "length" "4")])
2298 ;; ------------------------------------------------------------------------
2299 ;; Bitfield extract (xtrbN)
2300 ;; ------------------------------------------------------------------------
2302 ; sometimes we're better off using QI/HI mode and letting the machine indep.
2303 ; part expand insv and extv.
2304 ;
2305 ; e.g., sequences like:a [an insertion]
2306 ;
2307 ; ldw r8,(r6)
2308 ; movi r7,0x00ffffff
2309 ; and r8,r7 r7 dead
2310 ; stw r8,(r6) r8 dead
2311 ;
2312 ; become:
2313 ;
2314 ; movi r8,0
2315 ; stb r8,(r6) r8 dead
2316 ;
2317 ; it looks like always using SI mode is a win except in this type of code
2318 ; (when adjacent bit fields collapse on a byte or halfword boundary). when
2319 ; expanding with SI mode, non-adjacent bit field masks fold, but with QI/HI
2320 ; mode, they do not. one thought is to add some peepholes to cover cases
2321 ; like the above, but this is not a general solution.
2322 ;
2323 ; -mword-bitfields expands/inserts using SI mode. otherwise, do it with
2324 ; the smallest mode possible (using the machine indep. expansions). BRC
2326 ;(define_expand "extv"
2327 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2328 ; (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2329 ; (match_operand:SI 2 "const_int_operand" "")
2330 ; (match_operand:SI 3 "const_int_operand" "")))
2331 ; (clobber (reg:CC 17))]
2332 ; ""
2333 ; "
2334 ;{
2335 ; if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) % 8 != 0)
2336 ; {
2337 ; if (TARGET_W_FIELD)
2338 ; {
2339 ; rtx lshft = GEN_INT (32 - (INTVAL (operands[2]) + INTVAL (operands[3])));
2340 ; rtx rshft = GEN_INT (32 - INTVAL (operands[2]));
2341 ;
2342 ; emit_insn (gen_rtx_SET (operands[0], operands[1]));
2343 ; emit_insn (gen_rtx_SET (operands[0],
2344 ; gen_rtx_ASHIFT (SImode, operands[0], lshft)));
2345 ; emit_insn (gen_rtx_SET (operands[0],
2346 ; gen_rtx_ASHIFTRT (SImode, operands[0], rshft)));
2347 ; DONE;
2348 ; }
2349 ; else
2350 ; FAIL;
2351 ; }
2352 ;}")
2354 (define_expand "extv"
2355 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2356 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2357 (match_operand:SI 2 "const_int_operand" "")
2358 (match_operand:SI 3 "const_int_operand" "")))
2359 (clobber (reg:CC 17))]
2360 ""
2361 "
2362 {
2363 if (INTVAL (operands[2]) == 8 && INTVAL (operands[3]) % 8 == 0)
2364 {
2365 /* 8-bit field, aligned properly, use the xtrb[0123]+sext sequence. */
2366 /* not DONE, not FAIL, but let the RTL get generated.... */
2367 }
2368 else if (TARGET_W_FIELD)
2369 {
2370 /* Arbitrary placement; note that the tree->rtl generator will make
2371 something close to this if we return FAIL */
2372 rtx lshft = GEN_INT (32 - (INTVAL (operands[2]) + INTVAL (operands[3])));
2373 rtx rshft = GEN_INT (32 - INTVAL (operands[2]));
2374 rtx tmp1 = gen_reg_rtx (SImode);
2375 rtx tmp2 = gen_reg_rtx (SImode);
2377 emit_insn (gen_rtx_SET (tmp1, operands[1]));
2378 emit_insn (gen_rtx_SET (tmp2,
2379 gen_rtx_ASHIFT (SImode, tmp1, lshft)));
2380 emit_insn (gen_rtx_SET (operands[0],
2381 gen_rtx_ASHIFTRT (SImode, tmp2, rshft)));
2382 DONE;
2383 }
2384 else
2385 {
2386 /* Let the caller choose an alternate sequence. */
2387 FAIL;
2388 }
2389 }")
2391 (define_expand "extzv"
2392 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2393 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2394 (match_operand:SI 2 "const_int_operand" "")
2395 (match_operand:SI 3 "const_int_operand" "")))
2396 (clobber (reg:CC 17))]
2397 ""
2398 "
2399 {
2400 if (INTVAL (operands[2]) == 8 && INTVAL (operands[3]) % 8 == 0)
2401 {
2402 /* 8-bit field, aligned properly, use the xtrb[0123] sequence. */
2403 /* Let the template generate some RTL.... */
2404 }
2405 else if (CONST_OK_FOR_K ((1 << INTVAL (operands[2])) - 1))
2406 {
2407 /* A narrow bit-field (<=5 bits) means we can do a shift to put
2408 it in place and then use an andi to extract it.
2409 This is as good as a shiftleft/shiftright. */
2411 rtx shifted;
2412 rtx mask = GEN_INT ((1 << INTVAL (operands[2])) - 1);
2414 if (INTVAL (operands[3]) == 0)
2415 {
2416 shifted = operands[1];
2417 }
2418 else
2419 {
2420 rtx rshft = GEN_INT (INTVAL (operands[3]));
2421 shifted = gen_reg_rtx (SImode);
2422 emit_insn (gen_rtx_SET (shifted,
2423 gen_rtx_LSHIFTRT (SImode, operands[1], rshft)));
2424 }
2425 emit_insn (gen_rtx_SET (operands[0],
2426 gen_rtx_AND (SImode, shifted, mask)));
2427 DONE;
2428 }
2429 else if (TARGET_W_FIELD)
2430 {
2431 /* Arbitrary pattern; play shift/shift games to get it.
2432 * this is pretty much what the caller will do if we say FAIL */
2433 rtx lshft = GEN_INT (32 - (INTVAL (operands[2]) + INTVAL (operands[3])));
2434 rtx rshft = GEN_INT (32 - INTVAL (operands[2]));
2435 rtx tmp1 = gen_reg_rtx (SImode);
2436 rtx tmp2 = gen_reg_rtx (SImode);
2438 emit_insn (gen_rtx_SET (tmp1, operands[1]));
2439 emit_insn (gen_rtx_SET (tmp2,
2440 gen_rtx_ASHIFT (SImode, tmp1, lshft)));
2441 emit_insn (gen_rtx_SET (operands[0],
2442 gen_rtx_LSHIFTRT (SImode, tmp2, rshft)));
2443 DONE;
2444 }
2445 else
2446 {
2447 /* Make the compiler figure out some alternative mechanism. */
2448 FAIL;
2449 }
2451 /* Emit the RTL pattern; something will match it later. */
2452 }")
2454 (define_expand "insv"
2455 [(set (zero_extract:SI (match_operand:SI 0 "mcore_arith_reg_operand" "")
2456 (match_operand:SI 1 "const_int_operand" "")
2457 (match_operand:SI 2 "const_int_operand" ""))
2458 (match_operand:SI 3 "general_operand" ""))
2459 (clobber (reg:CC 17))]
2460 ""
2461 "
2462 {
2463 if (mcore_expand_insv (operands))
2464 {
2465 DONE;
2466 }
2467 else
2468 {
2469 FAIL;
2470 }
2471 }")
2473 ;;
2474 ;; the xtrb[0123] instructions handily get at 8-bit fields on nice boundaries.
2475 ;; but then, they do force you through r1.
2476 ;;
2477 ;; the combiner will build such patterns for us, so we'll make them available
2478 ;; for its use.
2479 ;;
2480 ;; Note that we have both SIGNED and UNSIGNED versions of these...
2481 ;;
2483 ;;
2484 ;; These no longer worry about the clobbering of CC bit; not sure this is
2485 ;; good...
2486 ;;
2487 ;; the SIGNED versions of these
2488 ;;
2489 (define_insn ""
2490 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b")
2491 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,r") (const_int 8) (const_int 24)))]
2492 ""
2493 "@
2494 asri %0,24
2495 xtrb0 %0,%1\;sextb %0"
2496 [(set_attr "type" "shift")])
2498 (define_insn ""
2499 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=b")
2500 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r") (const_int 8) (const_int 16)))]
2501 ""
2502 "xtrb1 %0,%1\;sextb %0"
2503 [(set_attr "type" "shift")])
2505 (define_insn ""
2506 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=b")
2507 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r") (const_int 8) (const_int 8)))]
2508 ""
2509 "xtrb2 %0,%1\;sextb %0"
2510 [(set_attr "type" "shift")])
2512 (define_insn ""
2513 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2514 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0") (const_int 8) (const_int 0)))]
2515 ""
2516 "sextb %0"
2517 [(set_attr "type" "shift")])
2519 ;; the UNSIGNED uses of xtrb[0123]
2520 ;;
2521 (define_insn ""
2522 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b")
2523 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,r") (const_int 8) (const_int 24)))]
2524 ""
2525 "@
2526 lsri %0,24
2527 xtrb0 %0,%1"
2528 [(set_attr "type" "shift")])
2530 (define_insn ""
2531 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=b")
2532 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r") (const_int 8) (const_int 16)))]
2533 ""
2534 "xtrb1 %0,%1"
2535 [(set_attr "type" "shift")])
2537 (define_insn ""
2538 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=b")
2539 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r") (const_int 8) (const_int 8)))]
2540 ""
2541 "xtrb2 %0,%1"
2542 [(set_attr "type" "shift")])
2544 ;; This can be peepholed if it follows a ldb ...
2545 (define_insn ""
2546 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b")
2547 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,r") (const_int 8) (const_int 0)))]
2548 ""
2549 "@
2550 zextb %0
2551 xtrb3 %0,%1\;zextb %0"
2552 [(set_attr "type" "shift")])
2555 ;; ------------------------------------------------------------------------
2556 ;; Block move - adapted from m88k.md
2557 ;; ------------------------------------------------------------------------
2559 (define_expand "cpymemsi"
2560 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
2561 (mem:BLK (match_operand:BLK 1 "" "")))
2562 (use (match_operand:SI 2 "general_operand" ""))
2563 (use (match_operand:SI 3 "immediate_operand" ""))])]
2564 ""
2565 "
2566 {
2567 if (mcore_expand_block_move (operands))
2568 DONE;
2569 else
2570 FAIL;
2571 }")
2573 ;; ;;; ??? These patterns are meant to be generated from expand_block_move,
2574 ;; ;;; but they currently are not.
2575 ;;
2576 ;; (define_insn ""
2577 ;; [(set (match_operand:QI 0 "mcore_arith_reg_operand" "=r")
2578 ;; (match_operand:BLK 1 "mcore_general_movsrc_operand" "m"))]
2579 ;; ""
2580 ;; "ld.b %0,%1"
2581 ;; [(set_attr "type" "load")])
2582 ;;
2583 ;; (define_insn ""
2584 ;; [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
2585 ;; (match_operand:BLK 1 "mcore_general_movsrc_operand" "m"))]
2586 ;; ""
2587 ;; "ld.h %0,%1"
2588 ;; [(set_attr "type" "load")])
2589 ;;
2590 ;; (define_insn ""
2591 ;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2592 ;; (match_operand:BLK 1 "mcore_general_movsrc_operand" "m"))]
2593 ;; ""
2594 ;; "ld.w %0,%1"
2595 ;; [(set_attr "type" "load")])
2596 ;;
2597 ;; (define_insn ""
2598 ;; [(set (match_operand:BLK 0 "mcore_general_movdst_operand" "=m")
2599 ;; (match_operand:QI 1 "mcore_arith_reg_operand" "r"))]
2600 ;; ""
2601 ;; "st.b %1,%0"
2602 ;; [(set_attr "type" "store")])
2603 ;;
2604 ;; (define_insn ""
2605 ;; [(set (match_operand:BLK 0 "mcore_general_movdst_operand" "=m")
2606 ;; (match_operand:HI 1 "mcore_arith_reg_operand" "r"))]
2607 ;; ""
2608 ;; "st.h %1,%0"
2609 ;; [(set_attr "type" "store")])
2610 ;;
2611 ;; (define_insn ""
2612 ;; [(set (match_operand:BLK 0 "mcore_general_movdst_operand" "=m")
2613 ;; (match_operand:SI 1 "mcore_arith_reg_operand" "r"))]
2614 ;; ""
2615 ;; "st.w %1,%0"
2616 ;; [(set_attr "type" "store")])
2617 \f
2618 ;; ------------------------------------------------------------------------
2619 ;; Misc Optimizing quirks
2620 ;; ------------------------------------------------------------------------
2622 ;; pair to catch constructs like: (int *)((p+=4)-4) which happen
2623 ;; in stdarg/varargs traversal. This changes a 3 insn sequence to a 2
2624 ;; insn sequence. -- RBE 11/30/95
2625 (define_insn ""
2626 [(parallel[
2627 (set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2628 (match_operand:SI 1 "mcore_arith_reg_operand" "+r"))
2629 (set (match_dup 1) (plus:SI (match_dup 1) (match_operand 2 "mcore_arith_any_imm_operand" "")))])]
2630 "GET_CODE(operands[2]) == CONST_INT"
2631 "#"
2632 [(set_attr "length" "4")])
2634 (define_split
2635 [(parallel[
2636 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2637 (match_operand:SI 1 "mcore_arith_reg_operand" ""))
2638 (set (match_dup 1) (plus:SI (match_dup 1) (match_operand 2 "mcore_arith_any_imm_operand" "")))])]
2639 "GET_CODE(operands[2]) == CONST_INT &&
2640 operands[0] != operands[1]"
2641 [(set (match_dup 0) (match_dup 1))
2642 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))])
2644 \f
2645 ;;; Peepholes
2647 ; note: in the following patterns, use mcore_is_dead() to ensure that the
2648 ; reg we may be trashing really is dead. reload doesn't always mark
2649 ; deaths, so mcore_is_dead() (see mcore.cc) scans forward to find its death. BRC
2651 ;;; A peephole to convert the 3 instruction sequence generated by reload
2652 ;;; to load a FP-offset address into a 2 instruction sequence.
2653 ;;; ??? This probably never matches anymore.
2654 (define_peephole
2655 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
2656 (match_operand:SI 1 "const_int_operand" "J"))
2657 (set (match_dup 0) (neg:SI (match_dup 0)))
2658 (set (match_dup 0)
2659 (plus:SI (match_dup 0)
2660 (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
2661 "CONST_OK_FOR_J (INTVAL (operands[1]))"
2662 "error\;mov %0,%2\;subi %0,%1")
2664 ;; Moves of inlinable constants are done late, so when a 'not' is generated
2665 ;; it is never combined with the following 'and' to generate an 'andn' b/c
2666 ;; the combiner never sees it. use a peephole to pick up this case (happens
2667 ;; mostly with bitfields) BRC
2669 (define_peephole
2670 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
2671 (match_operand:SI 1 "const_int_operand" "i"))
2672 (set (match_operand:SI 2 "mcore_arith_reg_operand" "r")
2673 (and:SI (match_dup 2) (match_dup 0)))]
2674 "mcore_const_trick_uses_not (INTVAL (operands[1])) &&
2675 operands[0] != operands[2] &&
2676 mcore_is_dead (insn, operands[0])"
2677 "* return mcore_output_andn (insn, operands);")
2679 ; when setting or clearing just two bits, it's cheapest to use two bseti's
2680 ; or bclri's. only happens when relaxing immediates. BRC
2682 (define_peephole
2683 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2684 (match_operand:SI 1 "const_int_operand" ""))
2685 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
2686 (ior:SI (match_dup 2) (match_dup 0)))]
2687 "TARGET_HARDLIT
2688 && mcore_num_ones (INTVAL (operands[1])) == 2
2689 && mcore_is_dead (insn, operands[0])"
2690 "* return mcore_output_bseti (operands[2], INTVAL (operands[1]));")
2692 (define_peephole
2693 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2694 (match_operand:SI 1 "const_int_operand" ""))
2695 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
2696 (and:SI (match_dup 2) (match_dup 0)))]
2697 "TARGET_HARDLIT && mcore_num_zeros (INTVAL (operands[1])) == 2 &&
2698 mcore_is_dead (insn, operands[0])"
2699 "* return mcore_output_bclri (operands[2], INTVAL (operands[1]));")
2701 ; change an and with a mask that has a single cleared bit into a bclri. this
2702 ; handles QI and HI mode values using the knowledge that the most significant
2703 ; bits don't matter.
2705 (define_peephole
2706 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2707 (match_operand:SI 1 "const_int_operand" ""))
2708 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
2709 (and:SI (match_operand:SI 3 "mcore_arith_reg_operand" "")
2710 (match_dup 0)))]
2711 "GET_CODE (operands[3]) == SUBREG &&
2712 GET_MODE (SUBREG_REG (operands[3])) == QImode &&
2713 mcore_num_zeros (INTVAL (operands[1]) | 0xffffff00) == 1 &&
2714 mcore_is_dead (insn, operands[0])"
2715 "*
2716 if (! mcore_is_same_reg (operands[2], operands[3]))
2717 output_asm_insn (\"mov\\t%2,%3\", operands);
2718 return mcore_output_bclri (operands[2], INTVAL (operands[1]) | 0xffffff00);")
2720 /* Do not fold these together -- mode is lost at final output phase. */
2722 (define_peephole
2723 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2724 (match_operand:SI 1 "const_int_operand" ""))
2725 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
2726 (and:SI (match_operand:SI 3 "mcore_arith_reg_operand" "")
2727 (match_dup 0)))]
2728 "GET_CODE (operands[3]) == SUBREG &&
2729 GET_MODE (SUBREG_REG (operands[3])) == HImode &&
2730 mcore_num_zeros (INTVAL (operands[1]) | 0xffff0000) == 1 &&
2731 operands[2] == operands[3] &&
2732 mcore_is_dead (insn, operands[0])"
2733 "*
2734 if (! mcore_is_same_reg (operands[2], operands[3]))
2735 output_asm_insn (\"mov\\t%2,%3\", operands);
2736 return mcore_output_bclri (operands[2], INTVAL (operands[1]) | 0xffff0000);")
2738 ; This peephole helps when using -mwide-bitfields to widen fields so they
2739 ; collapse. This, however, has the effect that a narrower mode is not used
2740 ; when desirable.
2741 ;
2742 ; e.g., sequences like:
2743 ;
2744 ; ldw r8,(r6)
2745 ; movi r7,0x00ffffff
2746 ; and r8,r7 r7 dead
2747 ; stw r8,(r6) r8 dead
2748 ;
2749 ; get peepholed to become:
2750 ;
2751 ; movi r8,0
2752 ; stb r8,(r6) r8 dead
2753 ;
2754 ; Do only easy addresses that have no offset. This peephole is also applied
2755 ; to halfwords. We need to check that the load is non-volatile before we get
2756 ; rid of it.
2758 (define_peephole
2759 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2760 (match_operand:SI 1 "memory_operand" ""))
2761 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
2762 (match_operand:SI 3 "const_int_operand" ""))
2763 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))
2764 (set (match_operand:SI 4 "memory_operand" "") (match_dup 0))]
2765 "mcore_is_dead (insn, operands[0]) &&
2766 ! MEM_VOLATILE_P (operands[1]) &&
2767 mcore_is_dead (insn, operands[2]) &&
2768 (mcore_byte_offset (INTVAL (operands[3])) > -1 ||
2769 mcore_halfword_offset (INTVAL (operands[3])) > -1) &&
2770 ! MEM_VOLATILE_P (operands[4]) &&
2771 GET_CODE (XEXP (operands[4], 0)) == REG"
2772 "*
2773 {
2774 int ofs;
2775 machine_mode mode;
2776 rtx base_reg = XEXP (operands[4], 0);
2778 if ((ofs = mcore_byte_offset (INTVAL (operands[3]))) > -1)
2779 mode = QImode;
2780 else if ((ofs = mcore_halfword_offset (INTVAL (operands[3]))) > -1)
2781 mode = HImode;
2782 else
2783 gcc_unreachable ();
2785 if (ofs > 0)
2786 operands[4] = gen_rtx_MEM (mode,
2787 gen_rtx_PLUS (SImode, base_reg, GEN_INT(ofs)));
2788 else
2789 operands[4] = gen_rtx_MEM (mode, base_reg);
2791 if (mode == QImode)
2792 return \"movi %0,0\\n\\tst.b %0,%4\";
2794 return \"movi %0,0\\n\\tst.h %0,%4\";
2795 }")
2797 ; from sop11. get btsti's for (LT A 0) where A is a QI or HI value
2799 (define_peephole
2800 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
2801 (sign_extend:SI (match_operand:QI 1 "mcore_arith_reg_operand" "0")))
2802 (set (reg:CC 17)
2803 (lt:CC (match_dup 0)
2804 (const_int 0)))]
2805 "mcore_is_dead (insn, operands[0])"
2806 "btsti %0,7")
2808 (define_peephole
2809 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
2810 (sign_extend:SI (match_operand:HI 1 "mcore_arith_reg_operand" "0")))
2811 (set (reg:CC 17)
2812 (lt:CC (match_dup 0)
2813 (const_int 0)))]
2814 "mcore_is_dead (insn, operands[0])"
2815 "btsti %0,15")
2817 ; Pick up a tst. This combination happens because the immediate is not
2818 ; allowed to fold into one of the operands of the tst. Does not happen
2819 ; when relaxing immediates. BRC
2821 (define_peephole
2822 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2823 (match_operand:SI 1 "mcore_arith_reg_operand" ""))
2824 (set (match_dup 0)
2825 (and:SI (match_dup 0)
2826 (match_operand:SI 2 "mcore_literal_K_operand" "")))
2827 (set (reg:CC 17) (ne:CC (match_dup 0) (const_int 0)))]
2828 "mcore_is_dead (insn, operands[0])"
2829 "movi %0,%2\;tst %1,%0")
2831 (define_peephole
2832 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2833 (if_then_else:SI (ne (zero_extract:SI
2834 (match_operand:SI 1 "mcore_arith_reg_operand" "")
2835 (const_int 1)
2836 (match_operand:SI 2 "mcore_literal_K_operand" ""))
2837 (const_int 0))
2838 (match_operand:SI 3 "mcore_arith_imm_operand" "")
2839 (match_operand:SI 4 "mcore_arith_imm_operand" "")))
2840 (set (reg:CC 17) (ne:CC (match_dup 0) (const_int 0)))]
2841 ""
2842 "*
2843 {
2844 unsigned int op0 = REGNO (operands[0]);
2846 if (GET_CODE (operands[3]) == REG)
2847 {
2848 if (REGNO (operands[3]) == op0 && GET_CODE (operands[4]) == CONST_INT
2849 && INTVAL (operands[4]) == 0)
2850 return \"btsti %1,%2\\n\\tclrf %0\";
2851 else if (GET_CODE (operands[4]) == REG)
2852 {
2853 if (REGNO (operands[4]) == op0)
2854 return \"btsti %1,%2\\n\\tmovf %0,%3\";
2855 else if (REGNO (operands[3]) == op0)
2856 return \"btsti %1,%2\\n\\tmovt %0,%4\";
2857 }
2859 gcc_unreachable ();
2860 }
2861 else if (GET_CODE (operands[3]) == CONST_INT
2862 && INTVAL (operands[3]) == 0
2863 && GET_CODE (operands[4]) == REG)
2864 return \"btsti %1,%2\\n\\tclrt %0\";
2866 gcc_unreachable ();
2867 }")
2869 ; experimental - do the constant folding ourselves. note that this isn't
2870 ; re-applied like we'd really want. i.e., four ands collapse into two
2871 ; instead of one. this is because peepholes are applied as a sliding
2872 ; window. the peephole does not generate new rtl's, but instead slides
2873 ; across the rtl's generating machine instructions. it would be nice
2874 ; if the peephole optimizer is changed to re-apply patterns and to gen
2875 ; new rtl's. this is more flexible. the pattern below helps when we're
2876 ; not using relaxed immediates. BRC
2878 ;(define_peephole
2879 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2880 ; (match_operand:SI 1 "const_int_operand" ""))
2881 ; (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
2882 ; (and:SI (match_dup 2) (match_dup 0)))
2883 ; (set (match_dup 0)
2884 ; (match_operand:SI 3 "const_int_operand" ""))
2885 ; (set (match_dup 2)
2886 ; (and:SI (match_dup 2) (match_dup 0)))]
2887 ; "!TARGET_RELAX_IMM && mcore_is_dead (insn, operands[0]) &&
2888 ; mcore_const_ok_for_inline (INTVAL (operands[1]) & INTVAL (operands[3]))"
2889 ; "*
2890 ;{
2891 ; rtx out_operands[2];
2892 ; out_operands[0] = operands[0];
2893 ; out_operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[3]));
2894 ;
2895 ; output_inline_const (SImode, out_operands);
2896 ;
2897 ; output_asm_insn (\"and %2,%0\", operands);
2898 ;
2899 ; return \"\";
2900 ;}")
2902 ; BRC: for inlining get rid of extra test - experimental
2903 ;(define_peephole
2904 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
2905 ; (ne:SI (reg:CC 17) (const_int 0)))
2906 ; (set (reg:CC 17) (ne:CC (match_dup 0) (const_int 0)))
2907 ; (set (pc)
2908 ; (if_then_else (eq (reg:CC 17) (const_int 0))
2909 ; (label_ref (match_operand 1 "" ""))
2910 ; (pc)))]
2911 ; ""
2912 ; "*
2913 ;{
2914 ; if (get_attr_length (insn) == 10)
2915 ; {
2916 ; output_asm_insn (\"bt 2f\\n\\tjmpi [1f]\", operands);
2917 ; output_asm_insn (\".align 2\\n1:\", operands);
2918 ; output_asm_insn (\".long %1\\n2:\", operands);
2919 ; return \"\";
2920 ; }
2921 ; return \"bf %l1\";
2922 ;}")
2924 \f
2925 ;;; Special patterns for dealing with the constant pool.
2927 ;;; 4 byte integer in line.
2929 (define_insn "consttable_4"
2930 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 0)]
2931 ""
2932 "*
2933 {
2934 assemble_integer (operands[0], 4, BITS_PER_WORD, 1);
2935 return \"\";
2936 }"
2937 [(set_attr "length" "4")])
2939 ;;; align to a four byte boundary.
2941 (define_insn "align_4"
2942 [(unspec_volatile [(const_int 0)] 1)]
2943 ""
2944 ".align 2")
2946 ;;; Handle extra constant pool entries created during final pass.
2948 (define_insn "consttable_end"
2949 [(unspec_volatile [(const_int 0)] 2)]
2950 ""
2951 "* return mcore_output_jump_label_table ();")
2952 \f
2953 ;;
2954 ;; Stack allocation -- in particular, for alloca().
2955 ;; this is *not* what we use for entry into functions.
2956 ;;
2957 ;; This is how we allocate stack space. If we are allocating a
2958 ;; constant amount of space and we know it is less than 4096
2959 ;; bytes, we need do nothing.
2960 ;;
2961 ;; If it is more than 4096 bytes, we need to probe the stack
2962 ;; periodically.
2963 ;;
2964 ;; operands[1], the distance is a POSITIVE number indicating that we
2965 ;; are allocating stack space
2966 ;;
2967 (define_expand "allocate_stack"
2968 [(set (reg:SI 0)
2969 (plus:SI (reg:SI 0)
2970 (match_operand:SI 1 "general_operand" "")))
2971 (set (match_operand:SI 0 "register_operand" "=r")
2972 (match_dup 2))]
2973 ""
2974 "
2975 {
2976 /* If he wants no probing, just do it for him. */
2977 if (mcore_stack_increment == 0)
2978 {
2979 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,operands[1]));
2980 ;; emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
2981 DONE;
2982 }
2984 /* For small constant growth, we unroll the code. */
2985 if (GET_CODE (operands[1]) == CONST_INT
2986 && INTVAL (operands[1]) < 8 * STACK_UNITS_MAXSTEP)
2987 {
2988 HOST_WIDE_INT left = INTVAL(operands[1]);
2990 /* If it's a long way, get close enough for a last shot. */
2991 if (left >= STACK_UNITS_MAXSTEP)
2992 {
2993 rtx tmp = gen_reg_rtx (Pmode);
2994 emit_insn (gen_movsi (tmp, GEN_INT (STACK_UNITS_MAXSTEP)));
2995 do
2996 {
2997 rtx memref = gen_rtx_MEM (SImode, stack_pointer_rtx);
2999 MEM_VOLATILE_P (memref) = 1;
3000 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
3001 emit_insn (gen_movsi (memref, stack_pointer_rtx));
3002 left -= STACK_UNITS_MAXSTEP;
3003 }
3004 while (left > STACK_UNITS_MAXSTEP);
3005 }
3006 /* Perform the final adjustment. */
3007 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-left)));
3008 ;; emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
3009 DONE;
3010 }
3011 else
3012 {
3013 rtx_code_label *out_label = 0;
3014 rtx_code_label *loop_label = gen_label_rtx ();
3015 rtx step = gen_reg_rtx (Pmode);
3016 rtx tmp = gen_reg_rtx (Pmode);
3017 rtx test, memref;
3019 #if 1
3020 emit_insn (gen_movsi (tmp, operands[1]));
3021 emit_insn (gen_movsi (step, GEN_INT (STACK_UNITS_MAXSTEP)));
3023 if (GET_CODE (operands[1]) != CONST_INT)
3024 {
3025 out_label = gen_label_rtx ();
3026 test = gen_rtx_GEU (VOIDmode, step, tmp); /* quick out */
3027 emit_jump_insn (gen_cbranchsi4 (test, step, tmp, out_label));
3028 }
3030 /* Run a loop that steps it incrementally. */
3031 emit_label (loop_label);
3033 /* Extend a step, probe, and adjust remaining count. */
3034 emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx, step));
3035 memref = gen_rtx_MEM (SImode, stack_pointer_rtx);
3036 MEM_VOLATILE_P (memref) = 1;
3037 emit_insn(gen_movsi(memref, stack_pointer_rtx));
3038 emit_insn(gen_subsi3(tmp, tmp, step));
3040 /* Loop condition -- going back up. */
3041 test = gen_rtx_LTU (VOIDmode, step, tmp);
3042 emit_jump_insn (gen_cbranchsi4 (test, step, tmp, loop_label));
3044 if (out_label)
3045 emit_label (out_label);
3047 /* Bump the residual. */
3048 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
3049 ;; emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
3050 DONE;
3051 #else
3052 /* simple one-shot -- ensure register and do a subtract.
3053 * This does NOT comply with the ABI. */
3054 emit_insn (gen_movsi (tmp, operands[1]));
3055 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
3056 ;; emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
3057 DONE;
3058 #endif
3059 }
3060 }")