| blob | 06ff698bfe7ecb96e2e3dfc1df12852af83dca0b |
1 ;; Machine description for RISC-V Bit Manipulation operations.
2 ;; Copyright (C) 2021-2024 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
9 ;; any later version.
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; ZBA extension.
22 (define_insn "*zero_extendsidi2_bitmanip"
23 [(set (match_operand:DI 0 "register_operand" "=r,r")
24 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
25 "TARGET_64BIT && TARGET_ZBA && !TARGET_XTHEADMEMIDX"
26 "@
27 zext.w\t%0,%1
28 lwu\t%0,%1"
29 [(set_attr "type" "bitmanip,load")
30 (set_attr "mode" "DI")])
32 (define_insn "*shNadd"
33 [(set (match_operand:X 0 "register_operand" "=r")
34 (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
35 (match_operand:QI 2 "imm123_operand" "Ds3"))
36 (match_operand:X 3 "register_operand" "r")))]
37 "TARGET_ZBA"
38 "sh%2add\t%0,%1,%3"
39 [(set_attr "type" "bitmanip")
40 (set_attr "mode" "<X:MODE>")])
42 ; When using strength-reduction, we will reduce a multiplication to a
43 ; sequence of shifts and adds. If this is performed with 32-bit types
44 ; and followed by a division, the lack of w-form sh[123]add will make
45 ; combination impossible and lead to a slli + addw being generated.
46 ; Split the sequence with the knowledge that a w-form div will perform
47 ; implicit sign-extensions.
48 (define_split
49 [(set (match_operand:DI 0 "register_operand")
50 (sign_extend:DI (div:SI (plus:SI (ashift:SI (subreg:SI (match_operand:DI 1 "register_operand") 0)
51 (match_operand:QI 2 "imm123_operand"))
52 (subreg:SI (match_operand:DI 3 "register_operand") 0))
53 (match_operand:SI 4 "register_operand"))))
54 (clobber (match_operand:DI 5 "register_operand"))]
55 "TARGET_64BIT && TARGET_ZBA"
56 [(set (match_dup 5) (plus:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
57 (set (match_dup 0) (sign_extend:DI (div:SI (subreg:SI (match_dup 5) 0) (match_dup 4))))])
59 ; Zba does not provide W-forms of sh[123]add(.uw)?, which leads to an
60 ; interesting irregularity: we can generate a signed 32-bit result
61 ; using slli(.uw)?+ addw, but a unsigned 32-bit result can be more
62 ; efficiently be generated as sh[123]add+zext.w (the .uw can be
63 ; dropped, if we zero-extend the output anyway).
64 ;
65 ; To enable this optimization, we split [ slli(.uw)?, addw, zext.w ]
66 ; into [ sh[123]add, zext.w ] for use during combine.
67 (define_split
68 [(set (match_operand:DI 0 "register_operand")
69 (zero_extend:DI (plus:SI (ashift:SI (subreg:SI (match_operand:DI 1 "register_operand") 0)
70 (match_operand:QI 2 "imm123_operand"))
71 (subreg:SI (match_operand:DI 3 "register_operand") 0))))]
72 "TARGET_64BIT && TARGET_ZBA"
73 [(set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
74 (set (match_dup 0) (zero_extend:DI (subreg:SI (match_dup 0) 0)))])
76 (define_split
77 [(set (match_operand:DI 0 "register_operand")
78 (zero_extend:DI (plus:SI (subreg:SI (and:DI (ashift:DI (match_operand:DI 1 "register_operand")
79 (match_operand:QI 2 "imm123_operand"))
80 (match_operand:DI 3 "consecutive_bits_operand")) 0)
81 (subreg:SI (match_operand:DI 4 "register_operand") 0))))]
82 "TARGET_64BIT && TARGET_ZBA
83 && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))"
84 [(set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 4)))
85 (set (match_dup 0) (zero_extend:DI (subreg:SI (match_dup 0) 0)))])
87 ; Make sure that an andi followed by a sh[123]add remains a two instruction
88 ; sequence--and is not torn apart into slli, slri, add.
89 (define_insn_and_split "*andi_add.uw"
90 [(set (match_operand:DI 0 "register_operand" "=r")
91 (plus:DI (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
92 (match_operand:QI 2 "imm123_operand" "Ds3"))
93 (match_operand:DI 3 "consecutive_bits_operand" ""))
94 (match_operand:DI 4 "register_operand" "r")))
95 (clobber (match_scratch:DI 5 "=&r"))]
96 "TARGET_64BIT && TARGET_ZBA
97 && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
98 && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2]))"
99 "#"
100 "&& reload_completed"
101 [(set (match_dup 5) (and:DI (match_dup 1) (match_dup 3)))
102 (set (match_dup 0) (plus:DI (ashift:DI (match_dup 5) (match_dup 2))
103 (match_dup 4)))]
104 {
105 operands[3] = GEN_INT (INTVAL (operands[3]) >> INTVAL (operands[2]));
106 }
107 [(set_attr "type" "bitmanip")])
109 (define_insn "*shNadduw"
110 [(set (match_operand:DI 0 "register_operand" "=r")
111 (plus:DI
112 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
113 (match_operand:QI 2 "imm123_operand" "Ds3"))
114 (match_operand 3 "immediate_operand" "n"))
115 (match_operand:DI 4 "register_operand" "r")))]
116 "TARGET_64BIT && TARGET_ZBA
117 && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
118 "sh%2add.uw\t%0,%1,%4"
119 [(set_attr "type" "bitmanip")
120 (set_attr "mode" "DI")])
122 ;; During combine, we may encounter an attempt to combine
123 ;; slli rtmp, rs, #imm
124 ;; zext.w rtmp, rtmp
125 ;; sh[123]add rd, rtmp, rs2
126 ;; which will lead to the immediate not satisfying the above constraints.
127 ;; By splitting the compound expression, we can simplify to a slli and a
128 ;; sh[123]add.uw.
129 (define_split
130 [(set (match_operand:DI 0 "register_operand")
131 (plus:DI (and:DI (ashift:DI (match_operand:DI 1 "register_operand")
132 (match_operand:QI 2 "immediate_operand"))
133 (match_operand:DI 3 "consecutive_bits_operand"))
134 (match_operand:DI 4 "register_operand")))
135 (clobber (match_operand:DI 5 "register_operand"))]
136 "TARGET_64BIT && TARGET_ZBA"
137 [(set (match_dup 5) (ashift:DI (match_dup 1) (match_dup 6)))
138 (set (match_dup 0) (plus:DI (and:DI (ashift:DI (match_dup 5)
139 (match_dup 7))
140 (match_dup 8))
141 (match_dup 4)))]
142 {
143 unsigned HOST_WIDE_INT mask = UINTVAL (operands[3]);
144 /* scale: shift within the sh[123]add.uw */
145 unsigned HOST_WIDE_INT scale = 32 - clz_hwi (mask);
146 /* bias: pre-scale amount (i.e. the prior shift amount) */
147 int bias = ctz_hwi (mask) - scale;
149 /* If the bias + scale don't add up to operand[2], reject. */
150 if ((scale + bias) != UINTVAL (operands[2]))
151 FAIL;
153 /* If the shift-amount is out-of-range for sh[123]add.uw, reject. */
154 if ((scale < 1) || (scale > 3))
155 FAIL;
157 /* If there's no bias, the '*shNadduw' pattern should have matched. */
158 if (bias == 0)
159 FAIL;
161 operands[6] = GEN_INT (bias);
162 operands[7] = GEN_INT (scale);
163 operands[8] = GEN_INT (0xffffffffULL << scale);
164 })
166 (define_insn "*add.uw"
167 [(set (match_operand:DI 0 "register_operand" "=r")
168 (plus:DI (zero_extend:DI
169 (match_operand:SI 1 "register_operand" "r"))
170 (match_operand:DI 2 "register_operand" "r")))]
171 "TARGET_64BIT && TARGET_ZBA"
172 "add.uw\t%0,%1,%2"
173 [(set_attr "type" "bitmanip")
174 (set_attr "mode" "DI")])
176 (define_insn "*slliuw"
177 [(set (match_operand:DI 0 "register_operand" "=r")
178 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
179 (match_operand:QI 2 "immediate_operand" "I"))
180 (match_operand 3 "immediate_operand" "n")))]
181 "TARGET_64BIT && TARGET_ZBA
182 && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
183 "slli.uw\t%0,%1,%2"
184 [(set_attr "type" "bitmanip")
185 (set_attr "mode" "DI")])
187 ;; Combine will reassociate the operands in the most useful way here. We
188 ;; just have to give it guidance on where to split the result to facilitate
189 ;; shNadd.uw generation.
190 (define_split
191 [(set (match_operand:DI 0 "register_operand")
192 (plus:DI (plus:DI (and:DI (ashift:DI (match_operand:DI 1 "register_operand")
193 (match_operand:QI 2 "imm123_operand"))
194 (match_operand 3 "consecutive_bits32_operand"))
195 (match_operand:DI 4 "register_operand"))
196 (match_operand 5 "immediate_operand")))]
197 "TARGET_64BIT && TARGET_ZBA"
198 [(set (match_dup 0)
199 (plus:DI (and:DI (ashift:DI (match_dup 1) (match_dup 2))
200 (match_dup 3))
201 (match_dup 4)))
202 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 5)))])
204 ;; ZBB extension.
206 (define_expand "clzdi2"
207 [(set (match_operand:DI 0 "register_operand")
208 (clz:DI (match_operand:DI 1 "register_operand")))]
209 "TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB)")
211 (define_expand "clzsi2"
212 [(set (match_operand:SI 0 "register_operand")
213 (clz:SI (match_operand:SI 1 "register_operand")))]
214 "TARGET_ZBB || (!TARGET_64BIT && TARGET_XTHEADBB)")
216 (define_expand "ctz<mode>2"
217 [(set (match_operand:GPR 0 "register_operand")
218 (ctz:GPR (match_operand:GPR 1 "register_operand")))]
219 "TARGET_ZBB")
221 (define_expand "popcount<mode>2"
222 [(set (match_operand:GPR 0 "register_operand")
223 (popcount:GPR (match_operand:GPR 1 "register_operand")))]
224 "TARGET_ZBB")
226 (define_insn "<optab>_not<mode>3"
227 [(set (match_operand:X 0 "register_operand" "=r")
228 (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
229 (match_operand:X 2 "register_operand" "r")))]
230 "TARGET_ZBB || TARGET_ZBKB"
231 "<insn>n\t%0,%2,%1"
232 [(set_attr "type" "bitmanip")
233 (set_attr "mode" "<X:MODE>")])
235 (define_insn_and_split "*<optab>_not_const<mode>"
236 [(set (match_operand:X 0 "register_operand" "=r")
237 (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
238 (match_operand:X 2 "const_arith_operand" "I")))
239 (clobber (match_scratch:X 3 "=&r"))]
240 "(TARGET_ZBB || TARGET_ZBKB) && !TARGET_ZCB
241 && !optimize_function_for_size_p (cfun)"
242 "#"
243 "&& reload_completed"
244 [(set (match_dup 3) (match_dup 2))
245 (set (match_dup 0) (bitmanip_bitwise:X (not:X (match_dup 1)) (match_dup 3)))]
246 ""
247 [(set_attr "type" "bitmanip")])
249 ;; '(a >= 0) ? b : 0' is emitted branchless (from if-conversion). Without a
250 ;; bit of extra help for combine (i.e., the below split), we end up emitting
251 ;; not/srai/and instead of combining the not into an andn.
252 (define_split
253 [(set (match_operand:DI 0 "register_operand")
254 (and:DI (neg:DI (ge:DI (match_operand:DI 1 "register_operand")
255 (const_int 0)))
256 (match_operand:DI 2 "register_operand")))
257 (clobber (match_operand:DI 3 "register_operand"))]
258 "TARGET_ZBB || TARGET_ZBKB"
259 [(set (match_dup 3) (ashiftrt:DI (match_dup 1) (const_int 63)))
260 (set (match_dup 0) (and:DI (not:DI (match_dup 3)) (match_dup 2)))])
262 (define_insn "*xor_not<mode>"
263 [(set (match_operand:X 0 "register_operand" "=r")
264 (not:X (xor:X (match_operand:X 1 "register_operand" "r")
265 (match_operand:X 2 "register_operand" "r"))))]
266 "TARGET_ZBB || TARGET_ZBKB"
267 "xnor\t%0,%1,%2"
268 [(set_attr "type" "bitmanip")
269 (set_attr "mode" "<X:MODE>")])
271 (define_insn "*<bitmanip_optab>si2"
272 [(set (match_operand:SI 0 "register_operand" "=r")
273 (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
274 "TARGET_ZBB"
275 "<bitmanip_insn>%~\t%0,%1"
276 [(set_attr "type" "<bitmanip_insn>")
277 (set_attr "mode" "SI")])
279 (define_insn "*<bitmanip_optab>disi2"
280 [(set (match_operand:DI 0 "register_operand" "=r")
281 (any_extend:DI
282 (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))]
283 "TARGET_64BIT && TARGET_ZBB"
284 "<bitmanip_insn>w\t%0,%1"
285 [(set_attr "type" "<bitmanip_insn>")
286 (set_attr "mode" "SI")])
288 ;; A SImode clz_ctz_pcnt may be extended to DImode via subreg.
289 (define_insn "*<bitmanip_optab>disi2_sext"
290 [(set (match_operand:DI 0 "register_operand" "=r")
291 (and:DI (subreg:DI
292 (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")) 0)
293 (match_operand:DI 2 "const_int_operand")))]
294 "TARGET_64BIT && TARGET_ZBB && ((INTVAL (operands[2]) & 0x3f) == 0x3f)"
295 "<bitmanip_insn>w\t%0,%1"
296 [(set_attr "type" "<bitmanip_insn>")
297 (set_attr "mode" "SI")])
299 (define_insn "*<bitmanip_optab>di2"
300 [(set (match_operand:DI 0 "register_operand" "=r")
301 (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))]
302 "TARGET_64BIT && TARGET_ZBB"
303 "<bitmanip_insn>\t%0,%1"
304 [(set_attr "type" "<bitmanip_insn>")
305 (set_attr "mode" "DI")])
307 (define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
308 [(set (match_operand:GPR 0 "register_operand" "=r,r")
309 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
310 "TARGET_ZBB && !TARGET_XTHEADMEMIDX"
311 "@
312 zext.h\t%0,%1
313 lhu\t%0,%1"
314 [(set_attr "type" "bitmanip,load")
315 (set_attr "mode" "<GPR:MODE>")])
317 (define_insn "*extend<SHORT:mode><SUPERQI:mode>2_bitmanip"
318 [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
319 (sign_extend:SUPERQI
320 (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
321 "TARGET_ZBB && !TARGET_XTHEADMEMIDX"
322 "@
323 sext.<SHORT:size>\t%0,%1
324 l<SHORT:size>\t%0,%1"
325 [(set_attr "type" "bitmanip,load")
326 (set_attr "mode" "<SUPERQI:MODE>")])
328 (define_expand "rotrdi3"
329 [(set (match_operand:DI 0 "register_operand")
330 (rotatert:DI (match_operand:DI 1 "register_operand")
331 (match_operand:QI 2 "arith_operand")))]
332 "TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB || TARGET_ZBKB)"
333 {
334 if (TARGET_XTHEADBB && !immediate_operand (operands[2], VOIDmode))
335 FAIL;
336 })
338 (define_insn "*rotrsi3"
339 [(set (match_operand:SI 0 "register_operand" "=r")
340 (rotatert:SI (match_operand:SI 1 "register_operand" "r")
341 (match_operand:QI 2 "arith_operand" "rI")))]
342 "TARGET_ZBB || TARGET_ZBKB"
343 "ror%i2%~\t%0,%1,%2"
344 [(set_attr "type" "bitmanip")])
346 (define_expand "rotrsi3"
347 [(set (match_operand:SI 0 "register_operand" "=r")
348 (rotatert:SI (match_operand:SI 1 "register_operand" "r")
349 (match_operand:QI 2 "arith_operand" "rI")))]
350 "TARGET_ZBB || TARGET_ZBKB || TARGET_XTHEADBB"
351 {
352 if (TARGET_XTHEADBB && !immediate_operand (operands[2], VOIDmode))
353 FAIL;
354 if (TARGET_64BIT && register_operand (operands[2], QImode))
355 {
356 rtx t = gen_reg_rtx (DImode);
357 emit_insn (gen_rotrsi3_sext (t, operands[1], operands[2]));
358 t = gen_lowpart (SImode, t);
359 SUBREG_PROMOTED_VAR_P (t) = 1;
360 SUBREG_PROMOTED_SET (t, SRP_SIGNED);
361 emit_move_insn (operands[0], t);
362 DONE;
363 }
364 })
366 (define_insn "*rotrdi3"
367 [(set (match_operand:DI 0 "register_operand" "=r")
368 (rotatert:DI (match_operand:DI 1 "register_operand" "r")
369 (match_operand:QI 2 "arith_operand" "rI")))]
370 "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
371 "ror%i2\t%0,%1,%2"
372 [(set_attr "type" "bitmanip")])
374 (define_insn "rotrsi3_sext"
375 [(set (match_operand:DI 0 "register_operand" "=r")
376 (sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r")
377 (match_operand:QI 2 "arith_operand" "rI"))))]
378 "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
379 "ror%i2%~\t%0,%1,%2"
380 [(set_attr "type" "bitmanip")])
382 (define_insn "*rotlsi3"
383 [(set (match_operand:SI 0 "register_operand" "=r")
384 (rotate:SI (match_operand:SI 1 "register_operand" "r")
385 (match_operand:QI 2 "register_operand" "r")))]
386 "TARGET_ZBB || TARGET_ZBKB"
387 "rol%~\t%0,%1,%2"
388 [(set_attr "type" "bitmanip")])
390 (define_expand "rotlsi3"
391 [(set (match_operand:SI 0 "register_operand" "=r")
392 (rotate:SI (match_operand:SI 1 "register_operand" "r")
393 (match_operand:QI 2 "register_operand" "r")))]
394 "TARGET_ZBB || TARGET_ZBKB"
395 {
396 if (TARGET_64BIT)
397 {
398 rtx t = gen_reg_rtx (DImode);
399 emit_insn (gen_rotlsi3_sext (t, operands[1], operands[2]));
400 t = gen_lowpart (SImode, t);
401 SUBREG_PROMOTED_VAR_P (t) = 1;
402 SUBREG_PROMOTED_SET (t, SRP_SIGNED);
403 emit_move_insn (operands[0], t);
404 DONE;
405 }
406 })
408 (define_insn "rotldi3"
409 [(set (match_operand:DI 0 "register_operand" "=r")
410 (rotate:DI (match_operand:DI 1 "register_operand" "r")
411 (match_operand:QI 2 "register_operand" "r")))]
412 "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
413 "rol\t%0,%1,%2"
414 [(set_attr "type" "bitmanip")])
416 (define_insn "rotlsi3_sext"
417 [(set (match_operand:DI 0 "register_operand" "=r")
418 (sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
419 (match_operand:QI 2 "register_operand" "r"))))]
420 "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
421 "rolw\t%0,%1,%2"
422 [(set_attr "type" "bitmanip")])
424 (define_insn_and_split "*<bitmanip_optab><GPR:mode>3_mask"
425 [(set (match_operand:GPR 0 "register_operand" "= r")
426 (bitmanip_rotate:GPR
427 (match_operand:GPR 1 "register_operand" " r")
428 (match_operator 4 "subreg_lowpart_operator"
429 [(and:GPR2
430 (match_operand:GPR2 2 "register_operand" "r")
431 (match_operand 3 "<GPR:shiftm1>" "<GPR:shiftm1p>"))])))]
432 "TARGET_ZBB || TARGET_ZBKB"
433 "#"
434 "&& 1"
435 [(set (match_dup 0)
436 (bitmanip_rotate:GPR (match_dup 1)
437 (match_dup 2)))]
438 "operands[2] = gen_lowpart (QImode, operands[2]);"
439 [(set_attr "type" "bitmanip")
440 (set_attr "mode" "<GPR:MODE>")])
442 (define_insn_and_split "*<bitmanip_optab>si3_sext_mask"
443 [(set (match_operand:DI 0 "register_operand" "= r")
444 (sign_extend:DI (bitmanip_rotate:SI
445 (match_operand:SI 1 "register_operand" " r")
446 (match_operator 4 "subreg_lowpart_operator"
447 [(and:GPR
448 (match_operand:GPR 2 "register_operand" "r")
449 (match_operand 3 "const_si_mask_operand"))]))))]
450 "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
451 "#"
452 "&& 1"
453 [(set (match_dup 0)
454 (sign_extend:DI (bitmanip_rotate:SI (match_dup 1)
455 (match_dup 2))))]
456 "operands[2] = gen_lowpart (QImode, operands[2]);"
457 [(set_attr "type" "bitmanip")
458 (set_attr "mode" "DI")])
460 ;; orc.b (or-combine) is added as an unspec for the benefit of the support
461 ;; for optimized string functions (such as strcmp).
462 (define_insn "orcb<mode>2"
463 [(set (match_operand:GPR 0 "register_operand" "=r")
464 (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")] UNSPEC_ORC_B))]
465 "TARGET_ZBB"
466 "orc.b\t%0,%1"
467 [(set_attr "type" "bitmanip")])
469 (define_expand "bswapdi2"
470 [(set (match_operand:DI 0 "register_operand")
471 (bswap:DI (match_operand:DI 1 "register_operand")))]
472 "TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB || TARGET_ZBKB)")
474 (define_expand "bswapsi2"
475 [(set (match_operand:SI 0 "register_operand")
476 (bswap:SI (match_operand:SI 1 "register_operand")))]
477 "TARGET_ZBB || TARGET_ZBKB || TARGET_XTHEADBB"
478 {
479 /* Expose bswapsi2 on TARGET_64BIT so that the gimple store
480 merging pass will create suitable bswap insns. We can actually
481 just FAIL that case when generating RTL and let the generic code
482 handle it. */
483 if (TARGET_64BIT && !TARGET_XTHEADBB)
484 FAIL;
485 })
488 (define_insn "*bswap<mode>2"
489 [(set (match_operand:X 0 "register_operand" "=r")
490 (bswap:X (match_operand:X 1 "register_operand" "r")))]
491 "TARGET_ZBB || TARGET_ZBKB"
492 "rev8\t%0,%1"
493 [(set_attr "type" "bitmanip")])
495 ;; HI bswap can be emulated using SI/DI bswap followed
496 ;; by a logical shift right
497 ;; SI bswap for TARGET_64BIT is already similarly in
498 ;; the common code.
499 (define_expand "bswaphi2"
500 [(set (match_operand:HI 0 "register_operand" "=r")
501 (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
502 "TARGET_ZBB"
503 {
504 rtx tmp = gen_reg_rtx (word_mode);
505 rtx newop1 = gen_lowpart (word_mode, operands[1]);
506 if (TARGET_64BIT)
507 emit_insn (gen_bswapdi2 (tmp, newop1));
508 else
509 emit_insn (gen_bswapsi2 (tmp, newop1));
510 rtx tmp1 = gen_reg_rtx (word_mode);
511 if (TARGET_64BIT)
512 emit_insn (gen_lshrdi3 (tmp1, tmp, GEN_INT (64 - 16)));
513 else
514 emit_insn (gen_lshrsi3 (tmp1, tmp, GEN_INT (32 - 16)));
515 emit_move_insn (operands[0], gen_lowpart (HImode, tmp1));
516 DONE;
517 })
519 (define_expand "<bitmanip_optab>di3"
520 [(set (match_operand:DI 0 "register_operand" "=r")
521 (bitmanip_minmax:DI (match_operand:DI 1 "register_operand" "r")
522 (match_operand:DI 2 "register_operand" "r")))]
523 "TARGET_64BIT && TARGET_ZBB")
525 (define_expand "<bitmanip_optab>si3"
526 [(set (match_operand:SI 0 "register_operand" "=r")
527 (bitmanip_minmax:SI (match_operand:SI 1 "register_operand" "r")
528 (match_operand:SI 2 "register_operand" "r")))]
529 "TARGET_ZBB"
530 {
531 if (TARGET_64BIT)
532 {
533 rtx t = gen_reg_rtx (DImode);
534 operands[1] = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, operands[1]));
535 operands[2] = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, operands[2]));
536 emit_insn (gen_<bitmanip_optab>di3 (t, operands[1], operands[2]));
537 emit_move_insn (operands[0], gen_lowpart (SImode, t));
538 DONE;
539 }
540 })
542 (define_insn "*<bitmanip_optab><mode>3"
543 [(set (match_operand:X 0 "register_operand" "=r")
544 (bitmanip_minmax:X (match_operand:X 1 "register_operand" "r")
545 (match_operand:X 2 "reg_or_0_operand" "rJ")))]
546 "TARGET_ZBB"
547 "<bitmanip_insn>\t%0,%1,%z2"
548 [(set_attr "type" "<bitmanip_insn>")])
550 ;; Optimize the common case of a SImode min/max against a constant
551 ;; that is safe both for sign- and zero-extension.
552 (define_split
553 [(set (match_operand:DI 0 "register_operand")
554 (sign_extend:DI
555 (subreg:SI
556 (bitmanip_minmax:DI (zero_extend:DI
557 (match_operand:SI 1 "register_operand"))
558 (match_operand:DI 2 "immediate_operand")) 0)))
559 (clobber (match_operand:DI 3 "register_operand"))
560 (clobber (match_operand:DI 4 "register_operand"))]
561 "TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0"
562 [(set (match_dup 0) (<uminmax_optab>:DI (match_dup 4) (match_dup 3)))]
563 "
564 {
565 /* Load the constant into a register. */
566 emit_move_insn (operands[3], operands[2]);
568 /* If operands[1] is a sign extended SUBREG, then we can use it
569 directly. Otherwise extend it into another temporary. */
570 if (SUBREG_P (operands[1])
571 && SUBREG_PROMOTED_VAR_P (operands[1])
572 && SUBREG_PROMOTED_SIGNED_P (operands[1]))
573 operands[4] = SUBREG_REG (operands[1]);
574 else
575 emit_move_insn (operands[4], gen_rtx_SIGN_EXTEND (DImode, operands[1]));
577 /* The minmax is actually emitted from the split pattern. */
578 }")
580 ;; ZBS extension.
582 (define_insn "*<bit_optab><mode>"
583 [(set (match_operand:X 0 "register_operand" "=r")
584 (any_or:X (ashift:X (const_int 1)
585 (match_operand:QI 2 "register_operand" "r"))
586 (match_operand:X 1 "register_operand" "r")))]
587 "TARGET_ZBS"
588 "<bit_optab>\t%0,%1,%2"
589 [(set_attr "type" "bitmanip")])
591 (define_insn "*<bit_optab><mode>_mask"
592 [(set (match_operand:X 0 "register_operand" "=r")
593 (any_or:X
594 (ashift:X
595 (const_int 1)
596 (subreg:QI
597 (and:X (match_operand:X 2 "register_operand" "r")
598 (match_operand 3 "<X:shiftm1>" "<X:shiftm1p>")) 0))
599 (match_operand:X 1 "register_operand" "r")))]
600 "TARGET_ZBS"
601 "<bit_optab>\t%0,%1,%2"
602 [(set_attr "type" "bitmanip")])
604 (define_insn "*bset<mode>_1"
605 [(set (match_operand:X 0 "register_operand" "=r")
606 (ashift:X (const_int 1)
607 (match_operand:QI 1 "register_operand" "r")))]
608 "TARGET_ZBS"
609 "bset\t%0,x0,%1"
610 [(set_attr "type" "bitmanip")])
612 ;; The result will always have bits 32..63 clear, so the zero-extend
613 ;; is redundant. We could split it to bset<mode>_1, but it seems
614 ;; unnecessary.
615 (define_insn "*bsetdi_2"
616 [(set (match_operand:DI 0 "register_operand" "=r")
617 (zero_extend:DI
618 (ashift:SI (const_int 1)
619 (match_operand:QI 1 "register_operand" "r"))))]
620 "TARGET_64BIT && TARGET_ZBS"
621 "bset\t%0,x0,%1"
622 [(set_attr "type" "bitmanip")])
624 ;; These two splitters take advantage of the limited range of the
625 ;; shift constant. With the limited range we know the SImode sign
626 ;; bit is never set, thus we can treat this as zero extending and
627 ;; generate the bsetdi_2 pattern.
628 (define_insn_and_split ""
629 [(set (match_operand:DI 0 "register_operand" "=r")
630 (any_extend:DI
631 (ashift:SI (const_int 1)
632 (subreg:QI
633 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
634 (match_operand 2 "const_int_operand")) 0))))
635 (clobber (match_scratch:X 3 "=&r"))]
636 "TARGET_64BIT
637 && TARGET_ZBS
638 && (TARGET_ZBB || TARGET_ZBKB)
639 && (INTVAL (operands[2]) & 0x1f) != 0x1f"
640 "#"
641 "&& reload_completed"
642 [(set (match_dup 3) (match_dup 2))
643 (set (match_dup 3) (and:DI (not:DI (match_dup 1)) (match_dup 3)))
644 (set (match_dup 0) (zero_extend:DI
645 (ashift:SI (const_int 1) (match_dup 4))))]
646 {
647 operands[4] = gen_lowpart (QImode, operands[3]);
648 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
649 }
650 [(set_attr "type" "bitmanip")])
652 (define_insn_and_split ""
653 [(set (match_operand:DI 0 "register_operand" "=r")
654 (any_extend:DI
655 (ashift:SI (const_int 1)
656 (subreg:QI
657 (and:DI (match_operand:DI 1 "register_operand" "r")
658 (match_operand 2 "const_int_operand")) 0))))]
659 "TARGET_64BIT
660 && TARGET_ZBS
661 && (INTVAL (operands[2]) & 0x1f) != 0x1f"
662 "#"
663 "&& 1"
664 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 2)))
665 (set (match_dup 0) (zero_extend:DI (ashift:SI
666 (const_int 1)
667 (subreg:QI (match_dup 0) 0))))]
668 { operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); }
669 [(set_attr "type" "bitmanip")])
671 ;; Similarly two patterns for IOR/XOR generating bset/binv to
672 ;; manipulate a bit in a register
673 (define_insn_and_split ""
674 [(set (match_operand:DI 0 "register_operand" "=r")
675 (any_or:DI
676 (any_extend:DI
677 (ashift:SI
678 (const_int 1)
679 (subreg:QI
680 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
681 (match_operand 2 "const_int_operand")) 0)))
682 (match_operand:DI 3 "register_operand" "r")))
683 (clobber (match_scratch:X 4 "=&r"))]
684 "TARGET_64BIT
685 && TARGET_ZBS
686 && (TARGET_ZBB || TARGET_ZBKB)
687 && (INTVAL (operands[2]) & 0x1f) != 0x1f"
688 "#"
689 "&& reload_completed"
690 [(set (match_dup 4) (match_dup 2))
691 (set (match_dup 4) (and:DI (not:DI (match_dup 1)) (match_dup 4)))
692 (set (match_dup 0) (any_or:DI (ashift:DI (const_int 1) (match_dup 5)) (match_dup 3)))]
693 {
694 operands[5] = gen_lowpart (QImode, operands[4]);
695 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
696 }
697 [(set_attr "type" "bitmanip")])
699 (define_insn_and_split ""
700 [(set (match_operand:DI 0 "register_operand" "=r")
701 (any_or:DI
702 (any_extend:DI
703 (ashift:SI
704 (const_int 1)
705 (subreg:QI
706 (and:DI (match_operand:DI 1 "register_operand" "r")
707 (match_operand 2 "const_int_operand")) 0)))
708 (match_operand:DI 3 "register_operand" "r")))
709 (clobber (match_scratch:X 4 "=&r"))]
710 "TARGET_64BIT
711 && TARGET_ZBS
712 && (INTVAL (operands[2]) & 0x1f) != 0x1f"
713 "#"
714 "&& reload_completed"
715 [(set (match_dup 4) (and:DI (match_dup 1) (match_dup 2)))
716 (set (match_dup 0) (any_or:DI (ashift:DI (const_int 1) (subreg:QI (match_dup 4) 0)) (match_dup 3)))]
717 { operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); }
718 [(set_attr "type" "bitmanip")])
720 ;; Similarly two patterns for AND generating bclr to
721 ;; manipulate a bit in a register
722 (define_insn_and_split ""
723 [(set (match_operand:DI 0 "register_operand" "=r")
724 (and:DI
725 (not:DI
726 (any_extend:DI
727 (ashift:SI
728 (const_int 1)
729 (subreg:QI
730 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
731 (match_operand 2 "const_int_operand")) 0))))
732 (match_operand:DI 3 "register_operand" "r")))
733 (clobber (match_scratch:X 4 "=&r"))]
734 "TARGET_64BIT
735 && TARGET_ZBS
736 && (TARGET_ZBB || TARGET_ZBKB)
737 && (INTVAL (operands[2]) & 0x1f) != 0x1f"
738 "#"
739 "&& reload_completed"
740 [(set (match_dup 4) (match_dup 2))
741 (set (match_dup 4) (and:DI (not:DI (match_dup 1)) (match_dup 4)))
742 (set (match_dup 0) (and:DI (rotate:DI (const_int -2) (match_dup 5)) (match_dup 3)))]
743 {
744 operands[5] = gen_lowpart (QImode, operands[4]);
745 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
746 }
747 [(set_attr "type" "bitmanip")])
750 (define_insn_and_split ""
751 [(set (match_operand:DI 0 "register_operand" "=r")
752 (and:DI
753 (not:DI
754 (any_extend:DI
755 (ashift:SI
756 (const_int 1)
757 (subreg:QI
758 (and:DI (match_operand:DI 1 "register_operand" "r")
759 (match_operand 2 "const_int_operand")) 0))))
760 (match_operand:DI 3 "register_operand" "r")))
761 (clobber (match_scratch:X 4 "=&r"))]
762 "TARGET_64BIT
763 && TARGET_ZBS
764 && (INTVAL (operands[2]) & 0x1f) != 0x1f"
765 "#"
766 "&& reload_completed"
767 [(set (match_dup 4) (and:DI (match_dup 1) (match_dup 2)))
768 (set (match_dup 0) (and:DI (rotate:DI (const_int -2) (match_dup 5)) (match_dup 3)))]
769 {
770 operands[5] = gen_lowpart (QImode, operands[4]);
771 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
772 }
773 [(set_attr "type" "bitmanip")])
775 (define_insn "*bset<mode>_1_mask"
776 [(set (match_operand:X 0 "register_operand" "=r")
777 (ashift:X (const_int 1)
778 (subreg:QI
779 (and:X (match_operand:X 1 "register_operand" "r")
780 (match_operand 2 "<X:shiftm1>" "<X:shiftm1p>")) 0)))]
781 "TARGET_ZBS"
782 "bset\t%0,x0,%1"
783 [(set_attr "type" "bitmanip")])
785 (define_insn "*<bit_optab>i<mode>"
786 [(set (match_operand:X 0 "register_operand" "=r")
787 (any_or:X (match_operand:X 1 "register_operand" "r")
788 (match_operand:X 2 "single_bit_mask_operand" "DbS")))]
789 "TARGET_ZBS"
790 "<bit_optab>i\t%0,%1,%S2"
791 [(set_attr "type" "bitmanip")])
793 ;; As long as the SImode operand is not a partial subreg, we can use a
794 ;; bseti without postprocessing, as the middle end is smart enough to
795 ;; stay away from the signbit.
796 (define_insn "*<bit_optab>idisi"
797 [(set (match_operand:DI 0 "register_operand" "=r")
798 (any_or:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
799 (match_operand 2 "single_bit_mask_operand" "i")))]
800 "TARGET_ZBS && TARGET_64BIT
801 && !partial_subreg_p (operands[1])"
802 "<bit_optab>i\t%0,%1,%S2"
803 [(set_attr "type" "bitmanip")])
805 ;; We can easily handle zero extensions
806 (define_split
807 [(set (match_operand:DI 0 "register_operand")
808 (any_or:DI (zero_extend:DI
809 (ashift:SI (const_int 1)
810 (match_operand:QI 1 "register_operand")))
811 (match_operand:DI 2 "single_bit_mask_operand")))
812 (clobber (match_operand:DI 3 "register_operand"))]
813 "TARGET_64BIT && TARGET_ZBS"
814 [(set (match_dup 3)
815 (match_dup 2))
816 (set (match_dup 0)
817 (any_or:DI (ashift:DI (const_int 1) (match_dup 1))
818 (match_dup 3)))])
820 ;; Yet another form of a bset/bclr that can be created by combine.
821 (define_insn "*bsetclr_zero_extract"
822 [(set (zero_extract:X (match_operand:X 0 "register_operand" "+r")
823 (const_int 1)
824 (zero_extend:X
825 (match_operand:QI 1 "register_operand" "r")))
826 (match_operand 2 "immediate_operand" "n"))]
827 "TARGET_ZBS
828 && (operands[2] == CONST0_RTX (<MODE>mode)
829 || operands[2] == CONST1_RTX (<MODE>mode))"
830 {
831 return (operands[2] == CONST0_RTX (<MODE>mode)
832 ? "bclr\t%0,%0,%1"
833 : "bset\t%0,%0,%1");
834 }
835 [(set_attr "type" "bitmanip")])
837 (define_insn "*bclr<mode>"
838 [(set (match_operand:X 0 "register_operand" "=r")
839 (and:X (rotate:X (const_int -2)
840 (match_operand:QI 2 "register_operand" "r"))
841 (match_operand:X 1 "register_operand" "r")))]
842 "TARGET_ZBS"
843 "bclr\t%0,%1,%2"
844 [(set_attr "type" "bitmanip")])
846 (define_insn "*bclri<mode>"
847 [(set (match_operand:X 0 "register_operand" "=r")
848 (and:X (match_operand:X 1 "register_operand" "r")
849 (match_operand:X 2 "not_single_bit_mask_operand" "DnS")))]
850 "TARGET_ZBS"
851 "bclri\t%0,%1,%T2"
852 [(set_attr "type" "bitmanip")])
854 ;; In case we have "val & ~IMM" where ~IMM has 2 bits set.
855 (define_insn_and_split "*bclri<mode>_nottwobits"
856 [(set (match_operand:X 0 "register_operand" "=r")
857 (and:X (match_operand:X 1 "register_operand" "r")
858 (match_operand:X 2 "const_nottwobits_not_arith_operand" "i")))]
859 "TARGET_ZBS && !paradoxical_subreg_p (operands[1])"
860 "#"
861 "&& reload_completed"
862 [(set (match_dup 0) (and:X (match_dup 1) (match_dup 3)))
863 (set (match_dup 0) (and:X (match_dup 0) (match_dup 4)))]
864 {
865 unsigned HOST_WIDE_INT bits = ~UINTVAL (operands[2]);
866 unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (bits);
868 operands[3] = GEN_INT (~bits | topbit);
869 operands[4] = GEN_INT (~topbit);
870 }
871 [(set_attr "type" "bitmanip")])
873 ;; In case of a paradoxical subreg, the sign bit and the high bits are
874 ;; not allowed to be changed
875 (define_insn_and_split "*bclridisi_nottwobits"
876 [(set (match_operand:DI 0 "register_operand" "=r")
877 (and:DI (match_operand:DI 1 "register_operand" "r")
878 (match_operand:DI 2 "const_nottwobits_not_arith_operand" "i")))]
879 "TARGET_64BIT && TARGET_ZBS
880 && clz_hwi (~UINTVAL (operands[2])) > 33"
881 "#"
882 "&& reload_completed"
883 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
884 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
885 {
886 unsigned HOST_WIDE_INT bits = ~UINTVAL (operands[2]);
887 unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (bits);
889 operands[3] = GEN_INT (~bits | topbit);
890 operands[4] = GEN_INT (~topbit);
891 }
892 [(set_attr "type" "bitmanip")])
894 ;; An outer AND with a constant where bits 31..63 are 0 can be seen as
895 ;; a virtual zero extension from 31 to 64 bits.
896 (define_split
897 [(set (match_operand:DI 0 "register_operand")
898 (and:DI (not:DI (subreg:DI
899 (ashift:SI (const_int 1)
900 (match_operand:QI 1 "register_operand")) 0))
901 (match_operand:DI 2 "arith_operand")))
902 (clobber (match_operand:DI 3 "register_operand"))]
903 "TARGET_64BIT && TARGET_ZBS
904 && clz_hwi (INTVAL (operands[2])) >= 33"
905 [(set (match_dup 3)
906 (match_dup 2))
907 (set (match_dup 0)
908 (and:DI (rotate:DI (const_int -2) (match_dup 1))
909 (match_dup 3)))])
911 (define_insn "*bext<mode>"
912 [(set (match_operand:X 0 "register_operand" "=r")
913 (zero_extract:X (match_operand:X 1 "register_operand" "r")
914 (const_int 1)
915 (zero_extend:X
916 (match_operand:QI 2 "register_operand" "r"))))]
917 "TARGET_ZBS"
918 "bext\t%0,%1,%2"
919 [(set_attr "type" "bitmanip")])
921 ;; This is a bext followed by a seqz. Normally this would be a 3->2 split
922 ;; But the and-not pattern with a constant operand is a define_insn_and_split,
923 ;; so this looks like a 2->2 split, which combine rejects. So implement it
924 ;; as a define_insn_and_split as well.
925 (define_insn_and_split "*bextseqzdisi"
926 [(set (match_operand:DI 0 "register_operand" "=r")
927 (and:DI
928 (not:DI
929 (subreg:DI
930 (lshiftrt:SI
931 (match_operand:SI 1 "register_operand" "r")
932 (match_operand:QI 2 "register_operand" "r")) 0))
933 (const_int 1)))]
934 "TARGET_64BIT && TARGET_ZBS"
935 "#"
936 "&& 1"
937 [(set (match_dup 0)
938 (zero_extract:DI (match_dup 1)
939 (const_int 1)
940 (zero_extend:DI (match_dup 2))))
941 (set (match_dup 0) (eq:DI (match_dup 0) (const_int 0)))]
942 "operands[1] = gen_lowpart (word_mode, operands[1]);"
943 [(set_attr "type" "bitmanip")])
945 (define_insn_and_split "*bextseqzdisi"
946 [(set (match_operand:X 0 "register_operand" "=r")
947 (and:X
948 (not:X
949 (lshiftrt:X
950 (match_operand:X 1 "register_operand" "r")
951 (match_operand:QI 2 "register_operand" "r")))
952 (const_int 1)))]
953 "TARGET_ZBS"
954 "#"
955 "&& 1"
956 [(set (match_dup 0)
957 (zero_extract:X (match_dup 1)
958 (const_int 1)
959 (zero_extend:X (match_dup 2))))
960 (set (match_dup 0) (eq:X (match_dup 0) (const_int 0)))]
961 "operands[1] = gen_lowpart (word_mode, operands[1]);"
962 [(set_attr "type" "bitmanip")])
964 ;; The logical-and against 0x1 implicitly extends the result. So we can treat
965 ;; an SImode bext as-if it's DImode without any explicit extension.
966 (define_insn "*bextdisi"
967 [(set (match_operand:DI 0 "register_operand" "=r")
968 (and:DI (subreg:DI (lshiftrt:SI
969 (match_operand:SI 1 "register_operand" "r")
970 (match_operand:QI 2 "register_operand" "r")) 0)
971 (const_int 1)))]
972 "TARGET_64BIT && TARGET_ZBS"
973 "bext\t%0,%1,%2"
974 [(set_attr "type" "bitmanip")])
976 ;; When performing `(a & (1UL << bitno)) ? 0 : -1` the combiner
977 ;; usually has the `bitno` typed as X-mode (i.e. no further
978 ;; zero-extension is performed around the bitno).
979 (define_insn "*bext<mode>"
980 [(set (match_operand:X 0 "register_operand" "=r")
981 (zero_extract:X (match_operand:X 1 "register_operand" "r")
982 (const_int 1)
983 (match_operand:X 2 "register_operand" "r")))]
984 "TARGET_ZBS"
985 "bext\t%0,%1,%2"
986 [(set_attr "type" "bitmanip")])
988 (define_insn "*bexti"
989 [(set (match_operand:X 0 "register_operand" "=r")
990 (zero_extract:X (match_operand:X 1 "register_operand" "r")
991 (const_int 1)
992 (match_operand 2 "immediate_operand" "n")))]
993 "TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
994 "bexti\t%0,%1,%2"
995 [(set_attr "type" "bitmanip")])
997 ;; Split for "(a & (1 << BIT_NO)) ? 0 : 1":
998 ;; We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1",
999 ;; so we don't have to use a temporary. Instead we extract the bit and then
1000 ;; invert bit 0 ("a ^ 1") only.
1001 (define_split
1002 [(set (match_operand:X 0 "register_operand")
1003 (and:X (not:X (lshiftrt:X (match_operand:X 1 "register_operand")
1004 (match_operand:QI 2 "register_operand")))
1005 (const_int 1)))]
1006 "TARGET_ZBS"
1007 [(set (match_dup 0) (zero_extract:X (match_dup 1)
1008 (const_int 1)
1009 (match_dup 2)))
1010 (set (match_dup 0) (xor:X (match_dup 0) (const_int 1)))]
1011 "operands[2] = gen_lowpart (<MODE>mode, operands[2]);")
1013 ;; We can create a polarity-reversed mask (i.e. bit N -> { set = 0, clear = -1 })
1014 ;; using a bext(i) followed by an addi instruction.
1015 ;; This splits the canonical representation of "(a & (1 << BIT_NO)) ? 0 : -1".
1016 (define_split
1017 [(set (match_operand:GPR 0 "register_operand")
1018 (neg:GPR (eq:GPR (zero_extract:GPR (match_operand:GPR 1 "register_operand")
1019 (const_int 1)
1020 (match_operand 2))
1021 (const_int 0))))]
1022 "TARGET_ZBS"
1023 [(set (match_dup 0) (zero_extract:GPR (match_dup 1) (const_int 1) (match_dup 2)))
1024 (set (match_dup 0) (plus:GPR (match_dup 0) (const_int -1)))])
1026 ;; Catch those cases where we can use a bseti/binvi + ori/xori or
1027 ;; bseti/binvi + bseti/binvi instead of a lui + addi + or/xor sequence.
1028 (define_insn_and_split "*<or_optab>i<mode>_extrabit"
1029 [(set (match_operand:X 0 "register_operand" "=r")
1030 (any_or:X (match_operand:X 1 "register_operand" "r")
1031 (match_operand:X 2 "uimm_extra_bit_or_twobits" "i")))]
1032 "TARGET_ZBS"
1033 "#"
1034 "&& reload_completed"
1035 [(set (match_dup 0) (<or_optab>:X (match_dup 1) (match_dup 3)))
1036 (set (match_dup 0) (<or_optab>:X (match_dup 0) (match_dup 4)))]
1037 {
1038 unsigned HOST_WIDE_INT bits = UINTVAL (operands[2]);
1039 unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (bits);
1041 operands[3] = GEN_INT (bits &~ topbit);
1042 operands[4] = GEN_INT (topbit);
1043 }
1044 [(set_attr "type" "bitmanip")])
1046 ;; Same to use blcri + andi and blcri + bclri
1047 (define_insn_and_split "*andi<mode>_extrabit"
1048 [(set (match_operand:X 0 "register_operand" "=r")
1049 (and:X (match_operand:X 1 "register_operand" "r")
1050 (match_operand:X 2 "not_uimm_extra_bit_or_nottwobits" "i")))]
1051 "TARGET_ZBS"
1052 "#"
1053 "&& reload_completed"
1054 [(set (match_dup 0) (and:X (match_dup 1) (match_dup 3)))
1055 (set (match_dup 0) (and:X (match_dup 0) (match_dup 4)))]
1056 {
1057 unsigned HOST_WIDE_INT bits = UINTVAL (operands[2]);
1058 unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (~bits);
1060 operands[3] = GEN_INT (bits | topbit);
1061 operands[4] = GEN_INT (~topbit);
1062 }
1063 [(set_attr "type" "bitmanip")])
1065 ;; If we have the ZBA extension, then we can clear the upper half of a 64
1066 ;; bit object with a zext.w. So if we have AND where the constant would
1067 ;; require synthesis of two or more instructions, but 32->64 sign extension
1068 ;; of the constant is a simm12, then we can use zext.w+andi. If the adjusted
1069 ;; constant is a single bit constant, then we can use zext.w+bclri
1070 ;;
1071 ;; With the mvconst_internal pattern claiming a single insn to synthesize
1072 ;; constants, this must be a define_insn_and_split.
1073 (define_insn_and_split ""
1074 [(set (match_operand:DI 0 "register_operand" "=r")
1075 (and:DI (match_operand:DI 1 "register_operand" "r")
1076 (match_operand 2 "const_int_operand" "n")))]
1077 "TARGET_64BIT
1078 && TARGET_ZBA
1079 && !paradoxical_subreg_p (operands[1])
1080 /* Only profitable if synthesis takes more than one insn. */
1081 && riscv_const_insns (operands[2], false) != 1
1082 /* We need the upper half to be zero. */
1083 && (INTVAL (operands[2]) & HOST_WIDE_INT_C (0xffffffff00000000)) == 0
1084 /* And the the adjusted constant must either be something we can
1085 implement with andi or bclri. */
1086 && ((SMALL_OPERAND (sext_hwi (INTVAL (operands[2]), 32))
1087 || (TARGET_ZBS && popcount_hwi (INTVAL (operands[2])) == 31))
1088 && INTVAL (operands[2]) != 0x7fffffff)"
1089 "#"
1090 "&& 1"
1091 [(set (match_dup 0) (zero_extend:DI (match_dup 3)))
1092 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 2)))]
1093 "{
1094 operands[3] = gen_lowpart (SImode, operands[1]);
1095 operands[2] = GEN_INT (sext_hwi (INTVAL (operands[2]), 32));
1096 }"
1097 [(set_attr "type" "bitmanip")])
1099 ;; IF_THEN_ELSE: test for 2 bits of opposite polarity
1100 (define_insn_and_split "*branch<X:mode>_mask_twobits_equals_singlebit"
1101 [(set (pc)
1102 (if_then_else
1103 (match_operator 1 "equality_operator"
1104 [(and:X (match_operand:X 2 "register_operand" "r")
1105 (match_operand:X 3 "const_twobits_not_arith_operand" "i"))
1106 (match_operand:X 4 "single_bit_mask_operand" "i")])
1107 (label_ref (match_operand 0 "" ""))
1108 (pc)))
1109 (clobber (match_scratch:X 5 "=&r"))
1110 (clobber (match_scratch:X 6 "=&r"))]
1111 "TARGET_ZBS && TARGET_ZBB"
1112 "#"
1113 "&& reload_completed"
1114 [(set (match_dup 5) (zero_extract:X (match_dup 2)
1115 (const_int 1)
1116 (match_dup 8)))
1117 (set (match_dup 6) (zero_extract:X (match_dup 2)
1118 (const_int 1)
1119 (match_dup 9)))
1120 (set (match_dup 6) (and:X (not:X (match_dup 6)) (match_dup 5)))
1121 (set (pc) (if_then_else (match_op_dup 1 [(match_dup 6) (const_int 0)])
1122 (label_ref (match_dup 0))
1123 (pc)))]
1124 {
1125 unsigned HOST_WIDE_INT twobits_mask = UINTVAL (operands[3]);
1126 unsigned HOST_WIDE_INT singlebit_mask = UINTVAL (operands[4]);
1128 /* We should never see an unsatisfiable condition. */
1129 gcc_assert (twobits_mask & singlebit_mask);
1131 int setbit = ctz_hwi (singlebit_mask);
1132 int clearbit = ctz_hwi (twobits_mask & ~singlebit_mask);
1134 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == NE ? EQ : NE,
1135 <X:MODE>mode, operands[6], GEN_INT(0));
1137 operands[8] = GEN_INT (setbit);
1138 operands[9] = GEN_INT (clearbit);
1139 }
1140 [(set_attr "type" "bitmanip")])
1142 ;; IF_THEN_ELSE: test for (a & (1 << BIT_NO))
1143 (define_insn_and_split "*branch<X:mode>_bext"
1144 [(set (pc)
1145 (if_then_else
1146 (match_operator 1 "equality_operator"
1147 [(zero_extract:X (match_operand:X 2 "register_operand" "r")
1148 (const_int 1)
1149 (zero_extend:X
1150 (match_operand:QI 3 "register_operand" "r")))
1151 (const_int 0)])
1152 (label_ref (match_operand 0 "" ""))
1153 (pc)))
1154 (clobber (match_scratch:X 4 "=&r"))]
1155 "TARGET_ZBS"
1156 "#"
1157 "&& reload_completed"
1158 [(set (match_dup 4) (zero_extract:X (match_dup 2)
1159 (const_int 1)
1160 (zero_extend:X (match_dup 3))))
1161 (set (pc) (if_then_else (match_op_dup 1 [(match_dup 4) (const_int 0)])
1162 (label_ref (match_dup 0))
1163 (pc)))]
1164 ""
1165 [(set_attr "type" "bitmanip")])
1167 ;; ZBKC or ZBC extension
1168 (define_insn "riscv_clmul_<mode>"
1169 [(set (match_operand:GPR 0 "register_operand" "=r")
1170 (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
1171 (match_operand:GPR 2 "register_operand" "r")]
1172 UNSPEC_CLMUL))]
1173 "TARGET_ZBKC || TARGET_ZBC"
1174 "clmul\t%0,%1,%2"
1175 [(set_attr "type" "clmul")])
1177 (define_insn "riscv_clmulh_<mode>"
1178 [(set (match_operand:X 0 "register_operand" "=r")
1179 (unspec:X [(match_operand:X 1 "register_operand" "r")
1180 (match_operand:X 2 "register_operand" "r")]
1181 UNSPEC_CLMULH))]
1182 "TARGET_ZBKC || TARGET_ZBC"
1183 "clmulh\t%0,%1,%2"
1184 [(set_attr "type" "clmul")])
1186 ;; ZBC extension
1187 (define_insn "riscv_clmulr_<mode>"
1188 [(set (match_operand:X 0 "register_operand" "=r")
1189 (unspec:X [(match_operand:X 1 "register_operand" "r")
1190 (match_operand:X 2 "register_operand" "r")]
1191 UNSPEC_CLMULR))]
1192 "TARGET_ZBC"
1193 "clmulr\t%0,%1,%2"
1194 [(set_attr "type" "clmul")])