| blob | e111cb07284028646dd61302e35234e197ae10ed |
1 /* Subroutines used for code generation for RISC-V.
2 Copyright (C) 2011-2024 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #define IN_TARGET_CODE 1
24 #define INCLUDE_MEMORY
25 #define INCLUDE_STRING
81 /* This file should be included last. */
86 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
87 #define UNSPEC_ADDRESS_P(X) \
88 (GET_CODE (X) == UNSPEC \
89 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
90 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
92 /* Extract the symbol or label from UNSPEC wrapper X. */
93 #define UNSPEC_ADDRESS(X) \
94 XVECEXP (X, 0, 0)
96 /* Extract the symbol type from UNSPEC wrapper X. */
97 #define UNSPEC_ADDRESS_TYPE(X) \
98 ((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
100 /* Extract the backup dynamic frm rtl. */
101 #define DYNAMIC_FRM_RTL(c) ((c)->machine->mode_sw_info.dynamic_frm)
103 /* True the mode switching has static frm, or false. */
104 #define STATIC_FRM_P(c) ((c)->machine->mode_sw_info.static_frm_p)
106 /* True if we can use the instructions in the XTheadInt extension
107 to handle interrupts, or false. */
108 #define TH_INT_INTERRUPT(c) \
109 (TARGET_XTHEADINT \
111 && !TARGET_64BIT \
112 && (c)->machine->interrupt_handler_p \
114 && (c)->machine->interrupt_mode == MACHINE_MODE)
116 /* Information about a function's frame layout. */
118 /* The size of the frame in bytes. */
119 poly_int64 total_size;
121 /* Bit X is set if the function saves or restores GPR X. */
124 /* Likewise FPR X. */
127 /* Likewise for vector registers. */
130 /* How much the GPR save/restore routines adjust sp (or 0 if unused). */
133 /* the minimum number of bytes, in multiples of 16-byte address increments,
134 required to cover the registers in a multi push & pop. */
137 /* the number of additional 16-byte address increments allocated for the stack
138 frame in a multi push & pop. */
141 /* Offsets of fixed-point and floating-point save areas from frame bottom */
142 poly_int64 gp_sp_offset;
143 poly_int64 fp_sp_offset;
145 /* Top and bottom offsets of vector save areas from frame bottom. */
146 poly_int64 v_sp_offset_top;
147 poly_int64 v_sp_offset_bottom;
149 /* Offset of virtual frame pointer from stack pointer/frame bottom */
150 poly_int64 frame_pointer_offset;
152 /* Offset of hard frame pointer from stack pointer/frame bottom */
153 poly_int64 hard_frame_pointer_offset;
155 /* The offset of arg_pointer_rtx from the bottom of the frame. */
156 poly_int64 arg_pointer_offset;
158 /* Reset this struct, clean all field to zero. */
160 };
164 };
167 /* The RTL variable which stores the dynamic FRM value. We always use this
168 RTX to restore dynamic FRM rounding mode in mode switching. */
169 rtx dynamic_frm;
171 /* The boolean variables indicates there is at least one static rounding
172 mode instruction in the function or not. */
176 {
179 }
180 };
183 /* The number of extra stack bytes taken up by register varargs.
184 This area is allocated by the callee at the very top of the frame. */
187 /* True if current function is a naked function. */
190 /* True if current function is an interrupt function. */
192 /* For an interrupt handler, indicates the privilege level. */
195 /* True if attributes on current function have been checked. */
198 /* True if RA must be saved because of a far jump. */
201 /* The current frame information, calculated by riscv_compute_frame_info. */
204 /* The components already handled by separate shrink-wrapping, which should
205 not be considered by the prologue and epilogue. */
208 /* The mode switching information for the FRM rounding modes. */
210 };
212 /* Information about a single argument. */
214 /* True if the argument is at least partially passed on the stack. */
217 /* The number of integer registers allocated to this argument. */
220 /* The offset of the first register used, provided num_gprs is nonzero.
221 If passed entirely on the stack, the value is MAX_ARGS_IN_REGISTERS. */
224 /* The number of floating-point registers allocated to this argument. */
227 /* The offset of the first register used, provided num_fprs is nonzero. */
230 /* The number of vector registers allocated to this argument. */
233 /* The offset of the first register used, provided num_vrs is nonzero. */
236 /* The number of mask registers allocated to this argument. */
239 /* The offset of the first register used, provided num_mrs is nonzero. */
241 };
243 /* One stage in a constant building sequence. These sequences have
244 the form:
246 A = VALUE[0]
247 A = A CODE[1] VALUE[1]
248 A = A CODE[2] VALUE[2]
249 ...
251 where A is an accumulator, each CODE[i] is a binary rtl operation
252 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
258 };
260 /* The largest number of operations needed to load an integer constant.
261 The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI. */
262 #define RISCV_MAX_INTEGER_OPS 8
264 enum riscv_fusion_pairs
265 {
277 };
279 /* Costs of various operations on the different architectures. */
281 struct riscv_tune_param
282 {
298 };
301 /* Global variables for machine-dependent things. */
303 /* Whether unaligned accesses execute very slowly. */
306 /* Whether misaligned vector accesses are supported (i.e. do not
307 throw an exception). */
310 /* Whether user explicitly passed -mstrict-align. */
313 /* Stack alignment to assume/maintain. */
316 /* Whether in riscv_output_mi_thunk. */
319 /* If non-zero, this is an offset to be added to SP to redefine the CFA
320 when restoring the FP register from the stack. Only valid when generating
321 the epilogue. */
324 /* Which tuning parameters to use. */
327 /* Which automaton to use for tuning. */
330 /* The number of chunks in a single vector register. */
331 poly_uint16 riscv_vector_chunks;
333 /* The number of bytes in a vector chunk. */
336 /* Index R is the smallest register class that contains register R. */
370 };
372 /* RVV costs for VLS vector operations. */
392 };
394 /* RVV costs for VLA vector operations. */
396 {
415 },
416 };
418 /* RVV register move cost. */
424 };
426 /* Generic costs for vector insn classes. It is supposed to be the vector cost
427 models used by default if no other cost model was specified. */
438 };
440 /* Costs to use when optimizing for rocket. */
457 };
459 /* Costs to use when optimizing for Sifive 7 Series. */
476 };
478 /* Costs to use when optimizing for Sifive p400 Series. */
495 };
497 /* Costs to use when optimizing for Sifive p600 Series. */
514 };
516 /* Costs to use when optimizing for T-HEAD c906. */
533 };
535 /* Costs to use when optimizing for xiangshan nanhu. */
552 };
554 /* Costs to use when optimizing for a generic ooo profile. */
571 };
573 /* Costs to use when optimizing for size. */
590 };
598 /* Defining target-specific uses of __attribute__. */
600 {
601 /* Syntax: { name, min_len, max_len, decl_required, type_required,
602 function_type_required, affects_type_identity, handler,
603 exclude } */
605 /* The attribute telling no prologue/epilogue. */
607 NULL},
608 /* This attribute generates prologue/epilogue for interrupt handlers. */
610 NULL},
612 /* The following two are used for the built-in properties of the Vector type
613 and are not used externally */
616 /* This attribute is used to declare a function, forcing it to use the
617 standard vector calling convention variant. Syntax:
618 __attribute__((riscv_vector_cc)). */
620 /* This attribute is used to declare a new type, to appoint the exactly
621 bits size of the type. For example:
623 typedef vint8m1_t f_vint8m1_t __attribute__((riscv_rvv_vector_bits(256)));
625 The new created type f_vint8m1_t will be exactly 256 bits. It can be
626 be used in globals, structs, unions, and arrays instead of sizeless
627 types. */
630 };
633 {
635 };
638 {
639 /* This attribute is used to declare a function, forcing it to use the
640 standard vector calling convention variant. Syntax:
641 [[riscv::vector_cc]]. */
643 /* This attribute is used to declare a new type, to appoint the exactly
644 bits size of the type. For example:
646 typedef vint8m1_t f_vint8m1_t __attribute__((riscv_rvv_vector_bits(256)));
648 The new created type f_vint8m1_t will be exactly 256 bits. It can be
649 be used in globals, structs, unions, and arrays instead of sizeless
650 types. */
653 };
656 {
658 };
661 {
663 &riscv_nongnu_attribute_table
664 };
666 /* Order for the CLOBBERs/USEs of gpr_save. */
671 S10_REGNUM, S11_REGNUM
672 };
674 /* A table describing all the processors GCC knows about. */
676 #define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO) \
677 { TUNE_NAME, PIPELINE_MODEL, & TUNE_INFO},
679 };
681 /* Global variable to distinguish whether we should save and restore s0/fp for
682 function. */
686 {
688 POP_IDX,
689 POPRET_IDX,
690 POPRETZ_IDX,
691 ZCMP_OP_NUM
697 {
714 }
716 /* Implement TARGET_MIN_ARITHMETIC_PRECISION. */
718 static unsigned int
720 {
722 }
724 /* Get the arch string from an options object. */
729 {
731 }
736 {
743 }
745 /* Return the riscv_tune_info entry for the given name string, return nullptr
746 if NULL_P is true, otherwise return an placeholder and report error. */
750 {
765 }
767 /* Helper function for riscv_build_integer; arguments are as for
768 riscv_build_integer. */
770 static int
773 {
782 {
783 /* Simply ADDI or LUI. */
789 }
791 {
792 /* Simply BSETI. */
798 /* RISC-V sign-extends all 32bit values that live in a 32bit
799 register. To avoid paradoxes, we thus need to use the
800 sign-extended (negative) representation (-1 << 31) for the
801 value, if we want to build (1 << 31) in SImode. This will
802 then expand to an LUI instruction. */
807 }
809 /* End with ADDI. When constructing HImode constants, do not generate any
810 intermediate value that is not itself a valid HImode constant. The
811 XORI case below will handle those remaining HImode constants. */
815 {
822 {
829 }
830 }
832 /* End with XORI. */
834 {
837 {
844 }
845 }
847 /* Eliminate trailing zeros and end with SLLI. */
849 {
855 /* Don't eliminate the lower 12 bits if LUI might apply. */
859 || (TARGET_64BIT
860 && TARGET_ZBA
865 /* If X has bits 32..63 clear and bit 31 set, then go ahead and mark
866 it as desiring a "uw" operation for the shift. That way we can have
867 LUI+ADDI to generate the constant, then shift it into position
868 clearing out the undesirable bits. */
870 && TARGET_64BIT
871 && TARGET_ZBA
873 {
876 }
880 {
887 }
888 }
891 {
895 /* If all bits are one except a few that are zero, and the zero bits
896 are within a range of 11 bits, then we can synthesize a constant
897 by loading a small negative constant and rotating. */
900 {
902 /* The sign-bit might be zero, so just rotate to be safe. */
912 }
913 /* Handle the case where the 11 bit range of zero bits wraps around. */
916 {
918 /* The sign-bit might be zero, so just rotate to be safe. */
929 }
931 /* If LUI/ADDI are going to set bits 32..63 and we need a small
932 number of them cleared, we might be able to use bclri profitably.
934 Note we may allow clearing of bit 31 using bclri. There's a class
935 of constants with that bit clear where this helps. */
937 && TARGET_ZBS
939 {
940 /* Turn on all those upper bits and synthesize the result. */
944 /* Now iterate over the bits we want to clear until the cost is
945 too high or we're done. */
949 {
955 alt_cost++;
957 }
960 {
963 }
964 }
965 }
968 {
970 && (alt_cost
972 {
979 }
981 && (alt_cost
983 {
990 }
992 && (alt_cost
994 {
1001 }
1002 }
1004 /* We might be able to generate a constant close to our target
1005 then a final ADDI to get the desired constant. */
1009 {
1015 {
1022 }
1023 }
1025 /* Final cases, particularly focused on bseti. */
1027 {
1030 /* First handle any bits set by LUI. Be careful of the
1031 SImode sign bit!. */
1033 {
1039 i++;
1040 }
1042 /* Next, any bits we can handle with addi. */
1044 {
1050 i++;
1051 }
1053 /* And any residuals with bseti. */
1055 {
1062 i++;
1063 }
1065 /* If LUI+ADDI+BSETI resulted in a more efficient
1066 sequence, then use it. */
1068 {
1071 }
1072 }
1076 }
1078 /* Fill CODES with a sequence of rtl operations to load VALUE.
1079 Return the number of operations needed.
1081 ALLOW_NEW_PSEUDOS indicates if or caller wants to allow new pseudo
1082 registers or not. This is needed for cases where the integer synthesis and
1083 costing code are used in insn conditions, we can't have costing allow
1084 recognition at some points and reject at others. */
1086 static int
1089 {
1092 /* Eliminate leading zeros and end with SRLI. */
1094 {
1097 HOST_WIDE_INT shifted_val;
1099 /* Try filling trailing bits with 1s. */
1103 {
1110 }
1112 /* Try filling trailing bits with 0s. */
1116 {
1123 }
1124 }
1126 /* See if we can generate the inverted constant, then use
1127 not to get the desired constant.
1129 This can't be in riscv_build_integer_1 as it'll mutually
1130 recurse with another case in there. And it has to recurse
1131 into riscv_build_integer so we get the trailing 0s case
1132 above. */
1134 {
1142 {
1149 }
1150 }
1155 {
1164 {
1167 {
1173 }
1174 }
1175 }
1177 /* With pack we can generate a 64 bit constant with the same high
1178 and low 32 bits trivially. */
1180 {
1184 {
1190 }
1192 /* An arbitrary 64 bit constant can be synthesized in 5 instructions
1193 using zbkb. We may do better than that if the upper or lower half
1194 can be synthesized with a single LUI, ADDI or BSET. Regardless the
1195 basic steps are the same. */
1197 {
1202 /* Synthesize and get cost for each half. */
1203 lo_cost
1205 hi_cost
1208 /* If profitable, finish synthesis using zbkb. */
1210 {
1211 /* We need the low half independent of the high half. So
1212 mark it has creating a temporary we'll use later. */
1217 /* Now the high half synthesis. */
1221 /* Adjust the cost. */
1224 /* And finally (ab)use VEC_MERGE to indicate we want to
1225 put merge the two parts together. */
1230 }
1231 }
1233 }
1236 {
1247 /* Adjust the shift into the high half accordingly. */
1255 mode);
1257 /* For constants where the upper half is a shift of the lower half we
1258 can do a shift followed by an or. */
1260 {
1261 /* We need to save the first constant we build. */
1264 /* Now we want to shift the previously generated constant into the
1265 high half. */
1271 /* And the final step, IOR the two halves together. Since this uses
1272 the saved temporary, use CONCAT similar to what we do for Zbkb. */
1280 }
1283 {
1286 /* Check for a shNadd. */
1298 /* For constants where the upper half is a shNadd of the lower half
1299 we can do a similar transformation. */
1301 {
1314 }
1315 }
1318 {
1321 /* For constants were the halves differ by less than 2048 we can
1322 generate the upper half by using an addi on the lower half then
1323 using a shift 32 followed by an or. */
1325 {
1329 {
1346 }
1347 }
1348 }
1351 {
1352 /* For constants where the upper half is the lower half inverted we can flip
1353 it with an xor and do a shift 32 followed by an or. */
1355 {
1359 {
1376 }
1377 }
1378 }
1379 }
1382 }
1384 /* Return the cost of constructing VAL in the event that a scratch
1385 register is available. */
1387 static int
1389 {
1395 /* This routine isn't used by pattern conditions, so whether or
1396 not to allow new pseudos can be a function of where we are in the
1397 RTL pipeline. */
1407 }
1409 /* Return the cost of constructing the integer constant VAL. ALLOW_NEW_PSEUDOS
1410 potentially restricts if riscv_build_integer is allowed to create new
1411 pseudo registers. It must be false for calls directly or indirectly from
1412 conditions in patterns. */
1414 static int
1416 {
1420 }
1422 /* Try to split a 64b integer into 32b parts, then reassemble. */
1424 static rtx
1426 {
1435 else
1440 else
1441 {
1444 }
1449 {
1452 }
1454 }
1456 /* Return true if X is a thread-local symbol. */
1458 static bool
1460 {
1462 }
1464 /* Return true if symbol X binds locally. */
1466 static bool
1468 {
1473 else
1475 }
1477 /* Return the method that should be used to access SYMBOL_REF or
1478 LABEL_REF X. */
1480 static enum riscv_symbol_type
1482 {
1490 {
1499 }
1500 }
1502 /* Classify the base of symbolic expression X. */
1504 enum riscv_symbol_type
1506 {
1507 rtx offset;
1514 }
1516 /* Return true if X is a symbolic constant. If it is, store the type of
1517 the symbol in *SYMBOL_TYPE. */
1519 bool
1521 {
1522 rtx offset;
1526 {
1529 }
1532 else
1538 /* Nonzero offsets are only valid for references that don't use the GOT. */
1540 {
1544 /* GAS rejects offsets outside the range [-2^31, 2^31-1]. */
1549 }
1550 }
1552 /* Returns the number of instructions necessary to reference a symbol. */
1555 {
1557 {
1566 }
1567 }
1569 /* Immediate values loaded by the FLI.S instruction in Chapter 25 of the latest RISC-V ISA
1570 Manual draft. For details, please see:
1571 https://github.com/riscv/riscv-isa-manual/releases/tag/isa-449cd0c */
1574 {
1579 /* Only used for filling, ensuring that 29 and 30 of HF are the same. */
1582 };
1585 {
1590 };
1593 {
1602 };
1604 /* Display floating-point values at the assembly level, which is consistent
1605 with the zfa extension of llvm:
1606 https://reviews.llvm.org/D145645. */
1609 {
1610 "-1.0", "min", "1.52587890625e-05", "3.0517578125e-05", "0.00390625", "0.0078125", "0.0625", "0.125",
1614 };
1616 /* Return index of the FLI instruction table if rtx X is an immediate constant that can
1617 be moved using a single FLI instruction in zfa extension. Return -1 if not found. */
1619 int
1621 {
1636 /* Only support up to DF mode. */
1648 {
1653 /* When the lower 32 bits are not all 0, it is impossible to be in the table. */
1656 }
1657 else
1661 {
1673 }
1681 /* Perform a binary search to find target index. */
1688 {
1694 else
1696 }
1699 }
1701 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1703 static bool
1705 {
1706 /* With the post-reload usage, it seems best to just pass in FALSE
1707 rather than pass ALLOW_NEW_PSEUDOS through the call chain. */
1709 }
1711 /* Implement TARGET_CANNOT_FORCE_CONST_MEM.
1712 Return true if X cannot (or should not) be spilled to the
1713 constant pool. */
1715 static bool
1717 {
1721 /* There's no way to calculate VL-based values using relocations. */
1727 /* There is no assembler syntax for expressing an address-sized
1728 high part. */
1737 {
1741 /* As an optimization, don't spill symbolic constants that are as
1742 cheap to rematerialize as to access in the constant pool. */
1746 /* As an optimization, avoid needlessly generate dynamic relocations. */
1749 }
1751 /* TLS symbols must be computed by riscv_legitimize_move. */
1756 }
1758 /* Return true if register REGNO is a valid base register for mode MODE.
1759 STRICT_P is true if REG_OK_STRICT is in effect. */
1761 int
1763 machine_mode mode ATTRIBUTE_UNUSED,
1765 {
1767 {
1771 }
1773 /* These fake registers will be eliminated to either the stack or
1774 hard frame pointer, both of which are usually valid base registers.
1775 Reload deals with the cases where the eliminated form isn't valid. */
1780 }
1782 /* Get valid index register class.
1783 The RISC-V base instructions don't support index registers,
1784 but extensions might support that. */
1786 enum reg_class
1788 {
1793 }
1795 /* Return true if register REGNO is a valid index register.
1796 The RISC-V base instructions don't support index registers,
1797 but extensions might support that. */
1799 int
1801 {
1806 }
1808 /* Return true if X is a valid base register for mode MODE.
1809 STRICT_P is true if REG_OK_STRICT is in effect. */
1811 bool
1813 {
1819 }
1821 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
1822 can address a value of mode MODE. */
1824 static bool
1826 {
1827 /* Check that X is a signed 12-bit number. */
1831 /* We may need to split multiword moves, so make sure that every word
1832 is accessible. */
1838 }
1840 /* Should a symbol of type SYMBOL_TYPE should be split in two? */
1842 bool
1844 {
1852 }
1854 /* Return true if a LO_SUM can address a value of mode MODE when the
1855 LO_SUM symbol has type SYM_TYPE. X is the LO_SUM second operand, which
1856 is used when the mode is BLKmode. */
1858 static bool
1860 rtx x)
1861 {
1864 /* Check that symbols of type SYMBOL_TYPE can be used to access values
1865 of mode MODE. */
1869 /* Check that there is a known low-part relocation. */
1873 /* We can't tell size or alignment when we have BLKmode, so try extracting a
1874 decl from the symbol if possible. */
1876 {
1877 rtx offset;
1879 /* Extract the symbol from the LO_SUM operand, if any. */
1882 /* Might be a CODE_LABEL. We can compute align but not size for that,
1883 so don't bother trying to handle it. */
1887 /* Use worst case assumptions if we don't have a SYMBOL_REF_DECL. */
1896 }
1897 else
1898 {
1901 }
1903 /* We may need to split multiword moves, so make sure that each word
1904 can be accessed without inducing a carry. */
1910 }
1912 /* Return true if mode is the RVV enabled mode.
1913 For example: 'RVVMF2SI' mode is disabled,
1914 whereas 'RVVM1SI' mode is enabled if MIN_VLEN == 32. */
1916 bool
1918 {
1919 #define ENTRY(MODE, REQUIREMENT, ...) \
1920 case MODE##mode: \
1921 return REQUIREMENT;
1923 {
1927 }
1930 }
1932 /* Return true if mode is the RVV enabled tuple mode. */
1934 bool
1936 {
1937 #define TUPLE_ENTRY(MODE, REQUIREMENT, ...) \
1938 case MODE##mode: \
1939 return REQUIREMENT;
1941 {
1945 }
1948 }
1950 /* Return true if mode is the RVV enabled vls mode. */
1952 bool
1954 {
1955 #define VLS_ENTRY(MODE, REQUIREMENT) \
1956 case MODE##mode: \
1957 return REQUIREMENT;
1959 {
1963 }
1966 }
1968 /* Return true if it is either of below modes.
1969 1. RVV vector mode.
1970 2. RVV tuple mode.
1971 3. RVV vls mode. */
1973 static bool
1975 {
1978 }
1980 static unsigned
1983 {
1989 /* Ensure the vls mode is exact_div by scalar_unit_size. */
1993 }
1995 static machine_mode
1997 {
1999 {
2012 }
2013 }
2015 /* Call from ADJUST_NUNITS in riscv-modes.def. Return the correct
2016 NUNITS size for corresponding machine_mode. */
2018 poly_int64
2020 {
2023 {
2027 }
2029 }
2031 /* Call from ADJUST_NUNITS in riscv-modes.def. Return the correct
2032 NUNITS size for corresponding machine_mode. */
2034 poly_int64
2036 {
2038 {
2044 else
2046 }
2047 /* Set the disabled RVV modes size as 1 by default. */
2049 }
2051 /* Call from ADJUST_BYTESIZE in riscv-modes.def. Return the correct
2052 BYTE size for corresponding machine_mode. */
2054 poly_int64
2056 {
2058 {
2068 else
2070 }
2073 }
2075 /* Call from ADJUST_PRECISION in riscv-modes.def. Return the correct
2076 PRECISION size for corresponding machine_mode. */
2078 poly_int64
2080 {
2082 }
2084 /* Return true if X is a valid address for machine mode MODE. If it is,
2085 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2086 effect. */
2088 static bool
2091 {
2096 {
2105 /* RVV load/store disallow any offset. */
2116 /* RVV load/store disallow LO_SUM. */
2123 /* We have to trust the creator of the LO_SUM to do something vaguely
2124 sane. Target-independent code that creates a LO_SUM should also
2125 create and verify the matching HIGH. Target-independent code that
2126 adds an offset to a LO_SUM must prove that the offset will not
2127 induce a carry. Failure to do either of these things would be
2128 a bug, and we are not required to check for it here. The RISC-V
2129 backend itself should only create LO_SUMs for valid symbolic
2130 constants, with the high part being either a HIGH or a copy
2131 of _gp. */
2132 info->symbol_type
2138 /* We only allow the const0_rtx for the RVV load/store. For example:
2139 +----------------------------------------------------------+
2140 | li a5,0 |
2141 | vsetvli zero,a1,e32,m1,ta,ma |
2142 | vle32.v v24,0(a5) <- propagate the const 0 to a5 here. |
2143 | vs1r.v v24,0(a0) |
2144 +----------------------------------------------------------+
2145 It can be folded to:
2146 +----------------------------------------------------------+
2147 | vsetvli zero,a1,e32,m1,ta,ma |
2148 | vle32.v v24,0(zero) |
2149 | vs1r.v v24,0(a0) |
2150 +----------------------------------------------------------+
2151 This behavior will benefit the underlying RVV auto vectorization. */
2155 /* Small-integer addresses don't occur very often, but they
2156 are legitimate if x0 is a valid base register. */
2162 }
2163 }
2165 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2167 static bool
2170 {
2171 /* Disallow RVV modes base address.
2172 E.g. (mem:SI (subreg:DI (reg:V1DI 155) 0). */
2178 }
2180 /* Return true if hard reg REGNO can be used in compressed instructions. */
2182 static bool
2184 {
2185 /* x8-x15/f8-f15 are compressible registers. */
2189 }
2191 /* Return true if x is an unsigned 5-bit immediate scaled by 4. */
2193 static bool
2195 {
2199 }
2201 /* Return true if load/store from/to address x can be compressed. */
2203 static bool
2205 {
2208 reload_completed);
2210 /* Return false if address is not compressed_reg + small_offset. */
2213 /* Before reload, assume all registers are OK. */
2214 || (reload_completed
2221 }
2223 /* Return the number of instructions needed to load or store a value
2224 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2225 Assume that multiword moves may need to be split into word moves
2226 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2227 enough. */
2229 int
2231 {
2236 {
2237 /* This could be a pattern from the pic.md file. In which case we want
2238 this address to always have a cost of 3 to make it as expensive as the
2239 most expensive symbol. This prevents constant propagation from
2240 preferring symbols over register plus offset. */
2242 }
2244 /* BLKmode is used for single unaligned loads and stores and should
2245 not count as a multiword mode. */
2253 }
2255 /* Return the number of instructions needed to load constant X.
2256 Return 0 if X isn't a valid constant.
2258 ALLOW_NEW_PSEUDOS controls whether or not we're going to be allowed
2259 to create new pseduos. It must be FALSE for any call directly or
2260 indirectly from a pattern's condition. */
2262 int
2264 {
2266 rtx offset;
2269 {
2275 /* This is simply an LUI. */
2279 {
2281 /* Force complicated constants to memory. */
2283 }
2286 /* See if we can use FMV directly. */
2290 /* We can use x0 to load floating-point zero. */
2293 {
2294 /* TODO: This is not accurate, we will need to
2295 adapt the COST of CONST_VECTOR in the future
2296 for the following cases:
2298 - 1. const duplicate vector with element value
2299 in range of [-16, 15].
2300 - 2. const duplicate vector with element value
2301 out range of [-16, 15].
2302 - 3. const series vector.
2303 ...etc. */
2305 {
2306 rtx elt;
2308 {
2310 /* Duplicate values of 0/1 can be emitted using vmv.v.i. */
2313 /* We don't allow CONST_VECTOR for DI vector on RV32
2314 system since the ELT constant value can not held
2315 within a single register to disable reload a DI
2316 register vec_duplicate into vmv.v.x. */
2321 /* Constants in range -16 ~ 15 integer or 0.0 floating-point
2322 can be emitted using vmv.v.i. */
2326 /* Any int/FP constants can always be broadcast from a
2327 scalar register. Loading of a floating-point
2328 constant incurs a literal-pool access. Allow this in
2329 order to increase vectorization possibilities. */
2333 else
2334 {
2335 /* We need as many insns as it takes to load the constant
2336 into a GPR and one vmv.v.x. */
2339 else
2341 }
2342 }
2344 /* const series vector. */
2347 {
2348 /* This cost is not accurate, we will need to adapt the COST
2349 accurately according to BASE && STEP. */
2351 }
2354 {
2355 /* Some cases are unhandled so we need construct a builder to
2356 detect/allow those cases to be handled by the fallthrough
2357 handler. */
2362 {
2365 }
2369 {
2371 {
2372 /* TODO: This cost is not accurate. */
2374 }
2375 else
2376 {
2377 /* TODO: This cost is not accurate. */
2379 }
2380 }
2382 {
2383 /* TODO: This cost is not accurate. */
2385 }
2387 /* Fallthrough. */
2388 }
2389 }
2391 /* TODO: We may support more const vector in the future. */
2393 }
2396 /* See if we can refer to X directly. */
2400 /* Otherwise try splitting the constant into a base and offset. */
2403 {
2407 }
2414 /* TODO: In RVV, we get CONST_POLY_INT by using csrr VLENB
2415 instruction and several scalar shift or mult instructions,
2416 it is so far unknown. We set it to 4 temporarily. */
2422 }
2423 }
2425 /* X is a doubleword constant that can be handled by splitting it into
2426 two words and loading each word separately. Return the number of
2427 instructions required to do this. */
2429 int
2431 {
2434 /* This is not called from pattern conditions, so we can let
2435 our location in the RTL pipeline control whether or not
2436 new pseudos are created. */
2442 }
2444 /* Return the number of instructions needed to implement INSN,
2445 given that it loads from or stores to MEM. */
2447 int
2449 {
2450 machine_mode mode;
2452 rtx set;
2457 /* Try to prove that INSN does not need to be split. */
2462 {
2466 }
2469 }
2471 /* Emit a move from SRC to DEST. Assume that the move expanders can
2472 handle all moves if !can_create_pseudo_p (). The distinction is
2473 important because, unlike emit_move_insn, the move expanders know
2474 how to force Pmode objects into the constant pool even when the
2475 constant pool address is not itself legitimate. */
2477 rtx
2479 {
2483 }
2485 /* Emit an instruction of the form (set TARGET SRC). */
2487 static rtx
2489 {
2492 }
2494 /* Emit an instruction of the form (set DEST (CODE X)). */
2496 rtx
2498 {
2500 }
2502 /* Emit an instruction of the form (set DEST (CODE X Y)). */
2504 rtx
2506 {
2508 }
2510 /* Compute (CODE X Y) and store the result in a new register
2511 of mode MODE. Return that new register. */
2513 static rtx
2515 {
2517 }
2519 static rtx
2521 {
2526 }
2528 /* Copy VALUE to a register and return that register. If new pseudos
2529 are allowed, copy it into a new register, otherwise use DEST. */
2531 static rtx
2533 {
2536 else
2537 {
2540 }
2541 }
2543 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2544 then add CONST_INT OFFSET to the result. */
2546 static rtx
2549 {
2555 }
2557 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2558 type SYMBOL_TYPE. */
2560 rtx
2562 {
2567 }
2569 /* If OP is an UNSPEC address, return the address to which it refers,
2570 otherwise return OP itself. */
2572 static rtx
2574 {
2581 }
2583 /* If riscv_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2584 high part to BASE and return the result. Just return BASE otherwise.
2585 TEMP is as for riscv_force_temporary.
2587 The returned expression can be used as the first operand to a LO_SUM. */
2589 static rtx
2591 {
2594 }
2596 /* Load an entry from the GOT for a TLS GD access. */
2599 {
2602 else
2604 }
2606 /* Load an entry from the GOT for a TLS IE access. */
2609 {
2612 else
2614 }
2616 /* Add in the thread pointer for a TLS LE access. */
2619 {
2623 else
2625 }
2627 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2628 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2629 constant in that context and can be split into high and low parts.
2630 If so, and if LOW_OUT is nonnull, emit the high part and store the
2631 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2633 TEMP is as for riscv_force_temporary and is used to load the high
2634 part into a register.
2636 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2637 a legitimize SET_SRC for an .md pattern, otherwise the low part
2638 is guaranteed to be a legitimate address for mode MODE. */
2640 bool
2642 {
2653 {
2658 {
2662 }
2666 {
2669 rtx label;
2676 /* ??? Ugly hack to make weak symbols work. May need to change the
2677 RTL for the auipc and/or low patterns to get a better fix for
2678 this. */
2687 else
2692 seqno++;
2693 }
2698 }
2701 }
2703 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2704 riscv_force_temporary; it is only needed when OFFSET is not a
2705 SMALL_OPERAND. */
2707 static rtx
2709 {
2711 {
2712 rtx high;
2714 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2715 The addition inside the macro CONST_HIGH_PART may cause an
2716 overflow, so we need to force a sign-extension check. */
2721 }
2723 }
2725 /* The __tls_get_attr symbol. */
2728 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2729 the TLS symbol we are referencing and TYPE is the symbol type to use
2730 (either global dynamic or local dynamic). RESULT is an RTX for the
2731 return value location. */
2735 {
2755 }
2757 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2758 its address. The return value will be both a valid address and a valid
2759 SET_SRC (either a REG or a LO_SUM). */
2761 static rtx
2763 {
2767 #if 0
2768 /* TLS copy relocs are now deprecated and should not be used. */
2769 /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */
2772 #endif
2775 {
2777 /* Rely on section anchors for the optimization that LDM TLS
2778 provides. The anchor's address is loaded with GD TLS. */
2781 {
2788 }
2789 else
2790 {
2794 loc);
2795 }
2799 /* la.tls.ie; tp-relative add */
2817 }
2819 }
2820 \f
2821 /* If X is not a valid address for mode MODE, force it into a register. */
2823 static rtx
2825 {
2827 {
2830 else
2831 {
2832 /* It's only safe for the thunk function.
2833 Use ra as the temp register. */
2838 }
2839 }
2842 }
2844 /* Modify base + offset so that offset fits within a compressed load/store insn
2845 and the excess is added to base. */
2847 static rtx
2849 {
2851 /* Leave OFFSET as an unsigned 5-bit offset scaled by 4 and put the excess
2852 into HIGH. */
2860 }
2862 /* Helper for riscv_legitimize_address. Given X, return true if it
2863 is a left shift by 1, 2 or 3 positions or a multiply by 2, 4 or 8.
2865 This respectively represent canonical shift-add rtxs or scaled
2866 memory addresses. */
2867 static bool
2869 {
2877 }
2879 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2880 be legitimized in a way that the generic machinery might not expect,
2881 return a new address, otherwise return NULL. MODE is the mode of
2882 the memory being accessed. */
2884 static rtx
2886 machine_mode mode)
2887 {
2888 rtx addr;
2893 /* See if the address can split into a high part and a LO_SUM. */
2897 /* Handle BASE + OFFSET. */
2900 {
2904 /* Handle (plus (plus (mult (a) (mem_shadd_constant)) (fp)) (C)) case. */
2907 {
2911 {
2913 /* If we were given a MULT, we must fix the constant
2914 as we're going to create the ASHIFT form. */
2927 }
2928 }
2935 /* Convert BASE + LARGE_OFFSET into NEW_BASE + SMALL_OFFSET to allow
2936 possible compressed load/store. */
2938 else
2941 }
2944 }
2946 /* Load VALUE into DEST. TEMP is as for riscv_force_temporary. ORIG_MODE
2947 is the original src mode before promotion. */
2949 void
2951 machine_mode orig_mode)
2952 {
2954 machine_mode mode;
2959 /* We use the original mode for the riscv_build_integer call, because HImode
2960 values are given special treatment. */
2966 else
2967 {
2970 {
2977 {
2978 /* UNKNOWN means load the constant value into X. */
2980 }
2982 {
2983 /* If the sequence requires using a "uw" form of an insn, we're
2984 going to have to construct the RTL ourselves and put it in
2985 a register to avoid force_reg/force_operand from mucking
2986 things up. */
2990 /* Create the proper mask for the slli.uw instruction. */
2994 /* Right now the only "uw" form we use is slli, we may add more
2995 in the future. */
3000 }
3002 {
3008 }
3010 {
3012 {
3013 /* The two values should have no bits in common, so we can
3014 use PLUS instead of IOR which has a higher chance of
3015 using a compressed instruction. */
3017 }
3018 else
3019 {
3026 }
3027 }
3028 else
3032 /* If this entry in the code table indicates we should save away
3033 the temporary holding the current value of X, then do so. */
3035 {
3039 }
3040 }
3041 }
3044 }
3046 /* Subroutine of riscv_legitimize_move. Move constant SRC into register
3047 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3048 move_operand. */
3050 static void
3052 {
3055 /* Split moves of big integers into smaller pieces. */
3057 {
3060 }
3063 {
3066 }
3068 /* Split moves of symbolic constants into high/low pairs. */
3070 {
3073 }
3075 /* Generate the appropriate access sequences for TLS symbols. */
3077 {
3080 }
3082 /* If we have (const (plus symbol offset)), and that expression cannot
3083 be forced into memory, load the symbol first and add in the offset. Also
3084 prefer to do this even if the constant _can_ be forced into memory, as it
3085 usually produces better code. */
3089 {
3093 }
3095 /* Handle below format.
3096 (const:DI
3097 (plus:DI
3098 (symbol_ref:DI ("ic") [flags 0x2] <var_decl 0x7fe57740be10 ic>) <- op_0
3099 (const_poly_int:DI [16, 16]) // <- op_1
3100 ))
3101 */
3104 {
3113 }
3117 /* When using explicit relocs, constant pool references are sometimes
3118 not legitimate addresses. */
3121 }
3123 /* Report when we try to do something that requires vector when vector is
3124 disabled. This is an error of last resort and isn't very high-quality. It
3125 usually involves attempts to measure the vector length in some way. */
3127 static void
3129 {
3132 /* Avoid reporting a slew of messages for a single oversight. */
3138 " option %<-march%>, or by using the %<target%>"
3141 }
3143 /* Helper function to operation for rtx_code CODE. */
3144 static void
3146 rtx op2)
3147 {
3149 {
3150 rtx result;
3153 else
3155 OPTAB_DIRECT);
3157 }
3158 else
3159 {
3160 rtx pat;
3161 /* The following implementation is for prologue and epilogue.
3162 Because prologue and epilogue can not use pseudo register.
3163 We can't using expand_simple_binop or expand_simple_unop. */
3166 else
3169 }
3170 }
3172 /* Expand mult operation with constant integer, multiplicand also used as a
3173 * temporary register. */
3175 static void
3177 HOST_WIDE_INT multiplier)
3178 {
3180 {
3183 }
3189 {
3192 else
3194 }
3195 else
3196 {
3198 {
3199 /*
3200 multiplicand = [BYTES_PER_RISCV_VECTOR].
3201 1. const_poly_int:P [BYTES_PER_RISCV_VECTOR * 8].
3202 Sequence:
3203 csrr a5, vlenb
3204 slli a5, a5, 3
3205 2. const_poly_int:P [-BYTES_PER_RISCV_VECTOR * 8].
3206 Sequence:
3207 csrr a5, vlenb
3208 slli a5, a5, 3
3209 neg a5, a5
3210 */
3215 }
3217 {
3218 /*
3219 multiplicand = [BYTES_PER_RISCV_VECTOR].
3220 1. const_poly_int:P [BYTES_PER_RISCV_VECTOR * 7].
3221 Sequence:
3222 csrr a5, vlenb
3223 slli a4, a5, 3
3224 sub a5, a4, a5
3225 2. const_poly_int:P [-BYTES_PER_RISCV_VECTOR * 7].
3226 Sequence:
3227 csrr a5, vlenb
3228 slli a4, a5, 3
3229 sub a5, a4, a5 + neg a5, a5 => sub a5, a5, a4
3230 */
3233 QImode));
3236 else
3238 }
3240 {
3241 /*
3242 multiplicand = [BYTES_PER_RISCV_VECTOR].
3243 1. const_poly_int:P [BYTES_PER_RISCV_VECTOR * 9].
3244 Sequence:
3245 csrr a5, vlenb
3246 slli a4, a5, 3
3247 add a5, a4, a5
3248 2. const_poly_int:P [-BYTES_PER_RISCV_VECTOR * 9].
3249 Sequence:
3250 csrr a5, vlenb
3251 slli a4, a5, 3
3252 add a5, a4, a5
3253 neg a5, a5
3254 */
3257 QImode));
3261 }
3262 else
3263 {
3264 /* We use multiplication for remaining cases. */
3266 TARGET_MUL
3271 }
3272 }
3273 }
3275 /* Analyze src and emit const_poly_int mov sequence. */
3277 void
3279 {
3281 /* It use HOST_WIDE_INT instead of int since 32bit type is not enough
3282 for e.g. (const_poly_int:DI [549755813888, 549755813888]). */
3287 /* Calculate (const_poly_int:MODE [m, n]) using scalar instructions.
3288 For any (const_poly_int:MODE [m, n]), the calculation formula is as
3289 follows.
3290 constant = m - n.
3291 When minimum VLEN = 32, poly of VLENB = (4, 4).
3292 base = vlenb(4, 4) or vlenb/2(2, 2) or vlenb/4(1, 1).
3293 When minimum VLEN > 32, poly of VLENB = (8, 8).
3294 base = vlenb(8, 8) or vlenb/2(4, 4) or vlenb/4(2, 2) or vlenb/8(1, 1).
3295 magn = (n, n) / base.
3296 (m, n) = base * magn + constant.
3297 This calculation doesn't need div operation. */
3301 else
3302 {
3306 }
3309 {
3313 }
3314 else
3315 {
3318 {
3321 {
3324 }
3325 }
3327 }
3341 else
3342 {
3343 /* Handle the constant value is not a 12-bit value. */
3344 rtx high;
3346 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3347 The addition inside the macro CONST_HIGH_PART may cause an
3348 overflow, so we need to force a sign-extension check. */
3354 }
3355 }
3357 /* Take care below subreg const_poly_int move:
3359 1. (set (subreg:DI (reg:TI 237) 8)
3360 (subreg:DI (const_poly_int:TI [4, 2]) 8))
3361 =>
3362 (set (subreg:DI (reg:TI 237) 8)
3363 (const_int 0)) */
3365 static bool
3367 {
3379 {
3380 /* The const_poly_int cannot exceed int64, just set zero here. */
3383 }
3385 /* The below transform will be covered in somewhere else.
3386 Thus, ignore this here.
3387 (set (subreg:DI (reg:TI 237) 0)
3388 (subreg:DI (const_poly_int:TI [4, 2]) 0))
3389 =>
3390 (set (subreg:DI (reg:TI 237) 0)
3391 (const_poly_int:DI [4, 2])) */
3394 }
3396 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3397 sequence that is valid. */
3399 bool
3401 {
3403 {
3404 /*
3405 Handle:
3406 (insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156)
3407 (const_int 96 [0x60])) [0 S1 A8])
3408 (const_poly_int:QI [8, 8]))
3409 "../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil))
3410 */
3412 {
3415 }
3418 {
3421 }
3427 {
3428 /* In RV32 system, handle (const_poly_int:QI [m, n])
3429 (const_poly_int:HI [m, n]).
3430 In RV64 system, handle (const_poly_int:QI [m, n])
3431 (const_poly_int:HI [m, n])
3432 (const_poly_int:SI [m, n]). */
3437 }
3438 else
3439 {
3440 /* In RV32 system, handle (const_poly_int:SI [m, n])
3441 (const_poly_int:DI [m, n]).
3442 In RV64 system, handle (const_poly_int:DI [m, n]).
3443 FIXME: Maybe we could gen SImode in RV32 and then sign-extend to
3444 DImode, the offset should not exceed 4GiB in general. */
3447 }
3449 }
3455 /* Expand
3456 (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0))
3457 Expand this data movement instead of simply forbid it since
3458 we can improve the code generation for this following scenario
3459 by RVV auto-vectorization:
3460 (set (reg:V8QI 149) (vec_duplicate:V8QI (reg:QI))
3461 (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0))
3462 Since RVV mode and scalar mode are in different REG_CLASS,
3463 we need to explicitly move data from V_REGS to GR_REGS by scalar move. */
3465 {
3469 /* We should be able to handle both partial and paradoxical subreg. */
3478 {
3479 /* If we want to extract 64bit value but ELEN < 64,
3480 we use RVV vector mode with EEW = 32 to extract
3481 the highpart and lowpart. */
3485 }
3488 {
3493 {
3496 }
3499 {
3500 rtx result;
3505 else
3512 {
3514 /* If Pmode = SImode and mode = DImode, we just need to
3515 extract element of index = 1 from the vector and move it
3516 into the highpart of the DEST since DEST consists of 2
3517 scalar registers. */
3519 else
3520 {
3528 }
3529 }
3530 }
3534 else
3536 }
3537 else
3541 }
3542 /* Expand
3543 (set (reg:QI target) (mem:QI (address)))
3544 to
3545 (set (reg:DI temp) (zero_extend:DI (mem:QI (address))))
3546 (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
3547 with auto-sign/zero extend. */
3552 {
3553 rtx temp_reg;
3559 zero_extend_p));
3562 }
3565 {
3566 rtx reg;
3569 {
3570 /* Apply the equivalent of PROMOTE_MODE here for constants to
3571 improve cse. */
3578 {
3581 }
3582 else
3587 }
3588 else
3592 }
3594 /* In order to fit NaN boxing, expand
3595 (set FP_REG (reg:HF/BF src))
3596 to
3597 (set (reg:SI/DI mask) (const_int -65536)
3598 (set (reg:SI/DI temp) (zero_extend:SI/DI (subreg:HI (reg:HF/BF src) 0)))
3599 (set (reg:SI/DI temp) (ior:SI/DI (reg:SI/DI mask) (reg:SI/DI temp)))
3600 (set (reg:HF/BF dest) (unspec:HF/BF[ (reg:SI/DI temp) ] UNSPEC_FMV_FP16_X))
3601 */
3604 && !TARGET_ZFHMIN
3609 {
3617 else
3621 UNSPEC_FMV_FP16_X));
3624 }
3626 /* We need to deal with constants that would be legitimate
3627 immediate_operands but aren't legitimate move_operands. */
3629 {
3633 }
3635 /* RISC-V GCC may generate non-legitimate address due to we provide some
3636 pattern for optimize access PIC local symbol and it's make GCC generate
3637 unrecognizable instruction during optimizing. */
3640 reload_completed))
3641 {
3643 }
3646 reload_completed))
3647 {
3649 }
3652 }
3654 /* Return true if there is an instruction that implements CODE and accepts
3655 X as an immediate operand. */
3657 static int
3659 {
3661 {
3665 /* All shift counts are truncated to a valid constant. */
3674 /* These instructions take 12-bit signed immediates. */
3678 /* We add 1 to the immediate and use SLT. */
3682 /* Likewise SLTU, but reject the always-true case. */
3687 /* We can emulate an immediate of 1 by using GT/GTU against x0. */
3691 /* By default assume that x0 can be used for 0. */
3693 }
3694 }
3696 /* Return the cost of binary operation X, given that the instruction
3697 sequence for a word-sized or smaller operation takes SINGLE_INSNS
3698 instructions and that the sequence of a double-word operation takes
3699 DOUBLE_INSNS instructions. */
3701 static int
3703 {
3708 }
3710 /* Return the cost of sign- or zero-extending OP. */
3712 static int
3714 {
3719 /* We can use ANDI. */
3722 /* ZBA provide zext.w. */
3726 /* ZBB provide zext.h, sext.b and sext.h. */
3728 {
3734 }
3737 /* We can use SEXT.W. */
3740 /* We need to use a shift left and a shift right. */
3742 }
3744 /* Implement TARGET_RTX_COSTS. */
3746 #define SINGLE_SHIFT_COST 1
3748 static bool
3751 {
3752 /* TODO: We set RVV instruction cost as 1 by default.
3753 Cost Model need to be well analyzed and supported in the future. */
3755 {
3758 }
3764 {
3766 /* If we are called for an INSN that's a simple set of a register,
3767 then cost based on the SET_SRC alone. */
3770 {
3772 {
3775 }
3778 }
3780 /* Otherwise return FALSE indicating we should recurse into both the
3781 SET_DEST and SET_SRC combining the cost of both. */
3785 /* trivial constants checked using OUTER_CODE in case they are
3786 encodable in insn itself w/o need for additional insn(s). */
3788 {
3791 }
3792 /* Fall through. */
3797 /* With TARGET_SUPPORTS_WIDE_INT const int can't be in CONST_DOUBLE
3798 rtl object. Weird recheck due to switch-case fall through above. */
3801 /* Fall through. */
3804 /* Non trivial CONST_INT Fall through: check if need multiple insns. */
3806 {
3807 /* 1. Hoist will GCSE constants only if TOTAL returned is non-zero.
3808 2. For constants loaded more than once, the approach so far has
3809 been to duplicate the operation than to CSE the constant.
3810 3. TODO: make cost more accurate specially if riscv_const_insns
3811 returns > 1. */
3814 }
3820 /* If the address is legitimate, return the number of
3821 instructions it needs. */
3823 {
3824 /* When optimizing for size, make uncompressible 32-bit addresses
3825 more expensive so that compressible 32-bit addresses are
3826 preferred. */
3830 cost++;
3834 }
3835 /* Otherwise use the default handling. */
3843 {
3844 /* For predicated conditional-move operations we assume the cost
3845 of a single instruction even though there are actually two. */
3848 }
3861 {
3864 }
3866 {
3869 {
3872 }
3874 {
3877 }
3878 }
3886 /* slli.uw pattern for zba. */
3889 {
3899 }
3900 /* bclri pattern for zbs. */
3903 {
3906 }
3907 /* bclr pattern for zbs. */
3913 {
3916 }
3921 /* orn, andn and xorn pattern for zbb. */
3924 {
3927 }
3929 /* bset[i] and binv[i] pattern for zbs. */
3931 && TARGET_ZBS
3935 {
3938 }
3940 /* Double-word operations use two single-word operations. */
3945 /* This is an SImode shift. */
3951 {
3954 }
3955 /* bit extraction pattern (zbs:bext, xtheadbs:tst). */
3959 {
3962 }
3968 {
3971 }
3975 /* bset pattern for zbs. */
3979 {
3982 }
3999 /* This is an SImode shift. */
4002 {
4005 }
4006 /* Fall through. */
4016 /* Branch comparisons have VOIDmode, so use the first operand's
4017 mode instead. */
4021 else
4027 /* (FEQ(A, A) & FEQ(B, B)) compared against 0. */
4033 /* (FEQ(A, A) & FEQ(B, B)) compared against FEQ(A, B). */
4039 /* (FLT(A, A) || FGT(B, B)). */
4048 /* FLT or FLE, but guarded by an FFLAGS read and write. */
4056 else
4061 /* add.uw pattern for zba. */
4068 {
4071 }
4072 /* shNadd pattern for zba. */
4081 {
4084 }
4085 /* Before strength-reduction, the shNadd can be expressed as the addition
4086 of a multiplication with a power-of-two. If this case is not handled,
4087 the strength-reduction in expmed.c will calculate an inflated cost. */
4096 {
4099 }
4100 /* shNadd.uw pattern for zba.
4101 [(set (match_operand:DI 0 "register_operand" "=r")
4102 (plus:DI
4103 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
4104 (match_operand:QI 2 "immediate_operand" "I"))
4105 (match_operand 3 "immediate_operand" ""))
4106 (match_operand:DI 4 "register_operand" "r")))]
4107 "TARGET_64BIT && TARGET_ZBA
4108 && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
4109 && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
4110 */
4115 {
4132 {
4135 }
4137 }
4141 else
4146 {
4149 {
4155 }
4156 }
4160 else
4168 /* Estimate the cost of a library call. */
4174 else
4182 {
4185 }
4186 /* Fall through. */
4191 /* Estimate the cost of a library call. */
4195 else
4200 /* This is an SImode shift. */
4202 {
4205 }
4206 /* Fall through. */
4213 {
4214 /* RISC-V only defines rev8 for XLEN, so we will need an extra
4215 shift-right instruction for smaller modes. */
4218 }
4238 {
4239 /* Make AUIPC cheap to avoid spilling its result to the stack. */
4242 }
4247 }
4248 }
4250 /* Implement TARGET_ADDRESS_COST. */
4252 static int
4254 addr_space_t as ATTRIBUTE_UNUSED,
4256 {
4257 /* When optimizing for size, make uncompressible 32-bit addresses more
4258 * expensive so that compressible 32-bit addresses are preferred. */
4264 }
4266 /* Implement TARGET_INSN_COST. We factor in the branch cost in the cost
4267 calculation for conditional branches: one unit is considered the cost
4268 of microarchitecture-dependent actual branch execution and therefore
4269 multiplied by BRANCH_COST and any remaining units are considered fixed
4270 branch overhead. Branches on a floating-point condition incur an extra
4271 instruction cost as they will be split into an FCMP operation followed
4272 by a branch on an integer condition. */
4274 static int
4276 {
4281 {
4287 {
4291 }
4292 }
4294 }
4296 /* Implement TARGET_MAX_NOCE_IFCVT_SEQ_COST. Like the default implementation,
4297 but we consider cost units of branch instructions equal to cost units of
4298 other instructions. */
4300 static unsigned int
4302 {
4306 {
4309 }
4310 else
4311 {
4314 }
4317 }
4319 /* Implement TARGET_NOCE_CONVERSION_PROFITABLE_P. We replace the cost of a
4320 conditional branch assumed by `noce_find_if_block' at `COSTS_N_INSNS (2)'
4321 by our actual conditional branch cost, observing that our branches test
4322 conditions directly, so there is no preparatory extra condition-set
4323 instruction. */
4325 static bool
4328 {
4334 /* Hack alert! When `noce_try_store_flag_mask' uses `cstore<mode>4'
4335 to emit a conditional set operation on DImode output it comes up
4336 with a sequence such as:
4338 (insn 26 0 27 (set (reg:SI 140)
4339 (eq:SI (reg/v:DI 137 [ c ])
4340 (const_int 0 [0]))) 302 {*seq_zero_disi}
4341 (nil))
4342 (insn 27 26 28 (set (reg:DI 139)
4343 (zero_extend:DI (reg:SI 140))) 116 {*zero_extendsidi2_internal}
4344 (nil))
4346 because our `cstore<mode>4' pattern expands to an insn that gives
4347 a SImode output. The output of conditional set is 0 or 1 boolean,
4348 so it is valid for input in any scalar integer mode and therefore
4349 combine later folds the zero extend operation into an equivalent
4350 conditional set operation that produces a DImode output, however
4351 this redundant zero extend operation counts towards the cost of
4352 the replacement sequence. Compensate for that by incrementing the
4353 cost of the original sequence as well as the maximum sequence cost
4354 accordingly. Likewise for sign extension. */
4357 {
4364 {
4371 {
4374 }
4378 /* Do something similar for the moves that are likely to
4379 turn into NOP moves by the time the register allocator is
4380 done. These are also side effects of how our sCC expanders
4381 work. We'll want to check and update LAST_DEST here too. */
4388 {
4393 }
4394 else
4399 }
4400 else
4402 }
4405 }
4407 /* Return one word of double-word value OP. HIGH_P is true to select the
4408 high part or false to select the low part. */
4410 rtx
4412 {
4426 }
4428 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4430 bool
4432 {
4436 /* There is no need to split if the FLI instruction in the `Zfa` extension can be used. */
4440 /* Allow FPR <-> FPR and FPR <-> MEM moves, and permit the special case
4441 of zeroing an FPR with FCVT.D.W. */
4450 }
4452 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4453 this function handles 64-bit moves for which riscv_split_64bit_move_p
4454 holds. For 64-bit targets, this function handles 128-bit moves. */
4456 void
4458 {
4459 /* ZFA or XTheadFmv has instructions for accessing the upper bits of a double. */
4461 {
4463 {
4469 else
4472 }
4474 {
4479 {
4483 }
4484 else
4485 {
4488 }
4490 }
4491 }
4493 /* The operation can be split into two normal moves. Decide in
4494 which order to do them. */
4497 {
4500 }
4501 else
4502 {
4505 }
4506 }
4508 /* Constant VAL is known to be sum of two S12 constants. Break it into
4509 comprising BASE and OFF.
4510 Numerically S12 is -2048 to 2047, however it uses the more conservative
4511 range -2048 to 2032 as offsets pertain to stack related registers. */
4513 void
4516 {
4518 {
4521 }
4523 {
4526 }
4527 else
4528 {
4530 }
4531 }
4533 \f
4534 /* Return the appropriate instructions to move SRC into DEST. Assume
4535 that SRC is operand 1 and DEST is operand 0. */
4539 {
4541 machine_mode mode;
4559 {
4562 {
4566 /* Using fmv.x.s + sign-extend to emulate fmv.x.h. */
4572 }
4576 {
4581 }
4584 {
4592 /* Should never reach here. */
4594 }
4601 {
4606 }
4607 }
4610 {
4612 {
4618 {
4622 /* High 16 bits should be all-1, otherwise HW will treated
4623 as a n-bit canonical NaN, but isn't matter for softfloat. */
4630 /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */
4633 }
4634 }
4637 {
4642 }
4643 }
4645 {
4648 {
4657 }
4661 {
4668 }
4669 }
4671 {
4674 {
4681 }
4685 {
4692 }
4693 }
4695 {
4696 /* We only want a single full vector register VLEN read after reload. */
4699 }
4701 }
4705 {
4710 }
4712 \f
4713 /* Return true if CMP1 is a suitable second operand for integer ordering
4714 test CODE. See also the *sCC patterns in riscv.md. */
4716 static bool
4718 {
4720 {
4741 }
4742 }
4744 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4745 integer ordering test *CODE, or if an equivalent combination can
4746 be formed by adjusting *CODE and *CMP1. When returning true, update
4747 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4748 them alone. */
4750 static bool
4752 machine_mode mode)
4753 {
4754 HOST_WIDE_INT plus_one;
4761 {
4765 {
4769 }
4775 {
4779 }
4784 }
4786 }
4788 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4789 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4790 is nonnull, it's OK to set TARGET to the inverse of the result and
4791 flip *INVERT_PTR instead. */
4793 static void
4796 {
4797 machine_mode mode;
4799 /* First see if there is a RISCV instruction that can do this operation.
4800 If not, try doing the same for the inverse operation. If that also
4801 fails, force CMP1 into a register and try again. */
4805 else
4806 {
4809 {
4812 }
4814 {
4818 }
4819 else
4820 {
4823 }
4824 }
4825 }
4827 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4828 The register will have the same mode as CMP0. */
4830 static rtx
4832 {
4838 }
4840 /* Helper function for riscv_extend_comparands to Sign-extend the OP.
4841 However if the OP is SI subreg promoted with an inner DI, such as
4842 (subreg/s/v:SI (reg/v:DI) 0)
4843 just peel off the SUBREG to get DI, avoiding extraneous extension. */
4845 static void
4847 {
4854 else
4856 }
4858 /* Sign- or zero-extend OP0 and OP1 for integer comparisons. */
4860 static void
4862 {
4863 /* Comparisons consider all XLEN bits, so extend sub-XLEN values. */
4865 {
4866 /* It is more profitable to zero-extend QImode values. But not if the
4867 first operand has already been sign-extended, and the second one is
4868 is a constant or has already been sign-extended also. */
4878 {
4882 else
4884 }
4885 else
4886 {
4891 }
4892 }
4893 }
4895 /* Convert a comparison into something that can be used in a branch or
4896 conditional move. On entry, *OP0 and *OP1 are the values being
4897 compared and *CODE is the code used to compare them.
4899 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4900 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are
4901 emitted. */
4903 static void
4906 {
4908 {
4912 {
4916 }
4918 }
4921 {
4925 {
4926 /* Convert e.g. OP0 == 2048 into OP0 - 2048 == 0. */
4928 {
4932 }
4933 }
4934 else
4935 {
4938 };
4940 /* Convert e.g. (OP0 <= 0xFFF) into (OP0 < 0x1000). */
4942 {
4943 HOST_WIDE_INT new_rhs;
4953 {
4956 }
4958 }
4959 }
4960 }
4967 }
4969 /* Like riscv_emit_int_compare, but for floating-point comparisons. */
4971 static void
4974 {
4980 {
4983 /* Fall through. */
4986 /* a == a && b == b */
4994 /* ordered(a, b) > (a == b) */
5002 #define UNORDERED_COMPARISON(CODE, CMP) \
5003 case CODE: \
5004 *code = EQ; \
5005 *op0 = gen_reg_rtx (word_mode); \
5006 if (GET_MODE (cmp_op0) == SFmode && TARGET_64BIT) \
5007 emit_insn (gen_f##CMP##_quietsfdi4 (*op0, cmp_op0, cmp_op1)); \
5008 else if (GET_MODE (cmp_op0) == SFmode) \
5009 emit_insn (gen_f##CMP##_quietsfsi4 (*op0, cmp_op0, cmp_op1)); \
5010 else if (GET_MODE (cmp_op0) == DFmode && TARGET_64BIT) \
5011 emit_insn (gen_f##CMP##_quietdfdi4 (*op0, cmp_op0, cmp_op1)); \
5012 else if (GET_MODE (cmp_op0) == DFmode) \
5013 emit_insn (gen_f##CMP##_quietdfsi4 (*op0, cmp_op0, cmp_op1)); \
5014 else if (GET_MODE (cmp_op0) == HFmode && TARGET_64BIT) \
5015 emit_insn (gen_f##CMP##_quiethfdi4 (*op0, cmp_op0, cmp_op1)); \
5016 else if (GET_MODE (cmp_op0) == HFmode) \
5017 emit_insn (gen_f##CMP##_quiethfsi4 (*op0, cmp_op0, cmp_op1)); \
5018 else \
5019 gcc_unreachable (); \
5020 *op1 = const0_rtx; \
5021 break;
5034 #undef UNORDERED_COMPARISON
5040 else
5041 {
5044 }
5052 /* We have instructions for these cases. */
5059 /* (a < b) | (a > b) */
5068 }
5069 }
5071 /* CODE-compare OP0 and OP1. Store the result in TARGET. */
5073 void
5075 {
5079 /* For sub-word targets on rv64, do the computation in DImode
5080 then extract the lowpart for the final target, marking it
5081 as sign extended. Note that it's also properly zero extended,
5082 but it's probably more profitable to expose it as sign extended. */
5083 rtx t;
5086 else
5090 {
5093 }
5094 else
5098 {
5103 }
5104 }
5106 /* Like riscv_expand_int_scc, but for floating-point comparisons. */
5108 void
5111 {
5116 {
5119 }
5120 else
5122 }
5124 /* Jump to LABEL if (CODE OP0 OP1) holds. */
5126 void
5128 {
5131 else
5135 {
5139 }
5143 }
5145 /* Emit a cond move: If OP holds, move CONS to DEST; else move ALT to DEST.
5146 Return 0 if expansion failed. */
5148 bool
5150 {
5160 {
5164 /* An integer comparison must be comparing WORD_MODE objects. We
5165 must enforce that so that we don't strip away a sign_extension
5166 thinking it is unnecessary. We might consider using
5167 riscv_extend_operands if they are not already properly extended. */
5172 /* In the fallback generic case use MODE rather than WORD_MODE for
5173 the output of the SCC instruction, to match the mode of the NEG
5174 operation below. The output of SCC is 0 or 1 boolean, so it is
5175 valid for input in any scalar integer mode. */
5181 /* Canonicalize the comparison. It must be an equality comparison
5182 of integer operands, or with SFB it can be any comparison of
5183 integer operands. If it isn't, then emit an SCC instruction
5184 so that we can then use an equality comparison against zero. */
5187 {
5190 /* If riscv_expand_int_scc inverts the condition, then it will
5191 flip the value of INVERT. We need to know where so that
5192 we can adjust it for our needs. */
5196 /* Emit an SCC-like instruction into a temporary so that we can
5197 use an EQ/NE comparison. We can support both FP and integer
5198 conditional moves. */
5204 else
5209 /* We've generated a new comparison. Update the local variables. */
5213 }
5218 {
5222 /* The expander is a bit loose in its specification of the true
5223 arm of the conditional move. That allows us to support more
5224 cases for extensions which are more general than SFB. But
5225 does mean we need to force CONS into a register at this point. */
5227 /* With XTheadCondMov we need to force ALT into a register too. */
5232 }
5234 {
5249 }
5250 /* 0, reg or 0, imm */
5254 {
5262 }
5263 /* imm, imm */
5266 {
5274 alt)));
5275 /* CONS might not fit into a signed 12 bit immediate suitable
5276 for an addi instruction. If that's the case, force it
5277 into a register. */
5282 }
5283 /* imm, reg */
5285 {
5286 /* Optimize for register value of 0. */
5288 {
5295 }
5303 /* TEMP2 and/or CONS might not fit into a signed 12 bit immediate
5304 suitable for an addi instruction. If that's the case, force it
5305 into a register. */
5315 temp1)));
5318 }
5319 /* reg, 0 or imm, 0 */
5323 {
5330 }
5331 /* reg, imm */
5333 {
5334 /* Optimize for register value of 0. */
5336 {
5343 }
5351 /* TEMP2 and/or ALT might not fit into a signed 12 bit immediate
5352 suitable for an addi instruction. If that's the case, force it
5353 into a register. */
5362 temp1,
5366 }
5367 /* reg, reg */
5369 {
5373 {
5380 }
5391 cons)));
5395 alt)));
5398 }
5399 }
5402 }
5404 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5405 least PARM_BOUNDARY bits of alignment, but will be given anything up
5406 to PREFERRED_STACK_BOUNDARY bits if the type requires it. */
5408 static unsigned int
5410 {
5413 /* Use natural alignment if the type is not aggregate data. */
5416 else
5420 }
5422 /* If MODE represents an argument that can be passed or returned in
5423 floating-point registers, return the number of registers, else 0. */
5425 static unsigned
5427 {
5429 {
5435 }
5438 }
5441 const_tree type;
5442 HOST_WIDE_INT offset;
5445 /* Identify subfields of aggregates that are candidates for passing in
5446 floating-point registers. */
5448 static int
5453 {
5455 {
5457 /* Can't handle incomplete types nor sizes that are not fixed. */
5465 {
5469 /* The C++ front end strips zero-length bit-fields from structs.
5470 So we need to ignore them in the C front end to make C code
5471 compatible with C++ code. */
5476 ;
5477 else
5478 {
5482 ignore_zero_width_bit_field_p);
5483 }
5486 }
5490 {
5491 HOST_WIDE_INT n_elts;
5497 ignore_zero_width_bit_field_p);
5499 /* Can't handle incomplete types nor sizes that are not fixed. */
5503 || !index
5517 {
5523 }
5526 }
5529 {
5530 /* Complex type need consume 2 field, so n must be 0. */
5537 {
5544 }
5547 }
5555 {
5559 }
5560 else
5562 }
5563 }
5565 /* Identify candidate aggregates for passing in floating-point registers.
5566 Candidates have at most two fields after flattening. */
5568 static int
5572 {
5577 ignore_zero_width_bit_field_p);
5578 }
5580 /* See whether TYPE is a record whose fields should be returned in one or
5581 two floating-point registers. If so, populate FIELDS accordingly. */
5583 static unsigned
5586 {
5589 /* This is the old ABI, which differs for C++ and C. */
5593 {
5596 }
5598 /* This is the new ABI, which is the same for C++ and C. */
5602 {
5605 }
5608 {
5612 }
5615 }
5617 /* See whether TYPE is a record whose fields should be returned in one or
5618 floating-point register and one integer register. If so, populate
5619 FIELDS accordingly. */
5621 static bool
5624 {
5627 /* This is the old ABI, which differs for C++ and C. */
5631 {
5634 }
5636 /* This is the new ABI, which is the same for C++ and C. */
5640 {
5643 }
5650 {
5654 }
5657 }
5659 /* Return the representation of an argument passed or returned in an FPR
5660 when the value has mode VALUE_MODE and the type has TYPE_MODE. The
5661 two modes may be different for structures like:
5663 struct __attribute__((packed)) foo { float f; }
5665 where the SFmode value "f" is passed in REGNO but the struct itself
5666 has mode BLKmode. */
5668 static rtx
5670 machine_mode value_mode,
5671 HOST_WIDE_INT offset)
5672 {
5676 {
5679 }
5681 }
5683 /* Pass or return a composite value in the FPR pair REGNO and REGNO + 1.
5684 MODE is the mode of the composite. MODE1 and OFFSET1 are the mode and
5685 byte offset for the first value, likewise MODE2 and OFFSET2 for the
5686 second value. */
5688 static rtx
5692 HOST_WIDE_INT offset2)
5693 {
5694 return gen_rtx_PARALLEL
5703 }
5705 static rtx
5708 {
5718 {
5722 {
5726 }
5727 }
5738 }
5740 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5741 for a call to a function whose data type is FNTYPE.
5742 For a library call, FNTYPE is 0. */
5744 void
5746 {
5751 else
5753 }
5755 /* Return true if TYPE is a vector type that can be passed in vector registers.
5756 */
5758 static bool
5760 {
5761 /* Currently, only builtin scalable vector type is allowed, in the future,
5762 more vector types may be allowed, such as GNU vector type, etc. */
5764 }
5766 static unsigned int
5769 /* Subroutine of riscv_get_arg_info. */
5771 static rtx
5774 {
5779 {
5780 /* For scalable mask return value. */
5784 /* For the first scalable mask argument. */
5786 {
5789 }
5790 else
5791 {
5792 /* Rest scalable mask arguments are treated as scalable data
5793 arguments. */
5794 }
5795 }
5797 /* The number and alignment of vector registers need for this scalable vector
5798 argument. When the mode size is less than a full vector, we use 1 vector
5799 register to pass. Just call TARGET_HARD_REGNO_NREGS for the number
5800 information. */
5809 /* For scalable data and scalable tuple return value. */
5813 /* Iterate through the USED_VRS array to find vector register groups that have
5814 not been allocated and the first register is aligned with LMUL. */
5816 {
5817 /* The index in USED_VRS array. */
5819 /* Find the first register unused. */
5821 {
5823 /* Ensure there are NREGS continuous unused registers. */
5826 {
5828 /* Update I to the last aligned register which
5829 cannot be used and the next iteration will add
5830 LMUL step to I. */
5833 }
5836 {
5840 }
5841 }
5842 }
5845 }
5847 /* Fill INFO with information about a single argument, and return an RTL
5848 pattern to pass or return the argument. Return NULL_RTX if argument cannot
5849 pass or return in registers, then the argument may be passed by reference or
5850 through the stack or . CUM is the cumulative state for earlier arguments.
5851 MODE is the mode of this argument and TYPE is its type (if known). NAMED is
5852 true if this is a named (fixed) argument rather than a variable one. RETURN_P
5853 is true if returning the argument, or false if passing the argument. */
5855 static rtx
5859 {
5869 /* Passed by reference when the scalable vector argument is anonymous. */
5874 {
5879 /* Pass one- or two-element floating-point aggregates in FPRs. */
5883 {
5899 }
5901 /* Pass real and complex floating-point numbers in FPRs. */
5905 {
5916 }
5918 /* Pass structs with one float and one integer in an FPR and a GPR. */
5922 {
5933 }
5935 /* For scalable vector argument. */
5939 /* For vls mode aggregated in gpr. */
5942 }
5944 /* Work out the size of the argument. */
5948 /* Doubleword-aligned varargs start on an even register boundary. */
5952 /* Partition the argument between registers and stack. */
5961 }
5963 /* Implement TARGET_FUNCTION_ARG. */
5965 static rtx
5967 {
5972 /* Return the calling convention that used by the current function. */
5976 }
5978 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5980 static void
5983 {
5989 /* Set the corresponding register in USED_VRS to used status. */
5991 {
5994 }
5997 {
6000 /* Avoid repeating the message */
6002 }
6004 /* Advance the register count. This has the effect of setting
6005 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
6006 argument required us to skip the final GPR and pass the whole
6007 argument on the stack. */
6011 }
6013 /* Implement TARGET_ARG_PARTIAL_BYTES. */
6015 static int
6018 {
6024 }
6026 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
6027 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
6028 VALTYPE is null and MODE is the mode of the return value. */
6030 rtx
6032 {
6034 CUMULATIVE_ARGS args;
6037 {
6042 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
6043 return values, promote the mode here too. */
6045 }
6050 }
6052 /* Implement TARGET_PASS_BY_REFERENCE. */
6054 static bool
6056 {
6061 /* ??? std_gimplify_va_arg_expr passes NULL for cum. Fortunately, we
6062 never pass variadic arguments in floating-point and vector registers,
6063 so we can avoid the call to riscv_get_arg_info in this case. */
6065 {
6068 /* Don't pass by reference if we can use a floating-point register. */
6072 /* Don't pass by reference if we can use general register(s) for vls. */
6076 /* Don't pass by reference if we can use vector register groups. */
6079 }
6081 /* Passed by reference when:
6082 1. The scalable vector argument is anonymous.
6083 2. Args cannot be passed through vector registers. */
6087 /* Pass by reference if the data do not fit in two integer registers. */
6089 }
6091 /* Implement TARGET_RETURN_IN_MEMORY. */
6093 static bool
6095 {
6096 CUMULATIVE_ARGS args;
6099 /* The rules for returning in memory are the same as for passing the
6100 first named argument by reference. */
6104 }
6106 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
6108 static void
6112 {
6113 CUMULATIVE_ARGS local_cum;
6116 /* The caller has advanced CUM up to, but not beyond, the last named
6117 argument. Advance a local copy of CUM past the last "real" named
6118 argument, to find out how many registers are left over. */
6124 /* Found out how many registers we need to save. */
6128 {
6137 }
6140 }
6142 /* Return the descriptor of the Standard Vector Calling Convention Variant. */
6146 {
6149 {
6150 HARD_REG_SET full_reg_clobbers
6152 /* Callee-saved vector registers: v1-v7, v24-v31. */
6158 }
6160 }
6162 static bool
6164 {
6172 }
6174 bool
6176 {
6187 }
6189 static int
6191 {
6211 }
6213 static int
6215 {
6245 }
6247 static void
6249 {
6253 {
6257 }
6264 {
6269 }
6276 {
6283 }
6287 {
6292 }
6296 {
6300 }
6305 {
6307 input_location,
6311 }
6312 }
6314 /* Return true if a function with type FNTYPE returns its value in
6315 RISC-V V registers. */
6317 static bool
6319 {
6323 {
6326 }
6327 else
6329 }
6331 /* Return true if a function with type FNTYPE takes arguments in
6332 RISC-V V registers. */
6334 static bool
6336 {
6339 {
6342 {
6345 }
6346 }
6349 }
6351 /* Return true if FUNC is a riscv_vector_cc function.
6352 For more details please reference the below link.
6353 https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67 */
6354 static bool
6356 {
6367 }
6369 /* Implement TARGET_FNTYPE_ABI. */
6373 {
6374 /* Implement the vector calling convention. For more details please
6375 reference the below link.
6376 https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389 */
6383 }
6385 /* Return riscv calling convention of call_insn. */
6386 riscv_cc
6388 {
6396 }
6398 /* Implement TARGET_INSN_CALLEE_ABI. */
6402 {
6407 }
6409 /* Handle an attribute requiring a FUNCTION_DECL;
6410 arguments as in struct attribute_spec.handler. */
6411 static tree
6413 tree args ATTRIBUTE_UNUSED,
6415 {
6417 {
6419 name);
6421 }
6424 }
6426 /* Verify type based attributes. NODE is the what the attribute is being
6427 applied to. NAME is the attribute name. ARGS are the attribute args.
6428 FLAGS gives info about the context. NO_ADD_ATTRS should be set to true if
6429 the attribute should be ignored. */
6431 static tree
6434 {
6435 /* Check for an argument. */
6437 {
6439 {
6444 {
6447 name);
6450 }
6455 {
6460 }
6461 }
6462 }
6465 }
6467 static tree
6471 {
6478 {
6483 }
6488 {
6491 }
6496 {
6499 }
6502 unsigned HOST_WIDE_INT type_mode_bits
6506 {
6511 }
6518 /* The operations like alu/cmp on vbool*_t is not well defined,
6519 continue to treat vbool*_t as indivisible. */
6526 }
6528 /* Return true if function TYPE is an interrupt function. */
6529 static bool
6531 {
6533 }
6535 /* Return true if FUNC is a naked function. */
6536 static bool
6538 {
6543 }
6545 /* Implement TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS. */
6546 static bool
6548 {
6549 /* Naked functions should not allocate stack slots for arguments. */
6551 }
6553 /* Implement TARGET_WARN_FUNC_RETURN. */
6554 static bool
6556 {
6557 /* Naked functions are implemented entirely in assembly, including the
6558 return sequence, so suppress warnings about this. */
6560 }
6562 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
6564 static void
6566 {
6569 }
6571 /* Make ADDR suitable for use as a call or sibcall target. */
6573 rtx
6575 {
6577 {
6581 }
6583 }
6585 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6586 in context CONTEXT. HI_RELOC indicates a high-part reloc. */
6588 static void
6590 {
6594 {
6610 }
6615 }
6617 /* Return the memory model that encapsulates both given models. */
6619 enum memmodel
6621 {
6629 {
6636 else
6644 }
6645 }
6647 /* Return true if the .AQ suffix should be added to an AMO to implement the
6648 acquire portion of memory model MODEL. */
6650 static bool
6652 {
6653 /* ZTSO amo mappings require no annotations. */
6658 {
6671 }
6672 }
6674 /* Return true if the .RL suffix should be added to an AMO to implement the
6675 release portion of memory model MODEL. */
6677 static bool
6679 {
6680 /* ZTSO amo mappings require no annotations. */
6685 {
6698 }
6699 }
6701 /* Get REGNO alignment of vector mode.
6702 The alignment = LMUL when the LMUL >= 1.
6703 Otherwise, alignment = 1. */
6704 int
6706 {
6707 /* 3.3.2. LMUL = 2,4,8, register numbers should be multiple of 2,4,8.
6708 but for mask vector register, register numbers can be any number. */
6712 {
6716 else
6718 }
6725 }
6727 /* Define ASM_OUTPUT_OPCODE to do anything special before
6728 emitting an opcode. */
6731 {
6736 }
6738 /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are:
6740 'h' Print the high-part relocation associated with OP, after stripping
6741 any outermost HIGH.
6742 'R' Print the low-part relocation associated with OP.
6743 'C' Print the integer branch condition for comparison OP.
6744 'N' Print the inverse of the integer branch condition for comparison OP.
6745 'A' Print the atomic operation suffix for memory model OP.
6746 'I' Print the LR suffix for memory model OP.
6747 'J' Print the SC suffix for memory model OP.
6748 'L' Print a non-temporal locality hints instruction.
6749 'z' Print x0 if OP is zero, otherwise print OP normally.
6750 'i' Print i if the operand is not a register.
6751 'S' Print shift-index of single-bit mask OP.
6752 'T' Print shift-index of inverted single-bit mask OP.
6753 '~' Print w if TARGET_64BIT is true; otherwise not print anything.
6755 Note please keep this list and the list in riscv.md in sync. */
6757 static void
6759 {
6760 /* `~` does not take an operand so op will be null
6761 Check for before accessing op.
6762 */
6764 {
6768 }
6773 {
6775 /* Print 'OP' variant for RVV instructions.
6776 1. If the operand is VECTOR REG, we print 'v'(vnsrl.wv).
6777 2. If the operand is CONST_INT/CONST_VECTOR, we print 'i'(vnsrl.wi).
6778 3. If the operand is SCALAR REG, we print 'x'(vnsrl.wx). */
6780 {
6785 else
6787 }
6788 else
6789 {
6792 else
6794 }
6796 }
6798 rtx elt;
6802 else
6803 {
6812 else
6814 }
6816 }
6818 rtx elt;
6823 else
6826 }
6829 {
6830 /* Calculate lmul according to mode and print the value. */
6833 }
6835 {
6836 /* If it is a const_int value, it denotes the VLMUL field enum. */
6839 {
6863 }
6864 }
6865 else
6868 }
6871 {
6872 /* Print for RVV mask operand.
6873 If op is reg, print ",v0.t".
6874 Otherwise, don't print anything. */
6877 }
6879 {
6880 /* Tail && Mask policy. */
6882 }
6883 else
6886 }
6898 /* The RTL names match the instruction names. */
6903 /* The RTL names match the instruction names. */
6917 }
6922 /* LR ops only have an annotation for SEQ_CST in the Ztso mapping. */
6929 }
6934 /* SC ops only have an annotation for SEQ_CST in the Ztso mapping. */
6941 }
6944 {
6947 {
6957 }
6962 }
6974 {
6978 }
6980 {
6984 }
6986 {
6991 }
6993 {
6999 }
7002 {
7012 else
7017 {
7019 {
7022 }
7026 {
7029 }
7032 }
7039 else
7042 }
7043 }
7044 }
7046 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P */
7047 static bool
7049 {
7051 }
7053 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
7055 static void
7057 {
7065 {
7087 }
7090 }
7092 static bool
7094 {
7096 }
7098 /* Return true if EXP should be placed in the small data section. */
7100 static bool
7102 {
7103 /* Because default_use_anchors_for_symbol_p doesn't gather small data to use
7104 the anchor symbol to address nearby objects. In large model, it can get
7105 the better result using the anchor optimization. */
7113 {
7116 }
7119 }
7121 /* Switch to the appropriate section for output of DECL. */
7126 {
7128 {
7134 }
7135 }
7137 /* Switch to the appropriate section for output of DECL. */
7139 static void
7141 {
7146 {
7153 }
7155 {
7162 /* If we're using one_only, then there needs to be a .gnu.linkonce
7163 prefix to the section name. */
7170 }
7172 }
7174 /* Constant pools are per-function when in large code model. */
7178 {
7180 }
7182 static bool
7184 {
7185 /* We can't use blocks for constants when we're using a per-function
7186 constant pool. */
7188 }
7190 /* Return a section for X, handling small data. */
7195 {
7196 /* The literal pool stays with the function. */
7203 {
7205 {
7206 /* Rename .rodata.cst* to .srodata.cst*. */
7210 }
7214 }
7217 }
7219 /* Make the last instruction frame-related and note that it performs
7220 the operation described by FRAME_PATTERN. */
7222 static void
7224 {
7225 rtx insn;
7230 frame_pattern,
7232 }
7234 /* Return a frame-related rtx that stores REG at MEM.
7235 REG must be a single register. */
7237 static rtx
7239 {
7243 }
7245 /* Returns true if the current function might contain a far jump. */
7247 static bool
7249 {
7255 /* We can't change far_jump_used during or after reload, as there is
7256 no chance to change stack frame layout. So we must rely on the
7257 conservative heuristic below having done the right thing. */
7261 /* Estimate the function length. */
7265 /* Conservatively determine whether some jump might exceed 1 MiB
7266 displacement. */
7271 }
7273 /* Return true, if the current function must save the incoming return
7274 address. */
7276 static bool
7278 {
7279 /* The $ra register is call-clobbered: if this is not a leaf function,
7280 save it. */
7284 /* We need to save the incoming return address if __builtin_eh_return
7285 is being used to set a different return address. */
7289 /* Far jumps/branches use $ra as a temporary to set up the target jump
7290 location (clobbering the incoming return address). */
7294 /* We need to save it if anyone has used that. */
7298 /* Need not to use ra for leaf when frame pointer is turned off by
7299 option whatever the omit-leaf-frame's value. */
7305 }
7307 /* Return true if the current function must save register REGNO. */
7309 static bool
7311 {
7319 /* Save callee-saved V registers. */
7330 /* If this is an interrupt handler, then must save extra registers. */
7332 {
7333 /* zero register is always zero. */
7337 /* The function will return the stack pointer to its original value. */
7341 /* By convention, we assume that gp and tp are safe. */
7345 /* We must save every register used in this function. If this is not a
7346 leaf function, then we must save all temporary registers. */
7350 }
7353 }
7355 /* Return TRUE if Zcmp push and pop insns should be
7356 avoided. FALSE otherwise.
7357 Only use multi push & pop if all GPRs masked can be covered,
7358 and stack access is SP based,
7359 and GPRs are at top of the stack frame,
7360 and no conflicts in stack allocation with other features */
7361 static bool
7363 {
7373 }
7375 /* Determine whether to use multi push insn. */
7376 static bool
7378 {
7383 }
7385 /* Return TRUE if a libcall to save/restore GPRs should be
7386 avoided. FALSE otherwise. */
7387 static bool
7389 {
7392 || frame_pointer_needed
7399 }
7401 /* Determine whether to call GPR save/restore routines. */
7402 static bool
7404 {
7409 }
7411 /* Determine which GPR save/restore routine to call. */
7413 static unsigned
7415 {
7420 }
7422 /* calculate number of s regs in multi push and pop.
7423 Note that {s0-s10} is not valid in Zcmp, use {s0-s11} instead. */
7424 static unsigned
7426 {
7430 }
7432 /* calculate number of regs(ra, s0-sx) in multi push and pop. */
7433 static unsigned
7435 {
7436 /* 1 is for ra */
7438 }
7440 /* Handle 16 bytes align for poly_int. */
7441 static poly_int64
7443 {
7445 }
7447 static HOST_WIDE_INT
7449 {
7451 }
7453 /* Handle stack align for poly_int. */
7454 static poly_int64
7456 {
7458 }
7460 static HOST_WIDE_INT
7462 {
7464 }
7466 /* Populate the current function's riscv_frame_info structure.
7468 RISC-V stack frames grown downward. High addresses are at the top.
7470 +-------------------------------+
7471 | |
7472 | incoming stack arguments |
7473 | |
7474 +-------------------------------+ <-- incoming stack pointer
7475 | |
7476 | callee-allocated save area |
7477 | for arguments that are |
7478 | split between registers and |
7479 | the stack |
7480 | |
7481 +-------------------------------+ <-- arg_pointer_rtx
7482 | |
7483 | callee-allocated save area |
7484 | for register varargs |
7485 | |
7486 +-------------------------------+ <-- hard_frame_pointer_rtx;
7487 | | stack_pointer_rtx + gp_sp_offset
7488 | GPR save area | + UNITS_PER_WORD
7489 | |
7490 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
7491 | | + UNITS_PER_FP_REG
7492 | FPR save area |
7493 | |
7494 +-------------------------------+ <-- stack_pointer_rtx
7495 | | + v_sp_offset_top
7496 | Vector Registers save area |
7497 | |
7498 | ----------------------------- | <-- stack_pointer_rtx
7499 | padding | + v_sp_offset_bottom
7500 +-------------------------------+ <-- frame_pointer_rtx (virtual)
7501 | |
7502 | local variables |
7503 | |
7504 P +-------------------------------+
7505 | |
7506 | outgoing stack arguments |
7507 | |
7508 +-------------------------------+ <-- stack_pointer_rtx
7510 Dynamic stack allocations such as alloca insert data at point P.
7511 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
7512 hard_frame_pointer_rtx unchanged. */
7514 static HOST_WIDE_INT riscv_first_stack_step (struct riscv_frame_info *frame, poly_int64 remaining_size);
7516 static void
7518 {
7520 poly_int64 offset;
7527 /* Adjust the outgoing arguments size if required. Keep it in sync with what
7528 the mid-end is doing. */
7531 /* In an interrupt function, there are two cases in which t0 needs to be used:
7532 1, If we have a large frame, then we need to save/restore t0. We check for
7533 this before clearing the frame struct.
7534 2, Need to save and restore some CSRs in the frame. */
7536 {
7541 }
7546 {
7547 /* Find out which GPRs we need to save. */
7550 || (interrupt_save_prologue_temp
7554 /* If this function calls eh_return, we must also save and restore the
7555 EH data registers. */
7560 /* Find out which FPRs we need to save. This loop must iterate over
7561 the same space as its companion in riscv_for_each_saved_reg. */
7567 /* Find out which V registers we need to save. */
7571 {
7573 num_v_saved++;
7574 }
7575 }
7578 {
7581 /* 1 is for ra */
7583 /* Only use save/restore routines if they don't alter the stack size. */
7586 {
7587 /* Libcall saves/restores 3 registers at once, so we need to
7588 allocate 12 bytes for callee-saved register. */
7593 }
7596 {
7597 /* num(ra, s0-sx) */
7601 }
7602 }
7604 /* In an interrupt function, we need extra space for the initial saves of CSRs. */
7607 || (TARGET_ZFINX
7608 /* Except for RISCV_PROLOGUE_TEMP_REGNUM. */
7610 /* Save and restore FCSR. */
7611 /* TODO: When P or V extensions support interrupts, some of their CSRs
7612 may also need to be saved and restored. */
7615 /* At the bottom of the frame are any outgoing stack arguments. */
7617 /* Next are local stack variables. */
7619 /* The virtual frame pointer points above the local variables. */
7621 /* Next are the callee-saved VRs. */
7625 frame->v_sp_offset_bottom
7627 /* Next are the callee-saved FPRs. */
7631 /* Next are the callee-saved GPRs. */
7633 {
7635 /* align to 16 bytes and add paddings to GPR part to honor
7636 both stack alignment and zcmp pus/pop size alignment. */
7641 }
7643 /* The hard frame pointer points above the callee-saved GPRs. */
7645 /* Above the hard frame pointer is the callee-allocated varags save area. */
7647 /* Next is the callee-allocated area for pretend stack arguments. */
7649 /* Arg pointer must be below pretend args, but must be above alignment
7650 padding. */
7654 /* Next points the incoming stack pointer and any incoming arguments. */
7655 }
7657 /* Implement TARGET_CAN_INLINE_P. Determine whether inlining the function
7658 CALLER into the function CALLEE is safe. Inlining should be rejected if
7659 there is no always_inline attribute and the target options differ except
7660 for differences in ISA extensions or performance tuning options like the
7661 code model, TLS dialect, and stack protector, etc. Inlining is
7662 permissible when the non-ISA extension options are identical and the ISA
7663 extensions of CALLEE are a subset of those of CALLER, thereby improving
7664 the performance of Function Multi-Versioning. */
7666 static bool
7668 {
7672 /* It's safe to inline if callee has no opts. */
7684 /* Callee and caller should have the same target options except for ISA. */
7691 /* Callee's ISA should be a subset of the caller's ISA. */
7695 /* If the callee has always_inline set, we can ignore the rest attributes. */
7718 }
7720 /* Make sure that we're not trying to eliminate to the wrong hard frame
7721 pointer. */
7723 static bool
7725 {
7727 }
7729 /* Helper to determine if reg X pertains to stack. */
7730 bool
7732 {
7738 }
7740 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
7741 or argument pointer. TO is either the stack pointer or hard frame
7742 pointer. */
7744 poly_int64
7746 {
7755 else
7762 else
7766 }
7768 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
7769 previous frame. */
7771 rtx
7773 {
7778 }
7780 /* Emit code to change the current function's return address to
7781 ADDRESS. SCRATCH is available as a scratch register, if needed.
7782 ADDRESS and SCRATCH are both word-mode GPRs. */
7784 void
7786 {
7787 rtx slot_address;
7793 }
7795 /* Save register REG to MEM. Make the instruction frame-related. */
7797 static void
7799 {
7802 }
7804 /* Restore register REG from MEM. */
7806 static void
7808 {
7815 {
7816 rtx cfa_adjust_rtx
7820 }
7824 }
7826 /* A function to save or store a register. The first argument is the
7827 register and the second is the stack slot. */
7830 /* Use FN to save or restore register REGNO. MODE is the register's
7831 mode and OFFSET is the offset of its save slot from the current
7832 stack pointer. */
7834 static void
7837 {
7838 rtx mem;
7842 }
7844 /* Return the next register up from REGNO up to LIMIT for the callee
7845 to save or restore. OFFSET will be adjusted accordingly.
7846 If INC is set, then REGNO will be incremented first.
7847 Returns INVALID_REGNUM if there is no such next register. */
7849 static unsigned int
7852 {
7854 regno++;
7857 {
7859 {
7862 }
7864 regno++;
7865 }
7867 }
7869 /* Return TRUE if provided REGNO is eh return data register. */
7871 static bool
7873 {
7881 {
7883 }
7886 }
7888 /* Call FN for each register that is saved by the current function.
7889 SP_OFFSET is the offset of the current stack pointer from the start
7890 of the frame. */
7892 static void
7895 {
7901 /* Save the link register and s-registers. */
7907 {
7911 /* If this is a normal return in a function that calls the eh_return
7912 builtin, then do not restore the eh return data registers as that
7913 would clobber the return value. But we do still need to save them
7914 in the prologue, and restore them for an exception return, so we
7915 need special handling here. */
7920 /* In an interrupt function, save and restore some necessary CSRs in the stack
7921 to avoid changes in CSRs. */
7925 || (TARGET_ZFINX
7927 {
7928 /* Always assume FCSR occupy UNITS_PER_WORD to prevent stack
7929 offset misaligned later. */
7932 {
7938 }
7939 else
7940 {
7946 }
7948 }
7951 {
7952 /* Get the next reg/offset pair. */
7956 /* Validate everything before emitting a mempair instruction. */
7961 {
7969 /* If the operands fit into a mempair insn, then emit one. */
7971 {
7976 }
7977 }
7978 }
7981 }
7983 /* This loop must iterate over the same space as its companion in
7984 riscv_compute_frame_info. */
7985 first_fp_offset
7989 {
7998 num_masked_fp++;
7999 }
8000 }
8002 /* Call FN for each V register that is saved by the current function. */
8004 static void
8007 {
8010 {
8014 else
8015 {
8017 rtx insn
8020 }
8021 }
8023 /* Select the mode where LMUL is 1 and SEW is largest. */
8027 {
8028 /* This loop must iterate over the same space as its companion in
8029 riscv_compute_frame_info. */
8032 {
8035 {
8038 {
8041 stack_pointer_rtx,
8043 }
8044 else
8051 }
8052 }
8053 }
8054 else
8055 {
8056 /* This loop must iterate over the same space as its companion in
8057 riscv_compute_frame_info. */
8060 {
8063 {
8070 }
8071 }
8072 }
8073 }
8075 /* For stack frames that can't be allocated with a single ADDI instruction,
8076 compute the best value to initially allocate. It must at a minimum
8077 allocate enough space to spill the callee-saved registers. If TARGET_RVC,
8078 try to pick a value that will allow compression of the register saves
8079 without adding extra instructions. */
8081 static HOST_WIDE_INT
8083 {
8084 HOST_WIDE_INT remaining_const_size;
8086 remaining_const_size
8089 else
8092 /* First step must be set to the top of vector registers save area if any
8093 vector registers need be preserved. */
8100 poly_int64 callee_saved_first_step =
8103 HOST_WIDE_INT min_first_step =
8109 /* As an optimization, use the least-significant bits of the total frame
8110 size, so that the second adjustment step is just LUI + ADD. */
8117 {
8118 /* If we need two subtracts, and one is small enough to allow compressed
8119 loads and stores, then put that one first. */
8124 /* If we need LUI + ADDI + ADD for the second adjustment step, then start
8125 with the minimum first step, so that we can get compressed loads and
8126 stores. */
8129 }
8132 }
8134 static rtx
8136 {
8144 {
8145 /* The save order is ra, s0, s1, s2 to s11. */
8152 else
8157 stack_pointer_rtx,
8158 offset));
8162 }
8164 /* Debug info for adjust sp. */
8165 adjust_sp_rtx =
8169 dwarf);
8171 }
8173 static rtx
8175 {
8187 {
8188 /* The save order is s11-s0, ra
8189 from high to low addr. */
8198 }
8200 /* Debug info for adjust sp. */
8201 adjust_sp_rtx
8206 }
8208 static void
8210 {
8213 else
8215 }
8217 /*zcmp multi push and pop code_for_push_pop function ptr array */
8243 code_for_gpr_multi_popret_up_to_s11,
8244 code_for_gpr_multi_popretz_up_to_s11}};
8246 /* Set a probe loop for stack clash protection. */
8247 static void
8250 HOST_WIDE_INT offset)
8251 {
8254 /* Loop. */
8258 /* Allocate and probe stack. */
8261 STACK_CLASH_CALLER_GUARD));
8264 /* Adjust the remaining vector length. */
8268 /* Branch if there's still more bytes to probe. */
8273 }
8275 /* Adjust scalable frame of vector for prologue && epilogue. */
8277 static void
8279 {
8287 /* If doing stack clash protection then we use a loop to allocate and probe
8288 the stack. */
8290 {
8292 {
8296 {
8300 }
8303 }
8305 HOST_WIDE_INT min_probe_threshold
8309 {
8310 /* This is done to provide unwinding information for the stack
8311 adjustments we're about to do, however to prevent the optimizers
8312 from removing the T3 move and leaving the CFA note (which would be
8313 very wrong) we tie the old and new stack pointer together.
8314 The tie will expand to nothing but the optimizers will not touch
8315 the instruction. */
8321 /* We want the CFA independent of the stack pointer for the
8322 duration of the loop. */
8325 }
8328 min_probe_threshold);
8330 /* Allocate the residual. */
8333 /* Now reset the CFA register if needed. */
8335 {
8339 }
8342 }
8346 else
8353 adjust_frame_rtx
8358 NULL_RTX);
8361 }
8363 static rtx
8366 {
8372 }
8374 static unsigned
8376 {
8383 }
8385 /* Allocate SIZE bytes of stack space using TEMP1 as a scratch register.
8386 If SIZE is not large enough to require a probe this function will only
8387 adjust the stack.
8389 We emit barriers after each stack adjustment to prevent optimizations from
8390 breaking the invariant that we never drop the stack more than a page. This
8391 invariant is needed to make it easier to correctly handle asynchronous
8392 events, e.g. if we were to allow the stack to be dropped by more than a page
8393 and then have multiple probes up and we take a signal somewhere in between
8394 then the signal handler doesn't know the state of the stack and can make no
8395 assumptions about which pages have been probed. */
8397 static void
8399 {
8400 HOST_WIDE_INT guard_size
8405 rtx insn;
8407 /* We should always have a positive probe threshold. */
8410 /* If SIZE is not large enough to require probing, just adjust the stack and
8411 exit. */
8414 {
8416 {
8419 else
8421 }
8424 {
8427 }
8429 {
8438 }
8439 else
8440 {
8446 }
8448 /* We must have allocated the remainder of the stack frame.
8449 Emit a stack tie if we have a frame pointer so that the
8450 allocation is ordered WRT fp setup and subsequent writes
8451 into the frame. */
8456 }
8462 "Stack clash prologue: " HOST_WIDE_INT_PRINT_DEC
8465 /* Round size to the nearest multiple of guard_size, and calculate the
8466 residual as the difference between the original size and the rounded
8467 size. */
8471 /* We can handle a small number of allocations/probes inline. Otherwise
8472 punt to a loop. */
8474 {
8477 {
8483 guard_used_by_caller));
8485 }
8487 }
8488 else
8489 {
8490 /* Compute the ending address. */
8496 {
8497 /* We want the CFA independent of the stack pointer for the
8498 duration of the loop. */
8502 }
8504 /* This allocates and probes the stack. */
8508 /* Now reset the CFA register if needed. */
8510 {
8515 }
8518 }
8520 /* Handle any residuals. Residuals of at least MIN_PROBE_THRESHOLD have to
8521 be probed. This maintains the requirement that each page is probed at
8522 least once. For initial probing we probe only if the allocation is
8523 more than GUARD_SIZE - buffer, and below the saved registers we probe
8524 if the amount is larger than buffer. GUARD_SIZE - buffer + buffer ==
8525 GUARD_SIZE. This works that for any allocation that is large enough to
8526 trigger a probe here, we'll have at least one, and if they're not large
8527 enough for this code to emit anything for them, The page would have been
8528 probed by the saving of FP/LR either by this function or any callees. If
8529 we don't have any callees then we won't have more stack adjustments and so
8530 are still safe. */
8532 {
8541 {
8544 "Stack clash prologue residuals: "
8545 HOST_WIDE_INT_PRINT_DEC " bytes, probing will be required."
8549 guard_used_by_caller));
8551 }
8552 }
8553 }
8555 /* Expand the "prologue" pattern. */
8557 void
8559 {
8574 /* prefer multi-push to save-restore libcall. */
8576 {
8578 /* If there are vector registers that need to be saved, then it can only
8579 be reduced to the frame->v_sp_offset_top position at most, since the
8580 vector registers will need to be saved one by one by decreasing the SP
8581 later. */
8582 poly_int64 remaining_size_above_varea
8593 else
8599 /* emit multi push insn & dwarf along with it. */
8607 /* Temporarily fib that we need not save GPRs. */
8610 /* push FPRs into the additional reserved space by cm.push. */
8612 {
8613 unsigned mask_fprs_push
8619 }
8620 }
8621 /* When optimizing for size, call a subroutine to save the registers. */
8623 {
8633 }
8637 {
8640 /* RISCV_PROLOGUE_TEMP may be used to handle some CSR for
8641 interrupts, such as fcsr. */
8655 }
8657 /* Save the GP, FP registers. */
8659 {
8661 {
8667 }
8669 }
8671 /* Undo the above fib. */
8675 /* Set up the frame pointer, if we're using one. */
8677 {
8683 }
8685 /* Save the V registers. */
8689 /* Allocate the rest of the frame. */
8691 {
8692 /* Two step adjustment:
8693 1.scalable frame. 2.constant frame. */
8696 {
8697 /* First for scalable frame. */
8702 }
8704 /* Second step for constant frame. */
8707 {
8708 /* We must have allocated stack space for the scalable frame.
8709 Emit a stack tie if we have a frame pointer so that the
8710 allocation is ordered WRT fp setup and subsequent writes
8711 into the frame. */
8715 }
8718 }
8720 {
8723 else
8725 }
8726 }
8728 static rtx
8730 {
8738 /* Debug info for adjust sp. */
8739 adjust_sp_rtx
8746 {
8749 }
8752 }
8754 static rtx
8756 {
8761 /* Debug info for adjust sp. */
8762 adjust_sp_rtx =
8766 dwarf);
8770 {
8773 }
8776 }
8778 static void
8781 {
8782 rtx insn;
8788 else
8795 }
8797 /* Expand an "epilogue", "sibcall_epilogue", or "eh_return_internal" pattern;
8798 style says which. */
8800 void
8802 {
8803 /* Split the frame into 3 steps. STEP1 is the amount of stack we should
8804 deallocate before restoring the registers. STEP2 is the amount we
8805 should deallocate afterwards including the callee saved regs. STEP3
8806 is the amount deallocated by save-restore libcall.
8808 Start off by assuming that no registers need to be restored. */
8814 bool use_multi_pop_normal
8816 bool use_multi_pop_sibcall
8820 bool use_restore_libcall
8821 = !use_multi_pop
8826 unsigned multipop_size
8831 rtx insn;
8833 /* We need to add memory barrier to prevent read from deallocated stack. */
8838 {
8844 }
8847 {
8850 }
8852 /* Reset the epilogue cfa info before starting to emit the epilogue. */
8855 /* Move past any dynamic stack allocations. */
8857 {
8858 /* Emit a barrier to prevent loads from a deallocated stack. */
8869 {
8875 }
8876 else
8877 {
8880 {
8882 }
8884 {
8888 }
8889 else
8890 {
8894 }
8895 }
8899 adjust));
8903 dwarf_adj);
8912 {
8916 }
8917 }
8922 /* If we need to restore registers, deallocate as much stack as
8923 possible in the second step without going out of range. */
8925 {
8929 step2
8931 }
8938 poly_int64 step1;
8939 /* STEP1 must be set to the bottom of vector registers save area if any
8940 vector registers need be preserved. */
8942 {
8945 }
8946 else
8949 /* Set TARGET to BASE + STEP1. */
8951 {
8952 /* Emit a barrier to prevent loads from a deallocated stack. */
8956 /* Restore the scalable frame which is assigned in prologue. */
8958 {
8964 }
8966 /* Get an rtx for STEP1 that we can add to BASE.
8967 Skip if adjust equal to zero. */
8970 {
8973 {
8977 stack_pointer_rtx,
8981 }
8983 {
8986 }
8989 stack_pointer_rtx,
8990 adjust));
8992 rtx cfa_adjust_rtx
8995 Pmode));
9001 }
9002 }
9004 {
9005 /* Tell riscv_restore_reg to emit dwarf to redefine CFA when restoring
9006 old value of FP. */
9008 }
9011 {
9014 {
9018 }
9019 }
9025 {
9028 /* RISCV_PROLOGUE_TEMP may be used to handle some CSR for
9029 interrupts, such as fcsr. */
9033 }
9035 /* Restore the registers. */
9042 {
9047 }
9055 /* Deallocate the final bit of the frame. */
9057 {
9062 rtx cfa_adjust_rtx
9069 }
9072 {
9073 /* restore FPRs pushed by cm.push. */
9080 /* Undo the above fib. */
9084 multipop_size);
9087 }
9089 {
9097 }
9099 /* Add in the __builtin_eh_return stack adjustment. */
9102 EH_RETURN_STACKADJ_RTX));
9104 /* Return from interrupt. */
9106 {
9117 else
9119 }
9122 }
9124 /* Implement EPILOGUE_USES. */
9126 bool
9128 {
9133 {
9134 /* An interrupt function restores temp regs, so we must indicate that
9135 they are live at function end. */
9139 }
9142 }
9144 static bool
9146 {
9153 }
9155 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
9157 static sbitmap
9159 {
9160 HOST_WIDE_INT offset;
9170 {
9171 /* We can only wrap registers that have small operand offsets.
9172 For large offsets a pseudo register might be needed which
9173 cannot be created during the shrink wrapping pass. */
9178 }
9183 {
9186 /* We can only wrap registers that have small operand offsets.
9187 For large offsets a pseudo register might be needed which
9188 cannot be created during the shrink wrapping pass. */
9193 }
9195 /* Don't mess with the hard frame pointer. */
9202 }
9204 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
9206 static sbitmap
9208 {
9216 function_abi_aggregator callee_abis;
9223 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
9243 }
9245 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
9247 static void
9249 {
9250 /* Nothing to do for riscv. */
9251 }
9253 static void
9255 {
9256 HOST_WIDE_INT offset;
9262 {
9267 }
9272 {
9279 }
9280 }
9282 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
9284 static void
9286 {
9288 }
9290 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
9292 static void
9294 {
9296 }
9298 static void
9300 {
9308 }
9310 /* Return nonzero if this function is known to have a null epilogue.
9311 This allows the optimizer to omit jumps to jumps if no stack
9312 was created. */
9314 bool
9316 {
9319 }
9321 /* Given that there exists at least one variable that is set (produced)
9322 by OUT_INSN and read (consumed) by IN_INSN, return true iff
9323 IN_INSN represents one or more memory store operations and none of
9324 the variables set by OUT_INSN is used by IN_INSN as the address of a
9325 store operation. If either IN_INSN or OUT_INSN does not represent
9326 a "single" RTL SET expression (as loosely defined by the
9327 implementation of the single_set function) or a PARALLEL with only
9328 SETs, CLOBBERs, and USEs inside, this function returns false.
9330 Borrowed from rs6000, riscv_store_data_bypass_p checks for certain
9331 conditions that result in assertion failures in the generic
9332 store_data_bypass_p function and returns FALSE in such cases.
9334 This is required to make -msave-restore work with the sifive-7
9335 pipeline description. */
9337 bool
9339 {
9347 {
9349 {
9352 {
9355 {
9357 {
9364 }
9365 }
9366 }
9367 }
9368 }
9369 else
9370 {
9376 {
9384 {
9387 {
9392 {
9399 }
9400 }
9401 }
9402 }
9403 }
9406 }
9408 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
9410 When floating-point registers are wider than integer ones, moves between
9411 them must go through memory. */
9413 static bool
9415 reg_class_t class2)
9416 {
9420 && !TARGET_XTHEADFMV
9422 }
9424 /* Implement TARGET_REGISTER_MOVE_COST. */
9426 static int
9429 {
9435 }
9437 /* Implement TARGET_HARD_REGNO_NREGS. */
9439 static unsigned int
9441 {
9443 {
9444 /* Handle fractional LMUL, it only occupy part of vector register but
9445 still need one vector register to hold. */
9450 }
9452 /* For tuple modes, the number of register = NF * LMUL. */
9454 {
9461 else
9462 {
9465 }
9466 }
9468 /* For VLS modes, we allocate registers according to TARGET_MIN_VLEN. */
9470 {
9474 else
9476 }
9478 /* mode for VL or VTYPE are just a marker, not holding value,
9479 so it always consume one register. */
9484 /* Assume every valid non-vector mode fits in one vector register. */
9491 /* All other registers are word-sized. */
9493 }
9495 /* Implement TARGET_HARD_REGNO_MODE_OK. */
9497 static bool
9499 {
9503 {
9509 }
9511 {
9522 /* Only use callee-saved registers if a potential callee is guaranteed
9523 to spill the requisite width. */
9528 }
9530 {
9540 }
9544 else
9547 /* Require same callee-savedness for all registers. */
9553 /* Only use even registers in RV32 ZDINX */
9558 }
9561 }
9563 /* Implement TARGET_MODES_TIEABLE_P.
9565 Don't allow floating-point modes to be tied, since type punning of
9566 single-precision and double-precision is implementation defined. */
9568 static bool
9570 {
9571 /* We don't allow different REG_CLASS modes tieable since it
9572 will cause ICE in register allocation (RA).
9573 E.g. V2SI and DI are not tieable. */
9579 }
9581 /* Implement TARGET_CLASS_MAX_NREGS. */
9583 static unsigned char
9585 {
9596 }
9598 /* Implement TARGET_MEMORY_MOVE_COST. */
9600 static int
9602 {
9605 }
9607 /* Return the number of instructions that can be issued per cycle. */
9609 static int
9611 {
9613 }
9615 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9616 static int
9618 {
9626 /* GHOST insns are used for blockage and similar cases which
9627 effectively end a cycle. */
9631 /* If we ever encounter an insn with an unknown type, trip
9632 an assert so we can find and fix this problem. */
9635 /* If we ever encounter an insn without an insn reservation, trip
9636 an assert so we can find and fix this problem. */
9640 }
9642 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
9643 instruction fusion of some sort. */
9645 static bool
9647 {
9649 }
9651 /* Return true iff the instruction fusion described by OP is enabled. */
9653 static bool
9655 {
9657 }
9659 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
9660 should be kept together during scheduling. */
9662 static bool
9664 {
9667 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
9676 {
9677 /* We are trying to match the following:
9678 prev (slli) == (set (reg:DI rD)
9679 (ashift:DI (reg:DI rS) (const_int 32)))
9680 curr (slri) == (set (reg:DI rD)
9681 (lshiftrt:DI (reg:DI rD) (const_int <shift>)))
9682 with <shift> being either 32 for FUSE_ZEXTW, or
9683 `less than 32 for FUSE_ZEXTWS. */
9699 }
9702 {
9703 /* We are trying to match the following:
9704 prev (slli) == (set (reg:DI rD)
9705 (ashift:DI (reg:DI rS) (const_int 48)))
9706 curr (slri) == (set (reg:DI rD)
9707 (lshiftrt:DI (reg:DI rD) (const_int 48))) */
9720 }
9723 {
9724 /* We are trying to match the following:
9725 prev (add) == (set (reg:DI rD)
9726 (plus:DI (reg:DI rS1) (reg:DI rS2))
9727 curr (ld) == (set (reg:DI rD)
9728 (mem:DI (reg:DI rD))) */
9738 /* We are trying to match the following:
9739 prev (add) == (set (reg:DI rD)
9740 (plus:DI (reg:DI rS1) (reg:DI rS2)))
9741 curr (lw) == (set (any_extend:DI (mem:SUBX (reg:DI rD)))) */
9752 }
9755 {
9756 /* We are trying to match the following:
9757 prev (add) == (set (reg:DI rS)
9758 (plus:DI (reg:DI rS) (const_int))
9759 curr (ld) == (set (reg:DI rD)
9760 (mem:DI (reg:DI rS))) */
9769 }
9772 {
9773 /* We are trying to match the following:
9774 prev (lui) == (set (reg:DI rD) (const_int UPPER_IMM_20))
9775 curr (addi) == (set (reg:DI rD)
9776 (plus:DI (reg:DI rD) (const_int IMM12))) */
9786 }
9789 {
9790 /* We are trying to match the following:
9791 prev (auipc) == (set (reg:DI rD) (unspec:DI [...] UNSPEC_AUIPC))
9792 curr (addi) == (set (reg:DI rD)
9793 (plus:DI (reg:DI rD) (const_int IMM12)))
9794 and
9795 prev (auipc) == (set (reg:DI rD) (unspec:DI [...] UNSPEC_AUIPC))
9796 curr (addi) == (set (reg:DI rD)
9797 (lo_sum:DI (reg:DI rD) (const_int IMM12))) */
9807 }
9810 {
9811 /* We are trying to match the following:
9812 prev (lui) == (set (reg:DI rD) (const_int UPPER_IMM_20))
9813 curr (ld) == (set (reg:DI rD)
9814 (mem:DI (plus:DI (reg:DI rD) (const_int IMM12)))) */
9835 }
9838 {
9839 /* We are trying to match the following:
9840 prev (auipc) == (set (reg:DI rD) (unspec:DI [...] UNSPEC_AUIPC))
9841 curr (ld) == (set (reg:DI rD)
9842 (mem:DI (plus:DI (reg:DI rD) (const_int IMM12)))) */
9849 }
9852 {
9853 /* We are trying to match the following:
9854 prev (sd) == (set (mem (plus (reg sp|fp) (const_int)))
9855 (reg rS1))
9856 curr (sd) == (set (mem (plus (reg sp|fp) (const_int)))
9857 (reg rS2)) */
9861 /* We can probably relax this condition. The documentation is a bit
9862 unclear about sub-word cases. So we just model DImode for now. */
9865 {
9871 /* Fail if we did not find both bases. */
9875 /* Fail if either base is not a register. */
9879 /* Fail if the bases are not the same register. */
9883 /* Originally the thought was to check MEM_ALIGN, but that was
9884 reporting incorrect alignments, even for SP/FP accesses, so we
9885 gave up on that approach. Instead just check for stack/hfp
9886 which we know are aligned. */
9891 /* The two stores must be contained within opposite halves of the
9892 same 16 byte aligned block of memory. We know that the stack
9893 pointer and the frame pointer have suitable alignment. So we
9894 just need to check the offsets of the two stores for suitable
9895 alignment. */
9896 /* Get the smaller offset into OFFSET_PREV. */
9900 /* If the smaller offset (OFFSET_PREV) is not 16 byte aligned,
9901 then fail. */
9905 /* The higher offset must be 8 bytes more than the lower
9906 offset. */
9908 }
9909 }
9912 }
9914 /* Adjust the cost/latency of instructions for scheduling.
9915 For now this is just used to change the latency of vector instructions
9916 according to their LMUL. We assume that an insn with LMUL == 8 requires
9917 eight times more execution cycles than the same insn with LMUL == 1.
9918 As this may cause very high latencies which lead to scheduling artifacts
9919 we currently only perform the adjustment when -madjust-lmul-cost is given.
9920 */
9921 static int
9924 {
9925 /* Only do adjustments for the generic out-of-order scheduling model. */
9935 {
9936 /* TODO: For ordered reductions scale the base cost relative to the
9937 number of units. */
9938 ;
9939 }
9941 /* Don't do any LMUL-based latency adjustment unless explicitly asked to. */
9945 /* vsetvl has a vlmul attribute but its latency does not depend on it. */
9954 {
9975 }
9977 /* If the latency was nonzero, keep it that way. */
9981 }
9983 /* Auxiliary function to emit RISC-V ELF attribute. */
9984 static void
9986 {
9995 }
9997 /* Output .variant_cc for function symbol which follows vector calling
9998 convention. */
10000 static void
10002 {
10004 {
10007 {
10011 }
10012 }
10013 }
10015 /* Implement ASM_DECLARE_FUNCTION_NAME. */
10017 void
10019 {
10024 {
10034 ? local_arch_str
10041 }
10042 }
10044 void
10046 {
10051 {
10053 }
10054 }
10056 /* Implement ASM_OUTPUT_DEF_FROM_DECLS. */
10058 void
10060 {
10065 }
10067 /* Implement ASM_OUTPUT_EXTERNAL. */
10069 void
10071 {
10074 }
10076 /* Implement TARGET_ASM_FILE_START. */
10078 static void
10080 {
10083 /* Instruct GAS to generate position-[in]dependent code. */
10086 /* If the user specifies "-mno-relax" on the command line then disable linker
10087 relaxation in the assembler. */
10091 /* If the user specifies "-mcsr-check" on the command line then enable csr
10092 check in the assembler. */
10098 }
10100 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
10101 in order to avoid duplicating too much logic from elsewhere. */
10103 static void
10106 tree function)
10107 {
10114 /* Pretend to be a post-reload pass while generating rtl. */
10117 /* Mark the end of the (empty) prologue. */
10120 /* Determine if we can use a sibcall to call FUNCTION directly. */
10123 /* We need two temporary registers in some cases. */
10127 /* Find out which register contains the "this" pointer. */
10130 else
10133 /* Add DELTA to THIS_RTX. */
10135 {
10138 {
10141 }
10143 }
10145 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
10147 {
10148 rtx addr;
10150 /* Set TEMP1 to *THIS_RTX. */
10153 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
10156 /* Load the offset and add it to THIS_RTX. */
10159 }
10161 /* Jump to the target function. */
10166 /* Run just enough of rest_of_compilation. This sequence was
10167 "borrowed" from alpha.cc. */
10177 /* Clean up the vars set above. Note that final_end_function resets
10178 the global pointer for us. */
10181 }
10183 /* Allocate a chunk of memory for per-function machine-dependent data. */
10187 {
10189 }
10191 /* Return the VLEN value associated with -march and -mrvv-vector-bits.
10192 TODO: So far we only support length-agnostic value. */
10193 static poly_uint16
10195 {
10199 {
10200 /* When targeting minimum VLEN > 32, we should use 64-bit chunk size.
10201 Otherwise we can not include SEW = 64bits.
10202 Runtime invariant: The single indeterminate represent the
10203 number of 64-bit chunks in a vector beyond minimum length of 64 bits.
10204 Thus the number of bytes in a vector is 8 + 8 * x1 which is
10205 riscv_vector_chunks * 8 = poly_int (8, 8). */
10207 /* Adjust BYTES_PER_RISCV_VECTOR according to TARGET_MIN_VLEN:
10208 - TARGET_MIN_VLEN = 64bit: [8,8]
10209 - TARGET_MIN_VLEN = 128bit: [16,16]
10210 - TARGET_MIN_VLEN = 256bit: [32,32]
10211 - TARGET_MIN_VLEN = 512bit: [64,64]
10212 - TARGET_MIN_VLEN = 1024bit: [128,128]
10213 - TARGET_MIN_VLEN = 2048bit: [256,256]
10214 - TARGET_MIN_VLEN = 4096bit: [512,512]
10215 FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit. */
10217 }
10218 else
10219 {
10220 /* When targeting minimum VLEN = 32, we should use 32-bit
10221 chunk size. Runtime invariant: The single indeterminate represent the
10222 number of 32-bit chunks in a vector beyond minimum length of 32 bits.
10223 Thus the number of bytes in a vector is 4 + 4 * x1 which is
10224 riscv_vector_chunks * 4 = poly_int (4, 4). */
10227 }
10229 /* Set riscv_vector_chunks as poly (1, 1) run-time constant if TARGET_VECTOR
10230 is enabled. Set riscv_vector_chunks as 1 compile-time constant if
10231 TARGET_VECTOR is disabled. riscv_vector_chunks is used in "riscv-modes.def"
10232 to set RVV mode size. The RVV machine modes size are run-time constant if
10233 TARGET_VECTOR is enabled. The RVV machine modes size remains default
10234 compile-time constant if TARGET_VECTOR is disabled. */
10236 {
10238 {
10245 }
10246 }
10247 else
10249 }
10251 /* 'Unpack' up the internal tuning structs and update the options
10252 in OPTS. The caller must have set up selected_tune and selected_arch
10253 as all the other target-specific codegen decisions are
10254 derived from them. */
10255 void
10257 {
10260 /* The presence of the M extension implies that division instructions
10261 are present, so include them unless explicitly disabled. */
10267 /* We might use a multiplication to calculate the scalable vector length at
10268 runtime. Therefore, require the M extension. */
10272 /* Likewise floating-point division and square root. */
10277 /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
10278 if both -mtune and -mcpu are not given. */
10283 ? &optimize_size_tune_info
10286 /* Use -mtune's setting for slow_unaligned_access, even when optimizing
10287 for size. For architectures that trap and emulate unaligned accesses,
10288 the performance cost is too great, even for -Os. Similarly, if
10289 -m[no-]strict-align is left unspecified, heed -mtune's advice. */
10293 /* By default, when -mno-vector-strict-align is not specified, do not allow
10294 unaligned vector memory accesses except if -mtune's setting explicitly
10295 allows it. */
10299 /* Make a note if user explicitly passed -mstrict-align for later
10300 builtin macro generation. Can't use target_flags_explicitly since
10301 it is set even for -mno-strict-align. */
10308 /* If the user hasn't specified a branch cost, use the processor's
10309 default. */
10313 /* FIXME: We don't allow TARGET_MIN_VLEN > 4096 since the datatypes of
10314 both GET_MODE_SIZE and GET_MODE_BITSIZE are poly_uint16.
10316 We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535. */
10321 /* FIXME: We don't support RVV in big-endian for now, we may enable RVV with
10322 big-endian after finishing full coverage testing. */
10326 /* Convert -march and -mrvv-vector-bits to a chunks count. */
10328 }
10330 /* Implement TARGET_OPTION_OVERRIDE. */
10332 void
10334 {
10335 #ifdef SUBTARGET_OVERRIDE_OPTIONS
10336 SUBTARGET_OVERRIDE_OPTIONS;
10337 #endif
10344 /* Always prefer medlow than medany for RV32 since medlow can access
10345 full address space. */
10359 /* We need to save the fp with ra for non-leaf functions with no fp and ra
10360 for leaf functions while no-omit-frame-pointer with
10361 omit-leaf-frame-pointer. The x_flag_omit_frame_pointer has the first
10362 priority to determine whether the frame pointer is needed. If we do not
10363 override it, the fp and ra will be stored for leaf functions, which is not
10364 our wanted. */
10367 {
10372 }
10374 /* We get better code with explicit relocs for CM_MEDLOW, but
10375 worse code for the others (for now). Pick the best default. */
10380 /* Require that the ISA supports the requested floating-point ABI. */
10385 /* RVE requires specific ABI. */
10387 {
10392 }
10394 /* ILP32E does not support the 'd' extension. */
10400 {
10404 }
10406 /* Zfinx require abi ilp32, ilp32e, lp64 or lp64e. */
10412 /* We do not yet support ILP32 on RV64. */
10416 /* Validate -mpreferred-stack-boundary= value. */
10419 {
10428 }
10431 #ifdef HAVE_AS_RISCV_ATTRIBUTE
10433 #else
10439 #endif
10443 {
10446 riscv_stack_protector_guard_offset_str);
10447 }
10452 {
10454 "%<-mstack-protector-guard-reg%> must be used "
10456 }
10459 {
10468 }
10471 {
10486 }
10490 /* Enforce that interval is the same size as guard size so the mid-end does
10491 the right thing. */
10493 param_stack_clash_protection_probe_interval,
10494 guard_size);
10496 /* The maybe_set calls won't update the value if the user has explicitly set
10497 one. Which means we need to validate that probing interval and guard size
10498 are equal. */
10499 int probe_interval
10506 param_sched_pressure_algorithm,
10507 SCHED_PRESSURE_MODEL);
10509 /* Function to allocate machine-dependent function status. */
10514 /* Save these options as the default ones in case we push and pop them later
10515 while processing functions with potential target attributes. */
10516 target_option_default_node = target_option_current_node
10518 }
10520 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
10521 Used by riscv_set_current_function to
10522 make sure optab availability predicates are recomputed when necessary. */
10524 void
10526 {
10531 else
10533 }
10535 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
10536 using the information saved in PTR. */
10538 static void
10542 {
10544 }
10548 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
10550 static void
10552 {
10553 /* We have only x0~x15 on RV32E/RV64E. */
10555 {
10558 }
10561 {
10564 }
10567 {
10570 }
10572 /* In the soft-float ABI, there are no callee-saved FP registers. */
10574 {
10577 }
10580 {
10588 }
10589 }
10591 /* Return a register priority for hard reg REGNO. */
10593 static int
10595 {
10596 /* Favor compressed registers to improve the odds of RVC instruction
10597 selection. */
10602 }
10604 /* Implement TARGET_TRAMPOLINE_INIT. */
10606 static void
10608 {
10614 /* Work out the offsets of the pointers from the start of the
10615 trampoline code. */
10618 /* Get pointers to the beginning and end of the code block. */
10625 {
10629 /* lui t2, hi(chain)
10630 lui t0, hi(func)
10631 addi t2, t2, lo(chain)
10632 jr t0, lo(func)
10633 */
10639 /* 0xfff. */
10645 /* Gen lui t2, hi(chain). */
10647 fixup_value);
10649 uimm_mask);
10657 /* Gen lui t0, hi(func). */
10659 fixup_value);
10661 uimm_mask);
10669 /* Gen addi t2, t2, lo(chain). */
10671 imm12_mask);
10674 lo_chain_code = OPCODE_ADDI
10684 /* Gen jr t0, lo(func). */
10686 imm12_mask);
10696 }
10697 else
10698 {
10702 /* auipc t2, 0
10703 l[wd] t0, target_function_offset(t2)
10704 l[wd] t2, static_chain_offset(t2)
10705 jr t0
10706 */
10718 /* Copy the trampoline code. */
10720 {
10725 }
10727 /* Set up the static chain pointer field. */
10731 /* Set up the target function field. */
10734 }
10736 /* Flush the code part of the trampoline. */
10739 }
10741 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
10743 static bool
10745 tree exp ATTRIBUTE_UNUSED)
10746 {
10747 /* Don't use sibcalls when use save-restore routine. */
10751 /* Don't use sibcall for naked functions. */
10755 /* Don't use sibcall for interrupt functions. */
10759 /* Don't use sibcalls in the large model, because a sibcall instruction
10760 expanding and a epilogue expanding both use RISCV_PROLOGUE_TEMP
10761 register. */
10766 }
10768 /* Get the interrupt type, return UNKNOWN_MODE if it's not
10769 interrupt function. */
10770 static enum riscv_privilege_levels
10772 {
10779 tree attr_args
10784 {
10793 }
10794 else
10795 /* Interrupt attributes are machine mode by default. */
10797 }
10799 /* Implement `TARGET_SET_CURRENT_FUNCTION'. Unpack the codegen decisions
10800 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
10801 of the function, if such exists. This function may be called multiple
10802 times on a single function so use aarch64_previous_fndecl to avoid
10803 setting up identical state. */
10805 /* Sanity checking for above function attributes. */
10806 static void
10808 {
10816 {
10826 {
10839 }
10841 /* Don't print the above diagnostics more than once. */
10843 }
10848 tree old_tree = (riscv_previous_fndecl
10854 /* If current function has no attributes but the previous one did,
10855 use the default node. */
10859 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
10860 the default have been handled by aarch64_save_restore_target_globals from
10861 aarch64_pragma_target_parse. */
10867 /* First set the target options. */
10871 /* The ISA extension can vary based on the function extension like target.
10872 Thus, make sure that the machine modes are reflected correctly here. */
10876 }
10878 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
10879 static tree
10881 {
10882 tree combined_attrs;
10884 enum riscv_privilege_levels old_interrupt_type
10886 enum riscv_privilege_levels new_interrupt_type
10889 /* Check old and new has same interrupt type. */
10895 /* Create combined attributes. */
10900 }
10902 /* Implement TARGET_CANNOT_COPY_INSN_P. */
10904 static bool
10906 {
10908 }
10910 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. */
10912 static bool
10914 {
10917 }
10919 static bool
10921 {
10923 }
10925 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
10927 static bool
10929 reg_class_t rclass)
10930 {
10931 /* We have RVV VLS modes and VLA modes sharing same REG_CLASS.
10932 In 'cprop_hardreg' stage, we will try to do hard reg copy propagation
10933 between wider mode (FROM) and narrow mode (TO).
10935 E.g. We should not allow copy propagation
10936 - RVVMF8BI (precision = [16, 16]) -> V32BI (precision = [32, 0])
10937 since we can't order their size which will cause ICE in regcprop.
10939 TODO: Even though they are have different size, they always change
10940 the whole register. We may enhance such case in regcprop to optimize
10941 it in the future. */
10946 /* Subregs of modes larger than one vector are ambiguous.
10947 A V4DImode with rv64gcv_zvl128b could, for example, span two registers/one
10948 register group of two at VLEN = 128 or one register at VLEN >= 256 and
10949 we cannot, statically, determine which part of it to extract.
10950 Therefore prevent that. */
10957 }
10959 /* Implement TARGET_CONSTANT_ALIGNMENT. */
10961 static HOST_WIDE_INT
10963 {
10968 }
10970 /* Implement TARGET_PROMOTE_FUNCTION_MODE. */
10972 /* This function is equivalent to default_promote_function_mode_always_promote
10973 except that it returns a promoted mode even if type is NULL_TREE. This is
10974 needed by libcalls which have no type (only a mode) such as fixed conversion
10975 routines that take a signed or unsigned char/short/int argument and convert
10976 it to a fixed type. */
10978 static machine_mode
10980 machine_mode mode,
10982 const_tree fntype ATTRIBUTE_UNUSED,
10984 {
10995 }
10997 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
10999 static void
11001 {
11002 /* Do nothing unless we have -msave-restore */
11005 }
11007 /* Return nonzero if register FROM_REGNO can be renamed to register
11008 TO_REGNO. */
11010 bool
11013 {
11014 /* Interrupt functions can only use registers that have already been
11015 saved by the prologue, even if they would normally be
11016 call-clobbered. */
11018 }
11020 /* Implement TARGET_NEW_ADDRESS_PROFITABLE_P. */
11022 bool
11024 {
11025 /* Prefer old address if it is less expensive. */
11031 }
11033 /* Helper function for generating gpr_save pattern. */
11035 rtx
11037 {
11039 /* 1 for unspec 2 for clobber t0/t1 and 1 for ra. */
11050 {
11053 rtx elt;
11055 /* t0 and t1 are CLOBBERs, others are USEs. */
11058 else
11062 }
11064 /* Largest number of caller-save register must set in mask if we are
11065 not using __riscv_save_0. */
11070 }
11072 static HOST_WIDE_INT
11074 {
11076 }
11078 static HOST_WIDE_INT
11080 {
11082 }
11084 bool
11086 {
11091 }
11093 /* Return true if it's valid gpr_save pattern. */
11095 bool
11097 {
11104 {
11107 {
11108 /* First element in parallel is unspec. */
11113 }
11114 else
11115 {
11116 /* Two CLOBBER and USEs, must check the order. */
11122 }
11124 }
11126 }
11128 /* Implement TARGET_ASAN_SHADOW_OFFSET. */
11130 static unsigned HOST_WIDE_INT
11132 {
11133 /* We only have libsanitizer support for RV64 at present.
11135 This number must match ASAN_SHADOW_OFFSET_CONST in the file
11136 libsanitizer/asan/asan_mapping.h. */
11138 }
11140 /* Implement TARGET_MANGLE_TYPE. */
11144 {
11145 /* Half-precision float, _Float16 is "DF16_" and __bf16 is "DF16b". */
11147 {
11155 }
11157 /* Mangle all vector type for vector extension. */
11158 /* The mangle name follows the rule of RVV LLVM
11159 that is "u" + length of (abi_name) + abi_name. */
11161 {
11165 }
11167 /* Use the default mangling. */
11169 }
11171 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11173 static bool
11175 {
11178 else
11180 }
11182 /* Implement TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P - return TRUE
11183 if MODE is HFmode or BFmode, and punt to the generic implementation
11184 otherwise. */
11186 static bool
11188 {
11191 else
11193 }
11195 /* Set the value of FLT_EVAL_METHOD.
11196 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
11198 0: evaluate all operations and constants, whose semantic type has at
11199 most the range and precision of type float, to the range and
11200 precision of float; evaluate all other operations and constants to
11201 the range and precision of the semantic type;
11203 N, where _FloatN is a supported interchange floating type
11204 evaluate all operations and constants, whose semantic type has at
11205 most the range and precision of _FloatN type, to the range and
11206 precision of the _FloatN type; evaluate all other operations and
11207 constants to the range and precision of the semantic type;
11209 If we have the zfh/zhinx/zvfh extensions then we support _Float16
11210 in native precision, so we should set this to 16. */
11211 static enum flt_eval_method
11213 {
11215 {
11219 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
11226 }
11228 }
11230 /* Implement TARGET_FLOATN_MODE. */
11231 static opt_scalar_float_mode
11233 {
11238 }
11240 /* Record that we have no arithmetic or comparison libfuncs for
11241 machine_mode MODE. */
11242 static void
11244 {
11245 /* Half-precision float or Brain float operations. The compiler handles all
11246 operations with NULL libfuncs by converting to SFmode. */
11248 /* Arithmetic. */
11255 /* Comparisons. */
11263 }
11265 static void
11267 {
11271 /* Convert between BFmode and HFmode using only trunc libfunc if needed. */
11276 }
11278 #if CHECKING_P
11279 void
11281 {
11287 }
11288 #endif
11290 #if CHECKING_P
11291 #undef TARGET_RUN_TARGET_SELFTESTS
11292 #define TARGET_RUN_TARGET_SELFTESTS selftest::riscv_run_selftests
11295 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11297 static bool
11299 {
11304 }
11306 /* Implement TARGET_VERIFY_TYPE_CONTEXT. */
11308 static bool
11311 {
11313 }
11315 /* Implement TARGET_VECTOR_ALIGNMENT. */
11317 static HOST_WIDE_INT
11319 {
11320 /* ??? Checking the mode isn't ideal, but VECTOR_BOOLEAN_TYPE_P can
11321 be set for non-predicate vectors of booleans. Modes are the most
11322 direct way we have of identifying real RVV predicate types. */
11323 /* FIXME: RVV didn't mention the alignment of bool, we uses
11324 one byte align. */
11328 widest_int min_size
11331 }
11333 /* Implement REGMODE_NATURAL_SIZE. */
11335 poly_uint64
11337 {
11338 /* The natural size for RVV data modes is one RVV data vector,
11339 and similarly for predicates. We can't independently modify
11340 anything smaller than that. */
11341 /* ??? For now, only do this for variable-width RVV registers.
11342 Doing it for constant-sized registers breaks lower-subreg.c. */
11345 {
11348 {
11352 }
11354 {
11355 /* RVV mask modes always consume a single register. */
11358 }
11362 /* For -march=rv64gc_zve32f, the natural vector register size
11363 is 32bits which is smaller than scalar register size, so we
11364 return minimum size between vector register size and scalar
11365 register size. */
11367 }
11369 }
11371 /* Implement the TARGET_DWARF_POLY_INDETERMINATE_VALUE hook. */
11373 static unsigned int
11376 {
11377 /* Polynomial invariant 1 == (VLENB / BYTES_PER_RISCV_VECTOR) - 1.
11378 1. TARGET_MIN_VLEN == 32, polynomial invariant 1 == (VLENB / 4) - 1.
11379 2. TARGET_MIN_VLEN > 32, polynomial invariant 1 == (VLENB / 8) - 1.
11380 */
11385 }
11387 /* Implement TARGET_ESTIMATED_POLY_VALUE. */
11389 static HOST_WIDE_INT
11392 {
11396 }
11398 /* Return true if the vector misalignment factor is supported by the
11399 target. */
11400 bool
11402 const_tree type ATTRIBUTE_UNUSED,
11405 {
11406 /* Depend on movmisalign pattern. */
11408 is_packed);
11409 }
11411 /* Implement TARGET_VECTORIZE_GET_MASK_MODE. */
11413 static opt_machine_mode
11415 {
11420 }
11422 /* Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. Assume for now that
11423 it isn't worth branching around empty masked ops (including masked
11424 stores). */
11426 static bool
11428 {
11430 }
11432 /* Return true if a shift-amount matches the trailing cleared bits on
11433 a bitmask. */
11435 bool
11437 {
11439 }
11441 static HARD_REG_SET
11443 {
11444 HARD_REG_SET zeroed_hardregs;
11447 /* Find a register to hold vl. */
11449 /* Skip the first GPR, otherwise the existing vl is kept due to the same
11450 between vl and avl. */
11452 {
11454 {
11457 }
11458 }
11464 /* Vector configurations need not be saved and restored here. The
11465 -fzero-call-used-regs=* option will zero all vector registers and
11466 return. So there's no vector operations between them. */
11471 {
11473 {
11478 {
11481 }
11488 }
11489 }
11492 }
11494 /* Generate a sequence of instructions that zero registers specified by
11495 NEED_ZEROED_HARDREGS. Return the ZEROED_HARDREGS that are actually
11496 zeroed. */
11497 HARD_REG_SET
11499 {
11500 HARD_REG_SET zeroed_hardregs;
11508 }
11510 /* Implement target hook TARGET_ARRAY_MODE. */
11512 static opt_machine_mode
11514 {
11515 machine_mode vmode;
11521 }
11523 /* Given memory reference MEM, expand code to compute the aligned
11524 memory address, shift and mask values and store them into
11525 *ALIGNED_MEM, *SHIFT, *MASK and *NOT_MASK. */
11527 void
11530 {
11531 /* Align the memory address to a word. */
11541 /* Calculate the shift amount. */
11547 /* Calculate the mask. */
11556 }
11558 /* Leftshift a subword within an SImode register. */
11560 void
11563 {
11570 }
11572 /* Return TRUE if we should use the divmod expander, FALSE otherwise. This
11573 allows the behavior to be tuned for specific implementations as well as
11574 when optimizing for size. */
11576 bool
11578 {
11580 }
11582 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11584 static machine_mode
11586 {
11591 }
11593 /* Implement target hook TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT. */
11595 static poly_uint64
11597 {
11601 }
11603 /* Return true if it is static FRM rounding mode. */
11605 static bool
11607 {
11609 {
11618 }
11621 }
11623 /* Implement the floating-point Mode Switching. */
11625 static void
11627 {
11634 {
11639 /* No need to emit when prev mode is DYN already. */
11644 /* No need to emit when prev mode is DYN or DYN_CALL already. */
11648 /* Restore frm value from backup when switch to DYN mode. */
11651 /* Set frm value when switch to static mode. */
11653 }
11654 }
11656 /* Implement Mode switching. */
11658 static void
11660 HARD_REG_SET regs_live ATTRIBUTE_UNUSED)
11661 {
11663 {
11673 }
11674 }
11676 /* Adjust the FRM_NONE insn after a call to FRM_DYN for the
11677 underlying emit. */
11679 static int
11681 {
11688 }
11690 /* Insert the backup frm insn to the end of the bb if and only if the call
11691 is the last insn of this bb. */
11693 static void
11695 {
11696 edge eg;
11698 edge_iterator eg_iterator;
11702 {
11705 else
11706 {
11713 }
11714 }
11717 {
11724 }
11727 }
11729 /* Return mode that frm must be switched into
11730 prior to the execution of insn. */
11732 static int
11734 {
11736 {
11737 /* The dynamic frm will be initialized only onece during cfun. */
11740 }
11743 {
11750 }
11755 /* After meet a call, we need to backup the frm because it may be
11756 updated during the call. Here, for each insn, we will check if
11757 the previous insn is a call or not. When previous insn is call,
11758 there will be 2 cases for the emit mode set.
11760 1. Current insn is not MODE_NONE, then the mode switch framework
11761 will do the mode switch from MODE_CALL to MODE_NONE natively.
11762 2. Current insn is MODE_NONE, we need to adjust the MODE_NONE to
11763 the MODE_DYN, and leave the mode switch itself to perform
11764 the emit mode set.
11765 */
11769 }
11771 /* Return mode that entity must be switched into
11772 prior to the execution of insn. */
11774 static int
11776 {
11780 {
11787 }
11788 }
11790 /* Return TRUE that an insn is asm. */
11792 static bool
11794 {
11798 }
11800 /* Return TRUE that an insn is unknown for VXRM. */
11802 static bool
11804 {
11805 /* Return true if there is a definition of VXRM. */
11809 /* A CALL function may contain an instruction that modifies the VXRM,
11810 return true in this situation. */
11814 /* Return true for all assembly since users may hardcode a assembly
11815 like this: asm volatile ("csrwi vxrm, 0"). */
11820 }
11822 /* Return TRUE that an insn is unknown dynamic for FRM. */
11824 static bool
11826 {
11827 /* Return true if there is a definition of FRM. */
11832 }
11834 /* Return the mode that an insn results in for VXRM. */
11836 static int
11838 {
11847 else
11849 }
11851 /* Return the mode that an insn results in for FRM. */
11853 static int
11855 {
11869 else
11871 }
11873 /* Return the mode that an insn results in. */
11875 static int
11877 {
11879 {
11886 }
11887 }
11889 /* Return a mode that ENTITY is assumed to be
11890 switched to at function entry. */
11892 static int
11894 {
11896 {
11900 {
11901 /* According to RVV 1.0 spec, all vector floating-point operations use
11902 the dynamic rounding mode in the frm register. Likewise in other
11903 similar places. */
11905 }
11908 }
11909 }
11911 /* Return a mode that ENTITY is assumed to be
11912 switched to at function exit. */
11914 static int
11916 {
11918 {
11925 }
11926 }
11928 static int
11930 {
11932 }
11934 /* Implement TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES. */
11935 unsigned int
11937 {
11942 }
11944 /* Implement TARGET_VECTORIZE_RELATED_MODE. */
11945 opt_machine_mode
11947 poly_uint64 nunits)
11948 {
11951 nunits);
11953 }
11955 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
11957 static bool
11961 {
11967 }
11969 static bool
11971 {
11973 }
11975 /* Return the appropriate common costs according to VECTYPE from COSTS. */
11978 {
11984 }
11986 /* Return the CPU vector costs according to -mtune if tune info has non-NULL
11987 vector cost. Otherwise, return the default generic vector costs. */
11990 {
11995 }
11997 /* Implement targetm.vectorize.builtin_vectorization_cost. */
11999 static int
12002 {
12012 {
12064 }
12067 }
12069 /* Implement targetm.vectorize.create_costs. */
12073 {
12076 /* Default vector costs. */
12078 }
12080 /* Implement TARGET_PREFERRED_ELSE_VALUE. */
12082 static tree
12085 {
12087 {
12091 }
12094 }
12096 /* If MEM is in the form of "base+offset", extract the two parts
12097 of address and set to BASE and OFFSET, otherwise return false
12098 after clearing BASE and OFFSET. */
12100 bool
12102 {
12103 rtx addr;
12110 {
12114 }
12118 {
12122 }
12128 }
12130 /* Implements target hook vector_mode_supported_any_target_p. */
12132 static bool
12134 {
12138 }
12140 /* Implements hook TARGET_FUNCTION_VALUE_REGNO_P. */
12142 static bool
12144 {
12155 }
12157 /* Implements hook TARGET_GET_RAW_RESULT_MODE. */
12159 static fixed_size_mode
12161 {
12166 }
12168 /* Generate a REG rtx of Xmode from the given rtx and mode.
12169 The rtx x can be REG (QI/HI/SI/DI) or const_int.
12170 The machine_mode mode is the original mode from define pattern.
12172 If rtx is REG and Xmode, the RTX x will be returned directly.
12174 If rtx is REG and non-Xmode, the zero extended to new REG of Xmode will be
12175 returned.
12177 If rtx is const_int, a new REG rtx will be created to hold the value of
12178 const_int and then returned.
12180 According to the gccint doc, the constants generated for modes with fewer
12181 bits than in HOST_WIDE_INT must be sign extended to full width. Thus there
12182 will be two cases here, take QImode as example.
12184 For .SAT_SUB (127, y) in QImode, we have (const_int 127) and one simple
12185 mov from const_int to the new REG rtx is good enough here.
12187 For .SAT_SUB (254, y) in QImode, we have (const_int -2) after define_expand.
12188 Aka 0xfffffffffffffffe in Xmode of RV64 but we actually need 0xfe in Xmode
12189 of RV64. So we need to cleanup the highest 56 bits of the new REG rtx moved
12190 from the (const_int -2).
12192 Then the underlying expanding can perform the code generation based on
12193 the REG rtx of Xmode, instead of taking care of these in expand func. */
12195 static rtx
12197 {
12201 {
12207 }
12211 else
12212 {
12217 }
12220 }
12222 /* Implements the unsigned saturation add standard name usadd for int mode.
12224 z = SAT_ADD(x, y).
12225 =>
12226 1. sum = x + y.
12227 2. sum = truncate (sum) for non-Xmode.
12228 3. lt = sum < x.
12229 4. lt = -lt.
12230 5. z = sum | lt. */
12232 void
12234 {
12242 /* Step-1: sum = x + y */
12245 /* Step-1.1: truncate sum for non-Xmode for overflow check. */
12247 {
12255 }
12257 /* Step-2: lt = sum < x */
12260 /* Step-3: lt = -lt */
12263 /* Step-4: xmode_dest = sum | lt */
12266 /* Step-5: dest = xmode_dest */
12268 }
12270 /* Return a new const RTX of MAX value based on given mode. Only
12271 int scalar mode is allowed. */
12273 static rtx
12275 {
12277 {
12288 }
12289 }
12291 /* Implements the signed saturation sub standard name ssadd for int mode.
12293 z = SAT_ADD(x, y).
12294 =>
12295 1. sum = x + y
12296 2. xor_0 = x ^ y
12297 3. xor_1 = x ^ sum
12298 4. lt = xor_1 < 0
12299 5. ge = xor_0 >= 0
12300 6. and = ge & lt
12301 7. lt = x < 0
12302 8. neg = -lt
12303 9. max = INT_MAX
12304 10. max = max ^ neg
12305 11. neg = -and
12306 12. max = max & neg
12307 13. and = and - 1
12308 14. z = sum & and
12309 15. z = z | max */
12311 void
12313 {
12329 /* Step-1: sum = x + y, xor_0 = x ^ y, xor_1 = x ^ sum. */
12334 /* Step-2: lt = xor_1 < 0, ge = xor_0 >= 0, and = ge & lt. */
12341 /* Step-3: lt = x < 0, neg = -lt */
12345 /* Step-4: max = 0x7f..., max = max ^ neg, neg = -and, max = max & neg */
12351 /* Step-5: and = and - 1, dest = sum & and */
12355 /* Step-6: xmode_dest = xmode_dest | xmode_max, dest = xmode_dest */
12358 }
12360 /* Implements the unsigned saturation sub standard name usadd for int mode.
12362 z = SAT_SUB(x, y).
12363 =>
12364 1. minus = x - y.
12365 2. lt = x < y.
12366 3. lt = lt - 1.
12367 4. z = minus & lt. */
12369 void
12371 {
12379 /* Step-1: minus = x - y */
12382 /* Step-2: lt = x < y */
12385 /* Step-3: lt = lt - 1 (lt + (-1)) */
12388 /* Step-4: xmode_dest = minus & lt */
12391 /* Step-5: dest = xmode_dest */
12393 }
12395 /* Implements the signed saturation sub standard name ssadd for int mode.
12397 z = SAT_SUB(x, y).
12398 =>
12399 1. minus = x - y
12400 2. xor_0 = x ^ y
12401 3. xor_1 = x ^ minus
12402 4. lt_0 = xor_1 < 0
12403 5. lt_1 = xor_0 < 0
12404 6. and = lt_0 & lt_1
12405 7. lt = x < 0
12406 8. neg = -lt
12407 9. max = INT_MAX
12408 10. max = max ^ neg
12409 11. neg = -and
12410 12. max = max & neg
12411 13. and = and - 1
12412 14. z = minus & and
12413 15. z = z | max */
12415 void
12417 {
12434 /* Step-1: mins = x - y, xor_0 = x ^ y, xor_1 = x ^ minus. */
12439 /* Step-2: and = xor_0 < 0 & xor_1 < 0. */
12445 /* Step-3: lt = x < 0, neg = -lt. */
12449 /* Step-4: max = 0x7f..., max = max ^ neg, neg = -and, max = max & neg. */
12455 /* Step-5: and = and - 1, dest = minus & and. */
12459 /* Step-6: dest = dest | max. */
12462 }
12464 /* Implement the unsigned saturation truncation for int mode.
12466 b = SAT_TRUNC (a);
12467 =>
12468 1. max = half truncated max
12469 2. lt = a < max
12470 3. lt = lt - 1 (lt 0, ge -1)
12471 4. d = a | lt
12472 5. b = (trunc)d */
12474 void
12476 {
12488 /* Step-1: max = half truncated max */
12491 /* Step-2: lt = src < max */
12494 /* Step-3: lt = lt - 1 */
12497 /* Step-4: xmode_dest = lt | src */
12500 /* Step-5: dest = xmode_dest */
12502 }
12504 /* Implement the signed saturation truncation for int mode.
12506 b = SAT_TRUNC (a);
12507 =>
12508 1. lt = a < max
12509 2. gt = min < a
12510 3. mask = lt & gt
12511 4. trunc_mask = -mask
12512 5. sat_mask = mask - 1
12513 6. lt = a < 0
12514 7. neg = -lt
12515 8. sat = neg ^ max
12516 9. trunc = src & trunc_mask
12517 10. sat = sat & sat_mask
12518 11. dest = trunc | sat */
12520 void
12522 {
12540 /* Step-1: lt = src < max, gt = min < src, mask = lt & gt */
12547 /* Step-2: sat_mask = mask - 1, trunc_mask = ~mask */
12551 /* Step-3: lt = src < 0, lt = -lt, sat = lt ^ narrow_max */
12556 /* Step-4: xmode_dest = (src & trunc_mask) | (sat & sat_mask) */
12561 /* Step-5: dest = xmode_dest */
12563 }
12565 /* Implement TARGET_C_MODE_FOR_FLOATING_TYPE. Return TFmode for
12566 TI_LONG_DOUBLE_TYPE which is for long double type, go with the
12567 default one for the others. */
12569 static machine_mode
12571 {
12575 }
12577 /* On riscv we have an ABI defined safe buffer. This constant is used to
12578 determining the probe offset for alloca. */
12580 static HOST_WIDE_INT
12582 {
12584 }
12586 /* Initialize the GCC target structure. */
12587 #undef TARGET_ASM_ALIGNED_HI_OP
12589 #undef TARGET_ASM_ALIGNED_SI_OP
12591 #undef TARGET_ASM_ALIGNED_DI_OP
12594 #undef TARGET_OPTION_OVERRIDE
12595 #define TARGET_OPTION_OVERRIDE riscv_option_override
12597 #undef TARGET_OPTION_RESTORE
12598 #define TARGET_OPTION_RESTORE riscv_option_restore
12600 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
12601 #define TARGET_OPTION_VALID_ATTRIBUTE_P riscv_option_valid_attribute_p
12603 #undef TARGET_LEGITIMIZE_ADDRESS
12604 #define TARGET_LEGITIMIZE_ADDRESS riscv_legitimize_address
12606 #undef TARGET_SCHED_ISSUE_RATE
12607 #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate
12608 #undef TARGET_SCHED_MACRO_FUSION_P
12609 #define TARGET_SCHED_MACRO_FUSION_P riscv_macro_fusion_p
12610 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
12611 #define TARGET_SCHED_MACRO_FUSION_PAIR_P riscv_macro_fusion_pair_p
12613 #undef TARGET_SCHED_VARIABLE_ISSUE
12614 #define TARGET_SCHED_VARIABLE_ISSUE riscv_sched_variable_issue
12616 #undef TARGET_SCHED_ADJUST_COST
12617 #define TARGET_SCHED_ADJUST_COST riscv_sched_adjust_cost
12619 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
12620 #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall
12622 #undef TARGET_SET_CURRENT_FUNCTION
12623 #define TARGET_SET_CURRENT_FUNCTION riscv_set_current_function
12625 #undef TARGET_REGISTER_MOVE_COST
12626 #define TARGET_REGISTER_MOVE_COST riscv_register_move_cost
12627 #undef TARGET_MEMORY_MOVE_COST
12628 #define TARGET_MEMORY_MOVE_COST riscv_memory_move_cost
12629 #undef TARGET_RTX_COSTS
12630 #define TARGET_RTX_COSTS riscv_rtx_costs
12631 #undef TARGET_ADDRESS_COST
12632 #define TARGET_ADDRESS_COST riscv_address_cost
12633 #undef TARGET_INSN_COST
12634 #define TARGET_INSN_COST riscv_insn_cost
12636 #undef TARGET_MAX_NOCE_IFCVT_SEQ_COST
12637 #define TARGET_MAX_NOCE_IFCVT_SEQ_COST riscv_max_noce_ifcvt_seq_cost
12638 #undef TARGET_NOCE_CONVERSION_PROFITABLE_P
12639 #define TARGET_NOCE_CONVERSION_PROFITABLE_P riscv_noce_conversion_profitable_p
12641 #undef TARGET_ASM_FILE_START
12642 #define TARGET_ASM_FILE_START riscv_file_start
12643 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
12644 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
12645 #undef TARGET_ASM_FILE_END
12646 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
12648 #undef TARGET_EXPAND_BUILTIN_VA_START
12649 #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start
12651 #undef TARGET_PROMOTE_FUNCTION_MODE
12652 #define TARGET_PROMOTE_FUNCTION_MODE riscv_promote_function_mode
12654 #undef TARGET_RETURN_IN_MEMORY
12655 #define TARGET_RETURN_IN_MEMORY riscv_return_in_memory
12657 #undef TARGET_ASM_OUTPUT_MI_THUNK
12658 #define TARGET_ASM_OUTPUT_MI_THUNK riscv_output_mi_thunk
12659 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
12660 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
12662 #undef TARGET_PRINT_OPERAND
12663 #define TARGET_PRINT_OPERAND riscv_print_operand
12664 #undef TARGET_PRINT_OPERAND_ADDRESS
12665 #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address
12666 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
12667 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P riscv_print_operand_punct_valid_p
12669 #undef TARGET_SETUP_INCOMING_VARARGS
12670 #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs
12671 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
12672 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS riscv_allocate_stack_slots_for_args
12673 #undef TARGET_STRICT_ARGUMENT_NAMING
12674 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
12675 #undef TARGET_MUST_PASS_IN_STACK
12676 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
12677 #undef TARGET_PASS_BY_REFERENCE
12678 #define TARGET_PASS_BY_REFERENCE riscv_pass_by_reference
12679 #undef TARGET_ARG_PARTIAL_BYTES
12680 #define TARGET_ARG_PARTIAL_BYTES riscv_arg_partial_bytes
12681 #undef TARGET_FUNCTION_ARG
12682 #define TARGET_FUNCTION_ARG riscv_function_arg
12683 #undef TARGET_FUNCTION_ARG_ADVANCE
12684 #define TARGET_FUNCTION_ARG_ADVANCE riscv_function_arg_advance
12685 #undef TARGET_FUNCTION_ARG_BOUNDARY
12686 #define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary
12687 #undef TARGET_FNTYPE_ABI
12688 #define TARGET_FNTYPE_ABI riscv_fntype_abi
12689 #undef TARGET_INSN_CALLEE_ABI
12690 #define TARGET_INSN_CALLEE_ABI riscv_insn_callee_abi
12692 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
12693 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
12694 riscv_get_separate_components
12696 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
12697 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
12698 riscv_components_for_bb
12700 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
12701 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
12702 riscv_disqualify_components
12704 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
12705 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
12706 riscv_emit_prologue_components
12708 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
12709 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
12710 riscv_emit_epilogue_components
12712 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
12713 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
12714 riscv_set_handled_components
12716 /* The generic ELF target does not always have TLS support. */
12717 #ifdef HAVE_AS_TLS
12718 #undef TARGET_HAVE_TLS
12719 #define TARGET_HAVE_TLS true
12720 #endif
12722 #undef TARGET_CANNOT_FORCE_CONST_MEM
12723 #define TARGET_CANNOT_FORCE_CONST_MEM riscv_cannot_force_const_mem
12725 #undef TARGET_LEGITIMATE_CONSTANT_P
12726 #define TARGET_LEGITIMATE_CONSTANT_P riscv_legitimate_constant_p
12728 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
12729 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P riscv_use_blocks_for_constant_p
12731 #undef TARGET_LEGITIMATE_ADDRESS_P
12732 #define TARGET_LEGITIMATE_ADDRESS_P riscv_legitimate_address_p
12734 #undef TARGET_CAN_INLINE_P
12735 #define TARGET_CAN_INLINE_P riscv_can_inline_p
12737 #undef TARGET_CAN_ELIMINATE
12738 #define TARGET_CAN_ELIMINATE riscv_can_eliminate
12740 #undef TARGET_CONDITIONAL_REGISTER_USAGE
12741 #define TARGET_CONDITIONAL_REGISTER_USAGE riscv_conditional_register_usage
12743 #undef TARGET_CLASS_MAX_NREGS
12744 #define TARGET_CLASS_MAX_NREGS riscv_class_max_nregs
12746 #undef TARGET_TRAMPOLINE_INIT
12747 #define TARGET_TRAMPOLINE_INIT riscv_trampoline_init
12749 #undef TARGET_IN_SMALL_DATA_P
12750 #define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p
12752 #undef TARGET_HAVE_SRODATA_SECTION
12753 #define TARGET_HAVE_SRODATA_SECTION true
12755 #undef TARGET_ASM_SELECT_SECTION
12756 #define TARGET_ASM_SELECT_SECTION riscv_select_section
12758 #undef TARGET_ASM_UNIQUE_SECTION
12759 #define TARGET_ASM_UNIQUE_SECTION riscv_unique_section
12761 #undef TARGET_ASM_SELECT_RTX_SECTION
12762 #define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section
12764 #undef TARGET_MIN_ANCHOR_OFFSET
12765 #define TARGET_MIN_ANCHOR_OFFSET (-IMM_REACH/2)
12767 #undef TARGET_MAX_ANCHOR_OFFSET
12768 #define TARGET_MAX_ANCHOR_OFFSET (IMM_REACH/2-1)
12770 #undef TARGET_REGISTER_PRIORITY
12771 #define TARGET_REGISTER_PRIORITY riscv_register_priority
12773 #undef TARGET_CANNOT_COPY_INSN_P
12774 #define TARGET_CANNOT_COPY_INSN_P riscv_cannot_copy_insn_p
12776 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
12777 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV riscv_atomic_assign_expand_fenv
12779 #undef TARGET_INIT_BUILTINS
12780 #define TARGET_INIT_BUILTINS riscv_init_builtins
12782 #undef TARGET_BUILTIN_DECL
12783 #define TARGET_BUILTIN_DECL riscv_builtin_decl
12785 #undef TARGET_GIMPLE_FOLD_BUILTIN
12786 #define TARGET_GIMPLE_FOLD_BUILTIN riscv_gimple_fold_builtin
12788 #undef TARGET_EXPAND_BUILTIN
12789 #define TARGET_EXPAND_BUILTIN riscv_expand_builtin
12791 #undef TARGET_HARD_REGNO_NREGS
12792 #define TARGET_HARD_REGNO_NREGS riscv_hard_regno_nregs
12793 #undef TARGET_HARD_REGNO_MODE_OK
12794 #define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok
12796 #undef TARGET_MODES_TIEABLE_P
12797 #define TARGET_MODES_TIEABLE_P riscv_modes_tieable_p
12799 #undef TARGET_SLOW_UNALIGNED_ACCESS
12800 #define TARGET_SLOW_UNALIGNED_ACCESS riscv_slow_unaligned_access
12802 #undef TARGET_OVERLAP_OP_BY_PIECES_P
12803 #define TARGET_OVERLAP_OP_BY_PIECES_P riscv_overlap_op_by_pieces
12805 #undef TARGET_SECONDARY_MEMORY_NEEDED
12806 #define TARGET_SECONDARY_MEMORY_NEEDED riscv_secondary_memory_needed
12808 #undef TARGET_CAN_CHANGE_MODE_CLASS
12809 #define TARGET_CAN_CHANGE_MODE_CLASS riscv_can_change_mode_class
12811 #undef TARGET_CONSTANT_ALIGNMENT
12812 #define TARGET_CONSTANT_ALIGNMENT riscv_constant_alignment
12814 #undef TARGET_MERGE_DECL_ATTRIBUTES
12815 #define TARGET_MERGE_DECL_ATTRIBUTES riscv_merge_decl_attributes
12817 #undef TARGET_ATTRIBUTE_TABLE
12818 #define TARGET_ATTRIBUTE_TABLE riscv_attribute_table
12820 #undef TARGET_WARN_FUNC_RETURN
12821 #define TARGET_WARN_FUNC_RETURN riscv_warn_func_return
12823 /* The low bit is ignored by jump instructions so is safe to use. */
12824 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
12825 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
12827 #undef TARGET_MACHINE_DEPENDENT_REORG
12828 #define TARGET_MACHINE_DEPENDENT_REORG riscv_reorg
12830 #undef TARGET_NEW_ADDRESS_PROFITABLE_P
12831 #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
12833 #undef TARGET_MANGLE_TYPE
12834 #define TARGET_MANGLE_TYPE riscv_mangle_type
12836 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12837 #define TARGET_SCALAR_MODE_SUPPORTED_P riscv_scalar_mode_supported_p
12839 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
12840 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
12841 riscv_libgcc_floating_mode_supported_p
12843 #undef TARGET_INIT_LIBFUNCS
12844 #define TARGET_INIT_LIBFUNCS riscv_init_libfuncs
12846 #undef TARGET_C_EXCESS_PRECISION
12847 #define TARGET_C_EXCESS_PRECISION riscv_excess_precision
12849 #undef TARGET_FLOATN_MODE
12850 #define TARGET_FLOATN_MODE riscv_floatn_mode
12852 #undef TARGET_ASAN_SHADOW_OFFSET
12853 #define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
12855 #ifdef TARGET_BIG_ENDIAN_DEFAULT
12856 #undef TARGET_DEFAULT_TARGET_FLAGS
12857 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN)
12858 #endif
12860 #undef TARGET_VECTOR_MODE_SUPPORTED_P
12861 #define TARGET_VECTOR_MODE_SUPPORTED_P riscv_vector_mode_supported_p
12863 #undef TARGET_VERIFY_TYPE_CONTEXT
12864 #define TARGET_VERIFY_TYPE_CONTEXT riscv_verify_type_context
12866 #undef TARGET_ESTIMATED_POLY_VALUE
12867 #define TARGET_ESTIMATED_POLY_VALUE riscv_estimated_poly_value
12869 #undef TARGET_VECTORIZE_GET_MASK_MODE
12870 #define TARGET_VECTORIZE_GET_MASK_MODE riscv_get_mask_mode
12872 #undef TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE
12873 #define TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE riscv_empty_mask_is_expensive
12875 #undef TARGET_VECTOR_ALIGNMENT
12876 #define TARGET_VECTOR_ALIGNMENT riscv_vector_alignment
12878 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
12879 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT riscv_support_vector_misalignment
12881 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
12882 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value
12884 #undef TARGET_ZERO_CALL_USED_REGS
12885 #define TARGET_ZERO_CALL_USED_REGS riscv_zero_call_used_regs
12887 #undef TARGET_ARRAY_MODE
12888 #define TARGET_ARRAY_MODE riscv_array_mode
12890 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
12891 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE riscv_preferred_simd_mode
12893 #undef TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT
12894 #define TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT \
12895 riscv_vectorize_preferred_vector_alignment
12897 #undef TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE
12898 #define TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE \
12899 riscv_stack_clash_protection_alloca_probe_range
12901 /* Mode switching hooks. */
12903 #undef TARGET_MODE_EMIT
12904 #define TARGET_MODE_EMIT riscv_emit_mode_set
12905 #undef TARGET_MODE_NEEDED
12906 #define TARGET_MODE_NEEDED riscv_mode_needed
12907 #undef TARGET_MODE_AFTER
12908 #define TARGET_MODE_AFTER riscv_mode_after
12909 #undef TARGET_MODE_ENTRY
12910 #define TARGET_MODE_ENTRY riscv_mode_entry
12911 #undef TARGET_MODE_EXIT
12912 #define TARGET_MODE_EXIT riscv_mode_exit
12913 #undef TARGET_MODE_PRIORITY
12914 #define TARGET_MODE_PRIORITY riscv_mode_priority
12916 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES
12917 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES \
12918 riscv_autovectorize_vector_modes
12920 #undef TARGET_VECTORIZE_RELATED_MODE
12921 #define TARGET_VECTORIZE_RELATED_MODE riscv_vectorize_related_mode
12923 #undef TARGET_VECTORIZE_VEC_PERM_CONST
12924 #define TARGET_VECTORIZE_VEC_PERM_CONST riscv_vectorize_vec_perm_const
12926 #undef TARGET_FRAME_POINTER_REQUIRED
12927 #define TARGET_FRAME_POINTER_REQUIRED riscv_frame_pointer_required
12929 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
12930 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
12931 riscv_builtin_vectorization_cost
12933 #undef TARGET_VECTORIZE_CREATE_COSTS
12934 #define TARGET_VECTORIZE_CREATE_COSTS riscv_vectorize_create_costs
12936 #undef TARGET_PREFERRED_ELSE_VALUE
12937 #define TARGET_PREFERRED_ELSE_VALUE riscv_preferred_else_value
12939 #undef TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P
12940 #define TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P riscv_vector_mode_supported_any_target_p
12942 #undef TARGET_FUNCTION_VALUE_REGNO_P
12943 #define TARGET_FUNCTION_VALUE_REGNO_P riscv_function_value_regno_p
12945 #undef TARGET_GET_RAW_RESULT_MODE
12946 #define TARGET_GET_RAW_RESULT_MODE riscv_get_raw_result_mode
12948 #undef TARGET_C_MODE_FOR_FLOATING_TYPE
12949 #define TARGET_C_MODE_FOR_FLOATING_TYPE riscv_c_mode_for_floating_type