gcc/config/riscv/thead-vector.md

   1 (define_c_enum "unspec" [
   2   UNSPEC_TH_VLB
   3   UNSPEC_TH_VLBU
   4   UNSPEC_TH_VLH
   5   UNSPEC_TH_VLHU
   6   UNSPEC_TH_VLW
   7   UNSPEC_TH_VLWU
   8
   9   UNSPEC_TH_VLSB
  10   UNSPEC_TH_VLSBU
  11   UNSPEC_TH_VLSH
  12   UNSPEC_TH_VLSHU
  13   UNSPEC_TH_VLSW
  14   UNSPEC_TH_VLSWU
  15
  16   UNSPEC_TH_VLXB
  17   UNSPEC_TH_VLXBU
  18   UNSPEC_TH_VLXH
  19   UNSPEC_TH_VLXHU
  20   UNSPEC_TH_VLXW
  21   UNSPEC_TH_VLXWU
  22
  23   UNSPEC_TH_VSUXB
  24   UNSPEC_TH_VSUXH
  25   UNSPEC_TH_VSUXW
  26
  27   UNSPEC_TH_VWLDST
  28 ])
  29
  30 (define_int_iterator UNSPEC_TH_VLMEM_OP [
  31   UNSPEC_TH_VLB UNSPEC_TH_VLBU
  32   UNSPEC_TH_VLH UNSPEC_TH_VLHU
  33   UNSPEC_TH_VLW UNSPEC_TH_VLWU
  34 ])
  35
  36 (define_int_iterator UNSPEC_TH_VLSMEM_OP [
  37   UNSPEC_TH_VLSB UNSPEC_TH_VLSBU
  38   UNSPEC_TH_VLSH UNSPEC_TH_VLSHU
  39   UNSPEC_TH_VLSW UNSPEC_TH_VLSWU
  40 ])
  41
  42 (define_int_iterator UNSPEC_TH_VLXMEM_OP [
  43   UNSPEC_TH_VLXB UNSPEC_TH_VLXBU
  44   UNSPEC_TH_VLXH UNSPEC_TH_VLXHU
  45   UNSPEC_TH_VLXW UNSPEC_TH_VLXWU
  46 ])
  47
  48 (define_int_attr vlmem_op_attr [
  49   (UNSPEC_TH_VLB "b") (UNSPEC_TH_VLBU "bu")
  50   (UNSPEC_TH_VLH "h") (UNSPEC_TH_VLHU "hu")
  51   (UNSPEC_TH_VLW "w") (UNSPEC_TH_VLWU "wu")
  52   (UNSPEC_TH_VLSB "b") (UNSPEC_TH_VLSBU "bu")
  53   (UNSPEC_TH_VLSH "h") (UNSPEC_TH_VLSHU "hu")
  54   (UNSPEC_TH_VLSW "w") (UNSPEC_TH_VLSWU "wu")
  55   (UNSPEC_TH_VLXB "b") (UNSPEC_TH_VLXBU "bu")
  56   (UNSPEC_TH_VLXH "h") (UNSPEC_TH_VLXHU "hu")
  57   (UNSPEC_TH_VLXW "w") (UNSPEC_TH_VLXWU "wu")
  58   (UNSPEC_TH_VSUXB "b")
  59   (UNSPEC_TH_VSUXH "h")
  60   (UNSPEC_TH_VSUXW "w")
  61 ])
  62
  63 (define_int_attr vlmem_order_attr [
  64   (UNSPEC_TH_VLXB "")
  65   (UNSPEC_TH_VLXH "")
  66   (UNSPEC_TH_VLXW "")
  67   (UNSPEC_TH_VSUXB "u")
  68   (UNSPEC_TH_VSUXH "u")
  69   (UNSPEC_TH_VSUXW "u")
  70 ])
  71
  72 (define_int_iterator UNSPEC_TH_VSMEM_OP [
  73   UNSPEC_TH_VLB
  74   UNSPEC_TH_VLH
  75   UNSPEC_TH_VLW
  76 ])
  77
  78 (define_int_iterator UNSPEC_TH_VSSMEM_OP [
  79   UNSPEC_TH_VLSB
  80   UNSPEC_TH_VLSH
  81   UNSPEC_TH_VLSW
  82 ])
  83
  84 (define_int_iterator UNSPEC_TH_VSXMEM_OP [
  85   UNSPEC_TH_VLXB
  86   UNSPEC_TH_VLXH
  87   UNSPEC_TH_VLXW
  88   UNSPEC_TH_VSUXB
  89   UNSPEC_TH_VSUXH
  90   UNSPEC_TH_VSUXW
  91 ])
  92
  93 (define_mode_iterator V_VLS_VT [V VLS VT])
  94 (define_mode_iterator V_VB_VLS_VT [V VB VLS VT])
  95
  96 (define_split
  97   [(set (match_operand:V_VB_VLS_VT 0 "reg_or_mem_operand")
  98         (match_operand:V_VB_VLS_VT 1 "reg_or_mem_operand"))]
  99   "TARGET_XTHEADVECTOR"
 100   [(const_int 0)]
 101   {
 102     emit_insn (gen_pred_th_whole_mov (<MODE>mode, operands[0], operands[1],
 103                                       RVV_VLMAX, GEN_INT(riscv_vector::VLMAX)));
 104     DONE;
 105   })
 106
 107 (define_insn_and_split "@pred_th_whole_mov<mode>"
 108   [(set (match_operand:V_VLS_VT 0 "reg_or_mem_operand"  "=vr,vr, m")
 109         (unspec:V_VLS_VT
 110           [(match_operand:V_VLS_VT 1 "reg_or_mem_operand" " vr, m,vr")
 111            (match_operand 2 "vector_length_operand"   " rK, rK, rK")
 112            (match_operand 3 "const_1_operand"         "  i, i, i")
 113            (reg:SI VL_REGNUM)
 114            (reg:SI VTYPE_REGNUM)]
 115         UNSPEC_TH_VWLDST))]
 116   "TARGET_XTHEADVECTOR"
 117   "@
 118    vmv.v.v\t%0,%1
 119    vle.v\t%0,%1
 120    vse.v\t%1,%0"
 121   "&& REG_P (operands[0]) && REG_P (operands[1])
 122    && REGNO (operands[0]) == REGNO (operands[1])"
 123   [(const_int 0)]
 124   ""
 125   [(set_attr "type" "vimov,vlds,vlds")
 126    (set_attr "mode" "<MODE>")
 127    (set (attr "ta") (symbol_ref "riscv_vector::TAIL_UNDISTURBED"))
 128    (set (attr "ma") (symbol_ref "riscv_vector::MASK_UNDISTURBED"))
 129    (set (attr "avl_type_idx") (const_int 3))
 130    (set_attr "vl_op_idx" "2")])
 131
 132 (define_insn_and_split "@pred_th_whole_mov<mode>"
 133   [(set (match_operand:VB 0 "reg_or_mem_operand"  "=vr,vr, m")
 134         (unspec:VB
 135           [(match_operand:VB 1 "reg_or_mem_operand" " vr, m,vr")
 136            (match_operand 2 "vector_length_operand"   " rK, rK, rK")
 137            (match_operand 3 "const_1_operand"         "  i, i, i")
 138            (reg:SI VL_REGNUM)
 139            (reg:SI VTYPE_REGNUM)]
 140         UNSPEC_TH_VWLDST))]
 141   "TARGET_XTHEADVECTOR"
 142   "@
 143    vmv.v.v\t%0,%1
 144    vle.v\t%0,%1
 145    vse.v\t%1,%0"
 146   "&& REG_P (operands[0]) && REG_P (operands[1])
 147    && REGNO (operands[0]) == REGNO (operands[1])"
 148   [(const_int 0)]
 149   ""
 150   [(set_attr "type" "vimov,vlds,vlds")
 151    (set_attr "mode" "<MODE>")
 152    (set (attr "ta") (symbol_ref "riscv_vector::TAIL_UNDISTURBED"))
 153    (set (attr "ma") (symbol_ref "riscv_vector::MASK_UNDISTURBED"))
 154    (set (attr "avl_type_idx") (const_int 3))
 155    (set_attr "vl_op_idx" "2")
 156    (set (attr "sew") (const_int 8))
 157    (set (attr "vlmul") (symbol_ref "riscv_vector::LMUL_1"))])
 158
 159 (define_insn_and_split "*pred_th_mov<mode>"
 160   [(set (match_operand:VB_VLS 0 "nonimmediate_operand"               "=vr,   m,  vr,  vr,  vr")
 161         (if_then_else:VB_VLS
 162           (unspec:VB_VLS
 163             [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1")
 164              (match_operand 4 "vector_length_operand"            " rK,  rK,  rK,  rK,  rK")
 165              (match_operand 5 "const_int_operand"                "  i,   i,   i,   i,   i")
 166              (reg:SI VL_REGNUM)
 167              (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 168           (match_operand:VB_VLS 3 "vector_move_operand"              "  m,  vr,  vr, Wc0, Wc1")
 169           (match_operand:VB_VLS 2 "vector_undef_operand"             " vu,  vu,  vu,  vu,  vu")))]
 170   "TARGET_XTHEADVECTOR"
 171   "@
 172    #
 173    #
 174    vmcpy.m\t%0,%3
 175    vmclr.m\t%0
 176    vmset.m\t%0"
 177   "&& !reload_completed"
 178   [(const_int 0)]
 179   {
 180     if ((MEM_P (operands[0]) || MEM_P (operands[3]))
 181         || (REG_P (operands[0]) && REG_P (operands[3])
 182             && INTVAL (operands[5]) == riscv_vector::VLMAX))
 183       {
 184         emit_move_insn (operands[0], operands[3]);
 185         DONE;
 186       }
 187     FAIL;
 188   }
 189   [(set_attr "type" "vldm,vstm,vmalu,vmalu,vmalu")
 190    (set_attr "mode" "<MODE>")])
 191
 192 (define_expand "@pred_mov_width<vlmem_op_attr><mode>"
 193   [(set (match_operand:V_VLS 0 "nonimmediate_operand")
 194     (if_then_else:V_VLS
 195       (unspec:<VM>
 196         [(match_operand:<VM> 1 "vector_mask_operand")
 197          (match_operand 4 "vector_length_operand")
 198          (match_operand 5 "const_int_operand")
 199          (match_operand 6 "const_int_operand")
 200          (match_operand 7 "const_int_operand")
 201          (reg:SI VL_REGNUM)
 202          (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLMEM_OP)
 203       (match_operand:V_VLS 3 "vector_move_operand")
 204       (match_operand:V_VLS 2 "vector_merge_operand")))]
 205   "TARGET_XTHEADVECTOR"
 206   {})
 207
 208 (define_insn_and_split "*pred_mov_width<vlmem_op_attr><mode>"
 209   [(set (match_operand:V_VLS 0 "nonimmediate_operand"       "=vr,    vr,    vd,     m,    vr,    vr")
 210     (if_then_else:V_VLS
 211       (unspec:<VM>
 212         [(match_operand:<VM> 1 "vector_mask_operand"       "vmWc1,   Wc1,    vm, vmWc1,   Wc1,   Wc1")
 213          (match_operand 4 "vector_length_operand"             "   rK,    rK,    rK,    rK,    rK,    rK")
 214          (match_operand 5 "const_int_operand"             "    i,     i,     i,     i,     i,     i")
 215          (match_operand 6 "const_int_operand"             "    i,     i,     i,     i,     i,     i")
 216          (match_operand 7 "const_int_operand"             "    i,     i,     i,     i,     i,     i")
 217          (reg:SI VL_REGNUM)
 218          (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLMEM_OP)
 219       (match_operand:V_VLS 3 "reg_or_mem_operand"             "    m,     m,     m,    vr,    vr,    vr")
 220       (match_operand:V_VLS 2 "vector_merge_operand"         "    0,    vu,    vu,    vu,    vu,     0")))]
 221   "(TARGET_XTHEADVECTOR
 222     && (register_operand (operands[0], <MODE>mode)
 223         || register_operand (operands[3], <MODE>mode)))"
 224   "@
 225    vl<vlmem_op_attr>.v\t%0,%3%p1
 226    vl<vlmem_op_attr>.v\t%0,%3
 227    vl<vlmem_op_attr>.v\t%0,%3,%1.t
 228    vs<vlmem_op_attr>.v\t%3,%0%p1
 229    vmv.v.v\t%0,%3
 230    vmv.v.v\t%0,%3"
 231   "&& riscv_vector::whole_reg_to_reg_move_p (operands, <MODE>mode, 7)"
 232   [(set (match_dup 0) (match_dup 3))]
 233   ""
 234   [(set_attr "type" "vlde,vlde,vlde,vste,vimov,vimov")
 235    (set_attr "mode" "<MODE>")])
 236
 237 (define_insn "@pred_store_width<vlmem_op_attr><mode>"
 238   [(set (match_operand:VI 0 "memory_operand"             "+m")
 239         (if_then_else:VI
 240           (unspec:<VM>
 241             [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
 242              (match_operand 3 "vector_length_operand"    "   rK")
 243              (match_operand 4 "const_int_operand"       "    i")
 244              (reg:SI VL_REGNUM)
 245              (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSMEM_OP)
 246           (match_operand:VI 2 "register_operand"         "    vr")
 247           (match_dup 0)))]
 248   "TARGET_XTHEADVECTOR"
 249   "vs<vlmem_op_attr>.v\t%2,%0%p1"
 250   [(set_attr "type" "vste")
 251    (set_attr "mode" "<MODE>")
 252    (set (attr "avl_type_idx") (const_int 4))
 253    (set_attr "vl_op_idx" "3")])
 254
 255 (define_insn "@pred_strided_load_width<vlmem_op_attr><mode>"
 256   [(set (match_operand:VI 0 "register_operand"        "=vr,    vr,    vd")
 257         (if_then_else:VI
 258           (unspec:<VM>
 259             [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,   Wc1,    vm")
 260              (match_operand 5 "vector_length_operand"    "   rK,    rK,    rK")
 261              (match_operand 6 "const_int_operand"       "    i,     i,     i")
 262              (match_operand 7 "const_int_operand"       "    i,     i,     i")
 263              (match_operand 8 "const_int_operand"       "    i,     i,     i")
 264              (reg:SI VL_REGNUM)
 265              (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLSMEM_OP)
 266           (unspec:VI
 267             [(match_operand:VI 3 "memory_operand"        "    m,     m,     m")
 268              (match_operand 4 "pmode_reg_or_0_operand"   "   rJ,    rJ,    rJ")] UNSPEC_TH_VLSMEM_OP)
 269           (match_operand:VI 2 "vector_merge_operand"      "    0,    vu,    vu")))]
 270   "TARGET_XTHEADVECTOR"
 271   "vls<vlmem_op_attr>.v\t%0,%3,%z4%p1"
 272   [(set_attr "type" "vlds")
 273    (set_attr "mode" "<MODE>")])
 274
 275 (define_insn "@pred_strided_store_width<vlmem_op_attr><mode>"
 276   [(set (match_operand:VI 0 "memory_operand"             "+m")
 277         (if_then_else:VI
 278           (unspec:<VM>
 279             [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
 280              (match_operand 4 "vector_length_operand"    "   rK")
 281              (match_operand 5 "const_int_operand"       "    i")
 282              (reg:SI VL_REGNUM)
 283              (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSSMEM_OP)
 284           (unspec:VI
 285             [(match_operand 2 "pmode_reg_or_0_operand"   "   rJ")
 286              (match_operand:VI 3 "register_operand"       "   vr")] UNSPEC_TH_VSSMEM_OP)
 287           (match_dup 0)))]
 288   "TARGET_XTHEADVECTOR"
 289   "vss<vlmem_op_attr>.v\t%3,%0,%z2%p1"
 290   [(set_attr "type" "vsts")
 291    (set_attr "mode" "<MODE>")
 292    (set (attr "avl_type_idx") (const_int 5))])
 293
 294 (define_insn "@pred_indexed_load_width<vlmem_op_attr><mode>"
 295   [(set (match_operand:VI 0 "register_operand"       "=vd, vr,vd, vr")
 296         (if_then_else:VI
 297           (unspec:<VM>
 298             [(match_operand:<VM> 1 "vector_mask_operand"  " vm,Wc1,vm,Wc1")
 299              (match_operand 5 "vector_length_operand"     " rK, rK,rK, rK")
 300              (match_operand 6 "const_int_operand"        "  i,  i, i,  i")
 301              (match_operand 7 "const_int_operand"        "  i,  i, i,  i")
 302              (match_operand 8 "const_int_operand"        "  i,  i, i,  i")
 303              (reg:SI VL_REGNUM)
 304              (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLXMEM_OP)
 305           (unspec:VI
 306             [(match_operand 3 "pmode_reg_or_0_operand"    " rJ, rJ,rJ, rJ")
 307              (mem:BLK (scratch))
 308              (match_operand:VI 4 "register_operand" " vr, vr,vr, vr")] UNSPEC_TH_VLXMEM_OP)
 309           (match_operand:VI 2 "vector_merge_operand"       " vu, vu, 0,  0")))]
 310   "TARGET_XTHEADVECTOR"
 311   "vlx<vlmem_op_attr>.v\t%0,(%z3),%4%p1"
 312   [(set_attr "type" "vldux")
 313    (set_attr "mode" "<MODE>")])
 314
 315 (define_insn "@pred_indexed_<vlmem_order_attr>store_width<vlmem_op_attr><mode>"
 316   [(set (mem:BLK (scratch))
 317         (unspec:BLK
 318           [(unspec:<VM>
 319             [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
 320              (match_operand 4 "vector_length_operand"    "   rK")
 321              (match_operand 5 "const_int_operand"       "    i")
 322              (reg:SI VL_REGNUM)
 323              (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSXMEM_OP)
 324            (match_operand 1 "pmode_reg_or_0_operand"      "  rJ")
 325            (match_operand:VI 2 "register_operand" "  vr")
 326            (match_operand:VI 3 "register_operand"  "  vr")] UNSPEC_TH_VSXMEM_OP))]
 327   "TARGET_XTHEADVECTOR"
 328   "vs<vlmem_order_attr>x<vlmem_op_attr>.v\t%3,(%z1),%2%p0"
 329   [(set_attr "type" "vstux")
 330    (set_attr "mode" "<MODE>")])
 331
 332 (define_expand "@pred_th_extract<mode>"
 333   [(set (match_operand:<VEL> 0 "register_operand")
 334         (unspec:<VEL>
 335           [(vec_select:<VEL>
 336              (match_operand:V_VLSI 1 "register_operand")
 337              (parallel [(match_operand:DI 2 "register_operand" "r")]))
 338            (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
 339   "TARGET_XTHEADVECTOR"
 340 {})
 341
 342 (define_insn "*pred_th_extract<mode>"
 343   [(set (match_operand:<VEL> 0 "register_operand"   "=r")
 344   (unspec:<VEL>
 345     [(vec_select:<VEL>
 346        (match_operand:V_VLSI 1 "register_operand" "vr")
 347        (parallel [(match_operand:DI 2 "register_operand" "r")]))
 348      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
 349   "TARGET_XTHEADVECTOR"
 350   "vext.x.v\t%0,%1,%2"
 351   [(set_attr "type" "vimovvx")
 352    (set_attr "mode" "<MODE>")])