gcc/config/riscv/vector-crypto.md

   1 ;; Machine description for the RISC-V Vector Crypto  extensions.
   2 ;; Copyright (C) 2024 Free Software Foundation, Inc.
   3
   4 ;; This file is part of GCC.
   5
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 (define_c_enum "unspec" [
  21     ;; Zvbb unspecs
  22     UNSPEC_VBREV
  23     UNSPEC_VBREV8
  24     UNSPEC_VREV8
  25     UNSPEC_VCLMUL
  26     UNSPEC_VCLMULH
  27     UNSPEC_VGHSH
  28     UNSPEC_VGMUL
  29     UNSPEC_VAESEF
  30     UNSPEC_VAESEFVV
  31     UNSPEC_VAESEFVS
  32     UNSPEC_VAESEM
  33     UNSPEC_VAESEMVV
  34     UNSPEC_VAESEMVS
  35     UNSPEC_VAESDF
  36     UNSPEC_VAESDFVV
  37     UNSPEC_VAESDFVS
  38     UNSPEC_VAESDM
  39     UNSPEC_VAESDMVV
  40     UNSPEC_VAESDMVS
  41     UNSPEC_VAESZ
  42     UNSPEC_VAESZVVNULL
  43     UNSPEC_VAESZVS
  44     UNSPEC_VAESKF1
  45     UNSPEC_VAESKF2
  46     UNSPEC_VSHA2MS
  47     UNSPEC_VSHA2CH
  48     UNSPEC_VSHA2CL
  49     UNSPEC_VSM4K
  50     UNSPEC_VSM4R
  51     UNSPEC_VSM4RVV
  52     UNSPEC_VSM4RVS
  53     UNSPEC_VSM3ME
  54     UNSPEC_VSM3C
  55 ])
  56
  57 (define_int_attr rev  [(UNSPEC_VBREV "brev") (UNSPEC_VBREV8 "brev8") (UNSPEC_VREV8 "rev8")])
  58
  59 (define_int_attr h [(UNSPEC_VCLMUL "") (UNSPEC_VCLMULH "h")])
  60
  61 (define_int_attr vv_ins_name [(UNSPEC_VGMUL    "gmul" ) (UNSPEC_VAESEFVV "aesef")
  62                               (UNSPEC_VAESEMVV "aesem") (UNSPEC_VAESDFVV "aesdf")
  63                               (UNSPEC_VAESDMVV "aesdm") (UNSPEC_VAESEFVS "aesef")
  64                               (UNSPEC_VAESEMVS "aesem") (UNSPEC_VAESDFVS "aesdf")
  65                               (UNSPEC_VAESDMVS "aesdm") (UNSPEC_VAESZVS  "aesz" )
  66                               (UNSPEC_VSM4RVV  "sm4r" ) (UNSPEC_VSM4RVS  "sm4r" )])
  67
  68 (define_int_attr vv_ins1_name [(UNSPEC_VGHSH "ghsh")     (UNSPEC_VSHA2MS "sha2ms")
  69                                (UNSPEC_VSHA2CH "sha2ch") (UNSPEC_VSHA2CL "sha2cl")])
  70
  71 (define_int_attr vi_ins_name [(UNSPEC_VAESKF1 "aeskf1") (UNSPEC_VSM4K "sm4k")])
  72
  73 (define_int_attr vi_ins1_name [(UNSPEC_VAESKF2 "aeskf2") (UNSPEC_VSM3C "sm3c")])
  74
  75 (define_int_attr ins_type [(UNSPEC_VGMUL    "vv") (UNSPEC_VAESEFVV "vv")
  76                            (UNSPEC_VAESEMVV "vv") (UNSPEC_VAESDFVV "vv")
  77                            (UNSPEC_VAESDMVV "vv") (UNSPEC_VAESEFVS "vs")
  78                            (UNSPEC_VAESEMVS "vs") (UNSPEC_VAESDFVS "vs")
  79                            (UNSPEC_VAESDMVS "vs") (UNSPEC_VAESZVS  "vs")
  80                            (UNSPEC_VSM4RVV  "vv") (UNSPEC_VSM4RVS  "vs")])
  81
  82 (define_int_iterator UNSPEC_VRBB8 [UNSPEC_VBREV UNSPEC_VBREV8 UNSPEC_VREV8])
  83
  84 (define_int_iterator UNSPEC_CLMUL_VC [UNSPEC_VCLMUL UNSPEC_VCLMULH])
  85
  86 (define_int_iterator UNSPEC_CRYPTO_VV [UNSPEC_VGMUL    UNSPEC_VAESEFVV UNSPEC_VAESEMVV
  87                                        UNSPEC_VAESDFVV UNSPEC_VAESDMVV UNSPEC_VAESEFVS
  88                                        UNSPEC_VAESEMVS UNSPEC_VAESDFVS UNSPEC_VAESDMVS
  89                                        UNSPEC_VAESZVS  UNSPEC_VSM4RVV  UNSPEC_VSM4RVS])
  90
  91 (define_int_iterator UNSPEC_VGNHAB [UNSPEC_VGHSH UNSPEC_VSHA2MS UNSPEC_VSHA2CH UNSPEC_VSHA2CL])
  92
  93 (define_int_iterator UNSPEC_CRYPTO_VI [UNSPEC_VAESKF1 UNSPEC_VSM4K])
  94
  95 (define_int_iterator UNSPEC_CRYPTO_VI1 [UNSPEC_VAESKF2 UNSPEC_VSM3C])
  96
  97 ;; zvbb instructions patterns.
  98 ;; vandn.vv vandn.vx vrol.vv vrol.vx
  99 ;; vror.vv vror.vx vror.vi
 100 ;; vwsll.vv vwsll.vx vwsll.vi
 101 (define_insn "@pred_vandn<mode>"
 102   [(set (match_operand:V_VLSI 0 "register_operand"        "=vd, vr, vd, vr")
 103      (if_then_else:V_VLSI
 104        (unspec:<VM>
 105          [(match_operand:<VM> 1 "vector_mask_operand"     "vm,Wc1, vm,Wc1")
 106           (match_operand 5 "vector_length_operand"        "rK, rK, rK, rK")
 107           (match_operand 6 "const_int_operand"            " i,  i,  i,  i")
 108           (match_operand 7 "const_int_operand"            " i,  i,  i,  i")
 109           (match_operand 8 "const_int_operand"            " i,  i,  i,  i")
 110           (reg:SI VL_REGNUM)
 111           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 112        (and:V_VLSI
 113          (not:V_VLSI
 114             (match_operand:V_VLSI 4 "register_operand"    "vr, vr, vr, vr"))
 115          (match_operand:V_VLSI 3 "register_operand"       "vr, vr, vr, vr"))
 116        (match_operand:V_VLSI 2 "vector_merge_operand"     "vu, vu,  0,  0")))]
 117   "TARGET_ZVBB || TARGET_ZVKB"
 118   "vandn.vv\t%0,%3,%4%p1"
 119   [(set_attr "type" "vandn")
 120    (set_attr "mode" "<MODE>")])
 121
 122 (define_insn "@pred_vandn<mode>_scalar"
 123   [(set (match_operand:V_VLSI_QHS 0 "register_operand"    "=vd, vr,vd, vr")
 124      (if_then_else:V_VLSI_QHS
 125        (unspec:<VM>
 126          [(match_operand:<VM> 1 "vector_mask_operand"     " vm,Wc1,vm,Wc1")
 127           (match_operand 5 "vector_length_operand"        " rK, rK,rK, rK")
 128           (match_operand 6 "const_int_operand"            "  i,  i, i,  i")
 129           (match_operand 7 "const_int_operand"            "  i,  i, i,  i")
 130           (match_operand 8 "const_int_operand"            "  i,  i, i,  i")
 131           (reg:SI VL_REGNUM)
 132           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 133        (and:V_VLSI_QHS
 134          (not:V_VLSI_QHS
 135            (vec_duplicate:V_VLSI_QHS
 136              (match_operand:<VEL> 4 "register_operand"    " r,  r, r,  r")))
 137          (match_operand:V_VLSI_QHS 3 "register_operand"   "vr, vr,vr, vr"))
 138        (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, vu, 0,  0")))]
 139   "TARGET_ZVBB || TARGET_ZVKB"
 140   "vandn.vx\t%0,%3,%4%p1"
 141   [(set_attr "type" "vandn")
 142    (set_attr "mode" "<MODE>")])
 143
 144 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
 145 ;; we need to deal with SEW = 64 in RV32 system.
 146 (define_expand "@pred_vandn<mode>_scalar"
 147   [(set (match_operand:V_VLSI_D 0 "register_operand")
 148      (if_then_else:V_VLSI_D
 149        (unspec:<VM>
 150          [(match_operand:<VM> 1 "vector_mask_operand")
 151           (match_operand 5 "vector_length_operand")
 152           (match_operand 6 "const_int_operand")
 153           (match_operand 7 "const_int_operand")
 154           (match_operand 8 "const_int_operand")
 155           (reg:SI VL_REGNUM)
 156           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 157        (and:V_VLSI_D
 158          (not:V_VLSI_D
 159            (vec_duplicate:V_VLSI_D
 160              (match_operand:<VEL> 4 "reg_or_int_operand")))
 161          (match_operand:V_VLSI_D 3 "register_operand"))
 162        (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
 163   "TARGET_ZVBB || TARGET_ZVKB"
 164 {
 165   if (riscv_vector::sew64_scalar_helper (
 166         operands,
 167         /* scalar op */&operands[4],
 168         /* vl */operands[5],
 169         <MODE>mode,
 170         false,
 171         [] (rtx *operands, rtx broadcast_scalar) {
 172           emit_insn (gen_pred_vandn<mode> (operands[0], operands[1],
 173                operands[2], operands[3], broadcast_scalar, operands[5],
 174                operands[6], operands[7], operands[8]));
 175         },
 176         (riscv_vector::avl_type) INTVAL (operands[8])))
 177     DONE;
 178 })
 179
 180 (define_insn "*pred_vandn<mode>_scalar"
 181   [(set (match_operand:V_VLSI_D 0 "register_operand"        "=vd, vr,vd, vr")
 182      (if_then_else:V_VLSI_D
 183        (unspec:<VM>
 184          [(match_operand:<VM> 1 "vector_mask_operand"       " vm,Wc1,vm,Wc1")
 185           (match_operand 5 "vector_length_operand"          " rK, rK,rK, rK")
 186           (match_operand 6 "const_int_operand"              " i,   i, i,  i")
 187           (match_operand 7 "const_int_operand"              " i,   i, i,  i")
 188           (match_operand 8 "const_int_operand"              " i,   i, i,  i")
 189           (reg:SI VL_REGNUM)
 190           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 191        (and:V_VLSI_D
 192          (not:V_VLSI_D
 193            (vec_duplicate:V_VLSI_D
 194              (match_operand:<VEL> 4 "reg_or_0_operand"      " rJ, rJ,rJ, rJ")))
 195          (match_operand:V_VLSI_D 3 "register_operand"       " vr, vr,vr, vr"))
 196        (match_operand:V_VLSI_D 2 "vector_merge_operand"     " vu, vu, 0,  0")))]
 197   "TARGET_ZVBB || TARGET_ZVKB"
 198   "vandn.vx\t%0,%3,%z4%p1"
 199   [(set_attr "type" "vandn")
 200    (set_attr "mode" "<MODE>")])
 201
 202 (define_insn "*pred_vandn<mode>_extended_scalar"
 203   [(set (match_operand:V_VLSI_D 0 "register_operand"        "=vd, vr,vd, vr")
 204      (if_then_else:V_VLSI_D
 205        (unspec:<VM>
 206          [(match_operand:<VM> 1 "vector_mask_operand"       " vm,Wc1,vm,Wc1")
 207           (match_operand 5 "vector_length_operand"          " rK, rK,rK, rK")
 208           (match_operand 6 "const_int_operand"              " i,   i, i,  i")
 209           (match_operand 7 "const_int_operand"              " i,   i, i,  i")
 210           (match_operand 8 "const_int_operand"              " i,   i, i,  i")
 211           (reg:SI VL_REGNUM)
 212           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 213        (and:V_VLSI_D
 214          (not:V_VLSI_D
 215            (vec_duplicate:V_VLSI_D
 216              (sign_extend:<VEL>
 217                (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ,rJ, rJ"))))
 218          (match_operand:V_VLSI_D 3 "register_operand"       " vr, vr,vr, vr"))
 219        (match_operand:V_VLSI_D 2 "vector_merge_operand"     " vu, vu, 0,  0")))]
 220   "TARGET_ZVBB || TARGET_ZVKB"
 221   "vandn.vx\t%0,%3,%z4%p1"
 222   [(set_attr "type" "vandn")
 223    (set_attr "mode" "<MODE>")])
 224
 225 (define_insn "@pred_v<bitmanip_optab><mode>"
 226   [(set (match_operand:VI 0 "register_operand"        "=vd,vd, vr, vr")
 227      (if_then_else:VI
 228        (unspec:<VM>
 229          [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
 230           (match_operand 5 "vector_length_operand"    " rK,rK, rK, rK")
 231           (match_operand 6 "const_int_operand"        "  i, i,  i,  i")
 232           (match_operand 7 "const_int_operand"        "  i, i,  i,  i")
 233           (match_operand 8 "const_int_operand"        "  i, i,  i,  i")
 234           (reg:SI VL_REGNUM)
 235           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 236        (bitmanip_rotate:VI
 237          (match_operand:VI 3 "register_operand"       " vr,vr, vr, vr")
 238          (match_operand:VI 4 "register_operand"       " vr,vr, vr, vr"))
 239        (match_operand:VI 2 "vector_merge_operand"     " vu, 0, vu,  0")))]
 240   "TARGET_ZVBB || TARGET_ZVKB"
 241   "v<bitmanip_insn>.vv\t%0,%3,%4%p1"
 242   [(set_attr "type" "v<bitmanip_insn>")
 243    (set_attr "mode" "<MODE>")])
 244
 245 (define_insn "@pred_v<bitmanip_optab><mode>_scalar"
 246   [(set (match_operand:VI 0 "register_operand"        "=vd,vd, vr, vr")
 247      (if_then_else:VI
 248        (unspec:<VM>
 249          [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
 250           (match_operand 5 "vector_length_operand"    " rK,rK, rK, rK")
 251           (match_operand 6 "const_int_operand"        "  i, i,  i,  i")
 252           (match_operand 7 "const_int_operand"        "  i, i,  i,  i")
 253           (match_operand 8 "const_int_operand"        "  i, i,  i,  i")
 254           (reg:SI VL_REGNUM)
 255           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 256        (bitmanip_rotate:VI
 257          (match_operand:VI 3 "register_operand"       " vr,vr, vr, vr")
 258          (match_operand 4 "pmode_register_operand"    "  r, r,  r,  r"))
 259        (match_operand:VI 2 "vector_merge_operand"     " vu, 0, vu,  0")))]
 260   "TARGET_ZVBB || TARGET_ZVKB"
 261   "v<bitmanip_insn>.vx\t%0,%3,%4%p1"
 262   [(set_attr "type" "v<bitmanip_insn>")
 263    (set_attr "mode" "<MODE>")])
 264
 265 (define_insn "*pred_vror<mode>_scalar"
 266   [(set (match_operand:VI 0 "register_operand"        "=vd,vd, vr,vr")
 267      (if_then_else:VI
 268        (unspec:<VM>
 269          [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
 270           (match_operand 5 "vector_length_operand"    " rK,rK, rK, rK")
 271           (match_operand 6 "const_int_operand"        "  i, i,  i,  i")
 272           (match_operand 7 "const_int_operand"        "  i, i,  i,  i")
 273           (match_operand 8 "const_int_operand"        "  i, i,  i,  i")
 274           (reg:SI VL_REGNUM)
 275           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 276        (rotatert:VI
 277          (match_operand:VI 3 "register_operand"       " vr,vr, vr, vr")
 278          (match_operand    4 "const_csr_operand"      "  K, K,  K,  K"))
 279        (match_operand:VI 2 "vector_merge_operand"     " vu, 0, vu,  0")))]
 280   "TARGET_ZVBB || TARGET_ZVKB"
 281   "vror.vi\t%0,%3,%4%p1"
 282   [(set_attr "type" "vror")
 283    (set_attr "mode" "<MODE>")])
 284
 285 (define_insn "@pred_vwsll<mode>"
 286   [(set (match_operand:VWEXTI 0 "register_operand"     "=&vr")
 287      (if_then_else:VWEXTI
 288        (unspec:<VM>
 289          [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
 290           (match_operand 5 "vector_length_operand"    "  rK")
 291           (match_operand 6 "const_int_operand"        "   i")
 292           (match_operand 7 "const_int_operand"        "   i")
 293           (match_operand 8 "const_int_operand"        "   i")
 294           (reg:SI VL_REGNUM)
 295           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 296        (ashift:VWEXTI
 297          (zero_extend:VWEXTI
 298            (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "vr"))
 299          (match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand"  "vrvk"))
 300        (match_operand:VWEXTI 2 "vector_merge_operand" "0vu")))]
 301   "TARGET_ZVBB"
 302   "vwsll.v%o4\t%0,%3,%4%p1"
 303   [(set_attr "type" "vwsll")
 304    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
 305
 306 (define_insn "@pred_vwsll<mode>_scalar"
 307   [(set (match_operand:VWEXTI 0 "register_operand"              "=&vr,    &vr")
 308      (if_then_else:VWEXTI
 309        (unspec:<VM>
 310          [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1, vmWc1")
 311           (match_operand 5 "vector_length_operand"              "   rK,    rK")
 312           (match_operand 6 "const_int_operand"                  "    i,     i")
 313           (match_operand 7 "const_int_operand"                  "    i,     i")
 314           (match_operand 8 "const_int_operand"                  "    i,     i")
 315           (reg:SI VL_REGNUM)
 316           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 317        (ashift:VWEXTI
 318          (zero_extend:VWEXTI
 319            (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,    vr"))
 320          (match_operand 4 "pmode_reg_or_uimm5_operand"          "   rK,    rK"))
 321        (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
 322   "TARGET_ZVBB"
 323   "vwsll.v%o4\t%0,%3,%4%p1"
 324   [(set_attr "type" "vwsll")
 325    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
 326
 327 ;; vbrev.v vbrev8.v vrev8.v
 328 (define_insn "@pred_v<rev><mode>"
 329   [(set (match_operand:V_VLSI 0 "register_operand"        "=vd,vr,vd,vr")
 330      (if_then_else:V_VLSI
 331        (unspec:<VM>
 332          [(match_operand:<VM> 1 "vector_mask_operand"     "vm,Wc1,vm,Wc1")
 333           (match_operand 4 "vector_length_operand"        "rK,rK, rK, rK")
 334           (match_operand 5 "const_int_operand"            "i,  i,  i,  i")
 335           (match_operand 6 "const_int_operand"            "i,  i,  i,  i")
 336           (match_operand 7 "const_int_operand"            "i,  i,  i,  i")
 337           (reg:SI VL_REGNUM)
 338           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 339        (unspec:V_VLSI
 340          [(match_operand:V_VLSI 3 "register_operand"      "vr,vr, vr, vr")]UNSPEC_VRBB8)
 341        (match_operand:V_VLSI 2 "vector_merge_operand"     "vu,vu,  0,  0")))]
 342   "TARGET_ZVBB || TARGET_ZVKB"
 343   "v<rev>.v\t%0,%3%p1"
 344   [(set_attr "type" "v<rev>")
 345    (set_attr "mode" "<MODE>")])
 346
 347 ;; vclz.v vctz.v vcpop.v
 348 (define_insn "@pred_v<bitmanip_optab><mode>"
 349   [(set (match_operand:V_VLSI 0     "register_operand"      "=vd, vr")
 350      (clz_ctz_pcnt:V_VLSI
 351        (parallel
 352          [(match_operand:V_VLSI 2   "register_operand"      " vr, vr")
 353           (unspec:<VM>
 354             [(match_operand:<VM> 1  "vector_mask_operand"   " vm,Wc1")
 355              (match_operand 3       "vector_length_operand" " rK, rK")
 356              (match_operand 4       "const_int_operand"     "  i,  i")
 357              (reg:SI VL_REGNUM)
 358              (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)])))]
 359   "TARGET_ZVBB"
 360   "v<bitmanip_insn>.v\t%0,%2%p1"
 361   [(set_attr "type" "v<bitmanip_insn>")
 362    (set_attr "mode" "<MODE>")])
 363
 364 ;; zvbc instructions patterns.
 365 ;; vclmul.vv vclmul.vx
 366 ;; vclmulh.vv vclmulh.vx
 367 (define_insn "@pred_vclmul<h><mode>"
 368   [(set (match_operand:VI_D 0  "register_operand"     "=vd,vr,vd, vr")
 369      (if_then_else:VI_D
 370        (unspec:<VM>
 371          [(match_operand:<VM> 1 "vector_mask_operand" "vm,Wc1,vm,Wc1")
 372           (match_operand 5 "vector_length_operand"    "rK, rK,rK, rK")
 373           (match_operand 6 "const_int_operand"        " i,  i, i,  i")
 374           (match_operand 7 "const_int_operand"        " i,  i, i,  i")
 375           (match_operand 8 "const_int_operand"        " i,  i, i,  i")
 376           (reg:SI VL_REGNUM)
 377           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 378        (unspec:VI_D
 379          [(match_operand:VI_D 3 "register_operand"     "vr, vr,vr, vr")
 380           (match_operand:VI_D 4 "register_operand"     "vr, vr,vr, vr")] UNSPEC_CLMUL_VC)
 381        (match_operand:VI_D 2 "vector_merge_operand"    "vu, vu, 0,  0")))]
 382   "TARGET_ZVBC"
 383   "vclmul<h>.vv\t%0,%3,%4%p1"
 384   [(set_attr "type" "vclmul<h>")
 385    (set_attr "mode" "<MODE>")])
 386
 387 ;; Deal with SEW = 64 in RV32 system.
 388 (define_expand "@pred_vclmul<h><mode>_scalar"
 389   [(set (match_operand:VI_D 0 "register_operand")
 390      (if_then_else:VI_D
 391        (unspec:<VM>
 392          [(match_operand:<VM> 1 "vector_mask_operand")
 393           (match_operand 5 "vector_length_operand")
 394           (match_operand 6 "const_int_operand")
 395           (match_operand 7 "const_int_operand")
 396           (match_operand 8 "const_int_operand")
 397           (reg:SI VL_REGNUM)
 398           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 399        (unspec:VI_D
 400          [(vec_duplicate:VI_D
 401             (match_operand:<VEL> 4 "register_operand"))
 402           (match_operand:VI_D 3 "register_operand")] UNSPEC_CLMUL_VC)
 403        (match_operand:VI_D 2 "vector_merge_operand")))]
 404   "TARGET_ZVBC"
 405 {
 406   if (riscv_vector::sew64_scalar_helper (
 407         operands,
 408         /* scalar op */&operands[4],
 409         /* vl */operands[5],
 410         <MODE>mode,
 411         false,
 412         [] (rtx *operands, rtx broadcast_scalar) {
 413           emit_insn (gen_pred_vclmul<h><mode> (operands[0], operands[1],
 414                operands[2], operands[3], broadcast_scalar, operands[5],
 415                operands[6], operands[7], operands[8]));
 416         },
 417         (riscv_vector::avl_type) INTVAL (operands[8])))
 418     DONE;
 419 })
 420
 421 (define_insn "*pred_vclmul<h><mode>_scalar"
 422   [(set (match_operand:VI_D 0 "register_operand"       "=vd,vr,vd, vr")
 423     (if_then_else:VI_D
 424       (unspec:<VM>
 425         [(match_operand:<VM> 1 "vector_mask_operand"  "vm,Wc1,vm,Wc1")
 426         (match_operand 5 "vector_length_operand"      "rK, rK,rK, rK")
 427         (match_operand 6 "const_int_operand"          " i,  i, i,  i")
 428         (match_operand 7 "const_int_operand"          " i,  i, i,  i")
 429         (match_operand 8 "const_int_operand"          " i,  i, i,  i")
 430         (reg:SI VL_REGNUM)
 431         (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 432       (unspec:VI_D
 433         [(vec_duplicate:VI_D
 434            (match_operand:<VEL> 4 "reg_or_0_operand"   "rJ, rJ,rJ, rJ"))
 435          (match_operand:VI_D 3 "register_operand"      "vr, vr,vr, vr")] UNSPEC_CLMUL_VC)
 436       (match_operand:VI_D 2 "vector_merge_operand"     "vu, vu, 0,  0")))]
 437   "TARGET_ZVBC"
 438   "vclmul<h>.vx\t%0,%3,%4%p1"
 439   [(set_attr "type" "vclmul<h>")
 440    (set_attr "mode" "<MODE>")])
 441
 442 (define_insn "*pred_vclmul<h><mode>_extend_scalar"
 443   [(set (match_operand:VI_D 0 "register_operand"         "=vd,vr,vd, vr")
 444     (if_then_else:VI_D
 445       (unspec:<VM>
 446         [(match_operand:<VM> 1 "vector_mask_operand"    "vm,Wc1,vm,Wc1")
 447         (match_operand 5 "vector_length_operand"        "rK, rK,rK, rK")
 448         (match_operand 6 "const_int_operand"            " i,  i, i,  i")
 449         (match_operand 7 "const_int_operand"            " i,  i, i,  i")
 450         (match_operand 8 "const_int_operand"            " i,  i, i,  i")
 451         (reg:SI VL_REGNUM)
 452         (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 453       (unspec:VI_D
 454         [(vec_duplicate:VI_D
 455            (sign_extend:<VEL>
 456              (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ,rJ, rJ")))
 457          (match_operand:VI_D 3 "register_operand"        "vr, vr,vr, vr")] UNSPEC_CLMUL_VC)
 458       (match_operand:VI_D 2 "vector_merge_operand"       "vu, vu, 0,  0")))]
 459   "TARGET_ZVBC"
 460   "vclmul<h>.vx\t%0,%3,%4%p1"
 461   [(set_attr "type" "vclmul<h>")
 462    (set_attr "mode" "<MODE>")])
 463
 464 ;; zvknh[ab] and zvkg instructions patterns.
 465 ;; vsha2ms.vv vsha2ch.vv vsha2cl.vv vghsh.vv
 466 (define_insn "@pred_v<vv_ins1_name><mode>"
 467   [(set (match_operand:VQEXTI 0 "register_operand"     "=vr")
 468      (if_then_else:VQEXTI
 469        (unspec:<VM>
 470          [(match_operand 4 "vector_length_operand"     "rK")
 471           (match_operand 5 "const_int_operand"         " i")
 472           (match_operand 6 "const_int_operand"         " i")
 473           (reg:SI VL_REGNUM)
 474           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 475        (unspec:VQEXTI
 476           [(match_operand:VQEXTI 1 "register_operand" " 0")
 477            (match_operand:VQEXTI 2 "register_operand" "vr")
 478            (match_operand:VQEXTI 3 "register_operand" "vr")] UNSPEC_VGNHAB)
 479        (match_dup 1)))]
 480   "TARGET_ZVKNHA || TARGET_ZVKNHB || TARGET_ZVKG"
 481   "v<vv_ins1_name>.vv\t%0,%2,%3"
 482   [(set_attr "type" "v<vv_ins1_name>")
 483    (set_attr "mode" "<MODE>")])
 484
 485 ;; zvkned and zvksed amd zvkg instructions patterns.
 486 ;; vgmul.vv       vaesz.vs
 487 ;; vaesef.[vv,vs] vaesem.[vv,vs] vaesdf.[vv,vs] vaesdm.[vv,vs]
 488 ;; vsm4r.[vv,vs]
 489 (define_insn "@pred_crypto_vv<vv_ins_name><ins_type><mode>"
 490   [(set (match_operand:VSI 0 "register_operand"    "=vr")
 491      (if_then_else:VSI
 492        (unspec:<VM>
 493          [(match_operand 3 "vector_length_operand" " rK")
 494           (match_operand 4 "const_int_operand"     "  i")
 495           (match_operand 5 "const_int_operand"     "  i")
 496           (reg:SI VL_REGNUM)
 497           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 498        (unspec:VSI
 499          [(match_operand:VSI 1 "register_operand" " 0")
 500           (match_operand:VSI 2 "register_operand" "vr")] UNSPEC_CRYPTO_VV)
 501        (match_dup 1)))]
 502   "TARGET_ZVKNED || TARGET_ZVKSED || TARGET_ZVKG"
 503   "v<vv_ins_name>.<ins_type>\t%0,%2"
 504   [(set_attr "type" "v<vv_ins_name>")
 505    (set_attr "mode" "<MODE>")])
 506
 507 (define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x1<mode>_scalar"
 508   [(set (match_operand:VSI 0 "register_operand"    "=&vr")
 509      (if_then_else:VSI
 510        (unspec:<VM>
 511          [(match_operand 3 "vector_length_operand" "  rK")
 512           (match_operand 4 "const_int_operand"     "   i")
 513           (match_operand 5 "const_int_operand"     "   i")
 514           (reg:SI VL_REGNUM)
 515           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 516        (unspec:VSI
 517          [(match_operand:VSI 1 "register_operand" " 0")
 518           (match_operand:VSI 2 "register_operand" "vr")] UNSPEC_CRYPTO_VV)
 519        (match_dup 1)))]
 520   "TARGET_ZVKNED || TARGET_ZVKSED"
 521   "v<vv_ins_name>.<ins_type>\t%0,%2"
 522   [(set_attr "type" "v<vv_ins_name>")
 523    (set_attr "mode" "<MODE>")])
 524
 525 (define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x2<mode>_scalar"
 526   [(set (match_operand:<VSIX2> 0 "register_operand" "=&vr")
 527      (if_then_else:<VSIX2>
 528        (unspec:<VM>
 529          [(match_operand 3 "vector_length_operand"  "rK")
 530           (match_operand 4 "const_int_operand"      " i")
 531           (match_operand 5 "const_int_operand"      " i")
 532           (reg:SI VL_REGNUM)
 533           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 534        (unspec:<VSIX2>
 535          [(match_operand:<VSIX2> 1  "register_operand"   " 0")
 536           (match_operand:VLMULX2_SI 2 "register_operand" "vr")] UNSPEC_CRYPTO_VV)
 537        (match_dup 1)))]
 538   "TARGET_ZVKNED || TARGET_ZVKSED"
 539   "v<vv_ins_name>.<ins_type>\t%0,%2"
 540   [(set_attr "type" "v<vv_ins_name>")
 541    (set_attr "mode" "<MODE>")])
 542
 543 (define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x4<mode>_scalar"
 544  [(set (match_operand:<VSIX4> 0 "register_operand"      "=&vr")
 545     (if_then_else:<VSIX4>
 546       (unspec:<VM>
 547         [(match_operand 3 "vector_length_operand"       " rK")
 548          (match_operand 4 "const_int_operand"           "  i")
 549          (match_operand 5 "const_int_operand"           "  i")
 550          (reg:SI VL_REGNUM)
 551          (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 552        (unspec:<VSIX4>
 553          [(match_operand:<VSIX4> 1 "register_operand"    " 0")
 554           (match_operand:VLMULX4_SI 2 "register_operand" "vr")] UNSPEC_CRYPTO_VV)
 555        (match_dup 1)))]
 556  "TARGET_ZVKNED || TARGET_ZVKSED"
 557  "v<vv_ins_name>.<ins_type>\t%0,%2"
 558  [(set_attr "type" "v<vv_ins_name>")
 559   (set_attr "mode" "<MODE>")])
 560
 561 (define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x8<mode>_scalar"
 562  [(set (match_operand:<VSIX8> 0 "register_operand"      "=&vr")
 563     (if_then_else:<VSIX8>
 564       (unspec:<VM>
 565         [(match_operand 3 "vector_length_operand"       " rK")
 566          (match_operand 4 "const_int_operand"           "  i")
 567          (match_operand 5 "const_int_operand"           "  i")
 568          (reg:SI VL_REGNUM)
 569          (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 570       (unspec:<VSIX8>
 571         [(match_operand:<VSIX8> 1 "register_operand"    "  0")
 572          (match_operand:VLMULX8_SI 2 "register_operand" " vr")] UNSPEC_CRYPTO_VV)
 573       (match_dup 1)))]
 574  "TARGET_ZVKNED || TARGET_ZVKSED"
 575  "v<vv_ins_name>.<ins_type>\t%0,%2"
 576  [(set_attr "type" "v<vv_ins_name>")
 577   (set_attr "mode" "<MODE>")])
 578
 579 (define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x16<mode>_scalar"
 580  [(set (match_operand:<VSIX16> 0 "register_operand"      "=&vr")
 581     (if_then_else:<VSIX16>
 582       (unspec:<VM>
 583         [(match_operand 3 "vector_length_operand"        "  rK")
 584          (match_operand 4 "const_int_operand"            "   i")
 585          (match_operand 5 "const_int_operand"            "   i")
 586          (reg:SI VL_REGNUM)
 587          (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 588       (unspec:<VSIX16>
 589         [(match_operand:<VSIX16> 1 "register_operand"    "   0")
 590          (match_operand:VLMULX16_SI 2 "register_operand" "  vr")] UNSPEC_CRYPTO_VV)
 591       (match_dup 1)))]
 592  "TARGET_ZVKNED || TARGET_ZVKSED"
 593  "v<vv_ins_name>.<ins_type>\t%0,%2"
 594  [(set_attr "type" "v<vv_ins_name>")
 595   (set_attr "mode" "<MODE>")])
 596
 597 ;; vaeskf1.vi vsm4k.vi
 598 (define_insn "@pred_crypto_vi<vi_ins_name><mode>_scalar"
 599   [(set (match_operand:VSI 0 "register_operand"        "=vr, vr")
 600      (if_then_else:VSI
 601        (unspec:<VM>
 602          [(match_operand 4 "vector_length_operand"      "rK, rK")
 603           (match_operand 5 "const_int_operand"          " i,  i")
 604           (match_operand 6 "const_int_operand"          " i,  i")
 605           (reg:SI VL_REGNUM)
 606           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 607        (unspec:VSI
 608          [(match_operand:VSI 2       "register_operand" "vr, vr")
 609           (match_operand 3  "const_int_operand"         " i,  i")] UNSPEC_CRYPTO_VI)
 610        (match_operand:VSI 1 "vector_merge_operand"      "vu,  0")))]
 611   "TARGET_ZVKNED || TARGET_ZVKSED"
 612   "v<vi_ins_name>.vi\t%0,%2,%3"
 613   [(set_attr "type" "v<vi_ins_name>")
 614    (set_attr "mode" "<MODE>")])
 615
 616 ;; vaeskf2.vi vsm3c.vi
 617 (define_insn "@pred_vi<vi_ins1_name><mode>_nomaskedoff_scalar"
 618   [(set (match_operand:VSI 0 "register_operand"       "=vr")
 619      (if_then_else:VSI
 620        (unspec:<VM>
 621          [(match_operand 4 "vector_length_operand"    "rK")
 622           (match_operand 5 "const_int_operand"        " i")
 623           (match_operand 6 "const_int_operand"        " i")
 624           (reg:SI VL_REGNUM)
 625           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 626        (unspec:VSI
 627           [(match_operand:VSI 1   "register_operand"  " 0")
 628            (match_operand:VSI 2   "register_operand"  "vr")
 629            (match_operand 3 "const_int_operand" " i")] UNSPEC_CRYPTO_VI1)
 630        (match_dup 1)))]
 631   "TARGET_ZVKNED || TARGET_ZVKSH"
 632   "v<vi_ins1_name>.vi\t%0,%2,%3"
 633   [(set_attr "type" "v<vi_ins1_name>")
 634    (set_attr "mode" "<MODE>")])
 635
 636 ;; zvksh instructions patterns.
 637 ;; vsm3me.vv
 638 (define_insn "@pred_vsm3me<mode>"
 639   [(set (match_operand:VSI 0 "register_operand"    "=vr, vr")
 640      (if_then_else:VSI
 641        (unspec:<VM>
 642          [(match_operand 4 "vector_length_operand" " rK, rK")
 643           (match_operand 5 "const_int_operand"     "  i,  i")
 644           (match_operand 6 "const_int_operand"     "  i,  i")
 645           (reg:SI VL_REGNUM)
 646           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 647        (unspec:VSI
 648           [(match_operand:VSI 2 "register_operand" " vr, vr")
 649            (match_operand:VSI 3 "register_operand" " vr, vr")] UNSPEC_VSM3ME)
 650        (match_operand:VSI 1 "vector_merge_operand" " vu, 0")))]
 651   "TARGET_ZVKSH"
 652   "vsm3me.vv\t%0,%2,%3"
 653   [(set_attr "type" "vsm3me")
 654    (set_attr "mode" "<MODE>")])