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libcpp, c, middle-end: Optimize initializers using #embed in C
[official-gcc.git] / gcc / config / rl78 / rl78.h
bloba960aee3931c7cdb692c507090b0d665ec9e1336
1 /* GCC backend definitions for the Renesas RL78 processor.
2 Copyright (C) 2011-2024 Free Software Foundation, Inc.
3 Contributed by Red Hat.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20 \f
21
22 #define RL78_MUL_NONE (rl78_mul_type == MUL_NONE)
23 #define RL78_MUL_G13 (rl78_mul_type == MUL_G13)
24 #define RL78_MUL_G14 (rl78_mul_type == MUL_G14)
25
26 #define TARGET_G10 (rl78_cpu_type == CPU_G10)
27 #define TARGET_G13 (rl78_cpu_type == CPU_G13)
28 #define TARGET_G14 (rl78_cpu_type == CPU_G14)
29
30 #define TARGET_CPU_CPP_BUILTINS() \
31 do \
32 { \
33 builtin_define ("__RL78__"); \
34 builtin_assert ("cpu=RL78"); \
35 \
36 if (RL78_MUL_NONE) \
37 builtin_define ("__RL78_MUL_NONE__"); \
38 else if (RL78_MUL_G13) \
39 builtin_define ("__RL78_MUL_G13__"); \
40 else if (RL78_MUL_G14) \
41 builtin_define ("__RL78_MUL_G14__"); \
42 \
43 if (TARGET_G10) \
44 builtin_define ("__RL78_G10__"); \
45 else if (TARGET_G13) \
46 builtin_define ("__RL78_G13__"); \
47 else if (TARGET_G14) \
48 builtin_define ("__RL78_G14__"); \
49 } \
50 while (0)
51
52 #undef STARTFILE_SPEC
53 #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s"
54
55 #undef ENDFILE_SPEC
56 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
57
58 #undef ASM_SPEC
59 #define ASM_SPEC "\
60 %{mrelax:-relax} \
61 %{mg10:--mg10} \
62 %{mg13:--mg13} \
63 %{mg14:--mg14} \
64 %{mrl78:--mg14} \
65 %{mcpu=g10:--mg10} \
66 %{mcpu=g13:--mg13} \
67 %{mcpu=g14:--mg14} \
68 %{mcpu=rl78:--mg14} \
69 "
70
71 #undef LINK_SPEC
72 #define LINK_SPEC "\
73 %{mrelax:-relax} \
74 %{!r:--gc-sections} \
75 "
76
77 #undef LIB_SPEC
78 #define LIB_SPEC " \
79 --start-group \
80 -lc \
81 -lsim \
82 %{fprofile-arcs|fprofile-generate|coverage:-lgcov} \
83 --end-group \
84 %{!T*: %{msim:%Trl78-sim.ld}%{!msim:%Trl78.ld}} \
85 "
86 \f
87
88 #define BITS_BIG_ENDIAN 0
89 #define BYTES_BIG_ENDIAN 0
90 #define WORDS_BIG_ENDIAN 0
91
92 #ifdef IN_LIBGCC2
93 /* This is to get correct SI and DI modes in libgcc2.c (32 and 64 bits). */
94 #define UNITS_PER_WORD 4
95 /* We have a problem with libgcc2. It only defines two versions of
96 each function, one for "int" and one for "long long". Ie it assumes
97 that "sizeof (int) == sizeof (long)". For the RL78 this is not true
98 and we need a third set of functions. We explicitly define
99 LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
100 to get the SI and DI versions from the libgcc2.c sources, and we
101 provide our own set of HI functions, which is why this
102 definition is surrounded by #ifndef..#endif. */
103 #ifndef LIBGCC2_UNITS_PER_WORD
104 #define LIBGCC2_UNITS_PER_WORD 4
105 #endif
106 #else
107 /* Actual width of a word, in units (bytes). */
108 #define UNITS_PER_WORD 1
109 #endif
110
111 #define SHORT_TYPE_SIZE 16
112 #define INT_TYPE_SIZE 16
113 #define LONG_TYPE_SIZE 32
114 #define LONG_LONG_TYPE_SIZE 64
115
116 #define DEFAULT_SIGNED_CHAR 0
117
118 #define STRICT_ALIGNMENT 1
119 #define FUNCTION_BOUNDARY 8
120 #define BIGGEST_ALIGNMENT 16
121 #define STACK_BOUNDARY 16
122 #define PARM_BOUNDARY 16
123
124 #define STACK_GROWS_DOWNWARD 1
125 #define FRAME_GROWS_DOWNWARD 1
126 #define FIRST_PARM_OFFSET(FNDECL) 0
127
128 #define MAX_REGS_PER_ADDRESS 1
129
130 #define Pmode HImode
131 #define POINTER_SIZE 16
132 #undef SIZE_TYPE
133 #define SIZE_TYPE "unsigned int"
134 #undef PTRDIFF_TYPE
135 #define PTRDIFF_TYPE "int"
136 #undef WCHAR_TYPE
137 #define WCHAR_TYPE "long int"
138 #undef WCHAR_TYPE_SIZE
139 #define WCHAR_TYPE_SIZE BITS_PER_WORD
140 #define POINTERS_EXTEND_UNSIGNED 1
141 #define FUNCTION_MODE HImode
142 #define CASE_VECTOR_MODE Pmode
143 #define WORD_REGISTER_OPERATIONS 1
144 #define HAS_LONG_COND_BRANCH 0
145 #define HAS_LONG_UNCOND_BRANCH 0
146
147 #define MOVE_MAX 2
148
149 #define ADDR_SPACE_NEAR 1
150 #define ADDR_SPACE_FAR 2
151
152 #define HAVE_PRE_DECCREMENT 0
153 #define HAVE_POST_INCREMENT 0
154
155 #define MOVE_RATIO(SPEED) ((SPEED) ? 24 : 16)
156 #define SLOW_BYTE_ACCESS 0
157
158 #define STORE_FLAG_VALUE 1
159 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
160 \f
161
162 /* The RL78 has four register banks. Normal operation uses RB0 as
163 real registers, RB1 and RB2 as "virtual" registers (because we know
164 they'll be there, and not used as variables), and RB3 is reserved
165 for interrupt handlers. The virtual registers are accessed as
166 SADDRs:
167
168 FFEE0-FFEE7 RB0
169 FFEE8-FFEEF RB1
170 FFEF0-FFEF7 RB2
171 FFEF8-FFEFF RB3
172 */
173 #define REGISTER_NAMES \
174 { \
175 "x", "a", "c", "b", "e", "d", "l", "h", \
176 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
177 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
178 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
179 "sp", "ap", "psw", "es", "cs" \
180 }
181
182 #define ADDITIONAL_REGISTER_NAMES \
183 { \
184 { "ax", 0 }, \
185 { "bc", 2 }, \
186 { "de", 4 }, \
187 { "hl", 6 }, \
188 { "rp0", 0 }, \
189 { "rp1", 2 }, \
190 { "rp2", 4 }, \
191 { "rp3", 6 }, \
192 { "r0", 0 }, \
193 { "r1", 1 }, \
194 { "r2", 2 }, \
195 { "r3", 3 }, \
196 { "r4", 4 }, \
197 { "r5", 5 }, \
198 { "r6", 6 }, \
199 { "r7", 7 }, \
200 }
201
202 enum reg_class
203 {
204 NO_REGS, /* No registers in set. */
205 XREG,
206 AREG,
207 AXREG,
208 CREG,
209 BREG,
210 BCREG,
211 EREG,
212 DREG,
213 DEREG,
214 LREG,
215 HREG,
216 HLREG,
217 IDX_REGS,
218 QI_REGS,
219 SPREG,
220 R8W_REGS,
221 R10W_REGS,
222 INT_REGS,
223 V_REGS, /* Virtual registers. */
224 GR_REGS, /* Integer registers. */
225 PSWREG,
226 ALL_REGS, /* All registers. */
227 LIM_REG_CLASSES /* Max value + 1. */
228 };
229
230 #define REG_CLASS_NAMES \
231 { \
232 "NO_REGS", \
233 "XREG", \
234 "AREG", \
235 "AXREG", \
236 "CREG", \
237 "BREG", \
238 "BCREG", \
239 "EREG", \
240 "DREG", \
241 "DEREG", \
242 "LREG", \
243 "HREG", \
244 "HLREG", \
245 "IDX_REGS", \
246 "QI_REGS", \
247 "SPREG", \
248 "R8W_REGS", \
249 "R10W_REGS", \
250 "INT_REGS", \
251 "V_REGS", \
252 "GR_REGS", \
253 "PSWREG", \
254 "ALL_REGS" \
255 }
256
257 /* Note that no class may include the second register in $fp, because
258 we treat $fp as a single HImode register. */
259 #define REG_CLASS_CONTENTS \
260 { \
261 { 0x00000000, 0x00000000 }, /* No registers, */ \
262 { 0x00000001, 0x00000000 }, \
263 { 0x00000002, 0x00000000 }, \
264 { 0x00000003, 0x00000000 }, \
265 { 0x00000004, 0x00000000 }, \
266 { 0x00000008, 0x00000000 }, \
267 { 0x0000000c, 0x00000000 }, \
268 { 0x00000010, 0x00000000 }, \
269 { 0x00000020, 0x00000000 }, \
270 { 0x00000030, 0x00000000 }, \
271 { 0x00000040, 0x00000000 }, \
272 { 0x00000080, 0x00000000 }, \
273 { 0x000000c0, 0x00000000 }, \
274 { 0x0000000c, 0x00000000 }, /* B and C - index regs. */ \
275 { 0x000000ff, 0x00000000 }, /* all real registers. */ \
276 { 0x00000000, 0x00000001 }, /* SP */ \
277 { 0x00000300, 0x00000000 }, /* R8 - HImode */ \
278 { 0x00000c00, 0x00000000 }, /* R10 - HImode */ \
279 { 0xff000000, 0x00000000 }, /* INT - HImode */ \
280 { 0xff7fff00, 0x00000000 }, /* Virtual registers. */ \
281 { 0xff7fff00, 0x00000002 }, /* General registers. */ \
282 { 0x04000000, 0x00000004 }, /* PSW. */ \
283 { 0xff7fffff, 0x0000001f } /* All registers. */ \
284 }
285
286 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
287 #define N_REG_CLASSES (int) LIM_REG_CLASSES
288 #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) \
289 + UNITS_PER_WORD - 1) \
290 / UNITS_PER_WORD)
291
292 #define GENERAL_REGS GR_REGS
293 #define BASE_REG_CLASS V_REGS
294 #define INDEX_REG_CLASS V_REGS
295
296 #define FIRST_PSEUDO_REGISTER 37
297
298 #define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER \
299 ? GR_REGS : NO_REGS)
300
301 #define FRAME_POINTER_REGNUM 22
302 #define STACK_POINTER_REGNUM 32
303 #define ARG_POINTER_REGNUM 33
304 #define CC_REGNUM 34
305 #define FUNC_RETURN_REGNUM 8
306 #define STATIC_CHAIN_REGNUM 14
307
308 /* Trampolines are implemented with a separate data stack. The memory
309 on stack only holds the function pointer for the chosen stub.
310 */
311
312 #define TRAMPOLINE_SIZE 4
313 #define TRAMPOLINE_ALIGNMENT 16
314
315 #define ELIMINABLE_REGS \
316 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
317 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
318 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
319
320 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
321 (OFFSET) = rl78_initial_elimination_offset ((FROM), (TO))
322
323
324 #define FUNCTION_ARG_REGNO_P(N) 0
325 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8)
326 #define DEFAULT_PCC_STRUCT_RETURN 0
327
328 #define FIXED_REGISTERS \
329 { \
330 1,1,1,1, 1,1,1,1, \
331 0,0,0,0, 0,0,0,0, \
332 0,0,0,0, 0,0,1,1, \
333 1,1,1,1, 1,1,1,1, \
334 0, 1, 0, 1, 1 \
335 }
336
337 #define CALL_USED_REGISTERS \
338 { \
339 1,1,1,1, 1,1,1,1, \
340 1,1,1,1, 1,1,1,1, \
341 0,0,0,0, 0,0,1,1, \
342 1,1,1,1, 1,1,1,1, \
343 0, 1, 1, 1, 1 \
344 }
345
346 #define LIBCALL_VALUE(MODE) \
347 gen_rtx_REG ((MODE), \
348 FUNC_RETURN_REGNUM)
349
350 /* Order of allocation of registers. */
351
352 #define REG_ALLOC_ORDER \
353 { 8, 9, 10, 11, 12, 13, 14, 15, \
354 16, 17, 18, 19, 20, 21, 22, 23, \
355 0, 1, 6, 7, 2, 3, 4, 5, \
356 24, 25, 26, 27, 28, 29, 30, 31, \
357 32, 33, 34 \
358 }
359
360 #define REGNO_IN_RANGE(REGNO, MIN, MAX) \
361 (IN_RANGE ((REGNO), (MIN), (MAX)) \
362 || (reg_renumber != NULL \
363 && reg_renumber[(REGNO)] >= (MIN) \
364 && reg_renumber[(REGNO)] <= (MAX)))
365
366 #ifdef REG_OK_STRICT
367 #define REGNO_OK_FOR_BASE_P(regno) REGNO_IN_RANGE (regno, 16, 31)
368 #else
369 #define REGNO_OK_FOR_BASE_P(regno) 1
370 #endif
371
372 #define REGNO_OK_FOR_INDEX_P(regno) REGNO_OK_FOR_BASE_P (regno)
373
374 #define REGNO_MODE_CODE_OK_FOR_BASE_P(regno, mode, address_space, outer_code, index_code) \
375 rl78_regno_mode_code_ok_for_base_p (regno, mode, address_space, outer_code, index_code)
376
377 #define MODE_CODE_BASE_REG_CLASS(mode, address_space, outer_code, index_code) \
378 rl78_mode_code_base_reg_class (mode, address_space, outer_code, index_code)
379
380 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
381 ((COUNT) == 0 \
382 ? gen_rtx_MEM (Pmode, gen_rtx_PLUS (HImode, arg_pointer_rtx, GEN_INT (-4))) \
383 : NULL_RTX)
384
385 #define INCOMING_RETURN_ADDR_RTX gen_rtx_MEM (Pmode, stack_pointer_rtx)
386
387 #define ACCUMULATE_OUTGOING_ARGS 1
388
389 typedef unsigned int CUMULATIVE_ARGS;
390
391 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
392 (CUM) = 0
393
394 \f
395 /* FIXME */
396 #define NO_PROFILE_COUNTERS 1
397 #define PROFILE_BEFORE_PROLOGUE 1
398
399 #define FUNCTION_PROFILER(FILE, LABELNO) \
400 fprintf (FILE, "\tbsr\t__mcount\n");
401 \f
402
403 #define TEXT_SECTION_ASM_OP ".text"
404 #define DATA_SECTION_ASM_OP ".data"
405 #define BSS_SECTION_ASM_OP ".bss"
406 #define CTORS_SECTION_ASM_OP ".section \".ctors\",\"a\""
407 #define DTORS_SECTION_ASM_OP ".section \".dtors\",\"a\""
408
409 #define ASM_COMMENT_START " ;"
410 #define ASM_APP_ON ""
411 #define ASM_APP_OFF ""
412 #define LOCAL_LABEL_PREFIX ".L"
413 #undef USER_LABEL_PREFIX
414 #define USER_LABEL_PREFIX "_"
415
416 #define GLOBAL_ASM_OP "\t.global\t"
417
418 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
419 fprintf (FILE, "\t.long .L%d\n", VALUE)
420
421 /* This is how to output an element of a case-vector that is relative.
422 Note: The local label referenced by the "3b" below is emitted by
423 the tablejump insn. */
424
425 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
426 fprintf (FILE, "\t.long .L%d - 1b\n", VALUE)
427
428
429 #define ASM_OUTPUT_SYMBOL_REF(FILE, SYM) rl78_output_symbol_ref ((FILE), (SYM))
430
431 #define ASM_OUTPUT_LABELREF(FILE, SYM) rl78_output_labelref ((FILE), (SYM))
432
433 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
434 rl78_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
435
436 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
437 rl78_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
438
439 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
440 do \
441 { \
442 if ((LOG) == 0) \
443 break; \
444 fprintf (STREAM, "\t.balign %d\n", 1 << (LOG)); \
445 } \
446 while (0)
447
448 /* For PIC put jump tables into the text section so that the offsets that
449 they contain are always computed between two same-section symbols. */
450 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
451 \f
452 /* This is a version of REG_P that also returns TRUE for SUBREGs. */
453 #define RL78_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
454
455 /* Like REG_P except that this macro is true for SET expressions. */
456 #define SET_P(rtl) (GET_CODE (rtl) == SET)
457 \f
458 #undef PREFERRED_DEBUGGING_TYPE
459 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
460
461 #undef DWARF2_ADDR_SIZE
462 #define DWARF2_ADDR_SIZE 4
463
464 #define DWARF2_ASM_LINE_DEBUG_INFO 1
465
466 #define EXIT_IGNORE_STACK 0
467 #define INCOMING_FRAME_SP_OFFSET 4
468 \f
469
470 #define BRANCH_COST(SPEED,PREDICT) 1
471 #define REGISTER_MOVE_COST(MODE,FROM,TO) 2
472
473 #define EH_RETURN_DATA_REGNO(N) (N < 2 ? (8+(N)*2) : INVALID_REGNUM)
474 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (HImode, 20)
475
476 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) DW_EH_PE_udata4
477
478 /* NOTE: defined but zero means dwarf2 debugging, but sjlj EH. */
479 #define DWARF2_UNWIND_INFO 0
480
481 #define REGISTER_TARGET_PRAGMAS() rl78_register_pragmas()
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