1 /* { dg-require-effective-target vect_int } */
7 #define N (VECTOR_BITS * 2 / 32)
16 unsigned int out
[N
*8];
18 unsigned int in
[N
*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
20 unsigned int in
[N
* 8];
21 for (unsigned int i
= 0; i
< N
* 8; ++i
)
24 asm volatile ("" ::: "memory");
27 unsigned int ia
[N
*2], a0
, a1
, a2
, a3
;
29 /* The last stmt requires interleaving of not power of 2 size - not
31 for (i
= 0; i
< N
/2; i
++)
34 out
[i
*12 + 1] = in
[i
*12 + 1];
35 out
[i
*12 + 2] = in
[i
*12 + 2];
36 out
[i
*12 + 3] = in
[i
*12 + 3];
37 out
[i
*12 + 4] = in
[i
*12 + 4];
38 out
[i
*12 + 5] = in
[i
*12 + 5];
39 out
[i
*12 + 6] = in
[i
*12 + 6];
40 out
[i
*12 + 7] = in
[i
*12 + 7];
41 out
[i
*12 + 8] = in
[i
*12 + 8];
42 out
[i
*12 + 9] = in
[i
*12 + 9];
43 out
[i
*12 + 10] = in
[i
*12 + 10];
44 out
[i
*12 + 11] = in
[i
*12 + 11];
51 for (i
= 0; i
< N
/2; i
++)
53 if (out
[i
*12] != in
[i
*12]
54 || out
[i
*12 + 1] != in
[i
*12 + 1]
55 || out
[i
*12 + 2] != in
[i
*12 + 2]
56 || out
[i
*12 + 3] != in
[i
*12 + 3]
57 || out
[i
*12 + 4] != in
[i
*12 + 4]
58 || out
[i
*12 + 5] != in
[i
*12 + 5]
59 || out
[i
*12 + 6] != in
[i
*12 + 6]
60 || out
[i
*12 + 7] != in
[i
*12 + 7]
61 || out
[i
*12 + 8] != in
[i
*12 + 8]
62 || out
[i
*12 + 9] != in
[i
*12 + 9]
63 || out
[i
*12 + 10] != in
[i
*12 + 10]
64 || out
[i
*12 + 11] != in
[i
*12 + 11]
65 || ia
[i
] != in
[i
*12 + 7])
69 /* Hybrid SLP with unrolling by 2. */
70 for (i
= 0; i
< N
; i
++)
73 out
[i
*6 + 1] = in
[i
*6 + 1];
74 out
[i
*6 + 2] = in
[i
*6 + 2];
75 out
[i
*6 + 3] = in
[i
*6 + 3];
76 out
[i
*6 + 4] = in
[i
*6 + 4];
77 out
[i
*6 + 5] = in
[i
*6 + 5];
84 for (i
= 0; i
< N
/2; i
++)
86 if (out
[i
*6] != in
[i
*6]
87 || out
[i
*6 + 1] != in
[i
*6 + 1]
88 || out
[i
*6 + 2] != in
[i
*6 + 2]
89 || out
[i
*6 + 3] != in
[i
*6 + 3]
90 || out
[i
*6 + 4] != in
[i
*6 + 4]
91 || out
[i
*6 + 5] != in
[i
*6 + 5]
108 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! vect64 } } } } */
109 /* The unsupported interleaving works fine with V2SImode vectors given we
110 can always combine that from two vectors. */
111 /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target vect64 } } } */
112 /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { ! vect64 } } } } */
113 /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 4 "vect" { target vect64 } } } */