gcc/config/aarch64/aarch64-fusion-pairs.def

   1 /* Copyright (C) 2015-2025 Free Software Foundation, Inc.
   2    Contributed by ARM Ltd.
   3
   4    This file is part of GCC.
   5
   6    GCC is free software; you can redistribute it and/or modify it
   7    under the terms of the GNU General Public License as published
   8    by the Free Software Foundation; either version 3, or (at your
   9    option) any later version.
  10
  11    GCC is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GCC; see the file COPYING3.  If not see
  18    <http://www.gnu.org/licenses/>.  */
  19
  20 /* Pairs of instructions which can be fused. before including this file,
  21    define a macro:
  22
  23      AARCH64_FUSION_PAIR (name, internal_name)
  24
  25    Where:
  26
  27      NAME is a string giving a friendly name for the instructions to fuse.
  28      INTERNAL_NAME gives the internal name suitable for appending to
  29      AARCH64_FUSE_ to give an enum name. */
  30
  31 AARCH64_FUSION_PAIR ("mov+movk", MOV_MOVK)
  32 AARCH64_FUSION_PAIR ("adrp+add", ADRP_ADD)
  33 AARCH64_FUSION_PAIR ("movk+movk", MOVK_MOVK)
  34 AARCH64_FUSION_PAIR ("adrp+ldr", ADRP_LDR)
  35 AARCH64_FUSION_PAIR ("cmp+branch", CMP_BRANCH)
  36 AARCH64_FUSION_PAIR ("aes+aesmc", AES_AESMC)
  37 AARCH64_FUSION_PAIR ("alu+branch", ALU_BRANCH)
  38 AARCH64_FUSION_PAIR ("alu+cbz", ALU_CBZ)
  39 AARCH64_FUSION_PAIR ("addsub_2reg_const1", ADDSUB_2REG_CONST1)
  40 AARCH64_FUSION_PAIR ("cmp+csel", CMP_CSEL)
  41 AARCH64_FUSION_PAIR ("cmp+cset", CMP_CSET)
  42
  43 #undef AARCH64_FUSION_PAIR
  44
  45 /* Baseline fusion settings suitable for all cores.  */
  46 #define AARCH64_FUSE_BASE (AARCH64_FUSE_CMP_BRANCH | AARCH64_FUSE_AES_AESMC)
  47
  48 /* Baseline fusion settings suitable for all Neoverse cores.  */
  49 #define AARCH64_FUSE_NEOVERSE_BASE (AARCH64_FUSE_BASE | AARCH64_FUSE_CMP_CSEL \
  50                                     | AARCH64_FUSE_CMP_CSET)
  51
  52 #define AARCH64_FUSE_MOVK (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_MOVK_MOVK)