gcc/config/aarch64/aarch64-opts.h

   1 /* Copyright (C) 2011-2025 Free Software Foundation, Inc.
   2    Contributed by ARM Ltd.
   3
   4    This file is part of GCC.
   5
   6    GCC is free software; you can redistribute it and/or modify it
   7    under the terms of the GNU General Public License as published
   8    by the Free Software Foundation; either version 3, or (at your
   9    option) any later version.
  10
  11    GCC is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GCC; see the file COPYING3.  If not see
  18    <http://www.gnu.org/licenses/>.  */
  19
  20 /* Definitions for option handling for AArch64.  */
  21
  22 #ifndef GCC_AARCH64_OPTS_H
  23 #define GCC_AARCH64_OPTS_H
  24
  25 #ifndef USED_FOR_TARGET
  26 #include "bbitmap.h"
  27
  28 constexpr unsigned int AARCH64_NUM_ABI_ATTRIBUTES = 1;
  29
  30 typedef uint64_t aarch64_isa_mode;
  31
  32 constexpr unsigned int AARCH64_NUM_ISA_MODES = (0
  33 #define DEF_AARCH64_ISA_MODE(IDENT) + 1
  34 #include "aarch64-isa-modes.def"
  35 );
  36
  37 typedef bbitmap<2> aarch64_feature_flags;
  38 #endif
  39
  40 /* The various cores that implement AArch64.  */
  41 enum aarch64_cpu
  42 {
  43 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
  44   AARCH64_CPU_##INTERNAL_IDENT,
  45 #include "aarch64-cores.def"
  46   /* Used to mark the end of the processor table.  */
  47   aarch64_no_cpu
  48 };
  49
  50 enum aarch64_arch
  51 {
  52 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
  53   AARCH64_ARCH_##ARCH_IDENT,
  54 #include "aarch64-arches.def"
  55   aarch64_no_arch
  56 };
  57
  58 /* TLS types.  */
  59 enum aarch64_tls_type {
  60   TLS_TRADITIONAL,
  61   TLS_DESCRIPTORS
  62 };
  63
  64 /* The code model defines the address generation strategy.
  65    Most have a PIC and non-PIC variant.  */
  66 enum aarch64_code_model {
  67   /* Static code and data fit within a 1MB region.
  68      Not fully implemented, mostly treated as SMALL.  */
  69   AARCH64_CMODEL_TINY,
  70   /* Static code, data and GOT/PLT fit within a 1MB region.
  71      Not fully implemented, mostly treated as SMALL_PIC.  */
  72   AARCH64_CMODEL_TINY_PIC,
  73   /* Static code and data fit within a 4GB region.
  74      The default non-PIC code model.  */
  75   AARCH64_CMODEL_SMALL,
  76   /* Static code, data and GOT/PLT fit within a 4GB region.
  77      The default PIC code model.  */
  78   AARCH64_CMODEL_SMALL_PIC,
  79   /* -fpic for small memory model.
  80      GOT size to 28KiB (4K*8-4K) or 3580 entries.  */
  81   AARCH64_CMODEL_SMALL_SPIC,
  82   /* No assumptions about addresses of code and data.
  83      The PIC variant is not yet implemented.  */
  84   AARCH64_CMODEL_LARGE
  85 };
  86
  87 /* The register to use as a thread pointer for TLS accesses.
  88    tpidr_el0 by default, but can be changed through the -mtp option.  */
  89 enum aarch64_tp_reg {
  90   AARCH64_TPIDR_EL0 = 0,
  91   AARCH64_TPIDR_EL1 = 1,
  92   AARCH64_TPIDR_EL2 = 2,
  93   AARCH64_TPIDR_EL3 = 3,
  94   AARCH64_TPIDRRO_EL0 = 4
  95 };
  96
  97 /* SVE vector register sizes.  */
  98 enum aarch64_sve_vector_bits_enum {
  99   SVE_SCALABLE,
 100   SVE_NOT_IMPLEMENTED = SVE_SCALABLE,
 101   SVE_128 = 128,
 102   SVE_256 = 256,
 103   SVE_512 = 512,
 104   SVE_1024 = 1024,
 105   SVE_2048 = 2048
 106 };
 107
 108 /* Where to get the canary for the stack protector.  */
 109 enum stack_protector_guard {
 110   SSP_SYSREG,                   /* per-thread canary in special system register */
 111   SSP_GLOBAL                    /* global canary */
 112 };
 113
 114 /* The key type that -msign-return-address should use.  */
 115 enum aarch64_key_type {
 116   AARCH64_KEY_A,
 117   AARCH64_KEY_B
 118 };
 119
 120 /* An enum for setting the auto-vectorization preference:
 121    - AARCH64_AUTOVEC_DEFAULT: Use default heuristics
 122    - AARCH64_AUTOVEC_ASIMD_ONLY: Use only Advanced SIMD (Neon)
 123    for auto-vectorisation
 124    - AARCH64_AUTOVEC_SVE_ONLY: Use only SVE for auto-vectorisation
 125    - AARCH64_AUTOVEC_PREFER_ASIMD: Use both Neon and SVE,
 126    but prefer Neon when the costs are equal
 127    - AARCH64_AUTOVEC_PREFER_SVE: Use both Neon and SVE,
 128    but prefer SVE when the costs are equal.  */
 129 enum aarch64_autovec_preference_enum {
 130   AARCH64_AUTOVEC_DEFAULT,
 131   AARCH64_AUTOVEC_ASIMD_ONLY,
 132   AARCH64_AUTOVEC_SVE_ONLY,
 133   AARCH64_AUTOVEC_PREFER_ASIMD,
 134   AARCH64_AUTOVEC_PREFER_SVE
 135 };
 136
 137 /* An enum specifying how to handle load and store pairs using
 138    a fine-grained policy:
 139    - LDP_STP_POLICY_DEFAULT: Use the policy defined in the tuning structure.
 140    - LDP_STP_POLICY_ALIGNED: Emit ldp/stp if the source pointer is aligned
 141    to at least double the alignment of the type.
 142    - LDP_STP_POLICY_ALWAYS: Emit ldp/stp regardless of alignment.
 143    - LDP_STP_POLICY_NEVER: Do not emit ldp/stp.  */
 144 enum aarch64_ldp_stp_policy {
 145   AARCH64_LDP_STP_POLICY_DEFAULT,
 146   AARCH64_LDP_STP_POLICY_ALIGNED,
 147   AARCH64_LDP_STP_POLICY_ALWAYS,
 148   AARCH64_LDP_STP_POLICY_NEVER
 149 };
 150
 151 /* An enum specifying when the early-ra pass should be run:
 152    - AARCH64_EARLY_RA_ALL: for all functions
 153    - AARCH64_EARLY_RA_STRIDED: for functions that have access to strided
 154      multi-register instructions
 155    - AARCH64_EARLY_RA_NONE: for no functions.  */
 156 enum aarch64_early_ra_scope {
 157   AARCH64_EARLY_RA_ALL,
 158   AARCH64_EARLY_RA_STRIDED,
 159   AARCH64_EARLY_RA_NONE
 160 };
 161
 162 #endif