gcc/config/aarch64/aarch64-tuning-flags.def

   1 /* Copyright (C) 2015-2025 Free Software Foundation, Inc.
   2    Contributed by ARM Ltd.
   3
   4    This file is part of GCC.
   5
   6    GCC is free software; you can redistribute it and/or modify it
   7    under the terms of the GNU General Public License as published
   8    by the Free Software Foundation; either version 3, or (at your
   9    option) any later version.
  10
  11    GCC is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GCC; see the file COPYING3.  If not see
  18    <http://www.gnu.org/licenses/>.  */
  19
  20 /* Additional control over certain tuning parameters.  Before including
  21    this file, define a macro:
  22
  23      AARCH64_EXTRA_TUNING_OPTION (name, internal_name)
  24
  25    Where:
  26
  27      NAME is a string giving a friendly name for the tuning flag.
  28      INTERNAL_NAME gives the internal name suitable for appending to
  29      AARCH64_TUNE_ to give an enum name. */
  30
  31 AARCH64_EXTRA_TUNING_OPTION ("rename_fma_regs", RENAME_FMA_REGS)
  32
  33 /* Some of the optional shift to some arthematic instructions are
  34    considered cheap.  Logical shift left <=4 with or without a
  35    zero extend are considered cheap.  Sign extend; non logical shift left
  36    are not considered cheap.  */
  37 AARCH64_EXTRA_TUNING_OPTION ("cheap_shift_extend", CHEAP_SHIFT_EXTEND)
  38
  39 AARCH64_EXTRA_TUNING_OPTION ("cse_sve_vl_constants", CSE_SVE_VL_CONSTANTS)
  40
  41 AARCH64_EXTRA_TUNING_OPTION ("matched_vector_throughput", MATCHED_VECTOR_THROUGHPUT)
  42
  43 AARCH64_EXTRA_TUNING_OPTION ("avoid_cross_loop_fma", AVOID_CROSS_LOOP_FMA)
  44
  45 AARCH64_EXTRA_TUNING_OPTION ("fully_pipelined_fma", FULLY_PIPELINED_FMA)
  46
  47 /* Enable is the target prefers to use a fresh register for predicate outputs
  48    rather than re-use an input predicate register.  */
  49 AARCH64_EXTRA_TUNING_OPTION ("avoid_pred_rmw", AVOID_PRED_RMW)
  50
  51 /* Whether writes to the FPMR are cheap enough that:
  52
  53        msr     fpmr, <value>
  54
  55    is better than:
  56
  57        mrs     tmp, fpmr
  58        cmp     tmp, <value>
  59        beq     1f
  60        msr     fpmr, <value>
  61      1:
  62
  63    even when the branch is predictably taken.  */
  64 AARCH64_EXTRA_TUNING_OPTION ("cheap_fpmr_write", CHEAP_FPMR_WRITE)
  65
  66 /* Baseline tuning settings suitable for all modern cores.  */
  67 #define AARCH64_EXTRA_TUNE_BASE (AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND  \
  68                                  | AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA)
  69
  70 #undef AARCH64_EXTRA_TUNING_OPTION