1 /* Tuning model description for AArch64 architecture.
2 Copyright (C) 2009-2025 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 #ifndef GCC_AARCH64_H_EXYNOSM1
21 #define GCC_AARCH64_H_EXYNOSM1
25 static const struct cpu_addrcost_table exynosm1_addrcost_table
=
35 0, /* post_modify_ld3_st3 */
36 0, /* post_modify_ld4_st4 */
37 1, /* register_offset */
38 1, /* register_sextend */
39 2, /* register_zextend */
43 static const struct cpu_regmove_cost exynosm1_regmove_cost
=
46 /* Avoid the use of slow int<->fp moves for spilling by setting
47 their cost higher than memmov_cost (actual, 4 and 9). */
53 static const advsimd_vec_cost exynosm1_advsimd_vector_cost
=
55 3, /* int_stmt_cost */
57 0, /* ld2_st2_permute_cost */
58 0, /* ld3_st3_permute_cost */
59 0, /* ld4_st4_permute_cost */
61 3, /* reduc_i8_cost */
62 3, /* reduc_i16_cost */
63 3, /* reduc_i32_cost */
64 3, /* reduc_i64_cost */
65 3, /* reduc_f16_cost */
66 3, /* reduc_f32_cost */
67 3, /* reduc_f64_cost */
68 3, /* store_elt_extra_cost */
69 3, /* vec_to_scalar_cost */
70 3, /* scalar_to_vec_cost */
71 5, /* align_load_cost */
72 5, /* unalign_load_cost */
73 1, /* unalign_store_cost */
77 static const struct cpu_vector_cost exynosm1_vector_cost
=
79 1, /* scalar_int_stmt_cost */
80 1, /* scalar_fp_stmt_cost */
81 5, /* scalar_load_cost */
82 1, /* scalar_store_cost */
83 1, /* cond_taken_branch_cost */
84 1, /* cond_not_taken_branch_cost */
85 &exynosm1_advsimd_vector_cost
, /* advsimd */
87 nullptr /* issue_info */
90 /* Approximation modes for Exynos M1. */
91 static const cpu_approx_modes exynosm1_approx_modes
=
93 AARCH64_APPROX_NONE
, /* division */
94 AARCH64_APPROX_ALL
, /* sqrt */
95 AARCH64_APPROX_ALL
/* recip_sqrt */
98 static const cpu_prefetch_tune exynosm1_prefetch_tune
=
101 -1, /* l1_cache_size */
102 64, /* l1_cache_line_size */
103 -1, /* l2_cache_size */
104 true, /* prefetch_dynamic_strides */
105 -1, /* minimum_stride */
106 -1 /* default_opt_level */
109 static const struct tune_params exynosm1_tunings
=
111 &exynosm1_extra_costs
,
112 &exynosm1_addrcost_table
,
113 &exynosm1_regmove_cost
,
114 &exynosm1_vector_cost
,
115 &generic_branch_cost
,
116 &exynosm1_approx_modes
,
117 SVE_NOT_IMPLEMENTED
, /* sve_width */
124 }, /* memmov_cost. */
126 AARCH64_FUSE_BASE
, /* fusible_ops */
127 "4", /* function_align. */
128 "4", /* jump_align. */
129 "4", /* loop_align. */
130 2, /* int_reassoc_width. */
131 4, /* fp_reassoc_width. */
132 1, /* fma_reassoc_width. */
133 1, /* vec_reassoc_width. */
134 2, /* min_div_recip_mul_sf. */
135 2, /* min_div_recip_mul_df. */
136 48, /* max_case_values. */
137 tune_params::AUTOPREFETCHER_WEAK
, /* autoprefetcher_model. */
138 (AARCH64_EXTRA_TUNE_NONE
), /* tune_flags. */
139 &exynosm1_prefetch_tune
,
140 AARCH64_LDP_STP_POLICY_ALWAYS
, /* ldp_policy_model. */
141 AARCH64_LDP_STP_POLICY_ALWAYS
/* stp_policy_model. */
144 #endif /* GCC_AARCH64_H_EXYNOSM1. */