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[PR testsuite/116860] Testsuite adjustment for recently added tests
[official-gcc.git] / gcc / config / ia64 / ia64.h
blob5763daeaebb778d276526ee2dcacd874b6c58c44
1 /* Definitions of target machine GNU compiler. IA-64 version.
2 Copyright (C) 1999-2025 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 /* ??? Look at ABI group documents for list of preprocessor macros and
23 other features required for ABI compliance. */
24
25 /* ??? Functions containing a non-local goto target save many registers. Why?
26 See for instance execute/920428-2.c. */
27
28 \f
29 /* Run-time target specifications */
30
31 /* Target CPU builtins. */
32 #define TARGET_CPU_CPP_BUILTINS() \
33 do { \
34 builtin_assert("cpu=ia64"); \
35 builtin_assert("machine=ia64"); \
36 builtin_define("__ia64"); \
37 builtin_define("__ia64__"); \
38 builtin_define("__itanium__"); \
39 if (TARGET_BIG_ENDIAN) \
40 builtin_define("__BIG_ENDIAN__"); \
41 builtin_define("__SIZEOF_FPREG__=16"); \
42 builtin_define("__SIZEOF_FLOAT80__=16");\
43 builtin_define("__SIZEOF_FLOAT128__=16");\
44 } while (0)
45
46 #ifndef SUBTARGET_EXTRA_SPECS
47 #define SUBTARGET_EXTRA_SPECS
48 #endif
49
50 #define EXTRA_SPECS \
51 { "asm_extra", ASM_EXTRA_SPEC }, \
52 SUBTARGET_EXTRA_SPECS
53
54 #define CC1_SPEC "%(cc1_cpu) "
55
56 #define ASM_EXTRA_SPEC ""
57
58 /* Variables which are this size or smaller are put in the sdata/sbss
59 sections. */
60 extern unsigned int ia64_section_threshold;
61
62 /* If the assembler supports thread-local storage, assume that the
63 system does as well. If a particular target system has an
64 assembler that supports TLS -- but the rest of the system does not
65 support TLS -- that system should explicit define TARGET_HAVE_TLS
66 to false in its own configuration file. */
67 #if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS)
68 #define TARGET_HAVE_TLS true
69 #endif
70
71 #define TARGET_TLS14 (ia64_tls_size == 14)
72 #define TARGET_TLS22 (ia64_tls_size == 22)
73 #define TARGET_TLS64 (ia64_tls_size == 64)
74
75 #define TARGET_HPUX 0
76 #define TARGET_HPUX_LD 0
77
78 #define TARGET_ABI_OPEN_VMS 0
79
80 #ifndef TARGET_ILP32
81 #define TARGET_ILP32 0
82 #endif
83
84 #ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS
85 #define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0
86 #endif
87
88 /* Values for TARGET_INLINE_FLOAT_DIV, TARGET_INLINE_INT_DIV, and
89 TARGET_INLINE_SQRT. */
90
91 enum ia64_inline_type
92 {
93 INL_NO = 0,
94 INL_MIN_LAT = 1,
95 INL_MAX_THR = 2
96 };
97
98 /* Default target_flags if no switches are specified */
99
100 #ifndef TARGET_DEFAULT
101 #define TARGET_DEFAULT (MASK_DWARF2_ASM)
102 #endif
103
104 #ifndef TARGET_CPU_DEFAULT
105 #define TARGET_CPU_DEFAULT 0
106 #endif
107 \f
108 /* Driver configuration */
109
110 /* A C string constant that tells the GCC driver program options to pass to
111 `cc1'. It can also specify how to translate options you give to GCC into
112 options for GCC to pass to the `cc1'. */
113
114 #undef CC1_SPEC
115 #define CC1_SPEC "%{G*}"
116
117 /* A C string constant that tells the GCC driver program options to pass to
118 `cc1plus'. It can also specify how to translate options you give to GCC
119 into options for GCC to pass to the `cc1plus'. */
120
121 /* #define CC1PLUS_SPEC "" */
122 \f
123 /* Storage Layout */
124
125 /* Define this macro to have the value 1 if the most significant bit in a byte
126 has the lowest number; otherwise define it to have the value zero. */
127
128 #define BITS_BIG_ENDIAN 0
129
130 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
131
132 /* Define this macro to have the value 1 if, in a multiword object, the most
133 significant word has the lowest number. */
134
135 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
136
137 #define UNITS_PER_WORD 8
138
139 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
140
141 /* A C expression whose value is zero if pointers that need to be extended
142 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
143 they are zero-extended and negative one if there is a ptr_extend operation.
144
145 You need not define this macro if the `POINTER_SIZE' is equal to the width
146 of `Pmode'. */
147 /* Need this for 32-bit pointers, see hpux.h for setting it. */
148 /* #define POINTERS_EXTEND_UNSIGNED */
149
150 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
151 which has the specified mode and signedness is to be stored in a register.
152 This macro is only called when TYPE is a scalar type. */
153 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
154 do \
155 { \
156 if (GET_MODE_CLASS (MODE) == MODE_INT \
157 && GET_MODE_SIZE (MODE) < 4) \
158 (MODE) = SImode; \
159 } \
160 while (0)
161
162 #define PARM_BOUNDARY 64
163
164 /* Define this macro if you wish to preserve a certain alignment for the stack
165 pointer. The definition is a C expression for the desired alignment
166 (measured in bits). */
167
168 #define STACK_BOUNDARY 128
169
170 /* Align frames on double word boundaries */
171 #ifndef IA64_STACK_ALIGN
172 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
173 #endif
174
175 #define FUNCTION_BOUNDARY 128
176
177 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word
178 128-bit integers all require 128-bit alignment. */
179 #define BIGGEST_ALIGNMENT 128
180
181 /* If defined, a C expression to compute the alignment for a static variable.
182 TYPE is the data type, and ALIGN is the alignment that the object
183 would ordinarily have. The value of this macro is used instead of that
184 alignment to align the object. */
185
186 #define DATA_ALIGNMENT(TYPE, ALIGN) \
187 (TREE_CODE (TYPE) == ARRAY_TYPE \
188 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
189 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
190
191 #define STRICT_ALIGNMENT 1
192
193 /* Define this if you wish to imitate the way many other C compilers handle
194 alignment of bitfields and the structures that contain them.
195 The behavior is that the type written for a bit-field (`int', `short', or
196 other integer type) imposes an alignment for the entire structure, as if the
197 structure really did contain an ordinary field of that type. In addition,
198 the bit-field is placed within the structure so that it would fit within such
199 a field, not crossing a boundary for it. */
200 #define PCC_BITFIELD_TYPE_MATTERS 1
201
202 /* An integer expression for the size in bits of the largest integer machine
203 mode that should actually be used. */
204
205 /* Allow pairs of registers to be used, which is the intent of the default. */
206 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
207
208 /* By default, the C++ compiler will use function addresses in the
209 vtable entries. Setting this nonzero tells the compiler to use
210 function descriptors instead. The value of this macro says how
211 many words wide the descriptor is (normally 2). It is assumed
212 that the address of a function descriptor may be treated as a
213 pointer to a function.
214
215 For reasons known only to HP, the vtable entries (as opposed to
216 normal function descriptors) are 16 bytes wide in 32-bit mode as
217 well, even though the 3rd and 4th words are unused. */
218 #define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2)
219
220 /* Due to silliness in the HPUX linker, vtable entries must be
221 8-byte aligned even in 32-bit mode. Rather than create multiple
222 ABIs, force this restriction on everyone else too. */
223 #define TARGET_VTABLE_ENTRY_ALIGN 64
224
225 /* Due to the above, we need extra padding for the data entries below 0
226 to retain the alignment of the descriptors. */
227 #define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1)
228 \f
229 /* Layout of Source Language Data Types */
230
231 #define INT_TYPE_SIZE 32
232
233 #define SHORT_TYPE_SIZE 16
234
235 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
236
237 #define LONG_LONG_TYPE_SIZE 64
238
239 #define DEFAULT_SIGNED_CHAR 1
240
241 /* A C expression for a string describing the name of the data type to use for
242 size values. The typedef name `size_t' is defined using the contents of the
243 string. */
244 /* ??? Needs to be defined for P64 code. */
245 /* #define SIZE_TYPE */
246
247 /* A C expression for a string describing the name of the data type to use for
248 the result of subtracting two pointers. The typedef name `ptrdiff_t' is
249 defined using the contents of the string. See `SIZE_TYPE' above for more
250 information. */
251 /* ??? Needs to be defined for P64 code. */
252 /* #define PTRDIFF_TYPE */
253
254 /* A C expression for a string describing the name of the data type to use for
255 wide characters. The typedef name `wchar_t' is defined using the contents
256 of the string. See `SIZE_TYPE' above for more information. */
257 /* #define WCHAR_TYPE */
258
259 /* A C expression for the size in bits of the data type for wide characters.
260 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */
261 /* #define WCHAR_TYPE_SIZE */
262
263 \f
264 /* Register Basics */
265
266 /* Number of hardware registers known to the compiler.
267 We have 128 general registers, 128 floating point registers,
268 64 predicate registers, 8 branch registers, one frame pointer,
269 and several "application" registers. */
270
271 #define FIRST_PSEUDO_REGISTER 334
272
273 /* Ranges for the various kinds of registers. */
274 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
275 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
276 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
277 #define FP_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 254 && (REGNO) != 159)
278 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
279 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
280 #define GENERAL_REGNO_P(REGNO) \
281 (GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM)
282
283 #define GR_REG(REGNO) ((REGNO) + 0)
284 #define FR_REG(REGNO) ((REGNO) + 128)
285 #define PR_REG(REGNO) ((REGNO) + 256)
286 #define BR_REG(REGNO) ((REGNO) + 320)
287 #define OUT_REG(REGNO) ((REGNO) + 120)
288 #define IN_REG(REGNO) ((REGNO) + 112)
289 #define LOC_REG(REGNO) ((REGNO) + 32)
290
291 #define AR_CCV_REGNUM 329
292 #define AR_UNAT_REGNUM 330
293 #define AR_PFS_REGNUM 331
294 #define AR_LC_REGNUM 332
295 #define AR_EC_REGNUM 333
296
297 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
298 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
299 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
300
301 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
302 || (REGNO) == AR_UNAT_REGNUM)
303 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
304 && (REGNO) < FIRST_PSEUDO_REGISTER)
305 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
306 && (REGNO) < FIRST_PSEUDO_REGISTER)
307
308
309 /* ??? Don't really need two sets of macros. I like this one better because
310 it is less typing. */
311 #define R_GR(REGNO) GR_REG (REGNO)
312 #define R_FR(REGNO) FR_REG (REGNO)
313 #define R_PR(REGNO) PR_REG (REGNO)
314 #define R_BR(REGNO) BR_REG (REGNO)
315
316 /* An initializer that says which registers are used for fixed purposes all
317 throughout the compiled code and are therefore not available for general
318 allocation.
319
320 r0: constant 0
321 r1: global pointer (gp)
322 r12: stack pointer (sp)
323 r13: thread pointer (tp)
324 f0: constant 0.0
325 f1: constant 1.0
326 p0: constant true
327 fp: eliminable frame pointer */
328
329 /* The last 16 stacked regs are reserved for the 8 input and 8 output
330 registers. */
331
332 #define FIXED_REGISTERS \
333 { /* General registers. */ \
334 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
335 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
336 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
337 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
338 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
339 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
340 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
341 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
342 /* Floating-point registers. */ \
343 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
344 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
345 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
346 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
347 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
348 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
349 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
350 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
351 /* Predicate registers. */ \
352 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
353 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
354 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
355 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
356 /* Branch registers. */ \
357 0, 0, 0, 0, 0, 0, 0, 0, \
358 /*FP CCV UNAT PFS LC EC */ \
359 1, 1, 1, 1, 1, 1 \
360 }
361
362 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
363 problem which makes CALL_USED_REGISTERS *always* include
364 all the FIXED_REGISTERS. Until this problem has been
365 resolved this macro can be used to overcome this situation.
366 In particular, block_propagate() requires this list
367 be accurate, or we can remove registers which should be live.
368 This macro is used in regs_invalidated_by_call. */
369
370 #define CALL_REALLY_USED_REGISTERS \
371 { /* General registers. */ \
372 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, \
373 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
374 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
375 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
376 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
377 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
378 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
379 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
380 /* Floating-point registers. */ \
381 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
382 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
383 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
384 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
385 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
386 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
387 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
388 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
389 /* Predicate registers. */ \
390 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
391 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
392 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
393 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
394 /* Branch registers. */ \
395 1, 0, 0, 0, 0, 0, 1, 1, \
396 /*FP CCV UNAT PFS LC EC */ \
397 0, 1, 0, 1, 0, 0 \
398 }
399
400
401 /* Define this macro if the target machine has register windows. This C
402 expression returns the register number as seen by the called function
403 corresponding to the register number OUT as seen by the calling function.
404 Return OUT if register number OUT is not an outbound register. */
405
406 #define INCOMING_REGNO(OUT) \
407 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT))
408
409 /* Define this macro if the target machine has register windows. This C
410 expression returns the register number as seen by the calling function
411 corresponding to the register number IN as seen by the called function.
412 Return IN if register number IN is not an inbound register. */
413
414 #define OUTGOING_REGNO(IN) \
415 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN))
416
417 /* Define this macro if the target machine has register windows. This
418 C expression returns true if the register is call-saved but is in the
419 register window. */
420
421 #define LOCAL_REGNO(REGNO) \
422 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
423
424 /* We define CCImode in ia64-modes.def so we need a selector. */
425
426 #define SELECT_CC_MODE(OP,X,Y) CCmode
427 \f
428 /* Order of allocation of registers */
429
430 /* If defined, an initializer for a vector of integers, containing the numbers
431 of hard registers in the order in which GCC should prefer to use them
432 (from most preferred to least).
433
434 If this macro is not defined, registers are used lowest numbered first (all
435 else being equal).
436
437 One use of this macro is on machines where the highest numbered registers
438 must always be saved and the save-multiple-registers instruction supports
439 only sequences of consecutive registers. On such machines, define
440 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
441 allocatable register first. */
442
443 /* ??? Should the GR return value registers come before or after the rest
444 of the caller-save GRs? */
445
446 #define REG_ALLOC_ORDER \
447 { \
448 /* Caller-saved general registers. */ \
449 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \
450 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \
451 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \
452 R_GR (30), R_GR (31), \
453 /* Output registers. */ \
454 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \
455 R_GR (126), R_GR (127), \
456 /* Caller-saved general registers, also used for return values. */ \
457 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \
458 /* addl caller-saved general registers. */ \
459 R_GR (2), R_GR (3), \
460 /* Caller-saved FP registers. */ \
461 R_FR (6), R_FR (7), \
462 /* Caller-saved FP registers, used for parameters and return values. */ \
463 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \
464 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \
465 /* Rotating caller-saved FP registers. */ \
466 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \
467 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \
468 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \
469 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \
470 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \
471 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \
472 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \
473 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \
474 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \
475 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \
476 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \
477 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \
478 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \
479 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \
480 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \
481 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \
482 R_FR (126), R_FR (127), \
483 /* Caller-saved predicate registers. */ \
484 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \
485 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \
486 /* Rotating caller-saved predicate registers. */ \
487 R_PR (16), R_PR (17), \
488 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \
489 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \
490 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \
491 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \
492 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \
493 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \
494 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \
495 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \
496 /* Caller-saved branch registers. */ \
497 R_BR (6), R_BR (7), \
498 \
499 /* Stacked callee-saved general registers. */ \
500 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \
501 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \
502 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \
503 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \
504 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \
505 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \
506 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \
507 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \
508 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \
509 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \
510 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \
511 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \
512 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \
513 R_GR (108), \
514 /* Input registers. */ \
515 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \
516 R_GR (118), R_GR (119), \
517 /* Callee-saved general registers. */ \
518 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \
519 /* Callee-saved FP registers. */ \
520 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \
521 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \
522 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \
523 R_FR (30), R_FR (31), \
524 /* Callee-saved predicate registers. */ \
525 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \
526 /* Callee-saved branch registers. */ \
527 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \
528 \
529 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \
530 R_GR (109), R_GR (110), R_GR (111), \
531 \
532 /* Special general registers. */ \
533 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \
534 /* Special FP registers. */ \
535 R_FR (0), R_FR (1), \
536 /* Special predicate registers. */ \
537 R_PR (0), \
538 /* Special branch registers. */ \
539 R_BR (0), \
540 /* Other fixed registers. */ \
541 FRAME_POINTER_REGNUM, \
542 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
543 AR_EC_REGNUM \
544 }
545 \f
546 /* How Values Fit in Registers */
547
548 /* Specify the modes required to caller save a given hard regno.
549 We need to ensure floating pt regs are not saved as DImode. */
550
551 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
552 ((FR_REGNO_P (REGNO) && (NREGS) == 1) ? RFmode \
553 : choose_hard_reg_mode ((REGNO), (NREGS), NULL))
554 \f
555 /* Handling Leaf Functions */
556
557 /* A C initializer for a vector, indexed by hard register number, which
558 contains 1 for a register that is allowable in a candidate for leaf function
559 treatment. */
560 /* ??? This might be useful. */
561 /* #define LEAF_REGISTERS */
562
563 /* A C expression whose value is the register number to which REGNO should be
564 renumbered, when a function is treated as a leaf function. */
565 /* ??? This might be useful. */
566 /* #define LEAF_REG_REMAP(REGNO) */
567
568 \f
569 /* Register Classes */
570
571 /* An enumeral type that must be defined with all the register class names as
572 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
573 register class, followed by one more enumeral value, `LIM_REG_CLASSES',
574 which is not a register class but rather tells how many classes there
575 are. */
576 /* ??? When compiling without optimization, it is possible for the only use of
577 a pseudo to be a parameter load from the stack with a REG_EQUIV note.
578 Regclass handles this case specially and does not assign any costs to the
579 pseudo. The pseudo then ends up using the last class before ALL_REGS.
580 Thus we must not let either PR_REGS or BR_REGS be the last class. The
581 testcase for this is gcc.c-torture/execute/va-arg-7.c. */
582 enum reg_class
583 {
584 NO_REGS,
585 PR_REGS,
586 BR_REGS,
587 AR_M_REGS,
588 AR_I_REGS,
589 ADDL_REGS,
590 GR_REGS,
591 FP_REGS,
592 FR_REGS,
593 GR_AND_BR_REGS,
594 GR_AND_FR_REGS,
595 ALL_REGS,
596 LIM_REG_CLASSES
597 };
598
599 #define GENERAL_REGS GR_REGS
600
601 /* The number of distinct register classes. */
602 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
603
604 /* An initializer containing the names of the register classes as C string
605 constants. These names are used in writing some of the debugging dumps. */
606 #define REG_CLASS_NAMES \
607 { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
608 "ADDL_REGS", "GR_REGS", "FP_REGS", "FR_REGS", \
609 "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
610
611 /* An initializer containing the contents of the register classes, as integers
612 which are bit masks. The Nth integer specifies the contents of class N.
613 The way the integer MASK is interpreted is that register R is in the class
614 if `MASK & (1 << R)' is 1. */
615 #define REG_CLASS_CONTENTS \
616 { \
617 /* NO_REGS. */ \
618 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
619 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
620 0x00000000, 0x00000000, 0x0000 }, \
621 /* PR_REGS. */ \
622 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
623 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
624 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \
625 /* BR_REGS. */ \
626 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
627 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
628 0x00000000, 0x00000000, 0x00FF }, \
629 /* AR_M_REGS. */ \
630 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
631 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
632 0x00000000, 0x00000000, 0x0600 }, \
633 /* AR_I_REGS. */ \
634 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
635 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
636 0x00000000, 0x00000000, 0x3800 }, \
637 /* ADDL_REGS. */ \
638 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
639 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
640 0x00000000, 0x00000000, 0x0000 }, \
641 /* GR_REGS. */ \
642 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
643 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
644 0x00000000, 0x00000000, 0x0100 }, \
645 /* FP_REGS. */ \
646 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
647 0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF, \
648 0x00000000, 0x00000000, 0x0000 }, \
649 /* FR_REGS. */ \
650 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
651 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
652 0x00000000, 0x00000000, 0x0000 }, \
653 /* GR_AND_BR_REGS. */ \
654 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
655 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
656 0x00000000, 0x00000000, 0x01FF }, \
657 /* GR_AND_FR_REGS. */ \
658 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
659 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
660 0x00000000, 0x00000000, 0x0100 }, \
661 /* ALL_REGS. */ \
662 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
663 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
664 0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \
665 }
666
667 /* A C expression whose value is a register class containing hard register
668 REGNO. In general there is more than one such class; choose a class which
669 is "minimal", meaning that no smaller class also contains the register. */
670 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which
671 may call here with private (invalid) register numbers, such as
672 REG_VOLATILE. */
673 #define REGNO_REG_CLASS(REGNO) \
674 (ADDL_REGNO_P (REGNO) ? ADDL_REGS \
675 : GENERAL_REGNO_P (REGNO) ? GR_REGS \
676 : FR_REGNO_P (REGNO) ? (REGNO) != R_FR (31) \
677 && (REGNO) != R_FR(127) ? FP_REGS : FR_REGS \
678 : PR_REGNO_P (REGNO) ? PR_REGS \
679 : BR_REGNO_P (REGNO) ? BR_REGS \
680 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \
681 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \
682 : NO_REGS)
683
684 /* A macro whose definition is the name of the class to which a valid base
685 register must belong. A base register is one used in an address which is
686 the register value plus a displacement. */
687 #define BASE_REG_CLASS GENERAL_REGS
688
689 /* A macro whose definition is the name of the class to which a valid index
690 register must belong. An index register is one used in an address where its
691 value is either multiplied by a scale factor or added to another register
692 (as well as added to a displacement). This is needed for POST_MODIFY. */
693 #define INDEX_REG_CLASS GENERAL_REGS
694
695 /* A C expression which is nonzero if register number NUM is suitable for use
696 as a base register in operand addresses. It may be either a suitable hard
697 register or a pseudo register that has been allocated such a hard reg. */
698 #define REGNO_OK_FOR_BASE_P(REGNO) \
699 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))
700
701 /* A C expression which is nonzero if register number NUM is suitable for use
702 as an index register in operand addresses. It may be either a suitable hard
703 register or a pseudo register that has been allocated such a hard reg.
704 This is needed for POST_MODIFY. */
705 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
706
707 /* You should define this macro to indicate to the reload phase that it may
708 need to allocate at least one register for a reload in addition to the
709 register to contain the data. Specifically, if copying X to a register
710 CLASS in MODE requires an intermediate register, you should define this
711 to return the largest register class all of whose registers can be used
712 as intermediate registers or scratch registers. */
713
714 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
715 ia64_secondary_reload_class (CLASS, MODE, X)
716
717 /* A C expression for the maximum number of consecutive registers of
718 class CLASS needed to hold a value of mode MODE.
719 This is closely related to TARGET_HARD_REGNO_NREGS. */
720
721 #define CLASS_MAX_NREGS(CLASS, MODE) \
722 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
723 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XFmode) ? 1 \
724 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == RFmode) ? 1 \
725 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XCmode) ? 2 \
726 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
727 \f
728 /* Basic Stack Layout */
729
730 /* Define this macro if pushing a word onto the stack moves the stack pointer
731 to a smaller address. */
732 #define STACK_GROWS_DOWNWARD 1
733
734 /* Define this macro to nonzero if the addresses of local variable slots
735 are at negative offsets from the frame pointer. */
736 #define FRAME_GROWS_DOWNWARD 0
737
738 /* Offset from the stack pointer register to the first location at which
739 outgoing arguments are placed. If not specified, the default value of zero
740 is used. This is the proper value for most machines. */
741 /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */
742 #define STACK_POINTER_OFFSET 16
743
744 /* Offset from the argument pointer register to the first argument's address.
745 On some machines it may depend on the data type of the function. */
746 #define FIRST_PARM_OFFSET(FUNDECL) 0
747
748 /* A C expression whose value is RTL representing the value of the return
749 address for the frame COUNT steps up from the current frame, after the
750 prologue. */
751
752 /* ??? Frames other than zero would likely require interpreting the frame
753 unwind info, so we don't try to support them. We would also need to define
754 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */
755
756 #define RETURN_ADDR_RTX(COUNT, FRAME) \
757 ia64_return_addr_rtx (COUNT, FRAME)
758
759 /* A C expression whose value is RTL representing the location of the incoming
760 return address at the beginning of any function, before the prologue. This
761 RTL is either a `REG', indicating that the return value is saved in `REG',
762 or a `MEM' representing a location in the stack. This enables DWARF2
763 unwind info for C++ EH. */
764 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, BR_REG (0))
765
766 /* A C expression whose value is an integer giving the offset, in bytes, from
767 the value of the stack pointer register to the top of the stack frame at the
768 beginning of any function, before the prologue. The top of the frame is
769 defined to be the value of the stack pointer in the previous frame, just
770 before the call instruction. */
771 /* The CFA is past the red zone, not at the entry-point stack
772 pointer. */
773 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
774
775 /* We shorten debug info by using CFA-16 as DW_AT_frame_base. */
776 #define CFA_FRAME_BASE_OFFSET(FUNDECL) (-INCOMING_FRAME_SP_OFFSET)
777
778 \f
779 /* Register That Address the Stack Frame. */
780
781 /* The register number of the stack pointer register, which must also be a
782 fixed register according to `FIXED_REGISTERS'. On most machines, the
783 hardware determines which register this is. */
784
785 #define STACK_POINTER_REGNUM 12
786
787 /* The register number of the frame pointer register, which is used to access
788 automatic variables in the stack frame. On some machines, the hardware
789 determines which register this is. On other machines, you can choose any
790 register you wish for this purpose. */
791
792 #define FRAME_POINTER_REGNUM 328
793
794 /* Base register for access to local variables of the function. */
795 #define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
796
797 /* The register number of the arg pointer register, which is used to access the
798 function's argument list. */
799 /* r0 won't otherwise be used, so put the always eliminated argument pointer
800 in it. */
801 #define ARG_POINTER_REGNUM R_GR(0)
802
803 /* Due to the way varargs and argument spilling happens, the argument
804 pointer is not 16-byte aligned like the stack pointer. */
805 #define INIT_EXPANDERS \
806 do { \
807 ia64_init_expanders (); \
808 if (crtl->emit.regno_pointer_align) \
809 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \
810 } while (0)
811
812 /* Register numbers used for passing a function's static chain pointer. */
813 /* ??? The ABI sez the static chain should be passed as a normal parameter. */
814 #define STATIC_CHAIN_REGNUM 15
815 \f
816 /* Eliminating the Frame Pointer and the Arg Pointer */
817
818 /* If defined, this macro specifies a table of register pairs used to eliminate
819 unneeded registers that point into the stack frame. */
820
821 #define ELIMINABLE_REGS \
822 { \
823 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
824 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
825 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
826 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
827 }
828
829 /* This macro returns the initial difference between the specified pair
830 of registers. */
831 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
832 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
833 \f
834 /* Passing Function Arguments on the Stack */
835
836 /* If defined, the maximum amount of space required for outgoing arguments will
837 be computed and placed into the variable
838 `crtl->outgoing_args_size'. */
839
840 #define ACCUMULATE_OUTGOING_ARGS 1
841
842 \f
843 /* Function Arguments in Registers */
844
845 #define MAX_ARGUMENT_SLOTS 8
846 #define MAX_INT_RETURN_SLOTS 4
847 #define GR_ARG_FIRST IN_REG (0)
848 #define GR_RET_FIRST GR_REG (8)
849 #define GR_RET_LAST GR_REG (11)
850 #define FR_ARG_FIRST FR_REG (8)
851 #define FR_RET_FIRST FR_REG (8)
852 #define FR_RET_LAST FR_REG (15)
853 #define AR_ARG_FIRST OUT_REG (0)
854
855 /* A C type for declaring a variable that is used as the first argument of
856 `FUNCTION_ARG' and other related values. For some target machines, the type
857 `int' suffices and can hold the number of bytes of argument so far. */
858
859 enum ivms_arg_type {I64, FF, FD, FG, FS, FT};
860 /* VMS floating point formats VAX F, VAX D, VAX G, IEEE S, IEEE T. */
861
862 typedef struct ia64_args
863 {
864 int words; /* # words of arguments so far */
865 int int_regs; /* # GR registers used so far */
866 int fp_regs; /* # FR registers used so far */
867 int prototype; /* whether function prototyped */
868 enum ivms_arg_type atypes[8]; /* which VMS float type or if not float */
869 } CUMULATIVE_ARGS;
870
871 /* A C statement (sans semicolon) for initializing the variable CUM for the
872 state at the beginning of the argument list. */
873
874 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
875 do { \
876 (CUM).words = 0; \
877 (CUM).int_regs = 0; \
878 (CUM).fp_regs = 0; \
879 (CUM).prototype = ((FNTYPE) && prototype_p (FNTYPE)) || (LIBNAME); \
880 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \
881 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \
882 (CUM).atypes[6] = (CUM).atypes[7] = I64; \
883 } while (0)
884
885 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
886 arguments for the function being compiled. If this macro is undefined,
887 `INIT_CUMULATIVE_ARGS' is used instead. */
888
889 /* We set prototype to true so that we never try to return a PARALLEL from
890 function_arg. */
891 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
892 do { \
893 (CUM).words = 0; \
894 (CUM).int_regs = 0; \
895 (CUM).fp_regs = 0; \
896 (CUM).prototype = 1; \
897 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \
898 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \
899 (CUM).atypes[6] = (CUM).atypes[7] = I64; \
900 } while (0)
901
902 /* A C expression that is nonzero if REGNO is the number of a hard register in
903 which function arguments are sometimes passed. This does *not* include
904 implicit arguments such as the static chain and the structure-value address.
905 On many machines, no registers can be used for this purpose since all
906 function arguments are pushed on the stack. */
907 #define FUNCTION_ARG_REGNO_P(REGNO) \
908 (((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
909 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
910
911 \f
912 /* How Large Values are Returned */
913
914 #define DEFAULT_PCC_STRUCT_RETURN 0
915
916 \f
917 /* Caller-Saves Register Allocation */
918
919 /* A C expression to determine whether it is worthwhile to consider placing a
920 pseudo-register in a call-clobbered hard register and saving and restoring
921 it around each function call. The expression should be 1 when this is worth
922 doing, and 0 otherwise.
923
924 If you don't define this macro, a default is used which is good on most
925 machines: `4 * CALLS < REFS'. */
926 /* ??? Investigate. */
927 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
928
929 \f
930 /* Function Entry and Exit */
931
932 /* Define this macro as a C expression that is nonzero if the return
933 instruction or the function epilogue ignores the value of the stack pointer;
934 in other words, if it is safe to delete an instruction to adjust the stack
935 pointer before a return from the function. */
936
937 #define EXIT_IGNORE_STACK 1
938
939 /* Define this macro as a C expression that is nonzero for registers
940 used by the epilogue or the `return' pattern. */
941
942 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
943
944 /* Nonzero for registers used by the exception handling mechanism. */
945
946 #define EH_USES(REGNO) ia64_eh_uses (REGNO)
947
948 /* Output part N of a function descriptor for DECL. For ia64, both
949 words are emitted with a single relocation, so ignore N > 0. */
950 #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \
951 do { \
952 if ((PART) == 0) \
953 { \
954 assemble_external (DECL); \
955 if (TARGET_ILP32) \
956 fputs ("\tdata8.ua @iplt(", FILE); \
957 else \
958 fputs ("\tdata16.ua @iplt(", FILE); \
959 mark_decl_referenced (DECL); \
960 assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \
961 fputs (")\n", FILE); \
962 if (TARGET_ILP32) \
963 fputs ("\tdata8.ua 0\n", FILE); \
964 } \
965 } while (0)
966 \f
967 /* Generating Code for Profiling. */
968
969 /* A C statement or compound statement to output to FILE some assembler code to
970 call the profiling subroutine `mcount'. */
971
972 #undef FUNCTION_PROFILER
973 #define FUNCTION_PROFILER(FILE, LABELNO) \
974 ia64_output_function_profiler(FILE, LABELNO)
975
976 /* Neither hpux nor linux use profile counters. */
977 #define NO_PROFILE_COUNTERS 1
978 \f
979 /* Trampolines for Nested Functions. */
980
981 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of
982 the function containing a non-local goto target. */
983
984 #define STACK_SAVEAREA_MODE(LEVEL) \
985 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode)
986
987 /* A C expression for the size in bytes of the trampoline, as an integer. */
988
989 #define TRAMPOLINE_SIZE 32
990
991 /* Alignment required for trampolines, in bits. */
992
993 #define TRAMPOLINE_ALIGNMENT 64
994 \f
995 /* Addressing Modes */
996
997 /* Define this macro if the machine supports post-increment addressing. */
998
999 #define HAVE_POST_INCREMENT 1
1000 #define HAVE_POST_DECREMENT 1
1001 #define HAVE_POST_MODIFY_DISP 1
1002 #define HAVE_POST_MODIFY_REG 1
1003
1004 /* A C expression that is 1 if the RTX X is a constant which is a valid
1005 address. */
1006
1007 #define CONSTANT_ADDRESS_P(X) 0
1008
1009 /* The max number of registers that can appear in a valid memory address. */
1010
1011 #define MAX_REGS_PER_ADDRESS 2
1012
1013 \f
1014 /* Condition Code Status */
1015
1016 /* One some machines not all possible comparisons are defined, but you can
1017 convert an invalid comparison into a valid one. */
1018 /* ??? Investigate. See the alpha definition. */
1019 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
1020
1021 \f
1022 /* Describing Relative Costs of Operations */
1023
1024 /* A C expression for the cost of a branch instruction. A value of 1 is the
1025 default; other values are interpreted relative to that. Used by the
1026 if-conversion code as max instruction count. */
1027 /* ??? This requires investigation. The primary effect might be how
1028 many additional insn groups we run into, vs how good the dynamic
1029 branch predictor is. */
1030
1031 #define BRANCH_COST(speed_p, predictable_p) 6
1032
1033 /* Define this macro as a C expression which is nonzero if accessing less than
1034 a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1035 word of memory. */
1036
1037 #define SLOW_BYTE_ACCESS 1
1038
1039 /* Define this macro if it is as good or better to call a constant function
1040 address than to call an address kept in a register.
1041
1042 Indirect function calls are more expensive that direct function calls, so
1043 don't cse function addresses. */
1044
1045 #define NO_FUNCTION_CSE 1
1046
1047 \f
1048 /* Dividing the output into sections. */
1049
1050 /* A C expression whose value is a string containing the assembler operation
1051 that should precede instructions and read-only data. */
1052
1053 #define TEXT_SECTION_ASM_OP "\t.text"
1054
1055 /* A C expression whose value is a string containing the assembler operation to
1056 identify the following data as writable initialized data. */
1057
1058 #define DATA_SECTION_ASM_OP "\t.data"
1059
1060 /* If defined, a C expression whose value is a string containing the assembler
1061 operation to identify the following data as uninitialized global data. */
1062
1063 #define BSS_SECTION_ASM_OP "\t.bss"
1064
1065 #define IA64_DEFAULT_GVALUE 8
1066 \f
1067 /* Position Independent Code. */
1068
1069 /* The register number of the register used to address a table of static data
1070 addresses in memory. */
1071
1072 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of
1073 gen_rtx_REG (DImode, 1). */
1074
1075 /* ??? Should we set flag_pic? Probably need to define
1076 LEGITIMIZE_PIC_OPERAND_P to make that work. */
1077
1078 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1)
1079
1080 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
1081 clobbered by calls. */
1082
1083 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
1084
1085 \f
1086 /* The Overall Framework of an Assembler File. */
1087
1088 /* A C string constant describing how to begin a comment in the target
1089 assembler language. The compiler assumes that the comment will end at the
1090 end of the line. */
1091
1092 #define ASM_COMMENT_START "//"
1093
1094 /* A C string constant for text to be output before each `asm' statement or
1095 group of consecutive ones. */
1096
1097 #define ASM_APP_ON (TARGET_GNU_AS ? "#APP\n" : "//APP\n")
1098
1099 /* A C string constant for text to be output after each `asm' statement or
1100 group of consecutive ones. */
1101
1102 #define ASM_APP_OFF (TARGET_GNU_AS ? "#NO_APP\n" : "//NO_APP\n")
1103 \f
1104 /* Output and Generation of Labels. */
1105
1106 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1107 assembler definition of a label named NAME. */
1108
1109 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of
1110 why ia64_asm_output_label exists. */
1111
1112 extern int ia64_asm_output_label;
1113 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
1114 do { \
1115 ia64_asm_output_label = 1; \
1116 assemble_name (STREAM, NAME); \
1117 fputs (":\n", STREAM); \
1118 ia64_asm_output_label = 0; \
1119 } while (0)
1120
1121 /* Globalizing directive for a label. */
1122 #define GLOBAL_ASM_OP "\t.global "
1123
1124 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text
1125 necessary for declaring the name of an external symbol named NAME which is
1126 referenced in this compilation but not defined. */
1127
1128 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1129 ia64_asm_output_external (FILE, DECL, NAME)
1130
1131 /* A C statement to store into the string STRING a label whose name is made
1132 from the string PREFIX and the number NUM. */
1133
1134 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
1135 do { \
1136 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \
1137 } while (0)
1138
1139 /* ??? Not sure if using a ? in the name for Intel as is safe. */
1140
1141 #define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu")
1142
1143 /* A C statement to output to the stdio stream STREAM assembler code which
1144 defines (equates) the symbol NAME to have the value VALUE. */
1145
1146 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1147 do { \
1148 assemble_name (STREAM, NAME); \
1149 fputs (" = ", STREAM); \
1150 if (ISDIGIT (*VALUE)) \
1151 ia64_asm_output_label = 1; \
1152 assemble_name (STREAM, VALUE); \
1153 fputc ('\n', STREAM); \
1154 ia64_asm_output_label = 0; \
1155 } while (0)
1156
1157 \f
1158 /* Macros Controlling Initialization Routines. */
1159
1160 /* This is handled by sysv4.h. */
1161
1162 \f
1163 /* Output of Assembler Instructions. */
1164
1165 /* A C initializer containing the assembler's names for the machine registers,
1166 each one as a C string constant. */
1167
1168 #define REGISTER_NAMES \
1169 { \
1170 /* General registers. */ \
1171 "ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
1172 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
1173 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
1174 "r30", "r31", \
1175 /* Local registers. */ \
1176 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \
1177 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \
1178 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \
1179 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \
1180 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \
1181 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \
1182 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \
1183 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \
1184 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \
1185 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \
1186 /* Input registers. */ \
1187 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \
1188 /* Output registers. */ \
1189 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \
1190 /* Floating-point registers. */ \
1191 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
1192 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
1193 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
1194 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \
1195 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \
1196 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \
1197 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \
1198 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \
1199 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \
1200 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \
1201 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\
1202 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\
1203 "f120","f121","f122","f123","f124","f125","f126","f127", \
1204 /* Predicate registers. */ \
1205 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \
1206 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \
1207 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \
1208 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \
1209 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \
1210 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \
1211 "p60", "p61", "p62", "p63", \
1212 /* Branch registers. */ \
1213 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
1214 /* Frame pointer. Application registers. */ \
1215 "sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
1216 }
1217
1218 /* If defined, a C initializer for an array of structures containing a name and
1219 a register number. This macro defines additional names for hard registers,
1220 thus allowing the `asm' option in declarations to refer to registers using
1221 alternate names. */
1222
1223 #define ADDITIONAL_REGISTER_NAMES \
1224 { \
1225 { "gp", R_GR (1) }, \
1226 { "sp", R_GR (12) }, \
1227 { "in0", IN_REG (0) }, \
1228 { "in1", IN_REG (1) }, \
1229 { "in2", IN_REG (2) }, \
1230 { "in3", IN_REG (3) }, \
1231 { "in4", IN_REG (4) }, \
1232 { "in5", IN_REG (5) }, \
1233 { "in6", IN_REG (6) }, \
1234 { "in7", IN_REG (7) }, \
1235 { "out0", OUT_REG (0) }, \
1236 { "out1", OUT_REG (1) }, \
1237 { "out2", OUT_REG (2) }, \
1238 { "out3", OUT_REG (3) }, \
1239 { "out4", OUT_REG (4) }, \
1240 { "out5", OUT_REG (5) }, \
1241 { "out6", OUT_REG (6) }, \
1242 { "out7", OUT_REG (7) }, \
1243 { "loc0", LOC_REG (0) }, \
1244 { "loc1", LOC_REG (1) }, \
1245 { "loc2", LOC_REG (2) }, \
1246 { "loc3", LOC_REG (3) }, \
1247 { "loc4", LOC_REG (4) }, \
1248 { "loc5", LOC_REG (5) }, \
1249 { "loc6", LOC_REG (6) }, \
1250 { "loc7", LOC_REG (7) }, \
1251 { "loc8", LOC_REG (8) }, \
1252 { "loc9", LOC_REG (9) }, \
1253 { "loc10", LOC_REG (10) }, \
1254 { "loc11", LOC_REG (11) }, \
1255 { "loc12", LOC_REG (12) }, \
1256 { "loc13", LOC_REG (13) }, \
1257 { "loc14", LOC_REG (14) }, \
1258 { "loc15", LOC_REG (15) }, \
1259 { "loc16", LOC_REG (16) }, \
1260 { "loc17", LOC_REG (17) }, \
1261 { "loc18", LOC_REG (18) }, \
1262 { "loc19", LOC_REG (19) }, \
1263 { "loc20", LOC_REG (20) }, \
1264 { "loc21", LOC_REG (21) }, \
1265 { "loc22", LOC_REG (22) }, \
1266 { "loc23", LOC_REG (23) }, \
1267 { "loc24", LOC_REG (24) }, \
1268 { "loc25", LOC_REG (25) }, \
1269 { "loc26", LOC_REG (26) }, \
1270 { "loc27", LOC_REG (27) }, \
1271 { "loc28", LOC_REG (28) }, \
1272 { "loc29", LOC_REG (29) }, \
1273 { "loc30", LOC_REG (30) }, \
1274 { "loc31", LOC_REG (31) }, \
1275 { "loc32", LOC_REG (32) }, \
1276 { "loc33", LOC_REG (33) }, \
1277 { "loc34", LOC_REG (34) }, \
1278 { "loc35", LOC_REG (35) }, \
1279 { "loc36", LOC_REG (36) }, \
1280 { "loc37", LOC_REG (37) }, \
1281 { "loc38", LOC_REG (38) }, \
1282 { "loc39", LOC_REG (39) }, \
1283 { "loc40", LOC_REG (40) }, \
1284 { "loc41", LOC_REG (41) }, \
1285 { "loc42", LOC_REG (42) }, \
1286 { "loc43", LOC_REG (43) }, \
1287 { "loc44", LOC_REG (44) }, \
1288 { "loc45", LOC_REG (45) }, \
1289 { "loc46", LOC_REG (46) }, \
1290 { "loc47", LOC_REG (47) }, \
1291 { "loc48", LOC_REG (48) }, \
1292 { "loc49", LOC_REG (49) }, \
1293 { "loc50", LOC_REG (50) }, \
1294 { "loc51", LOC_REG (51) }, \
1295 { "loc52", LOC_REG (52) }, \
1296 { "loc53", LOC_REG (53) }, \
1297 { "loc54", LOC_REG (54) }, \
1298 { "loc55", LOC_REG (55) }, \
1299 { "loc56", LOC_REG (56) }, \
1300 { "loc57", LOC_REG (57) }, \
1301 { "loc58", LOC_REG (58) }, \
1302 { "loc59", LOC_REG (59) }, \
1303 { "loc60", LOC_REG (60) }, \
1304 { "loc61", LOC_REG (61) }, \
1305 { "loc62", LOC_REG (62) }, \
1306 { "loc63", LOC_REG (63) }, \
1307 { "loc64", LOC_REG (64) }, \
1308 { "loc65", LOC_REG (65) }, \
1309 { "loc66", LOC_REG (66) }, \
1310 { "loc67", LOC_REG (67) }, \
1311 { "loc68", LOC_REG (68) }, \
1312 { "loc69", LOC_REG (69) }, \
1313 { "loc70", LOC_REG (70) }, \
1314 { "loc71", LOC_REG (71) }, \
1315 { "loc72", LOC_REG (72) }, \
1316 { "loc73", LOC_REG (73) }, \
1317 { "loc74", LOC_REG (74) }, \
1318 { "loc75", LOC_REG (75) }, \
1319 { "loc76", LOC_REG (76) }, \
1320 { "loc77", LOC_REG (77) }, \
1321 { "loc78", LOC_REG (78) }, \
1322 { "loc79", LOC_REG (79) }, \
1323 }
1324
1325 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and
1326 `%I' options of `asm_fprintf' (see `final.cc'). */
1327
1328 #define REGISTER_PREFIX ""
1329 #define LOCAL_LABEL_PREFIX "."
1330 #define USER_LABEL_PREFIX ""
1331 #define IMMEDIATE_PREFIX ""
1332
1333 \f
1334 /* Output of dispatch tables. */
1335
1336 /* This macro should be provided on machines where the addresses in a dispatch
1337 table are relative to the table's own address. */
1338
1339 /* ??? Depends on the pointer size. */
1340
1341 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1342 do { \
1343 if (CASE_VECTOR_MODE == SImode) \
1344 fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE); \
1345 else \
1346 fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE); \
1347 } while (0)
1348
1349 /* Jump tables only need 4 or 8 byte alignment. */
1350
1351 #define ADDR_VEC_ALIGN(ADDR_VEC) (CASE_VECTOR_MODE == SImode ? 2 : 3)
1352
1353 \f
1354 /* Assembler Commands for Exception Regions. */
1355
1356 /* Select a format to encode pointers in exception handling data. CODE
1357 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1358 true if the symbol may be affected by dynamic relocations. */
1359 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1360 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \
1361 | ((GLOBAL) ? DW_EH_PE_indirect : 0) \
1362 | (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8))
1363
1364 /* Handle special EH pointer encodings. Absolute, pc-relative, and
1365 indirect are handled automatically. */
1366 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
1367 do { \
1368 const char *reltag = NULL; \
1369 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \
1370 reltag = "@segrel("; \
1371 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \
1372 reltag = "@gprel("; \
1373 if (reltag) \
1374 { \
1375 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1376 fputs (reltag, FILE); \
1377 assemble_name (FILE, XSTR (ADDR, 0)); \
1378 fputc (')', FILE); \
1379 goto DONE; \
1380 } \
1381 } while (0)
1382
1383 \f
1384 /* Assembler Commands for Alignment. */
1385
1386 /* ??? Investigate. */
1387
1388 /* The alignment (log base 2) to put in front of LABEL, which follows
1389 a BARRIER. */
1390
1391 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
1392
1393 /* The desired alignment for the location counter at the beginning
1394 of a loop. */
1395
1396 /* #define LOOP_ALIGN(LABEL) */
1397
1398 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
1399 section because it fails put zeros in the bytes that are skipped. */
1400
1401 #define ASM_NO_SKIP_IN_TEXT 1
1402
1403 /* A C statement to output to the stdio stream STREAM an assembler command to
1404 advance the location counter to a multiple of 2 to the POWER bytes. */
1405
1406 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1407 fprintf (STREAM, "\t.align %d\n", 1<<(POWER))
1408
1409 \f
1410 /* Macros Affecting all Debug Formats. */
1411
1412 /* This is handled in sysv4.h. */
1413 \f
1414 /* Macros for Dwarf Output. */
1415
1416 /* Define this macro if GCC should produce dwarf version 2 format debugging
1417 output in response to the `-g' option. */
1418
1419 #define DWARF2_DEBUGGING_INFO 1
1420
1421 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
1422
1423 /* Use tags for debug info labels, so that they don't break instruction
1424 bundles. This also avoids getting spurious DV warnings from the
1425 assembler. This is similar to (*targetm.asm_out.internal_label), except that we
1426 add brackets around the label. */
1427
1428 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
1429 fprintf (FILE, TARGET_GNU_AS ? "[.%s%d:]\n" : ".%s%d:\n", PREFIX, NUM)
1430
1431 /* Use section-relative relocations for debugging offsets. Unlike other
1432 targets that fake this by putting the section VMA at 0, IA-64 has
1433 proper relocations for them. */
1434 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL, OFFSET, SECTION) \
1435 do { \
1436 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1437 fputs ("@secrel(", FILE); \
1438 assemble_name (FILE, LABEL); \
1439 if ((OFFSET) != 0) \
1440 fprintf (FILE, "+" HOST_WIDE_INT_PRINT_DEC, \
1441 (HOST_WIDE_INT) (OFFSET)); \
1442 fputc (')', FILE); \
1443 } while (0)
1444
1445 /* Emit a PC-relative relocation. */
1446 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1447 do { \
1448 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1449 fputs ("@pcrel(", FILE); \
1450 assemble_name (FILE, LABEL); \
1451 fputc (')', FILE); \
1452 } while (0)
1453 \f
1454 /* Register Renaming Parameters. */
1455
1456 /* A C expression that is nonzero if hard register number REGNO2 can be
1457 considered for use as a rename register for REGNO1 */
1458
1459 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
1460 ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
1461
1462 \f
1463 /* Miscellaneous Parameters. */
1464
1465 /* Flag to mark data that is in the small address area (addressable
1466 via "addl", that is, within a 2MByte offset of 0. */
1467 #define SYMBOL_FLAG_SMALL_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
1468 #define SYMBOL_REF_SMALL_ADDR_P(X) \
1469 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0)
1470
1471 /* An alias for a machine mode name. This is the machine mode that elements of
1472 a jump-table should have. */
1473
1474 #define CASE_VECTOR_MODE ptr_mode
1475
1476 /* Define as C expression which evaluates to nonzero if the tablejump
1477 instruction expects the table to contain offsets from the address of the
1478 table. */
1479
1480 #define CASE_VECTOR_PC_RELATIVE 1
1481
1482 /* Define this macro if operations between registers with integral mode smaller
1483 than a word are always performed on the entire register. */
1484
1485 #define WORD_REGISTER_OPERATIONS 1
1486
1487 /* Define this macro to be a C expression indicating when insns that read
1488 memory in MODE, an integral mode narrower than a word, set the bits outside
1489 of MODE to be either the sign-extension or the zero-extension of the data
1490 read. */
1491
1492 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1493
1494 /* The maximum number of bytes that a single instruction can move quickly from
1495 memory to memory. */
1496 #define MOVE_MAX 8
1497
1498 /* A C expression describing the value returned by a comparison operator with
1499 an integral mode and stored by a store-flag instruction (`sCOND') when the
1500 condition is true. */
1501
1502 /* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1. */
1503
1504 /* An alias for the machine mode for pointers. */
1505
1506 /* ??? This would change if we had ILP32 support. */
1507
1508 #define Pmode DImode
1509
1510 /* An alias for the machine mode used for memory references to functions being
1511 called, in `call' RTL expressions. */
1512
1513 #define FUNCTION_MODE Pmode
1514
1515 /* A C expression for the maximum number of instructions to execute via
1516 conditional execution instructions instead of a branch. A value of
1517 BRANCH_COST+1 is the default if the machine does not use
1518 cc0, and 1 if it does use cc0. */
1519 /* ??? Investigate. */
1520 #define MAX_CONDITIONAL_EXECUTE 12
1521
1522 extern int ia64_final_schedule;
1523
1524 #define TARGET_UNWIND_TABLES_DEFAULT true
1525
1526 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
1527
1528 /* This function contains machine specific function data. */
1529 struct GTY(()) machine_function
1530 {
1531 /* The new stack pointer when unwinding from EH. */
1532 rtx ia64_eh_epilogue_sp;
1533
1534 /* The new bsp value when unwinding from EH. */
1535 rtx ia64_eh_epilogue_bsp;
1536
1537 /* The GP value save register. */
1538 rtx ia64_gp_save;
1539
1540 /* The number of varargs registers to save. */
1541 int n_varargs;
1542
1543 /* The number of the next unwind state to copy. */
1544 int state_num;
1545 };
1546
1547 #define DONT_USE_BUILTIN_SETJMP
1548
1549 /* Output any profiling code before the prologue. */
1550
1551 #undef PROFILE_BEFORE_PROLOGUE
1552 #define PROFILE_BEFORE_PROLOGUE 1
1553
1554 /* Initialize library function table. */
1555 #undef TARGET_INIT_LIBFUNCS
1556 #define TARGET_INIT_LIBFUNCS ia64_init_libfuncs
1557 \f
1558
1559 /* Switch on code for querying unit reservations. */
1560 #define CPU_UNITS_QUERY 1
1561
1562 /* End of ia64.h */
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