gcc/config/riscv/riscv-cores.def

   1 /* List of supported core and tune info for RISC-V.
   2    Copyright (C) 2020-2025 Free Software Foundation, Inc.
   3
   4    This file is part of GCC.
   5
   6    GCC is free software; you can redistribute it and/or modify it
   7    under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    GCC is distributed in the hope that it will be useful, but
  12    WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14    General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GCC; see the file COPYING3.  If not see
  18    <http://www.gnu.org/licenses/>.  */
  19
  20 /* This is a list of tune that implement RISC-V.
  21
  22    Before using #include to read this file, define a macro:
  23
  24       RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO)
  25
  26    The TUNE_NAME is the name of the micro-arch, represented as a string.
  27    The PIPELINE_MODEL is the pipeline model of the micro-arch, represented as a
  28    string, defined in riscv.md.
  29    The TUNE_INFO is the detail cost model for this core, represented as an
  30    identifier, reference to riscv.cc.  */
  31
  32 #ifndef RISCV_TUNE
  33 #define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO)
  34 #endif
  35
  36 RISCV_TUNE("rocket", generic, rocket_tune_info)
  37 RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
  38 RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
  39 RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
  40 RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info)
  41 RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
  42 RISCV_TUNE("tt-ascalon-d8", generic_ooo, tt_ascalon_d8_tune_info)
  43 RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
  44 RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)
  45 RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
  46 RISCV_TUNE("size", generic, optimize_size_tune_info)
  47
  48 #undef RISCV_TUNE
  49
  50 /* This is a list of cores that implement RISC-V.
  51
  52    Before using #include to read this file, define a macro:
  53
  54       RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH)
  55
  56    The CORE_NAME is the name of the core, represented as a string.
  57    The ARCH is the default arch of the core, represented as a string,
  58    can be NULL if no default arch.
  59    The MICRO_ARCH is the name of the core for which scheduling decisions
  60    will be made, represented as an identifier.  */
  61
  62 #ifndef RISCV_CORE
  63 #define RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH)
  64 #endif
  65
  66 RISCV_CORE("sifive-e20",      "rv32imc",    "rocket")
  67 RISCV_CORE("sifive-e21",      "rv32imac",   "rocket")
  68 RISCV_CORE("sifive-e24",      "rv32imafc",  "rocket")
  69 RISCV_CORE("sifive-e31",      "rv32imac",   "sifive-3-series")
  70 RISCV_CORE("sifive-e34",      "rv32imafc",  "sifive-3-series")
  71 RISCV_CORE("sifive-e76",      "rv32imafc",  "sifive-7-series")
  72
  73 RISCV_CORE("sifive-s21",      "rv64imac",   "rocket")
  74 RISCV_CORE("sifive-s51",      "rv64imac",   "sifive-5-series")
  75 RISCV_CORE("sifive-s54",      "rv64imafdc", "sifive-5-series")
  76 RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
  77
  78 RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
  79 RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
  80 RISCV_CORE("sifive-x280",     "rv64imafdcv_zfh_zba_zbb_zvfh_zvl512b", "sifive-7-series")
  81 RISCV_CORE("sifive-p450",     "rv64imafdc_za64rs_zic64b_zicbom_zicbop_zicboz_"
  82                               "ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_"
  83                               "zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs",
  84                               "sifive-p400-series")
  85 RISCV_CORE("sifive-p670",     "rv64imafdcv_za64rs_zic64b_zicbom_zicbop_zicboz_"
  86                               "ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_"
  87                               "zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs_"
  88                               "zvl128b_zvbb_zvknc_zvkng_zvksc_zvksg",
  89                               "sifive-p600-series")
  90
  91 RISCV_CORE("thead-c906",      "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
  92                               "xtheadcondmov_xtheadfmemidx_xtheadmac_"
  93                               "xtheadmemidx_xtheadmempair_xtheadsync",
  94                               "thead-c906")
  95
  96 RISCV_CORE("tt-ascalon-d8",   "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_"
  97                               "ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicsr_"
  98                               "zifencei_zihintntl_zihintpause_zimop_za64rs_"
  99                               "zawrs_zfa_zfbfmin_zfh_zcb_zcmop_zba_zbb_zbs_"
 100                               "zvbb_zvbc_zvfbfwma_zvfh_zvkng_zvl256b",
 101                               "tt-ascalon-d8")
 102
 103 RISCV_CORE("xiangshan-nanhu",      "rv64imafdc_zba_zbb_zbc_zbs_"
 104                               "zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_"
 105                               "svinval_zicbom_zicboz",
 106                               "xiangshan-nanhu")
 107 #undef RISCV_CORE