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Daily bump.
[official-gcc.git] / gcc / config / riscv / riscv-modes.def
blob55f7fd08c4dd16d9cd264e449378f36b58c06ef2
1 /* Extra machine modes for RISC-V target.
2 Copyright (C) 2011-2025 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 FLOAT_MODE (HF, 2, ieee_half_format);
23 FLOAT_MODE (TF, 16, ieee_quad_format);
24 FLOAT_MODE (BF, 2, 0);
25 /* Reuse definition from arm. */
26 ADJUST_FLOAT_FORMAT (BF, &arm_bfloat_half_format);
27
28 /* Vector modes. */
29
30 /* Encode the ratio of SEW/LMUL into the mask types. There are the following
31 * mask types. */
32
33 /* Encode the ratio of SEW/LMUL into the mask types.
34 There are the following mask types.
35
36 n = SEW/LMUL
37
38 |Modes| n = 1 | n = 2 | n = 4 | n = 8 | n = 16 | n = 32 | n = 64 |
39 |BI |RVVM1BI |RVVMF2BI |RVVMF4BI |RVVMF8BI |RVVMF16BI |RVVMF32BI |RVVMF64BI | */
40
41 /* For RVV modes, each boolean value occupies 1-bit.
42 4th argument specifies the minimal possible size of the vector mode,
43 and will adjust to the right size by ADJUST_BYTESIZE. */
44 VECTOR_BOOL_MODE (RVVM1BI, 64, BI, 8);
45 VECTOR_BOOL_MODE (RVVMF2BI, 32, BI, 4);
46 VECTOR_BOOL_MODE (RVVMF4BI, 16, BI, 2);
47 VECTOR_BOOL_MODE (RVVMF8BI, 8, BI, 1);
48 VECTOR_BOOL_MODE (RVVMF16BI, 4, BI, 1);
49 VECTOR_BOOL_MODE (RVVMF32BI, 2, BI, 1);
50 VECTOR_BOOL_MODE (RVVMF64BI, 1, BI, 1);
51
52 ADJUST_NUNITS (RVVM1BI, riscv_v_adjust_nunits (RVVM1BImode, 64));
53 ADJUST_NUNITS (RVVMF2BI, riscv_v_adjust_nunits (RVVMF2BImode, 32));
54 ADJUST_NUNITS (RVVMF4BI, riscv_v_adjust_nunits (RVVMF4BImode, 16));
55 ADJUST_NUNITS (RVVMF8BI, riscv_v_adjust_nunits (RVVMF8BImode, 8));
56 ADJUST_NUNITS (RVVMF16BI, riscv_v_adjust_nunits (RVVMF16BImode, 4));
57 ADJUST_NUNITS (RVVMF32BI, riscv_v_adjust_nunits (RVVMF32BImode, 2));
58 ADJUST_NUNITS (RVVMF64BI, riscv_v_adjust_nunits (RVVMF64BImode, 1));
59
60 ADJUST_ALIGNMENT (RVVM1BI, 1);
61 ADJUST_ALIGNMENT (RVVMF2BI, 1);
62 ADJUST_ALIGNMENT (RVVMF4BI, 1);
63 ADJUST_ALIGNMENT (RVVMF8BI, 1);
64 ADJUST_ALIGNMENT (RVVMF16BI, 1);
65 ADJUST_ALIGNMENT (RVVMF32BI, 1);
66 ADJUST_ALIGNMENT (RVVMF64BI, 1);
67
68 ADJUST_PRECISION (RVVM1BI, riscv_v_adjust_precision (RVVM1BImode, 64));
69 ADJUST_PRECISION (RVVMF2BI, riscv_v_adjust_precision (RVVMF2BImode, 32));
70 ADJUST_PRECISION (RVVMF4BI, riscv_v_adjust_precision (RVVMF4BImode, 16));
71 ADJUST_PRECISION (RVVMF8BI, riscv_v_adjust_precision (RVVMF8BImode, 8));
72 ADJUST_PRECISION (RVVMF16BI, riscv_v_adjust_precision (RVVMF16BImode, 4));
73 ADJUST_PRECISION (RVVMF32BI, riscv_v_adjust_precision (RVVMF32BImode, 2));
74 ADJUST_PRECISION (RVVMF64BI, riscv_v_adjust_precision (RVVMF64BImode, 1));
75
76 ADJUST_BYTESIZE (RVVM1BI, riscv_v_adjust_bytesize (RVVM1BImode, 8));
77 ADJUST_BYTESIZE (RVVMF2BI, riscv_v_adjust_bytesize (RVVMF2BImode, 4));
78 ADJUST_BYTESIZE (RVVMF4BI, riscv_v_adjust_bytesize (RVVMF4BImode, 2));
79 ADJUST_BYTESIZE (RVVMF8BI, riscv_v_adjust_bytesize (RVVMF8BImode, 1));
80 ADJUST_BYTESIZE (RVVMF16BI, riscv_v_adjust_bytesize (RVVMF16BImode, 1));
81 ADJUST_BYTESIZE (RVVMF32BI, riscv_v_adjust_bytesize (RVVMF32BImode, 1));
82 ADJUST_BYTESIZE (RVVMF64BI, riscv_v_adjust_bytesize (RVVMF64BImode, 1));
83
84 /* Encode SEW and LMUL into data types.
85 We enforce the constraint LMUL ≥ SEW/ELEN in the implementation.
86 There are the following data types for ELEN = 64.
87
88 |Modes|LMUL=1 |LMUL=2 |LMUL=4 |LMUL=8 |LMUL=1/2|LMUL=1/4|LMUL=1/8|
89 |DI |RVVM1DI|RVVM2DI|RVVM4DI|RVVM8DI|N/A |N/A |N/A |
90 |SI |RVVM1SI|RVVM2SI|RVVM4SI|RVVM8SI|RVVMF2SI|N/A |N/A |
91 |HI |RVVM1HI|RVVM2HI|RVVM4HI|RVVM8HI|RVVMF2HI|RVVMF4HI|N/A |
92 |QI |RVVM1QI|RVVM2QI|RVVM4QI|RVVM8QI|RVVMF2QI|RVVMF4QI|RVVMF8QI|
93 |DF |RVVM1DF|RVVM2DF|RVVM4DF|RVVM8DF|N/A |N/A |N/A |
94 |SF |RVVM1SF|RVVM2SF|RVVM4SF|RVVM8SF|RVVMF2SF|N/A |N/A |
95 |HF |RVVM1HF|RVVM2HF|RVVM4HF|RVVM8HF|RVVMF2HF|RVVMF4HF|N/A |
96 |BF |RVVM1BF|RVVM2BF|RVVM4BF|RVVM8BF|RVVMF2BF|RVVMF4BF|N/A |
97
98 There are the following data types for ELEN = 32.
99
100 |Modes|LMUL=1 |LMUL=2 |LMUL=4 |LMUL=8 |LMUL=1/2|LMUL=1/4|LMUL=1/8|
101 |SI |RVVM1SI|RVVM2SI|RVVM4SI|RVVM8SI|N/A |N/A |N/A |
102 |HI |RVVM1HI|RVVM2HI|RVVM4HI|RVVM8HI|RVVMF2HI|N/A |N/A |
103 |QI |RVVM1QI|RVVM2QI|RVVM4QI|RVVM8QI|RVVMF2QI|RVVMF4QI|N/A |
104 |SF |RVVM1SF|RVVM2SF|RVVM4SF|RVVM8SF|N/A |N/A |N/A |
105 |HF |RVVM1HF|RVVM2HF|RVVM4HF|RVVM8HF|RVVMF2HF|N/A |N/A |
106 |BF |RVVM1BF|RVVM2BF|RVVM4BF|RVVM8BF|RVVMF2BF|N/A |N/A | */
107
108 #define RVV_WHOLE_MODES(LMUL) \
109 VECTOR_MODE_WITH_PREFIX (RVVM, INT, QI, LMUL, 0); \
110 VECTOR_MODE_WITH_PREFIX (RVVM, INT, HI, LMUL, 0); \
111 VECTOR_MODE_WITH_PREFIX (RVVM, FLOAT, BF, LMUL, 0); \
112 VECTOR_MODE_WITH_PREFIX (RVVM, FLOAT, HF, LMUL, 0); \
113 VECTOR_MODE_WITH_PREFIX (RVVM, INT, SI, LMUL, 0); \
114 VECTOR_MODE_WITH_PREFIX (RVVM, FLOAT, SF, LMUL, 0); \
115 VECTOR_MODE_WITH_PREFIX (RVVM, INT, DI, LMUL, 0); \
116 VECTOR_MODE_WITH_PREFIX (RVVM, FLOAT, DF, LMUL, 0); \
117 \
118 ADJUST_NUNITS (RVVM##LMUL##QI, \
119 riscv_v_adjust_nunits (RVVM##LMUL##QImode, false, LMUL, 1)); \
120 ADJUST_NUNITS (RVVM##LMUL##HI, \
121 riscv_v_adjust_nunits (RVVM##LMUL##HImode, false, LMUL, 1)); \
122 ADJUST_NUNITS (RVVM##LMUL##SI, \
123 riscv_v_adjust_nunits (RVVM##LMUL##SImode, false, LMUL, 1)); \
124 ADJUST_NUNITS (RVVM##LMUL##DI, \
125 riscv_v_adjust_nunits (RVVM##LMUL##DImode, false, LMUL, 1)); \
126 ADJUST_NUNITS (RVVM##LMUL##BF, \
127 riscv_v_adjust_nunits (RVVM##LMUL##BFmode, false, LMUL, 1)); \
128 ADJUST_NUNITS (RVVM##LMUL##HF, \
129 riscv_v_adjust_nunits (RVVM##LMUL##HFmode, false, LMUL, 1)); \
130 ADJUST_NUNITS (RVVM##LMUL##SF, \
131 riscv_v_adjust_nunits (RVVM##LMUL##SFmode, false, LMUL, 1)); \
132 ADJUST_NUNITS (RVVM##LMUL##DF, \
133 riscv_v_adjust_nunits (RVVM##LMUL##DFmode, false, LMUL, 1)); \
134 \
135 ADJUST_ALIGNMENT (RVVM##LMUL##QI, 1); \
136 ADJUST_ALIGNMENT (RVVM##LMUL##HI, 2); \
137 ADJUST_ALIGNMENT (RVVM##LMUL##SI, 4); \
138 ADJUST_ALIGNMENT (RVVM##LMUL##DI, 8); \
139 ADJUST_ALIGNMENT (RVVM##LMUL##BF, 2); \
140 ADJUST_ALIGNMENT (RVVM##LMUL##HF, 2); \
141 ADJUST_ALIGNMENT (RVVM##LMUL##SF, 4); \
142 ADJUST_ALIGNMENT (RVVM##LMUL##DF, 8);
143
144 RVV_WHOLE_MODES (1)
145 RVV_WHOLE_MODES (2)
146 RVV_WHOLE_MODES (4)
147 RVV_WHOLE_MODES (8)
148
149 #define RVV_FRACT_MODE(TYPE, MODE, LMUL, ALIGN) \
150 VECTOR_MODE_WITH_PREFIX (RVVMF, TYPE, MODE, LMUL, 0); \
151 ADJUST_NUNITS (RVVMF##LMUL##MODE, \
152 riscv_v_adjust_nunits (RVVMF##LMUL##MODE##mode, true, LMUL, \
153 1)); \
154 \
155 ADJUST_ALIGNMENT (RVVMF##LMUL##MODE, ALIGN);
156
157 RVV_FRACT_MODE (INT, QI, 2, 1)
158 RVV_FRACT_MODE (INT, QI, 4, 1)
159 RVV_FRACT_MODE (INT, QI, 8, 1)
160 RVV_FRACT_MODE (INT, HI, 2, 2)
161 RVV_FRACT_MODE (INT, HI, 4, 2)
162 RVV_FRACT_MODE (FLOAT, BF, 2, 2)
163 RVV_FRACT_MODE (FLOAT, BF, 4, 2)
164 RVV_FRACT_MODE (FLOAT, HF, 2, 2)
165 RVV_FRACT_MODE (FLOAT, HF, 4, 2)
166 RVV_FRACT_MODE (INT, SI, 2, 4)
167 RVV_FRACT_MODE (FLOAT, SF, 2, 4)
168
169 /* Tuple modes for segment loads/stores according to NF.
170
171 Tuple modes format: RVV<LMUL>x<NF><BASEMODE>
172
173 When LMUL is MF8/MF4/MF2/M1, NF can be 2 ~ 8.
174 When LMUL is M2, NF can be 2 ~ 4.
175 When LMUL is M4, NF can be 4. */
176
177 #define RVV_NF8_MODES(NF) \
178 VECTOR_MODE_WITH_PREFIX (RVVMF8x, INT, QI, NF, 1); \
179 VECTOR_MODE_WITH_PREFIX (RVVMF4x, INT, QI, NF, 1); \
180 VECTOR_MODE_WITH_PREFIX (RVVMF2x, INT, QI, NF, 1); \
181 VECTOR_MODE_WITH_PREFIX (RVVM1x, INT, QI, NF, 1); \
182 VECTOR_MODE_WITH_PREFIX (RVVMF4x, INT, HI, NF, 1); \
183 VECTOR_MODE_WITH_PREFIX (RVVMF2x, INT, HI, NF, 1); \
184 VECTOR_MODE_WITH_PREFIX (RVVM1x, INT, HI, NF, 1); \
185 VECTOR_MODE_WITH_PREFIX (RVVMF4x, FLOAT, BF, NF, 1); \
186 VECTOR_MODE_WITH_PREFIX (RVVMF2x, FLOAT, BF, NF, 1); \
187 VECTOR_MODE_WITH_PREFIX (RVVM1x, FLOAT, BF, NF, 1); \
188 VECTOR_MODE_WITH_PREFIX (RVVMF4x, FLOAT, HF, NF, 1); \
189 VECTOR_MODE_WITH_PREFIX (RVVMF2x, FLOAT, HF, NF, 1); \
190 VECTOR_MODE_WITH_PREFIX (RVVM1x, FLOAT, HF, NF, 1); \
191 VECTOR_MODE_WITH_PREFIX (RVVMF2x, INT, SI, NF, 1); \
192 VECTOR_MODE_WITH_PREFIX (RVVM1x, INT, SI, NF, 1); \
193 VECTOR_MODE_WITH_PREFIX (RVVMF2x, FLOAT, SF, NF, 1); \
194 VECTOR_MODE_WITH_PREFIX (RVVM1x, FLOAT, SF, NF, 1); \
195 VECTOR_MODE_WITH_PREFIX (RVVM1x, INT, DI, NF, 1); \
196 VECTOR_MODE_WITH_PREFIX (RVVM1x, FLOAT, DF, NF, 1); \
197 \
198 ADJUST_NUNITS (RVVMF8x##NF##QI, \
199 riscv_v_adjust_nunits (RVVMF8x##NF##QImode, true, 8, NF)); \
200 ADJUST_NUNITS (RVVMF4x##NF##QI, \
201 riscv_v_adjust_nunits (RVVMF4x##NF##QImode, true, 4, NF)); \
202 ADJUST_NUNITS (RVVMF2x##NF##QI, \
203 riscv_v_adjust_nunits (RVVMF2x##NF##QImode, true, 2, NF)); \
204 ADJUST_NUNITS (RVVM1x##NF##QI, \
205 riscv_v_adjust_nunits (RVVM1x##NF##QImode, false, 1, NF)); \
206 ADJUST_NUNITS (RVVMF4x##NF##HI, \
207 riscv_v_adjust_nunits (RVVMF4x##NF##HImode, true, 4, NF)); \
208 ADJUST_NUNITS (RVVMF2x##NF##HI, \
209 riscv_v_adjust_nunits (RVVMF2x##NF##HImode, true, 2, NF)); \
210 ADJUST_NUNITS (RVVM1x##NF##HI, \
211 riscv_v_adjust_nunits (RVVM1x##NF##HImode, false, 1, NF)); \
212 ADJUST_NUNITS (RVVMF4x##NF##BF, \
213 riscv_v_adjust_nunits (RVVMF4x##NF##BFmode, true, 4, NF)); \
214 ADJUST_NUNITS (RVVMF2x##NF##BF, \
215 riscv_v_adjust_nunits (RVVMF2x##NF##BFmode, true, 2, NF)); \
216 ADJUST_NUNITS (RVVM1x##NF##BF, \
217 riscv_v_adjust_nunits (RVVM1x##NF##BFmode, false, 1, NF)); \
218 ADJUST_NUNITS (RVVMF4x##NF##HF, \
219 riscv_v_adjust_nunits (RVVMF4x##NF##HFmode, true, 4, NF)); \
220 ADJUST_NUNITS (RVVMF2x##NF##HF, \
221 riscv_v_adjust_nunits (RVVMF2x##NF##HFmode, true, 2, NF)); \
222 ADJUST_NUNITS (RVVM1x##NF##HF, \
223 riscv_v_adjust_nunits (RVVM1x##NF##HFmode, false, 1, NF)); \
224 ADJUST_NUNITS (RVVMF2x##NF##SI, \
225 riscv_v_adjust_nunits (RVVMF2x##NF##SImode, true, 2, NF)); \
226 ADJUST_NUNITS (RVVM1x##NF##SI, \
227 riscv_v_adjust_nunits (RVVM1x##NF##SImode, false, 1, NF)); \
228 ADJUST_NUNITS (RVVMF2x##NF##SF, \
229 riscv_v_adjust_nunits (RVVMF2x##NF##SFmode, true, 2, NF)); \
230 ADJUST_NUNITS (RVVM1x##NF##SF, \
231 riscv_v_adjust_nunits (RVVM1x##NF##SFmode, false, 1, NF)); \
232 ADJUST_NUNITS (RVVM1x##NF##DI, \
233 riscv_v_adjust_nunits (RVVM1x##NF##DImode, false, 1, NF)); \
234 ADJUST_NUNITS (RVVM1x##NF##DF, \
235 riscv_v_adjust_nunits (RVVM1x##NF##DFmode, false, 1, NF)); \
236 \
237 ADJUST_ALIGNMENT (RVVMF8x##NF##QI, 1); \
238 ADJUST_ALIGNMENT (RVVMF4x##NF##QI, 1); \
239 ADJUST_ALIGNMENT (RVVMF2x##NF##QI, 1); \
240 ADJUST_ALIGNMENT (RVVM1x##NF##QI, 1); \
241 ADJUST_ALIGNMENT (RVVMF4x##NF##HI, 2); \
242 ADJUST_ALIGNMENT (RVVMF2x##NF##HI, 2); \
243 ADJUST_ALIGNMENT (RVVM1x##NF##HI, 2); \
244 ADJUST_ALIGNMENT (RVVMF4x##NF##BF, 2); \
245 ADJUST_ALIGNMENT (RVVMF2x##NF##BF, 2); \
246 ADJUST_ALIGNMENT (RVVM1x##NF##BF, 2); \
247 ADJUST_ALIGNMENT (RVVMF4x##NF##HF, 2); \
248 ADJUST_ALIGNMENT (RVVMF2x##NF##HF, 2); \
249 ADJUST_ALIGNMENT (RVVM1x##NF##HF, 2); \
250 ADJUST_ALIGNMENT (RVVMF2x##NF##SI, 4); \
251 ADJUST_ALIGNMENT (RVVM1x##NF##SI, 4); \
252 ADJUST_ALIGNMENT (RVVMF2x##NF##SF, 4); \
253 ADJUST_ALIGNMENT (RVVM1x##NF##SF, 4); \
254 ADJUST_ALIGNMENT (RVVM1x##NF##DI, 8); \
255 ADJUST_ALIGNMENT (RVVM1x##NF##DF, 8);
256
257 RVV_NF8_MODES (8)
258 RVV_NF8_MODES (7)
259 RVV_NF8_MODES (6)
260 RVV_NF8_MODES (5)
261 RVV_NF8_MODES (4)
262 RVV_NF8_MODES (3)
263 RVV_NF8_MODES (2)
264
265 #define RVV_NF4_MODES(NF) \
266 VECTOR_MODE_WITH_PREFIX (RVVM2x, INT, QI, NF, 1); \
267 VECTOR_MODE_WITH_PREFIX (RVVM2x, INT, HI, NF, 1); \
268 VECTOR_MODE_WITH_PREFIX (RVVM2x, FLOAT, BF, NF, 1); \
269 VECTOR_MODE_WITH_PREFIX (RVVM2x, FLOAT, HF, NF, 1); \
270 VECTOR_MODE_WITH_PREFIX (RVVM2x, INT, SI, NF, 1); \
271 VECTOR_MODE_WITH_PREFIX (RVVM2x, FLOAT, SF, NF, 1); \
272 VECTOR_MODE_WITH_PREFIX (RVVM2x, INT, DI, NF, 1); \
273 VECTOR_MODE_WITH_PREFIX (RVVM2x, FLOAT, DF, NF, 1); \
274 \
275 ADJUST_NUNITS (RVVM2x##NF##QI, \
276 riscv_v_adjust_nunits (RVVM2x##NF##QImode, false, 2, NF)); \
277 ADJUST_NUNITS (RVVM2x##NF##HI, \
278 riscv_v_adjust_nunits (RVVM2x##NF##HImode, false, 2, NF)); \
279 ADJUST_NUNITS (RVVM2x##NF##BF, \
280 riscv_v_adjust_nunits (RVVM2x##NF##BFmode, false, 2, NF)); \
281 ADJUST_NUNITS (RVVM2x##NF##HF, \
282 riscv_v_adjust_nunits (RVVM2x##NF##HFmode, false, 2, NF)); \
283 ADJUST_NUNITS (RVVM2x##NF##SI, \
284 riscv_v_adjust_nunits (RVVM2x##NF##SImode, false, 2, NF)); \
285 ADJUST_NUNITS (RVVM2x##NF##SF, \
286 riscv_v_adjust_nunits (RVVM2x##NF##SFmode, false, 2, NF)); \
287 ADJUST_NUNITS (RVVM2x##NF##DI, \
288 riscv_v_adjust_nunits (RVVM2x##NF##DImode, false, 2, NF)); \
289 ADJUST_NUNITS (RVVM2x##NF##DF, \
290 riscv_v_adjust_nunits (RVVM2x##NF##DFmode, false, 2, NF)); \
291 \
292 ADJUST_ALIGNMENT (RVVM2x##NF##QI, 1); \
293 ADJUST_ALIGNMENT (RVVM2x##NF##HI, 2); \
294 ADJUST_ALIGNMENT (RVVM2x##NF##BF, 2); \
295 ADJUST_ALIGNMENT (RVVM2x##NF##HF, 2); \
296 ADJUST_ALIGNMENT (RVVM2x##NF##SI, 4); \
297 ADJUST_ALIGNMENT (RVVM2x##NF##SF, 4); \
298 ADJUST_ALIGNMENT (RVVM2x##NF##DI, 8); \
299 ADJUST_ALIGNMENT (RVVM2x##NF##DF, 8);
300
301 RVV_NF4_MODES (2)
302 RVV_NF4_MODES (3)
303 RVV_NF4_MODES (4)
304
305 #define RVV_NF2_MODES(NF) \
306 VECTOR_MODE_WITH_PREFIX (RVVM4x, INT, QI, NF, 1); \
307 VECTOR_MODE_WITH_PREFIX (RVVM4x, INT, HI, NF, 1); \
308 VECTOR_MODE_WITH_PREFIX (RVVM4x, FLOAT, BF, NF, 1); \
309 VECTOR_MODE_WITH_PREFIX (RVVM4x, FLOAT, HF, NF, 1); \
310 VECTOR_MODE_WITH_PREFIX (RVVM4x, INT, SI, NF, 1); \
311 VECTOR_MODE_WITH_PREFIX (RVVM4x, FLOAT, SF, NF, 1); \
312 VECTOR_MODE_WITH_PREFIX (RVVM4x, INT, DI, NF, 1); \
313 VECTOR_MODE_WITH_PREFIX (RVVM4x, FLOAT, DF, NF, 1); \
314 \
315 ADJUST_NUNITS (RVVM4x##NF##QI, \
316 riscv_v_adjust_nunits (RVVM4x##NF##QImode, false, 4, NF)); \
317 ADJUST_NUNITS (RVVM4x##NF##HI, \
318 riscv_v_adjust_nunits (RVVM4x##NF##HImode, false, 4, NF)); \
319 ADJUST_NUNITS (RVVM4x##NF##BF, \
320 riscv_v_adjust_nunits (RVVM4x##NF##BFmode, false, 4, NF)); \
321 ADJUST_NUNITS (RVVM4x##NF##HF, \
322 riscv_v_adjust_nunits (RVVM4x##NF##HFmode, false, 4, NF)); \
323 ADJUST_NUNITS (RVVM4x##NF##SI, \
324 riscv_v_adjust_nunits (RVVM4x##NF##SImode, false, 4, NF)); \
325 ADJUST_NUNITS (RVVM4x##NF##SF, \
326 riscv_v_adjust_nunits (RVVM4x##NF##SFmode, false, 4, NF)); \
327 ADJUST_NUNITS (RVVM4x##NF##DI, \
328 riscv_v_adjust_nunits (RVVM4x##NF##DImode, false, 4, NF)); \
329 ADJUST_NUNITS (RVVM4x##NF##DF, \
330 riscv_v_adjust_nunits (RVVM4x##NF##DFmode, false, 4, NF)); \
331 \
332 ADJUST_ALIGNMENT (RVVM4x##NF##QI, 1); \
333 ADJUST_ALIGNMENT (RVVM4x##NF##HI, 2); \
334 ADJUST_ALIGNMENT (RVVM4x##NF##BF, 2); \
335 ADJUST_ALIGNMENT (RVVM4x##NF##HF, 2); \
336 ADJUST_ALIGNMENT (RVVM4x##NF##SI, 4); \
337 ADJUST_ALIGNMENT (RVVM4x##NF##SF, 4); \
338 ADJUST_ALIGNMENT (RVVM4x##NF##DI, 8); \
339 ADJUST_ALIGNMENT (RVVM4x##NF##DF, 8);
340
341 RVV_NF2_MODES (2)
342
343 /* VLS modes used as SIMD auto-vectorization for epilogue. We know the
344 return type of GET_MODE_BITSIZE is poly_uint16 or unsigned short.
345 The maximum bitsize of all vector modes is 65536 = (8192 (LMUL1) * 8),
346 even though RISC-V 'V' ISA spec allow maximum bitsize = 65536 * 8.
347
348 Note: We don't enable of vector modes of TI/TF. */
349
350 VECTOR_BOOL_MODE (V1BI, 1, BI, 1); /* V1BI */
351 VECTOR_BOOL_MODE (V2BI, 2, BI, 1); /* V2BI */
352 VECTOR_BOOL_MODE (V4BI, 4, BI, 1); /* V4BI */
353 VECTOR_BOOL_MODE (V8BI, 8, BI, 1); /* V8BI */
354 VECTOR_BOOL_MODE (V16BI, 16, BI, 2); /* V16BI */
355 VECTOR_BOOL_MODE (V32BI, 32, BI, 4); /* V32BI */
356 VECTOR_BOOL_MODE (V64BI, 64, BI, 8); /* V64BI */
357 VECTOR_BOOL_MODE (V128BI, 128, BI, 16); /* V128BI */
358 VECTOR_BOOL_MODE (V256BI, 256, BI, 32); /* V256BI */
359 VECTOR_BOOL_MODE (V512BI, 512, BI, 64); /* V512BI */
360 VECTOR_BOOL_MODE (V1024BI, 1024, BI, 128); /* V1024BI */
361 VECTOR_BOOL_MODE (V2048BI, 2048, BI, 256); /* V2048BI */
362 VECTOR_BOOL_MODE (V4096BI, 4096, BI, 512); /* V4096BI */
363
364 ADJUST_ALIGNMENT (V1BI, 1);
365 ADJUST_ALIGNMENT (V2BI, 1);
366 ADJUST_ALIGNMENT (V4BI, 1);
367 ADJUST_ALIGNMENT (V8BI, 1);
368 ADJUST_ALIGNMENT (V16BI, 1);
369 ADJUST_ALIGNMENT (V32BI, 1);
370 ADJUST_ALIGNMENT (V64BI, 1);
371 ADJUST_ALIGNMENT (V128BI, 1);
372 ADJUST_ALIGNMENT (V256BI, 1);
373 ADJUST_ALIGNMENT (V512BI, 1);
374 ADJUST_ALIGNMENT (V1024BI, 1);
375 ADJUST_ALIGNMENT (V2048BI, 1);
376 ADJUST_ALIGNMENT (V4096BI, 1);
377
378 ADJUST_PRECISION (V1BI, 1);
379 ADJUST_PRECISION (V2BI, 2);
380 ADJUST_PRECISION (V4BI, 4);
381 ADJUST_PRECISION (V8BI, 8);
382 ADJUST_PRECISION (V16BI, 16);
383 ADJUST_PRECISION (V32BI, 32);
384 ADJUST_PRECISION (V64BI, 64);
385 ADJUST_PRECISION (V128BI, 128);
386 ADJUST_PRECISION (V256BI, 256);
387 ADJUST_PRECISION (V512BI, 512);
388 ADJUST_PRECISION (V1024BI, 1024);
389 ADJUST_PRECISION (V2048BI, 2048);
390 ADJUST_PRECISION (V4096BI, 4096);
391
392 #define VLS_MODES(NBYTES) \
393 VECTOR_MODE_WITH_PREFIX (V, INT, QI, NBYTES, 1); \
394 VECTOR_MODE_WITH_PREFIX (V, INT, HI, NBYTES / 2, 1); \
395 VECTOR_MODE_WITH_PREFIX (V, INT, SI, NBYTES / 4, 1); \
396 VECTOR_MODE_WITH_PREFIX (V, INT, DI, NBYTES / 8, 1); \
397 VECTOR_MODE_WITH_PREFIX (V, FLOAT, HF, NBYTES / 2, 1); \
398 VECTOR_MODE_WITH_PREFIX (V, FLOAT, SF, NBYTES / 4, 1); \
399 VECTOR_MODE_WITH_PREFIX (V, FLOAT, DF, NBYTES / 8, 1);
400
401 VECTOR_MODE_WITH_PREFIX (V, INT, QI, 1, 1); /* V1QI */
402 VECTOR_MODE_WITH_PREFIX (V, INT, HI, 1, 1); /* V1HI */
403 VECTOR_MODE_WITH_PREFIX (V, INT, SI, 1, 1); /* V1SI */
404 VECTOR_MODE_WITH_PREFIX (V, INT, DI, 1, 1); /* V1DI */
405 VECTOR_MODE_WITH_PREFIX (V, FLOAT, HF, 1, 1); /* V1HF */
406 VECTOR_MODE_WITH_PREFIX (V, FLOAT, SF, 1, 1); /* V1SF */
407 VECTOR_MODE_WITH_PREFIX (V, FLOAT, DF, 1, 1); /* V1DF */
408 VECTOR_MODE_WITH_PREFIX (V, INT, QI, 2, 1); /* V2QI */
409 VECTOR_MODE_WITH_PREFIX (V, INT, QI, 4, 1); /* V4QI */
410 VECTOR_MODE_WITH_PREFIX (V, INT, QI, 8, 1); /* V8QI */
411 VECTOR_MODE_WITH_PREFIX (V, INT, HI, 2, 1); /* V2HI */
412 VECTOR_MODE_WITH_PREFIX (V, INT, HI, 4, 1); /* V4HI */
413 VECTOR_MODE_WITH_PREFIX (V, FLOAT, HF, 2, 1); /* V2HF */
414 VECTOR_MODE_WITH_PREFIX (V, FLOAT, HF, 4, 1); /* V4HF */
415 VECTOR_MODE_WITH_PREFIX (V, INT, SI, 2, 1); /* V2SI */
416 VECTOR_MODE_WITH_PREFIX (V, FLOAT, SF, 2, 1); /* V2SF */
417 VLS_MODES (16); /* V16QI V8HI V4SI V2DI V8HF V4SF V2DF */
418 VLS_MODES (32); /* V32QI V16HI V8SI V4DI V16HF V8SF V4DF */
419 VLS_MODES (64); /* V64QI V32HI V16SI V8DI V32HF V16SF V8DF */
420 VLS_MODES (128); /* V128QI V64HI V32SI V16DI V64HF V32SF V16DF */
421 VLS_MODES (256); /* V256QI V128HI V64SI V32DI V128HF V64SF V32DF */
422 VLS_MODES (512); /* V512QI V256HI V128SI V64DI V256HF V128SF V64DF */
423 VLS_MODES (1024); /* V1024QI V512HI V256SI V128DI V512HF V256SF V128DF */
424 VLS_MODES (2048); /* V2048QI V1024HI V512SI V256DI V1024HF V512SF V256DF */
425 VLS_MODES (4096); /* V4096QI V2048HI V1024SI V512DI V2048HF V1024SF V512DF */
426
427 /* TODO: According to RISC-V 'V' ISA spec, the maximum vector length can
428 be 65536 for a single vector register which means the vector mode in
429 GCC can be maximum = 65536 * 8 bits (LMUL=8).
430 However, 'GET_MODE_SIZE' is using poly_uint16/unsigned short which will
431 overflow if we specify vector-length = 65536. To support this feature,
432 we need to change the codes outside the RISC-V port. We will support it in
433 the future. */
434 #define MAX_BITSIZE_MODE_ANY_MODE (4096 * 8)
435
436 /* Coefficient 1 is multiplied by the number of 64-bit/32-bit chunks in a vector
437 minus one. */
438 #define NUM_POLY_INT_COEFFS 2
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