gcc/config/riscv/sifive-vector.md

   1 ;; Machine description for RISC-V for GNU compiler.
   2 ;; Copyright (C) 2024-2025 Free Software Foundation, Inc.
   3 ;; Contributed by SiFive and PLCT Lab.
   4 ;; Based on RISC-V target for GNU compiler.
   5
   6 ;; This file is part of GCC.
   7
   8 ;; GCC is free software; you can redistribute it and/or modify
   9 ;; it under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 3, or (at your option)
  11 ;; any later version.
  12
  13 ;; GCC is distributed in the hope that it will be useful,
  14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;; GNU General Public License for more details.
  17
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22 (define_insn "@pred_matrix_mul_plus<u><mode>_qoq"
  23   [(set (match_operand:SF_VSI 0 "register_operand"                    "=&vr")
  24         (if_then_else:SF_VSI
  25           (unspec:<VM>
  26             [(match_operand:<VM> 1 "vector_mask_operand"             "vmWc1")
  27              (match_operand 5 "vector_length_operand"                "   rK")
  28              (match_operand 6 "const_int_operand"                    "    i")
  29              (match_operand 7 "const_int_operand"                    "    i")
  30              (match_operand 8 "const_int_operand"                    "    i")
  31              (reg:SI VL_REGNUM)
  32              (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
  33           (plus:SF_VSI
  34             (mult:SF_VSI
  35               (any_extend:SF_VSI
  36                 (match_operand:RVVM1QI 3 "register_operand" "   vr"))
  37               (any_extend:SF_VSI
  38                 (match_operand:<SF_VQMACC_QOQ> 4 "register_operand" "   vr")))
  39             (match_operand:SF_VSI 2 "register_operand"              "    0"))
  40           (match_dup 2)))]
  41   "TARGET_VECTOR && TARGET_XSFVQMACCQOQ"
  42   "sf.vqmacc<u>.4x8x4\t%0,%3,%4"
  43   [(set_attr "type" "sf_vqmacc")
  44    (set_attr "mode" "<MODE>")])
  45
  46 (define_insn "@pred_matrix_mul_plussu<mode>_qoq"
  47   [(set (match_operand:SF_VSI 0 "register_operand"                    "=&vr")
  48         (if_then_else:SF_VSI
  49           (unspec:<VM>
  50             [(match_operand:<VM> 1 "vector_mask_operand"             "vmWc1")
  51              (match_operand 5 "vector_length_operand"                "   rK")
  52              (match_operand 6 "const_int_operand"                    "    i")
  53              (match_operand 7 "const_int_operand"                    "    i")
  54              (match_operand 8 "const_int_operand"                    "    i")
  55              (reg:SI VL_REGNUM)
  56              (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
  57           (plus:SF_VSI
  58             (mult:SF_VSI
  59               (sign_extend:SF_VSI
  60                 (match_operand:RVVM1QI 3 "register_operand" "   vr"))
  61               (zero_extend:SF_VSI
  62                 (match_operand:<SF_VQMACC_QOQ> 4 "register_operand" "   vr")))
  63             (match_operand:SF_VSI 2 "register_operand"              "    0"))
  64           (match_dup 2)))]
  65   "TARGET_VECTOR && TARGET_XSFVQMACCQOQ"
  66   "sf.vqmaccsu.4x8x4\t%0,%3,%4"
  67   [(set_attr "type" "sf_vqmacc")
  68    (set_attr "mode" "<MODE>")])
  69
  70 (define_insn "@pred_matrix_mul_plusus<mode>_qoq"
  71   [(set (match_operand:SF_VSI 0 "register_operand"                    "=&vr")
  72         (if_then_else:SF_VSI
  73           (unspec:<VM>
  74             [(match_operand:<VM> 1 "vector_mask_operand"             "vmWc1")
  75              (match_operand 5 "vector_length_operand"                "   rK")
  76              (match_operand 6 "const_int_operand"                    "    i")
  77              (match_operand 7 "const_int_operand"                    "    i")
  78              (match_operand 8 "const_int_operand"                    "    i")
  79              (reg:SI VL_REGNUM)
  80              (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
  81           (plus:SF_VSI
  82             (mult:SF_VSI
  83               (zero_extend:SF_VSI
  84                 (match_operand:RVVM1QI 3 "register_operand" "   vr"))
  85               (sign_extend:SF_VSI
  86                 (match_operand:<SF_VQMACC_QOQ> 4 "register_operand" "   vr")))
  87             (match_operand:SF_VSI 2 "register_operand"              "    0"))
  88           (match_dup 2)))]
  89   "TARGET_VECTOR && TARGET_XSFVQMACCQOQ"
  90   "sf.vqmaccus.4x8x4\t%0,%3,%4"
  91   [(set_attr "type" "sf_vqmacc")
  92    (set_attr "mode" "<MODE>")])
  93
  94 (define_insn "@pred_matrix_mul_plus<u><mode>_dod"
  95   [(set (match_operand:SF_VSI 0 "register_operand"                    "=&vr")
  96         (if_then_else:SF_VSI
  97           (unspec:<VM>
  98             [(match_operand:<VM> 1 "vector_mask_operand"             "vmWc1")
  99              (match_operand 5 "vector_length_operand"                "   rK")
 100              (match_operand 6 "const_int_operand"                    "    i")
 101              (match_operand 7 "const_int_operand"                    "    i")
 102              (match_operand 8 "const_int_operand"                    "    i")
 103              (reg:SI VL_REGNUM)
 104              (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 105           (plus:SF_VSI
 106             (mult:SF_VSI
 107               (any_extend:SF_VSI
 108                 (match_operand:RVVM1QI 3 "register_operand" "   vr"))
 109               (any_extend:SF_VSI
 110                 (match_operand:<SF_VQMACC_DOD> 4 "register_operand" "   vr")))
 111             (match_operand:SF_VSI 2 "register_operand"              "    0"))
 112           (match_dup 2)))]
 113   "TARGET_VECTOR && TARGET_XSFVQMACCDOD"
 114   "sf.vqmacc<u>.2x8x2\t%0,%3,%4"
 115   [(set_attr "type" "sf_vqmacc")
 116    (set_attr "mode" "<MODE>")])
 117
 118 (define_insn "@pred_matrix_mul_plussu<mode>_dod"
 119   [(set (match_operand:SF_VSI 0 "register_operand"                    "=&vr")
 120         (if_then_else:SF_VSI
 121           (unspec:<VM>
 122             [(match_operand:<VM> 1 "vector_mask_operand"             "vmWc1")
 123              (match_operand 5 "vector_length_operand"                "   rK")
 124              (match_operand 6 "const_int_operand"                    "    i")
 125              (match_operand 7 "const_int_operand"                    "    i")
 126              (match_operand 8 "const_int_operand"                    "    i")
 127              (reg:SI VL_REGNUM)
 128              (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 129           (plus:SF_VSI
 130             (mult:SF_VSI
 131               (sign_extend:SF_VSI
 132                 (match_operand:RVVM1QI 3 "register_operand" "   vr"))
 133               (zero_extend:SF_VSI
 134                 (match_operand:<SF_VQMACC_DOD> 4 "register_operand" "   vr")))
 135             (match_operand:SF_VSI 2 "register_operand"              "    0"))
 136           (match_dup 2)))]
 137   "TARGET_VECTOR && TARGET_XSFVQMACCDOD"
 138   "sf.vqmaccsu.2x8x2\t%0,%3,%4"
 139   [(set_attr "type" "sf_vqmacc")
 140    (set_attr "mode" "<MODE>")])
 141
 142 (define_insn "@pred_matrix_mul_plusus<mode>_dod"
 143   [(set (match_operand:SF_VSI 0 "register_operand"                    "=&vr")
 144         (if_then_else:SF_VSI
 145           (unspec:<VM>
 146             [(match_operand:<VM> 1 "vector_mask_operand"             "vmWc1")
 147              (match_operand 5 "vector_length_operand"                "   rK")
 148              (match_operand 6 "const_int_operand"                    "    i")
 149              (match_operand 7 "const_int_operand"                    "    i")
 150              (match_operand 8 "const_int_operand"                    "    i")
 151              (reg:SI VL_REGNUM)
 152              (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 153           (plus:SF_VSI
 154             (mult:SF_VSI
 155               (zero_extend:SF_VSI
 156                 (match_operand:RVVM1QI 3 "register_operand" "   vr"))
 157               (sign_extend:SF_VSI
 158                 (match_operand:<SF_VQMACC_DOD> 4 "register_operand" "   vr")))
 159             (match_operand:SF_VSI 2 "register_operand"              "    0"))
 160           (match_dup 2)))]
 161   "TARGET_VECTOR && TARGET_XSFVQMACCDOD"
 162   "sf.vqmaccus.2x8x2\t%0,%3,%4"
 163   [(set_attr "type" "sf_vqmacc")
 164    (set_attr "mode" "<MODE>")])
 165
 166 (define_insn "@pred_sf_vfnrclip<v_su><mode>_x_f_qf"
 167   [(set (match_operand:SF_XF 0 "register_operand"        "=vd, vd, vr, vr")
 168         (if_then_else:SF_XF
 169           (unspec:<VM>
 170             [(match_operand:<VM> 1 "vector_mask_operand"     " vm, vm,Wc1,Wc1")
 171              (match_operand 5 "vector_length_operand"        " rK, rK, rK, rK")
 172              (match_operand 6 "const_int_operand"            "  i,  i,  i,  i")
 173              (match_operand 7 "const_int_operand"            "  i,  i,  i,  i")
 174              (match_operand 8 "const_int_operand"            "  i,  i,  i,  i")
 175              (reg:SI VL_REGNUM)
 176              (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 177           (unspec:SF_XF
 178             [(match_operand:SF 4 "register_operand"          "  f,  f,  f,  f")
 179              (match_operand:<SF_XFQF> 3 "register_operand"       " vr, vr, vr, vr")] SF_VFNRCLIP)
 180           (match_operand:SF_XF 2 "vector_merge_operand"  " vu,  0, vu,  0")))]
 181   "TARGET_VECTOR && TARGET_XSFVFNRCLIPXFQF"
 182   "sf.vfnrclip.x<v_su>.f.qf\t%0,%3,%4%p1"
 183   [(set_attr "type" "sf_vfnrclip")
 184    (set_attr "mode" "<MODE>")])