gcc/config/riscv/vector-bfloat16.md

   1 ;; Machine description for RISC-V bfloat16 extensions.
   2 ;; Copyright (C) 2024-2025 Free Software Foundation, Inc.
   3
   4 ;; This file is part of GCC.
   5
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 (define_mode_iterator VWEXTF_ZVFBF [
  21   (RVVM8SF  "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32")
  22   (RVVM4SF  "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32")
  23   (RVVM2SF  "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32")
  24   (RVVM1SF  "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32")
  25   (RVVMF2SF "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
  26 ])
  27
  28 (define_mode_attr V_FP32TOBF16_TRUNC [
  29   (RVVM8SF "RVVM4BF") (RVVM4SF "RVVM2BF") (RVVM2SF "RVVM1BF") (RVVM1SF "RVVMF2BF") (RVVMF2SF "RVVMF4BF")
  30 ])
  31
  32 (define_mode_attr VF32_SUBEL [
  33    (RVVM8SF "BF") (RVVM4SF "BF") (RVVM2SF "BF") (RVVM1SF "BF") (RVVMF2SF "BF")])
  34
  35 ;; Zvfbfmin extension
  36
  37 (define_insn "@pred_trunc<mode>_to_bf16"
  38   [(set (match_operand:<V_FP32TOBF16_TRUNC> 0 "register_operand"   "=vd, vd, vr, vr,  &vr,  &vr")
  39      (if_then_else:<V_FP32TOBF16_TRUNC>
  40        (unspec:<VM>
  41          [(match_operand:<VM> 1 "vector_mask_operand"              " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
  42           (match_operand 4 "vector_length_operand"                 " rK, rK, rK, rK,   rK,   rK")
  43           (match_operand 5 "const_int_operand"                     "  i,  i,  i,  i,    i,    i")
  44           (match_operand 6 "const_int_operand"                     "  i,  i,  i,  i,    i,    i")
  45           (match_operand 7 "const_int_operand"                     "  i,  i,  i,  i,    i,    i")
  46           (match_operand 8 "const_int_operand"                     "  i,  i,  i,  i,    i,    i")
  47           (reg:SI VL_REGNUM)
  48           (reg:SI VTYPE_REGNUM)
  49           (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
  50        (float_truncate:<V_FP32TOBF16_TRUNC>
  51           (match_operand:VWEXTF_ZVFBF 3 "register_operand"          "  0,  0,  0,  0,   vr,   vr"))
  52        (match_operand:<V_FP32TOBF16_TRUNC> 2 "vector_merge_operand" " vu,  0, vu,  0,   vu,    0")))]
  53   "TARGET_ZVFBFMIN"
  54   "vfncvtbf16.f.f.w\t%0,%3%p1"
  55   [(set_attr "type" "vfncvtbf16")
  56    (set_attr "mode" "<V_FP32TOBF16_TRUNC>")
  57    (set (attr "frm_mode")
  58         (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
  59
  60 (define_insn "@pred_extend_bf16_to_<mode>"
  61   [(set (match_operand:VWEXTF_ZVFBF 0 "register_operand"          "=&vr,  &vr")
  62     (if_then_else:VWEXTF_ZVFBF
  63       (unspec:<VM>
  64         [(match_operand:<VM> 1 "vector_mask_operand"              "vmWc1,vmWc1")
  65          (match_operand 4 "vector_length_operand"                 "   rK,   rK")
  66          (match_operand 5 "const_int_operand"                     "    i,    i")
  67          (match_operand 6 "const_int_operand"                     "    i,    i")
  68          (match_operand 7 "const_int_operand"                     "    i,    i")
  69          (reg:SI VL_REGNUM)
  70          (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
  71       (float_extend:VWEXTF_ZVFBF
  72          (match_operand:<V_FP32TOBF16_TRUNC> 3 "register_operand" "   vr,   vr"))
  73       (match_operand:VWEXTF_ZVFBF 2 "vector_merge_operand"        "   vu,    0")))]
  74   "TARGET_ZVFBFMIN"
  75   "vfwcvtbf16.f.f.v\t%0,%3%p1"
  76   [(set_attr "type" "vfwcvtbf16")
  77    (set_attr "mode" "<V_FP32TOBF16_TRUNC>")])
  78
  79
  80 (define_insn "@pred_widen_bf16_mul_<mode>"
  81   [(set (match_operand:VWEXTF_ZVFBF 0 "register_operand"             "=&vr")
  82     (if_then_else:VWEXTF_ZVFBF
  83       (unspec:<VM>
  84         [(match_operand:<VM> 1 "vector_mask_operand"                 "vmWc1")
  85          (match_operand 5 "vector_length_operand"                    "   rK")
  86          (match_operand 6 "const_int_operand"                        "    i")
  87          (match_operand 7 "const_int_operand"                        "    i")
  88          (match_operand 8 "const_int_operand"                        "    i")
  89          (match_operand 9 "const_int_operand"                        "    i")
  90          (reg:SI VL_REGNUM)
  91          (reg:SI VTYPE_REGNUM)
  92          (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
  93       (plus:VWEXTF_ZVFBF
  94         (mult:VWEXTF_ZVFBF
  95           (float_extend:VWEXTF_ZVFBF
  96             (match_operand:<V_FP32TOBF16_TRUNC> 3 "register_operand" "   vr"))
  97           (float_extend:VWEXTF_ZVFBF
  98             (match_operand:<V_FP32TOBF16_TRUNC> 4 "register_operand" "   vr")))
  99         (match_operand:VWEXTF_ZVFBF 2 "register_operand"             "    0"))
 100       (match_dup 2)))]
 101   "TARGET_ZVFBFWMA"
 102   "vfwmaccbf16.vv\t%0,%3,%4%p1"
 103   [(set_attr "type" "vfwmaccbf16")
 104    (set_attr "mode" "<V_FP32TOBF16_TRUNC>")
 105    (set (attr "frm_mode")
 106         (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
 107
 108 (define_insn "@pred_widen_bf16_mul_<mode>_scalar"
 109   [(set (match_operand:VWEXTF_ZVFBF 0 "register_operand"             "=&vr")
 110     (if_then_else:VWEXTF_ZVFBF
 111       (unspec:<VM>
 112         [(match_operand:<VM> 1 "vector_mask_operand"                 "vmWc1")
 113          (match_operand 5 "vector_length_operand"                    "   rK")
 114          (match_operand 6 "const_int_operand"                        "    i")
 115          (match_operand 7 "const_int_operand"                        "    i")
 116          (match_operand 8 "const_int_operand"                        "    i")
 117          (match_operand 9 "const_int_operand"                        "    i")
 118          (reg:SI VL_REGNUM)
 119          (reg:SI VTYPE_REGNUM)
 120          (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 121       (plus:VWEXTF_ZVFBF
 122         (mult:VWEXTF_ZVFBF
 123           (float_extend:VWEXTF_ZVFBF
 124             (vec_duplicate:<V_FP32TOBF16_TRUNC>
 125               (match_operand:<VF32_SUBEL> 3 "register_operand"       "    f")))
 126           (float_extend:VWEXTF_ZVFBF
 127             (match_operand:<V_FP32TOBF16_TRUNC> 4 "register_operand" "   vr")))
 128         (match_operand:VWEXTF_ZVFBF 2 "register_operand"             "    0"))
 129       (match_dup 2)))]
 130   "TARGET_ZVFBFWMA"
 131   "vfwmaccbf16.vf\t%0,%3,%4%p1"
 132   [(set_attr "type" "vfwmaccbf16")
 133    (set_attr "mode" "<V_FP32TOBF16_TRUNC>")
 134    (set (attr "frm_mode")
 135         (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])