| blob | cf22b39d6cb37886f1699a1c0f5ae5cb19ab040b |
1 ;; Machine description for RISC-V 'V' Extension for GNU compiler.
2 ;; Copyright (C) 2022-2025 Free Software Foundation, Inc.
3 ;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; This file describes the RISC-V 'V' Extension, Version 1.0.
22 ;;
23 ;; This file include :
24 ;;
25 ;; - Intrinsics (https://github.com/riscv/rvv-intrinsic-doc)
26 ;; - Auto-vectorization (autovec.md)
27 ;; - Optimization (autovec-opt.md)
29 (include "vector-iterators.md")
31 (define_constants [
32 (INVALID_ATTRIBUTE 255)
33 (X0_REGNUM 0)
34 ])
36 ;; True if the type is RVV instructions that include VTYPE
37 ;; global status register in the use op list.
38 ;; We known VTYPE has 4 fields: SEW, LMUL, TA, MA.
39 ;; The instruction need any of VTYPE field is set as true
40 ;; in this attribute.
41 (define_attr "has_vtype_op" "false,true"
42 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,\
43 vldux,vldox,vstux,vstox,vldff,\
44 vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,\
45 vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,
46 vmov,vimov,\
47 vsalu,vaalu,vsmul,vsshift,vnclip,\
48 vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp,\
49 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
50 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,\
51 vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
52 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
53 vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv,\
54 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
55 vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\
56 vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,\
57 vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
58 vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\
59 vfncvtbf16,vfwcvtbf16,vfwmaccbf16,\
60 sf_vqmacc,sf_vfnrclip")
61 (const_string "true")]
62 (const_string "false")))
64 ;; True if the type is RVV instructions that include VL
65 ;; global status register in the use op list.
66 ;; The instruction need vector length to be specified is set
67 ;; in this attribute.
68 (define_attr "has_vl_op" "false,true"
69 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,\
70 vldux,vldox,vstux,vstox,vldff,\
71 vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,\
72 vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,\
73 vsalu,vaalu,vsmul,vsshift,vnclip,\
74 vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp,\
75 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
76 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,\
77 vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
78 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
79 vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovxv,vfmovfv,\
80 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
81 vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\
82 vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,\
83 vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
84 vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\
85 vfncvtbf16,vfwcvtbf16,vfwmaccbf16")
86 (const_string "true")]
87 (const_string "false")))
89 ;; The default SEW of RVV instruction. This attribute doesn't mean the instruction
90 ;; is necessary to require SEW check for example vlm.v which require ratio to
91 ;; check. However, we need default value of SEW for vsetvl instruction since there
92 ;; is no field for ratio in the vsetvl instruction encoding.
93 (define_attr "sew" ""
94 (cond [(eq_attr "mode" "RVVMF8BI,RVVMF4BI,RVVMF2BI,RVVM1BI,\
95 RVVM8QI,RVVM4QI,RVVM2QI,RVVM1QI,RVVMF2QI,RVVMF4QI,RVVMF8QI,\
96 RVVM1x8QI,RVVMF2x8QI,RVVMF4x8QI,RVVMF8x8QI,\
97 RVVM1x7QI,RVVMF2x7QI,RVVMF4x7QI,RVVMF8x7QI,\
98 RVVM1x6QI,RVVMF2x6QI,RVVMF4x6QI,RVVMF8x6QI,\
99 RVVM1x5QI,RVVMF2x5QI,RVVMF4x5QI,RVVMF8x5QI,\
100 RVVM2x4QI,RVVM1x4QI,RVVMF2x4QI,RVVMF4x4QI,RVVMF8x4QI,\
101 RVVM2x3QI,RVVM1x3QI,RVVMF2x3QI,RVVMF4x3QI,RVVMF8x3QI,\
102 RVVM4x2QI,RVVM2x2QI,RVVM1x2QI,RVVMF2x2QI,RVVMF4x2QI,RVVMF8x2QI,\
103 V1QI,V2QI,V4QI,V8QI,V16QI,V32QI,V64QI,V128QI,V256QI,V512QI,V1024QI,V2048QI,V4096QI,\
104 V1BI,V2BI,V4BI,V8BI,V16BI,V32BI,V64BI,V128BI,V256BI,V512BI,V1024BI,V2048BI,V4096BI")
105 (const_int 8)
106 (eq_attr "mode" "RVVMF16BI")
107 (if_then_else (match_test "TARGET_XTHEADVECTOR")
108 (const_int 16)
109 (const_int 8))
110 (eq_attr "mode" "RVVMF32BI")
111 (if_then_else (match_test "TARGET_XTHEADVECTOR")
112 (const_int 32)
113 (const_int 8))
114 (eq_attr "mode" "RVVMF64BI")
115 (if_then_else (match_test "TARGET_XTHEADVECTOR")
116 (const_int 64)
117 (const_int 8))
118 (eq_attr "mode" "RVVM8HI,RVVM4HI,RVVM2HI,RVVM1HI,RVVMF2HI,RVVMF4HI,\
119 RVVM1x8HI,RVVMF2x8HI,RVVMF4x8HI,\
120 RVVM1x7HI,RVVMF2x7HI,RVVMF4x7HI,\
121 RVVM1x6HI,RVVMF2x6HI,RVVMF4x6HI,\
122 RVVM1x5HI,RVVMF2x5HI,RVVMF4x5HI,\
123 RVVM2x4HI,RVVM1x4HI,RVVMF2x4HI,RVVMF4x4HI,\
124 RVVM2x3HI,RVVM1x3HI,RVVMF2x3HI,RVVMF4x3HI,\
125 RVVM4x2HI,RVVM2x2HI,RVVM1x2HI,RVVMF2x2HI,RVVMF4x2HI,\
126 RVVM8BF,RVVM4BF,RVVM2BF,RVVM1BF,RVVMF2BF,RVVMF4BF,\
127 RVVM1x8BF,RVVMF2x8BF,RVVMF4x8BF,\
128 RVVM1x7BF,RVVMF2x7BF,RVVMF4x7BF,\
129 RVVM1x6BF,RVVMF2x6BF,RVVMF4x6BF,\
130 RVVM1x5BF,RVVMF2x5BF,RVVMF4x5BF,\
131 RVVM2x4BF,RVVM1x4BF,RVVMF2x4BF,RVVMF4x4BF,\
132 RVVM2x3BF,RVVM1x3BF,RVVMF2x3BF,RVVMF4x3BF,\
133 RVVM4x2BF,RVVM2x2BF,RVVM1x2BF,RVVMF2x2BF,RVVMF4x2BF,\
134 RVVM8HF,RVVM4HF,RVVM2HF,RVVM1HF,RVVMF2HF,RVVMF4HF,\
135 RVVM1x8HF,RVVMF2x8HF,RVVMF4x8HF,\
136 RVVM1x7HF,RVVMF2x7HF,RVVMF4x7HF,\
137 RVVM1x6HF,RVVMF2x6HF,RVVMF4x6HF,\
138 RVVM1x5HF,RVVMF2x5HF,RVVMF4x5HF,\
139 RVVM2x4HF,RVVM1x4HF,RVVMF2x4HF,RVVMF4x4HF,\
140 RVVM2x3HF,RVVM1x3HF,RVVMF2x3HF,RVVMF4x3HF,\
141 RVVM4x2HF,RVVM2x2HF,RVVM1x2HF,RVVMF2x2HF,RVVMF4x2HF,\
142 V1HI,V2HI,V4HI,V8HI,V16HI,V32HI,V64HI,V128HI,V256HI,V512HI,V1024HI,V2048HI,\
143 V1HF,V2HF,V4HF,V8HF,V16HF,V32HF,V64HF,V128HF,V256HF,V512HF,V1024HF,V2048HF")
144 (const_int 16)
145 (eq_attr "mode" "RVVM8SI,RVVM4SI,RVVM2SI,RVVM1SI,RVVMF2SI,\
146 RVVM8SF,RVVM4SF,RVVM2SF,RVVM1SF,RVVMF2SF,\
147 RVVM1x8SI,RVVMF2x8SI,\
148 RVVM1x7SI,RVVMF2x7SI,\
149 RVVM1x6SI,RVVMF2x6SI,\
150 RVVM1x5SI,RVVMF2x5SI,\
151 RVVMF2x4SI,RVVMF2x3SI,\
152 RVVM2x4SI,RVVM1x4SI,\
153 RVVM2x3SI,RVVM1x3SI,\
154 RVVM4x2SI,RVVM2x2SI,RVVM1x2SI,RVVMF2x2SI,\
155 RVVM1x8SF,RVVMF2x8SF,\
156 RVVM1x7SF,RVVMF2x7SF,\
157 RVVM1x6SF,RVVMF2x6SF,\
158 RVVM1x5SF,RVVMF2x5SF,\
159 RVVM2x4SF,RVVM1x4SF,RVVMF2x4SF,\
160 RVVM2x3SF,RVVM1x3SF,RVVMF2x3SF,\
161 RVVM4x2SF,RVVM2x2SF,RVVM1x2SF,RVVMF2x2SF,\
162 V1SI,V2SI,V4SI,V8SI,V16SI,V32SI,V64SI,V128SI,V256SI,V512SI,V1024SI,\
163 V1SF,V2SF,V4SF,V8SF,V16SF,V32SF,V64SF,V128SF,V256SF,V512SF,V1024SF")
164 (const_int 32)
165 (eq_attr "mode" "RVVM8DI,RVVM4DI,RVVM2DI,RVVM1DI,\
166 RVVM8DF,RVVM4DF,RVVM2DF,RVVM1DF,\
167 RVVM1x8DI,RVVM1x7DI,RVVM1x6DI,RVVM1x5DI,\
168 RVVM2x4DI,RVVM1x4DI,\
169 RVVM2x3DI,RVVM1x3DI,\
170 RVVM4x2DI,RVVM2x2DI,RVVM1x2DI,\
171 RVVM1x8DF,RVVM1x7DF,RVVM1x6DF,RVVM1x5DF,\
172 RVVM2x4DF,RVVM1x4DF,\
173 RVVM2x3DF,RVVM1x3DF,\
174 RVVM4x2DF,RVVM2x2DF,RVVM1x2DF,\
175 V1DI,V2DI,V4DI,V8DI,V16DI,V32DI,V64DI,V128DI,V256DI,V512DI,\
176 V1DF,V2DF,V4DF,V8DF,V16DF,V32DF,V64DF,V128DF,V256DF,V512DF")
177 (const_int 64)]
178 (const_int INVALID_ATTRIBUTE)))
180 ;; Ditto to LMUL.
181 (define_attr "vlmul" ""
182 (cond [(eq_attr "mode" "RVVM8QI,RVVM1BI") (symbol_ref "riscv_vector::LMUL_8")
183 (eq_attr "mode" "RVVM4QI,RVVMF2BI") (symbol_ref "riscv_vector::LMUL_4")
184 (eq_attr "mode" "RVVM2QI,RVVMF4BI") (symbol_ref "riscv_vector::LMUL_2")
185 (eq_attr "mode" "RVVM1QI,RVVMF8BI") (symbol_ref "riscv_vector::LMUL_1")
186 (eq_attr "mode" "RVVMF2QI,RVVMF16BI") (symbol_ref "TARGET_XTHEADVECTOR ? riscv_vector::LMUL_1 : riscv_vector::LMUL_F2")
187 (eq_attr "mode" "RVVMF4QI,RVVMF32BI") (symbol_ref "TARGET_XTHEADVECTOR ? riscv_vector::LMUL_1 : riscv_vector::LMUL_F4")
188 (eq_attr "mode" "RVVMF8QI,RVVMF64BI") (symbol_ref "TARGET_XTHEADVECTOR ? riscv_vector::LMUL_1 : riscv_vector::LMUL_F8")
189 (eq_attr "mode" "RVVM8HI") (symbol_ref "riscv_vector::LMUL_8")
190 (eq_attr "mode" "RVVM4HI") (symbol_ref "riscv_vector::LMUL_4")
191 (eq_attr "mode" "RVVM2HI") (symbol_ref "riscv_vector::LMUL_2")
192 (eq_attr "mode" "RVVM1HI") (symbol_ref "riscv_vector::LMUL_1")
193 (eq_attr "mode" "RVVMF2HI") (symbol_ref "riscv_vector::LMUL_F2")
194 (eq_attr "mode" "RVVMF4HI") (symbol_ref "riscv_vector::LMUL_F4")
195 (eq_attr "mode" "RVVM8BF") (symbol_ref "riscv_vector::LMUL_8")
196 (eq_attr "mode" "RVVM4BF") (symbol_ref "riscv_vector::LMUL_4")
197 (eq_attr "mode" "RVVM2BF") (symbol_ref "riscv_vector::LMUL_2")
198 (eq_attr "mode" "RVVM1BF") (symbol_ref "riscv_vector::LMUL_1")
199 (eq_attr "mode" "RVVMF2BF") (symbol_ref "riscv_vector::LMUL_F2")
200 (eq_attr "mode" "RVVMF4BF") (symbol_ref "riscv_vector::LMUL_F4")
201 (eq_attr "mode" "RVVM8HF") (symbol_ref "riscv_vector::LMUL_8")
202 (eq_attr "mode" "RVVM4HF") (symbol_ref "riscv_vector::LMUL_4")
203 (eq_attr "mode" "RVVM2HF") (symbol_ref "riscv_vector::LMUL_2")
204 (eq_attr "mode" "RVVM1HF") (symbol_ref "riscv_vector::LMUL_1")
205 (eq_attr "mode" "RVVMF2HF") (symbol_ref "riscv_vector::LMUL_F2")
206 (eq_attr "mode" "RVVMF4HF") (symbol_ref "riscv_vector::LMUL_F4")
207 (eq_attr "mode" "RVVM8SI") (symbol_ref "riscv_vector::LMUL_8")
208 (eq_attr "mode" "RVVM4SI") (symbol_ref "riscv_vector::LMUL_4")
209 (eq_attr "mode" "RVVM2SI") (symbol_ref "riscv_vector::LMUL_2")
210 (eq_attr "mode" "RVVM1SI") (symbol_ref "riscv_vector::LMUL_1")
211 (eq_attr "mode" "RVVMF2SI") (symbol_ref "riscv_vector::LMUL_F2")
212 (eq_attr "mode" "RVVM8SF") (symbol_ref "riscv_vector::LMUL_8")
213 (eq_attr "mode" "RVVM4SF") (symbol_ref "riscv_vector::LMUL_4")
214 (eq_attr "mode" "RVVM2SF") (symbol_ref "riscv_vector::LMUL_2")
215 (eq_attr "mode" "RVVM1SF") (symbol_ref "riscv_vector::LMUL_1")
216 (eq_attr "mode" "RVVMF2SF") (symbol_ref "riscv_vector::LMUL_F2")
217 (eq_attr "mode" "RVVM8DI") (symbol_ref "riscv_vector::LMUL_8")
218 (eq_attr "mode" "RVVM4DI") (symbol_ref "riscv_vector::LMUL_4")
219 (eq_attr "mode" "RVVM2DI") (symbol_ref "riscv_vector::LMUL_2")
220 (eq_attr "mode" "RVVM1DI") (symbol_ref "riscv_vector::LMUL_1")
221 (eq_attr "mode" "RVVM8DF") (symbol_ref "riscv_vector::LMUL_8")
222 (eq_attr "mode" "RVVM4DF") (symbol_ref "riscv_vector::LMUL_4")
223 (eq_attr "mode" "RVVM2DF") (symbol_ref "riscv_vector::LMUL_2")
224 (eq_attr "mode" "RVVM1DF") (symbol_ref "riscv_vector::LMUL_1")
225 (eq_attr "mode" "RVVM1x8QI") (symbol_ref "riscv_vector::LMUL_1")
226 (eq_attr "mode" "RVVMF2x8QI") (symbol_ref "riscv_vector::LMUL_F2")
227 (eq_attr "mode" "RVVMF4x8QI") (symbol_ref "riscv_vector::LMUL_F4")
228 (eq_attr "mode" "RVVMF8x8QI") (symbol_ref "riscv_vector::LMUL_F8")
229 (eq_attr "mode" "RVVM1x7QI") (symbol_ref "riscv_vector::LMUL_1")
230 (eq_attr "mode" "RVVMF2x7QI") (symbol_ref "riscv_vector::LMUL_F2")
231 (eq_attr "mode" "RVVMF4x7QI") (symbol_ref "riscv_vector::LMUL_F4")
232 (eq_attr "mode" "RVVMF8x7QI") (symbol_ref "riscv_vector::LMUL_F8")
233 (eq_attr "mode" "RVVM1x6QI") (symbol_ref "riscv_vector::LMUL_1")
234 (eq_attr "mode" "RVVMF2x6QI") (symbol_ref "riscv_vector::LMUL_F2")
235 (eq_attr "mode" "RVVMF4x6QI") (symbol_ref "riscv_vector::LMUL_F4")
236 (eq_attr "mode" "RVVMF8x6QI") (symbol_ref "riscv_vector::LMUL_F8")
237 (eq_attr "mode" "RVVM1x5QI") (symbol_ref "riscv_vector::LMUL_1")
238 (eq_attr "mode" "RVVMF2x5QI") (symbol_ref "riscv_vector::LMUL_F2")
239 (eq_attr "mode" "RVVMF4x5QI") (symbol_ref "riscv_vector::LMUL_F4")
240 (eq_attr "mode" "RVVMF8x5QI") (symbol_ref "riscv_vector::LMUL_F8")
241 (eq_attr "mode" "RVVM2x4QI") (symbol_ref "riscv_vector::LMUL_2")
242 (eq_attr "mode" "RVVM1x4QI") (symbol_ref "riscv_vector::LMUL_1")
243 (eq_attr "mode" "RVVMF2x4QI") (symbol_ref "riscv_vector::LMUL_F2")
244 (eq_attr "mode" "RVVMF4x4QI") (symbol_ref "riscv_vector::LMUL_F4")
245 (eq_attr "mode" "RVVMF8x4QI") (symbol_ref "riscv_vector::LMUL_F8")
246 (eq_attr "mode" "RVVM2x3QI") (symbol_ref "riscv_vector::LMUL_2")
247 (eq_attr "mode" "RVVM1x3QI") (symbol_ref "riscv_vector::LMUL_1")
248 (eq_attr "mode" "RVVMF2x3QI") (symbol_ref "riscv_vector::LMUL_F2")
249 (eq_attr "mode" "RVVMF4x3QI") (symbol_ref "riscv_vector::LMUL_F4")
250 (eq_attr "mode" "RVVMF8x3QI") (symbol_ref "riscv_vector::LMUL_F8")
251 (eq_attr "mode" "RVVM4x2QI") (symbol_ref "riscv_vector::LMUL_4")
252 (eq_attr "mode" "RVVM2x2QI") (symbol_ref "riscv_vector::LMUL_2")
253 (eq_attr "mode" "RVVM1x2QI") (symbol_ref "riscv_vector::LMUL_1")
254 (eq_attr "mode" "RVVMF2x2QI") (symbol_ref "riscv_vector::LMUL_F2")
255 (eq_attr "mode" "RVVMF4x2QI") (symbol_ref "riscv_vector::LMUL_F4")
256 (eq_attr "mode" "RVVMF8x2QI") (symbol_ref "riscv_vector::LMUL_F8")
257 (eq_attr "mode" "RVVM1x8HI") (symbol_ref "riscv_vector::LMUL_1")
258 (eq_attr "mode" "RVVMF2x8HI") (symbol_ref "riscv_vector::LMUL_F2")
259 (eq_attr "mode" "RVVMF4x8HI") (symbol_ref "riscv_vector::LMUL_F4")
260 (eq_attr "mode" "RVVM1x7HI") (symbol_ref "riscv_vector::LMUL_1")
261 (eq_attr "mode" "RVVMF2x7HI") (symbol_ref "riscv_vector::LMUL_F2")
262 (eq_attr "mode" "RVVMF4x7HI") (symbol_ref "riscv_vector::LMUL_F4")
263 (eq_attr "mode" "RVVM1x6HI") (symbol_ref "riscv_vector::LMUL_1")
264 (eq_attr "mode" "RVVMF2x6HI") (symbol_ref "riscv_vector::LMUL_F2")
265 (eq_attr "mode" "RVVMF4x6HI") (symbol_ref "riscv_vector::LMUL_F4")
266 (eq_attr "mode" "RVVM1x5HI") (symbol_ref "riscv_vector::LMUL_1")
267 (eq_attr "mode" "RVVMF2x5HI") (symbol_ref "riscv_vector::LMUL_F2")
268 (eq_attr "mode" "RVVMF4x5HI") (symbol_ref "riscv_vector::LMUL_F4")
269 (eq_attr "mode" "RVVM2x4HI") (symbol_ref "riscv_vector::LMUL_2")
270 (eq_attr "mode" "RVVM1x4HI") (symbol_ref "riscv_vector::LMUL_1")
271 (eq_attr "mode" "RVVMF2x4HI") (symbol_ref "riscv_vector::LMUL_F2")
272 (eq_attr "mode" "RVVMF4x4HI") (symbol_ref "riscv_vector::LMUL_F4")
273 (eq_attr "mode" "RVVM2x3HI") (symbol_ref "riscv_vector::LMUL_2")
274 (eq_attr "mode" "RVVM1x3HI") (symbol_ref "riscv_vector::LMUL_1")
275 (eq_attr "mode" "RVVMF2x3HI") (symbol_ref "riscv_vector::LMUL_F2")
276 (eq_attr "mode" "RVVMF4x3HI") (symbol_ref "riscv_vector::LMUL_F4")
277 (eq_attr "mode" "RVVM4x2HI") (symbol_ref "riscv_vector::LMUL_4")
278 (eq_attr "mode" "RVVM2x2HI") (symbol_ref "riscv_vector::LMUL_2")
279 (eq_attr "mode" "RVVM1x2HI") (symbol_ref "riscv_vector::LMUL_1")
280 (eq_attr "mode" "RVVMF2x2HI") (symbol_ref "riscv_vector::LMUL_F2")
281 (eq_attr "mode" "RVVMF4x2HI") (symbol_ref "riscv_vector::LMUL_F4")
282 (eq_attr "mode" "RVVM1x8BF") (symbol_ref "riscv_vector::LMUL_1")
283 (eq_attr "mode" "RVVMF2x8BF") (symbol_ref "riscv_vector::LMUL_F2")
284 (eq_attr "mode" "RVVMF4x8BF") (symbol_ref "riscv_vector::LMUL_F4")
285 (eq_attr "mode" "RVVM1x7BF") (symbol_ref "riscv_vector::LMUL_1")
286 (eq_attr "mode" "RVVMF2x7BF") (symbol_ref "riscv_vector::LMUL_F2")
287 (eq_attr "mode" "RVVMF4x7BF") (symbol_ref "riscv_vector::LMUL_F4")
288 (eq_attr "mode" "RVVM1x6BF") (symbol_ref "riscv_vector::LMUL_1")
289 (eq_attr "mode" "RVVMF2x6BF") (symbol_ref "riscv_vector::LMUL_F2")
290 (eq_attr "mode" "RVVMF4x6BF") (symbol_ref "riscv_vector::LMUL_F4")
291 (eq_attr "mode" "RVVM1x5BF") (symbol_ref "riscv_vector::LMUL_1")
292 (eq_attr "mode" "RVVMF2x5BF") (symbol_ref "riscv_vector::LMUL_F2")
293 (eq_attr "mode" "RVVMF4x5BF") (symbol_ref "riscv_vector::LMUL_F4")
294 (eq_attr "mode" "RVVM2x4BF") (symbol_ref "riscv_vector::LMUL_2")
295 (eq_attr "mode" "RVVM1x4BF") (symbol_ref "riscv_vector::LMUL_1")
296 (eq_attr "mode" "RVVMF2x4BF") (symbol_ref "riscv_vector::LMUL_F2")
297 (eq_attr "mode" "RVVMF4x4BF") (symbol_ref "riscv_vector::LMUL_F4")
298 (eq_attr "mode" "RVVM2x3BF") (symbol_ref "riscv_vector::LMUL_2")
299 (eq_attr "mode" "RVVM1x3BF") (symbol_ref "riscv_vector::LMUL_1")
300 (eq_attr "mode" "RVVMF2x3BF") (symbol_ref "riscv_vector::LMUL_F2")
301 (eq_attr "mode" "RVVMF4x3BF") (symbol_ref "riscv_vector::LMUL_F4")
302 (eq_attr "mode" "RVVM4x2BF") (symbol_ref "riscv_vector::LMUL_4")
303 (eq_attr "mode" "RVVM2x2BF") (symbol_ref "riscv_vector::LMUL_2")
304 (eq_attr "mode" "RVVM1x2BF") (symbol_ref "riscv_vector::LMUL_1")
305 (eq_attr "mode" "RVVMF2x2BF") (symbol_ref "riscv_vector::LMUL_F2")
306 (eq_attr "mode" "RVVMF4x2BF") (symbol_ref "riscv_vector::LMUL_F4")
307 (eq_attr "mode" "RVVM1x8HF") (symbol_ref "riscv_vector::LMUL_1")
308 (eq_attr "mode" "RVVMF2x8HF") (symbol_ref "riscv_vector::LMUL_F2")
309 (eq_attr "mode" "RVVMF4x8HF") (symbol_ref "riscv_vector::LMUL_F4")
310 (eq_attr "mode" "RVVM1x7HF") (symbol_ref "riscv_vector::LMUL_1")
311 (eq_attr "mode" "RVVMF2x7HF") (symbol_ref "riscv_vector::LMUL_F2")
312 (eq_attr "mode" "RVVMF4x7HF") (symbol_ref "riscv_vector::LMUL_F4")
313 (eq_attr "mode" "RVVM1x6HF") (symbol_ref "riscv_vector::LMUL_1")
314 (eq_attr "mode" "RVVMF2x6HF") (symbol_ref "riscv_vector::LMUL_F2")
315 (eq_attr "mode" "RVVMF4x6HF") (symbol_ref "riscv_vector::LMUL_F4")
316 (eq_attr "mode" "RVVM1x5HF") (symbol_ref "riscv_vector::LMUL_1")
317 (eq_attr "mode" "RVVMF2x5HF") (symbol_ref "riscv_vector::LMUL_F2")
318 (eq_attr "mode" "RVVMF4x5HF") (symbol_ref "riscv_vector::LMUL_F4")
319 (eq_attr "mode" "RVVM2x4HF") (symbol_ref "riscv_vector::LMUL_2")
320 (eq_attr "mode" "RVVM1x4HF") (symbol_ref "riscv_vector::LMUL_1")
321 (eq_attr "mode" "RVVMF2x4HF") (symbol_ref "riscv_vector::LMUL_F2")
322 (eq_attr "mode" "RVVMF4x4HF") (symbol_ref "riscv_vector::LMUL_F4")
323 (eq_attr "mode" "RVVM2x3HF") (symbol_ref "riscv_vector::LMUL_2")
324 (eq_attr "mode" "RVVM1x3HF") (symbol_ref "riscv_vector::LMUL_1")
325 (eq_attr "mode" "RVVMF2x3HF") (symbol_ref "riscv_vector::LMUL_F2")
326 (eq_attr "mode" "RVVMF4x3HF") (symbol_ref "riscv_vector::LMUL_F4")
327 (eq_attr "mode" "RVVM4x2HF") (symbol_ref "riscv_vector::LMUL_4")
328 (eq_attr "mode" "RVVM2x2HF") (symbol_ref "riscv_vector::LMUL_2")
329 (eq_attr "mode" "RVVM1x2HF") (symbol_ref "riscv_vector::LMUL_1")
330 (eq_attr "mode" "RVVMF2x2HF") (symbol_ref "riscv_vector::LMUL_F2")
331 (eq_attr "mode" "RVVMF4x2HF") (symbol_ref "riscv_vector::LMUL_F4")
332 (eq_attr "mode" "RVVM1x8SI") (symbol_ref "riscv_vector::LMUL_1")
333 (eq_attr "mode" "RVVMF2x8SI") (symbol_ref "riscv_vector::LMUL_F2")
334 (eq_attr "mode" "RVVM1x7SI") (symbol_ref "riscv_vector::LMUL_1")
335 (eq_attr "mode" "RVVMF2x7SI") (symbol_ref "riscv_vector::LMUL_F2")
336 (eq_attr "mode" "RVVM1x6SI") (symbol_ref "riscv_vector::LMUL_1")
337 (eq_attr "mode" "RVVMF2x6SI") (symbol_ref "riscv_vector::LMUL_F2")
338 (eq_attr "mode" "RVVM1x5SI") (symbol_ref "riscv_vector::LMUL_1")
339 (eq_attr "mode" "RVVMF2x5SI") (symbol_ref "riscv_vector::LMUL_F2")
340 (eq_attr "mode" "RVVM2x4SI") (symbol_ref "riscv_vector::LMUL_2")
341 (eq_attr "mode" "RVVM1x4SI") (symbol_ref "riscv_vector::LMUL_1")
342 (eq_attr "mode" "RVVMF2x4SI") (symbol_ref "riscv_vector::LMUL_F2")
343 (eq_attr "mode" "RVVM2x3SI") (symbol_ref "riscv_vector::LMUL_2")
344 (eq_attr "mode" "RVVM1x3SI") (symbol_ref "riscv_vector::LMUL_1")
345 (eq_attr "mode" "RVVMF2x3SI") (symbol_ref "riscv_vector::LMUL_F2")
346 (eq_attr "mode" "RVVM4x2SI") (symbol_ref "riscv_vector::LMUL_4")
347 (eq_attr "mode" "RVVM2x2SI") (symbol_ref "riscv_vector::LMUL_2")
348 (eq_attr "mode" "RVVM1x2SI") (symbol_ref "riscv_vector::LMUL_1")
349 (eq_attr "mode" "RVVMF2x2SI") (symbol_ref "riscv_vector::LMUL_F2")
350 (eq_attr "mode" "RVVM1x8SF") (symbol_ref "riscv_vector::LMUL_1")
351 (eq_attr "mode" "RVVMF2x8SF") (symbol_ref "riscv_vector::LMUL_F2")
352 (eq_attr "mode" "RVVM1x7SF") (symbol_ref "riscv_vector::LMUL_1")
353 (eq_attr "mode" "RVVMF2x7SF") (symbol_ref "riscv_vector::LMUL_F2")
354 (eq_attr "mode" "RVVM1x6SF") (symbol_ref "riscv_vector::LMUL_1")
355 (eq_attr "mode" "RVVMF2x6SF") (symbol_ref "riscv_vector::LMUL_F2")
356 (eq_attr "mode" "RVVM1x5SF") (symbol_ref "riscv_vector::LMUL_1")
357 (eq_attr "mode" "RVVMF2x5SF") (symbol_ref "riscv_vector::LMUL_F2")
358 (eq_attr "mode" "RVVM2x4SF") (symbol_ref "riscv_vector::LMUL_2")
359 (eq_attr "mode" "RVVM1x4SF") (symbol_ref "riscv_vector::LMUL_1")
360 (eq_attr "mode" "RVVMF2x4SF") (symbol_ref "riscv_vector::LMUL_F2")
361 (eq_attr "mode" "RVVM2x3SF") (symbol_ref "riscv_vector::LMUL_2")
362 (eq_attr "mode" "RVVM1x3SF") (symbol_ref "riscv_vector::LMUL_1")
363 (eq_attr "mode" "RVVMF2x3SF") (symbol_ref "riscv_vector::LMUL_F2")
364 (eq_attr "mode" "RVVM4x2SF") (symbol_ref "riscv_vector::LMUL_4")
365 (eq_attr "mode" "RVVM2x2SF") (symbol_ref "riscv_vector::LMUL_2")
366 (eq_attr "mode" "RVVM1x2SF") (symbol_ref "riscv_vector::LMUL_1")
367 (eq_attr "mode" "RVVMF2x2SF") (symbol_ref "riscv_vector::LMUL_F2")
368 (eq_attr "mode" "RVVM1x8DI") (symbol_ref "riscv_vector::LMUL_1")
369 (eq_attr "mode" "RVVM1x7DI") (symbol_ref "riscv_vector::LMUL_1")
370 (eq_attr "mode" "RVVM1x6DI") (symbol_ref "riscv_vector::LMUL_1")
371 (eq_attr "mode" "RVVM1x5DI") (symbol_ref "riscv_vector::LMUL_1")
372 (eq_attr "mode" "RVVM2x4DI") (symbol_ref "riscv_vector::LMUL_2")
373 (eq_attr "mode" "RVVM1x4DI") (symbol_ref "riscv_vector::LMUL_1")
374 (eq_attr "mode" "RVVM2x3DI") (symbol_ref "riscv_vector::LMUL_2")
375 (eq_attr "mode" "RVVM1x3DI") (symbol_ref "riscv_vector::LMUL_1")
376 (eq_attr "mode" "RVVM4x2DI") (symbol_ref "riscv_vector::LMUL_4")
377 (eq_attr "mode" "RVVM2x2DI") (symbol_ref "riscv_vector::LMUL_2")
378 (eq_attr "mode" "RVVM1x2DI") (symbol_ref "riscv_vector::LMUL_1")
379 (eq_attr "mode" "RVVM1x8DF") (symbol_ref "riscv_vector::LMUL_1")
380 (eq_attr "mode" "RVVM1x7DF") (symbol_ref "riscv_vector::LMUL_1")
381 (eq_attr "mode" "RVVM1x6DF") (symbol_ref "riscv_vector::LMUL_1")
382 (eq_attr "mode" "RVVM1x5DF") (symbol_ref "riscv_vector::LMUL_1")
383 (eq_attr "mode" "RVVM2x4DF") (symbol_ref "riscv_vector::LMUL_2")
384 (eq_attr "mode" "RVVM1x4DF") (symbol_ref "riscv_vector::LMUL_1")
385 (eq_attr "mode" "RVVM2x3DF") (symbol_ref "riscv_vector::LMUL_2")
386 (eq_attr "mode" "RVVM1x3DF") (symbol_ref "riscv_vector::LMUL_1")
387 (eq_attr "mode" "RVVM4x2DF") (symbol_ref "riscv_vector::LMUL_4")
388 (eq_attr "mode" "RVVM2x2DF") (symbol_ref "riscv_vector::LMUL_2")
389 (eq_attr "mode" "RVVM1x2DF") (symbol_ref "riscv_vector::LMUL_1")
391 ;; VLS modes.
392 (eq_attr "mode" "V1QI,V1BI") (symbol_ref "riscv_vector::get_vlmul(E_V1QImode)")
393 (eq_attr "mode" "V2QI,V2BI") (symbol_ref "riscv_vector::get_vlmul(E_V2QImode)")
394 (eq_attr "mode" "V4QI,V4BI") (symbol_ref "riscv_vector::get_vlmul(E_V4QImode)")
395 (eq_attr "mode" "V8QI,V8BI") (symbol_ref "riscv_vector::get_vlmul(E_V8QImode)")
396 (eq_attr "mode" "V16QI,V16BI") (symbol_ref "riscv_vector::get_vlmul(E_V16QImode)")
397 (eq_attr "mode" "V32QI,V32BI") (symbol_ref "riscv_vector::get_vlmul(E_V32QImode)")
398 (eq_attr "mode" "V64QI,V64BI") (symbol_ref "riscv_vector::get_vlmul(E_V64QImode)")
399 (eq_attr "mode" "V128QI,V128BI") (symbol_ref "riscv_vector::get_vlmul(E_V128QImode)")
400 (eq_attr "mode" "V256QI,V256BI") (symbol_ref "riscv_vector::get_vlmul(E_V256QImode)")
401 (eq_attr "mode" "V512QI,V512BI") (symbol_ref "riscv_vector::get_vlmul(E_V512QImode)")
402 (eq_attr "mode" "V1024QI,V1024BI") (symbol_ref "riscv_vector::get_vlmul(E_V1024QImode)")
403 (eq_attr "mode" "V2048QI,V2048BI") (symbol_ref "riscv_vector::get_vlmul(E_V2048QImode)")
404 (eq_attr "mode" "V4096QI,V4096BI") (symbol_ref "riscv_vector::get_vlmul(E_V4096QImode)")
405 (eq_attr "mode" "V1HI") (symbol_ref "riscv_vector::get_vlmul(E_V1HImode)")
406 (eq_attr "mode" "V2HI") (symbol_ref "riscv_vector::get_vlmul(E_V2HImode)")
407 (eq_attr "mode" "V4HI") (symbol_ref "riscv_vector::get_vlmul(E_V4HImode)")
408 (eq_attr "mode" "V8HI") (symbol_ref "riscv_vector::get_vlmul(E_V8HImode)")
409 (eq_attr "mode" "V16HI") (symbol_ref "riscv_vector::get_vlmul(E_V16HImode)")
410 (eq_attr "mode" "V32HI") (symbol_ref "riscv_vector::get_vlmul(E_V32HImode)")
411 (eq_attr "mode" "V64HI") (symbol_ref "riscv_vector::get_vlmul(E_V64HImode)")
412 (eq_attr "mode" "V128HI") (symbol_ref "riscv_vector::get_vlmul(E_V128HImode)")
413 (eq_attr "mode" "V256HI") (symbol_ref "riscv_vector::get_vlmul(E_V256HImode)")
414 (eq_attr "mode" "V512HI") (symbol_ref "riscv_vector::get_vlmul(E_V512HImode)")
415 (eq_attr "mode" "V1024HI") (symbol_ref "riscv_vector::get_vlmul(E_V1024HImode)")
416 (eq_attr "mode" "V2048HI") (symbol_ref "riscv_vector::get_vlmul(E_V2048HImode)")
417 (eq_attr "mode" "V1SI") (symbol_ref "riscv_vector::get_vlmul(E_V1SImode)")
418 (eq_attr "mode" "V2SI") (symbol_ref "riscv_vector::get_vlmul(E_V2SImode)")
419 (eq_attr "mode" "V4SI") (symbol_ref "riscv_vector::get_vlmul(E_V4SImode)")
420 (eq_attr "mode" "V8SI") (symbol_ref "riscv_vector::get_vlmul(E_V8SImode)")
421 (eq_attr "mode" "V16SI") (symbol_ref "riscv_vector::get_vlmul(E_V16SImode)")
422 (eq_attr "mode" "V32SI") (symbol_ref "riscv_vector::get_vlmul(E_V32SImode)")
423 (eq_attr "mode" "V64SI") (symbol_ref "riscv_vector::get_vlmul(E_V64SImode)")
424 (eq_attr "mode" "V128SI") (symbol_ref "riscv_vector::get_vlmul(E_V128SImode)")
425 (eq_attr "mode" "V256SI") (symbol_ref "riscv_vector::get_vlmul(E_V256SImode)")
426 (eq_attr "mode" "V512SI") (symbol_ref "riscv_vector::get_vlmul(E_V512SImode)")
427 (eq_attr "mode" "V1024SI") (symbol_ref "riscv_vector::get_vlmul(E_V1024SImode)")
428 (eq_attr "mode" "V1DI") (symbol_ref "riscv_vector::get_vlmul(E_V1DImode)")
429 (eq_attr "mode" "V2DI") (symbol_ref "riscv_vector::get_vlmul(E_V2DImode)")
430 (eq_attr "mode" "V4DI") (symbol_ref "riscv_vector::get_vlmul(E_V4DImode)")
431 (eq_attr "mode" "V8DI") (symbol_ref "riscv_vector::get_vlmul(E_V8DImode)")
432 (eq_attr "mode" "V16DI") (symbol_ref "riscv_vector::get_vlmul(E_V16DImode)")
433 (eq_attr "mode" "V32DI") (symbol_ref "riscv_vector::get_vlmul(E_V32DImode)")
434 (eq_attr "mode" "V64DI") (symbol_ref "riscv_vector::get_vlmul(E_V64DImode)")
435 (eq_attr "mode" "V128DI") (symbol_ref "riscv_vector::get_vlmul(E_V128DImode)")
436 (eq_attr "mode" "V256DI") (symbol_ref "riscv_vector::get_vlmul(E_V256DImode)")
437 (eq_attr "mode" "V512DI") (symbol_ref "riscv_vector::get_vlmul(E_V512DImode)")
438 (eq_attr "mode" "V1HF") (symbol_ref "riscv_vector::get_vlmul(E_V1HFmode)")
439 (eq_attr "mode" "V2HF") (symbol_ref "riscv_vector::get_vlmul(E_V2HFmode)")
440 (eq_attr "mode" "V4HF") (symbol_ref "riscv_vector::get_vlmul(E_V4HFmode)")
441 (eq_attr "mode" "V8HF") (symbol_ref "riscv_vector::get_vlmul(E_V8HFmode)")
442 (eq_attr "mode" "V16HF") (symbol_ref "riscv_vector::get_vlmul(E_V16HFmode)")
443 (eq_attr "mode" "V32HF") (symbol_ref "riscv_vector::get_vlmul(E_V32HFmode)")
444 (eq_attr "mode" "V64HF") (symbol_ref "riscv_vector::get_vlmul(E_V64HFmode)")
445 (eq_attr "mode" "V128HF") (symbol_ref "riscv_vector::get_vlmul(E_V128HFmode)")
446 (eq_attr "mode" "V256HF") (symbol_ref "riscv_vector::get_vlmul(E_V256HFmode)")
447 (eq_attr "mode" "V512HF") (symbol_ref "riscv_vector::get_vlmul(E_V512HFmode)")
448 (eq_attr "mode" "V1024HF") (symbol_ref "riscv_vector::get_vlmul(E_V1024HFmode)")
449 (eq_attr "mode" "V2048HF") (symbol_ref "riscv_vector::get_vlmul(E_V2048HFmode)")
450 (eq_attr "mode" "V1SF") (symbol_ref "riscv_vector::get_vlmul(E_V1SFmode)")
451 (eq_attr "mode" "V2SF") (symbol_ref "riscv_vector::get_vlmul(E_V2SFmode)")
452 (eq_attr "mode" "V4SF") (symbol_ref "riscv_vector::get_vlmul(E_V4SFmode)")
453 (eq_attr "mode" "V8SF") (symbol_ref "riscv_vector::get_vlmul(E_V8SFmode)")
454 (eq_attr "mode" "V16SF") (symbol_ref "riscv_vector::get_vlmul(E_V16SFmode)")
455 (eq_attr "mode" "V32SF") (symbol_ref "riscv_vector::get_vlmul(E_V32SFmode)")
456 (eq_attr "mode" "V64SF") (symbol_ref "riscv_vector::get_vlmul(E_V64SFmode)")
457 (eq_attr "mode" "V128SF") (symbol_ref "riscv_vector::get_vlmul(E_V128SFmode)")
458 (eq_attr "mode" "V256SF") (symbol_ref "riscv_vector::get_vlmul(E_V256SFmode)")
459 (eq_attr "mode" "V512SF") (symbol_ref "riscv_vector::get_vlmul(E_V512SFmode)")
460 (eq_attr "mode" "V1024SF") (symbol_ref "riscv_vector::get_vlmul(E_V1024SFmode)")
461 (eq_attr "mode" "V1DF") (symbol_ref "riscv_vector::get_vlmul(E_V1DFmode)")
462 (eq_attr "mode" "V2DF") (symbol_ref "riscv_vector::get_vlmul(E_V2DFmode)")
463 (eq_attr "mode" "V4DF") (symbol_ref "riscv_vector::get_vlmul(E_V4DFmode)")
464 (eq_attr "mode" "V8DF") (symbol_ref "riscv_vector::get_vlmul(E_V8DFmode)")
465 (eq_attr "mode" "V16DF") (symbol_ref "riscv_vector::get_vlmul(E_V16DFmode)")
466 (eq_attr "mode" "V32DF") (symbol_ref "riscv_vector::get_vlmul(E_V32DFmode)")
467 (eq_attr "mode" "V64DF") (symbol_ref "riscv_vector::get_vlmul(E_V64DFmode)")
468 (eq_attr "mode" "V128DF") (symbol_ref "riscv_vector::get_vlmul(E_V128DFmode)")
469 (eq_attr "mode" "V256DF") (symbol_ref "riscv_vector::get_vlmul(E_V256DFmode)")
470 (eq_attr "mode" "V512DF") (symbol_ref "riscv_vector::get_vlmul(E_V512DFmode)")]
471 (const_int INVALID_ATTRIBUTE)))
473 ;; It is valid for instruction that require sew/lmul ratio.
474 (define_attr "ratio" ""
475 (cond [(eq_attr "type" "vimov,vfmov,vldux,vldox,vstux,vstox,\
476 vialu,vshift,vicmp,vimul,vidiv,vsalu,\
477 vext,viwalu,viwmul,vicalu,vnshift,\
478 vimuladd,vimerge,vaalu,vsmul,vsshift,\
479 vnclip,viminmax,viwmuladd,\
480 vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,\
481 vfwalu,vfwmul,vfsqrt,vfrecp,vfsgnj,vfcmp,\
482 vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\
483 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,\
484 vfncvtftof,vfmuladd,vfwmuladd,vfclass,vired,\
485 viwred,vfredu,vfredo,vfwredu,vfwredo,vimovvx,\
486 vimovxv,vfmovvf,vfmovfv,vslideup,vslidedown,\
487 vislide1up,vislide1down,vfslide1up,vfslide1down,\
488 vgather,vcompress,vlsegdux,vlsegdox,vssegtux,vssegtox,\
489 vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,vror,vwsll,\
490 vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
491 vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,\
492 vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16")
493 (const_int INVALID_ATTRIBUTE)
494 (and (eq_attr "type" "vlde,vste,vlsegde,vssegte,vlsegds,vssegts,\
495 vlsegdff,vssegtux,vlsegdox,vlsegdux")
496 (match_test "TARGET_XTHEADVECTOR"))
497 (const_int INVALID_ATTRIBUTE)
498 (eq_attr "mode" "RVVM8QI,RVVM1BI") (const_int 1)
499 (eq_attr "mode" "RVVM4QI,RVVMF2BI") (const_int 2)
500 (eq_attr "mode" "RVVM2QI,RVVMF4BI") (const_int 4)
501 (eq_attr "mode" "RVVM1QI,RVVMF8BI") (const_int 8)
502 (eq_attr "mode" "RVVMF2QI,RVVMF16BI") (const_int 16)
503 (eq_attr "mode" "RVVMF4QI,RVVMF32BI") (const_int 32)
504 (eq_attr "mode" "RVVMF8QI,RVVMF64BI") (const_int 64)
505 (eq_attr "mode" "RVVM8HI") (const_int 2)
506 (eq_attr "mode" "RVVM4HI") (const_int 4)
507 (eq_attr "mode" "RVVM2HI") (const_int 8)
508 (eq_attr "mode" "RVVM1HI") (const_int 16)
509 (eq_attr "mode" "RVVMF2HI") (const_int 32)
510 (eq_attr "mode" "RVVMF4HI") (const_int 64)
511 (eq_attr "mode" "RVVM8BF") (const_int 2)
512 (eq_attr "mode" "RVVM4BF") (const_int 4)
513 (eq_attr "mode" "RVVM2BF") (const_int 8)
514 (eq_attr "mode" "RVVM1BF") (const_int 16)
515 (eq_attr "mode" "RVVMF2BF") (const_int 32)
516 (eq_attr "mode" "RVVMF4BF") (const_int 64)
517 (eq_attr "mode" "RVVM8HF") (const_int 2)
518 (eq_attr "mode" "RVVM4HF") (const_int 4)
519 (eq_attr "mode" "RVVM2HF") (const_int 8)
520 (eq_attr "mode" "RVVM1HF") (const_int 16)
521 (eq_attr "mode" "RVVMF2HF") (const_int 32)
522 (eq_attr "mode" "RVVMF4HF") (const_int 64)
523 (eq_attr "mode" "RVVM8SI") (const_int 4)
524 (eq_attr "mode" "RVVM4SI") (const_int 8)
525 (eq_attr "mode" "RVVM2SI") (const_int 16)
526 (eq_attr "mode" "RVVM1SI") (const_int 32)
527 (eq_attr "mode" "RVVMF2SI") (const_int 64)
528 (eq_attr "mode" "RVVM8SF") (const_int 4)
529 (eq_attr "mode" "RVVM4SF") (const_int 8)
530 (eq_attr "mode" "RVVM2SF") (const_int 16)
531 (eq_attr "mode" "RVVM1SF") (const_int 32)
532 (eq_attr "mode" "RVVMF2SF") (const_int 64)
533 (eq_attr "mode" "RVVM8DI") (const_int 8)
534 (eq_attr "mode" "RVVM4DI") (const_int 16)
535 (eq_attr "mode" "RVVM2DI") (const_int 32)
536 (eq_attr "mode" "RVVM1DI") (const_int 64)
537 (eq_attr "mode" "RVVM8DF") (const_int 8)
538 (eq_attr "mode" "RVVM4DF") (const_int 16)
539 (eq_attr "mode" "RVVM2DF") (const_int 32)
540 (eq_attr "mode" "RVVM1DF") (const_int 64)
541 (eq_attr "mode" "RVVM1x8QI") (const_int 8)
542 (eq_attr "mode" "RVVMF2x8QI") (const_int 16)
543 (eq_attr "mode" "RVVMF4x8QI") (const_int 32)
544 (eq_attr "mode" "RVVMF8x8QI") (const_int 64)
545 (eq_attr "mode" "RVVM1x7QI") (const_int 8)
546 (eq_attr "mode" "RVVMF2x7QI") (const_int 16)
547 (eq_attr "mode" "RVVMF4x7QI") (const_int 32)
548 (eq_attr "mode" "RVVMF8x7QI") (const_int 64)
549 (eq_attr "mode" "RVVM1x6QI") (const_int 8)
550 (eq_attr "mode" "RVVMF2x6QI") (const_int 16)
551 (eq_attr "mode" "RVVMF4x6QI") (const_int 32)
552 (eq_attr "mode" "RVVMF8x6QI") (const_int 64)
553 (eq_attr "mode" "RVVM1x5QI") (const_int 8)
554 (eq_attr "mode" "RVVMF2x5QI") (const_int 16)
555 (eq_attr "mode" "RVVMF4x5QI") (const_int 32)
556 (eq_attr "mode" "RVVMF8x5QI") (const_int 64)
557 (eq_attr "mode" "RVVM2x4QI") (const_int 4)
558 (eq_attr "mode" "RVVM1x4QI") (const_int 8)
559 (eq_attr "mode" "RVVMF2x4QI") (const_int 16)
560 (eq_attr "mode" "RVVMF4x4QI") (const_int 32)
561 (eq_attr "mode" "RVVMF8x4QI") (const_int 64)
562 (eq_attr "mode" "RVVM2x3QI") (const_int 4)
563 (eq_attr "mode" "RVVM1x3QI") (const_int 8)
564 (eq_attr "mode" "RVVMF2x3QI") (const_int 16)
565 (eq_attr "mode" "RVVMF4x3QI") (const_int 32)
566 (eq_attr "mode" "RVVMF8x3QI") (const_int 64)
567 (eq_attr "mode" "RVVM4x2QI") (const_int 2)
568 (eq_attr "mode" "RVVM2x2QI") (const_int 4)
569 (eq_attr "mode" "RVVM1x2QI") (const_int 8)
570 (eq_attr "mode" "RVVMF2x2QI") (const_int 16)
571 (eq_attr "mode" "RVVMF4x2QI") (const_int 32)
572 (eq_attr "mode" "RVVMF8x2QI") (const_int 64)
573 (eq_attr "mode" "RVVM1x8HI") (const_int 16)
574 (eq_attr "mode" "RVVMF2x8HI") (const_int 32)
575 (eq_attr "mode" "RVVMF4x8HI") (const_int 64)
576 (eq_attr "mode" "RVVM1x7HI") (const_int 16)
577 (eq_attr "mode" "RVVMF2x7HI") (const_int 32)
578 (eq_attr "mode" "RVVMF4x7HI") (const_int 64)
579 (eq_attr "mode" "RVVM1x6HI") (const_int 16)
580 (eq_attr "mode" "RVVMF2x6HI") (const_int 32)
581 (eq_attr "mode" "RVVMF4x6HI") (const_int 64)
582 (eq_attr "mode" "RVVM1x5HI") (const_int 16)
583 (eq_attr "mode" "RVVMF2x5HI") (const_int 32)
584 (eq_attr "mode" "RVVMF4x5HI") (const_int 64)
585 (eq_attr "mode" "RVVM2x4HI") (const_int 8)
586 (eq_attr "mode" "RVVM1x4HI") (const_int 16)
587 (eq_attr "mode" "RVVMF2x4HI") (const_int 32)
588 (eq_attr "mode" "RVVMF4x4HI") (const_int 64)
589 (eq_attr "mode" "RVVM2x3HI") (const_int 8)
590 (eq_attr "mode" "RVVM1x3HI") (const_int 16)
591 (eq_attr "mode" "RVVMF2x3HI") (const_int 32)
592 (eq_attr "mode" "RVVMF4x3HI") (const_int 64)
593 (eq_attr "mode" "RVVM4x2HI") (const_int 4)
594 (eq_attr "mode" "RVVM2x2HI") (const_int 8)
595 (eq_attr "mode" "RVVM1x2HI") (const_int 16)
596 (eq_attr "mode" "RVVMF2x2HI") (const_int 32)
597 (eq_attr "mode" "RVVMF4x2HI") (const_int 64)
598 (eq_attr "mode" "RVVM1x8BF") (const_int 16)
599 (eq_attr "mode" "RVVMF2x8BF") (const_int 32)
600 (eq_attr "mode" "RVVMF4x8BF") (const_int 64)
601 (eq_attr "mode" "RVVM1x7BF") (const_int 16)
602 (eq_attr "mode" "RVVMF2x7BF") (const_int 32)
603 (eq_attr "mode" "RVVMF4x7BF") (const_int 64)
604 (eq_attr "mode" "RVVM1x6BF") (const_int 16)
605 (eq_attr "mode" "RVVMF2x6BF") (const_int 32)
606 (eq_attr "mode" "RVVMF4x6BF") (const_int 64)
607 (eq_attr "mode" "RVVM1x5BF") (const_int 16)
608 (eq_attr "mode" "RVVMF2x5BF") (const_int 32)
609 (eq_attr "mode" "RVVMF4x5BF") (const_int 64)
610 (eq_attr "mode" "RVVM2x4BF") (const_int 8)
611 (eq_attr "mode" "RVVM1x4BF") (const_int 16)
612 (eq_attr "mode" "RVVMF2x4BF") (const_int 32)
613 (eq_attr "mode" "RVVMF4x4BF") (const_int 64)
614 (eq_attr "mode" "RVVM2x3BF") (const_int 8)
615 (eq_attr "mode" "RVVM1x3BF") (const_int 16)
616 (eq_attr "mode" "RVVMF2x3BF") (const_int 32)
617 (eq_attr "mode" "RVVMF4x3BF") (const_int 64)
618 (eq_attr "mode" "RVVM4x2BF") (const_int 4)
619 (eq_attr "mode" "RVVM2x2BF") (const_int 8)
620 (eq_attr "mode" "RVVM1x2BF") (const_int 16)
621 (eq_attr "mode" "RVVMF2x2BF") (const_int 32)
622 (eq_attr "mode" "RVVMF4x2BF") (const_int 64)
623 (eq_attr "mode" "RVVM1x8HF") (const_int 16)
624 (eq_attr "mode" "RVVMF2x8HF") (const_int 32)
625 (eq_attr "mode" "RVVMF4x8HF") (const_int 64)
626 (eq_attr "mode" "RVVM1x7HF") (const_int 16)
627 (eq_attr "mode" "RVVMF2x7HF") (const_int 32)
628 (eq_attr "mode" "RVVMF4x7HF") (const_int 64)
629 (eq_attr "mode" "RVVM1x6HF") (const_int 16)
630 (eq_attr "mode" "RVVMF2x6HF") (const_int 32)
631 (eq_attr "mode" "RVVMF4x6HF") (const_int 64)
632 (eq_attr "mode" "RVVM1x5HF") (const_int 16)
633 (eq_attr "mode" "RVVMF2x5HF") (const_int 32)
634 (eq_attr "mode" "RVVMF4x5HF") (const_int 64)
635 (eq_attr "mode" "RVVM2x4HF") (const_int 8)
636 (eq_attr "mode" "RVVM1x4HF") (const_int 16)
637 (eq_attr "mode" "RVVMF2x4HF") (const_int 32)
638 (eq_attr "mode" "RVVMF4x4HF") (const_int 64)
639 (eq_attr "mode" "RVVM2x3HF") (const_int 8)
640 (eq_attr "mode" "RVVM1x3HF") (const_int 16)
641 (eq_attr "mode" "RVVMF2x3HF") (const_int 32)
642 (eq_attr "mode" "RVVMF4x3HF") (const_int 64)
643 (eq_attr "mode" "RVVM4x2HF") (const_int 4)
644 (eq_attr "mode" "RVVM2x2HF") (const_int 8)
645 (eq_attr "mode" "RVVM1x2HF") (const_int 16)
646 (eq_attr "mode" "RVVMF2x2HF") (const_int 32)
647 (eq_attr "mode" "RVVMF4x2HF") (const_int 64)
648 (eq_attr "mode" "RVVM1x8SI") (const_int 32)
649 (eq_attr "mode" "RVVMF2x8SI") (const_int 64)
650 (eq_attr "mode" "RVVM1x7SI") (const_int 32)
651 (eq_attr "mode" "RVVMF2x7SI") (const_int 64)
652 (eq_attr "mode" "RVVM1x6SI") (const_int 32)
653 (eq_attr "mode" "RVVMF2x6SI") (const_int 64)
654 (eq_attr "mode" "RVVM1x5SI") (const_int 32)
655 (eq_attr "mode" "RVVMF2x5SI") (const_int 64)
656 (eq_attr "mode" "RVVM2x4SI") (const_int 16)
657 (eq_attr "mode" "RVVM1x4SI") (const_int 32)
658 (eq_attr "mode" "RVVMF2x4SI") (const_int 64)
659 (eq_attr "mode" "RVVM2x3SI") (const_int 16)
660 (eq_attr "mode" "RVVM1x3SI") (const_int 32)
661 (eq_attr "mode" "RVVMF2x3SI") (const_int 64)
662 (eq_attr "mode" "RVVM4x2SI") (const_int 8)
663 (eq_attr "mode" "RVVM2x2SI") (const_int 16)
664 (eq_attr "mode" "RVVM1x2SI") (const_int 32)
665 (eq_attr "mode" "RVVMF2x2SI") (const_int 64)
666 (eq_attr "mode" "RVVM1x8SF") (const_int 32)
667 (eq_attr "mode" "RVVMF2x8SF") (const_int 64)
668 (eq_attr "mode" "RVVM1x7SF") (const_int 32)
669 (eq_attr "mode" "RVVMF2x7SF") (const_int 64)
670 (eq_attr "mode" "RVVM1x6SF") (const_int 32)
671 (eq_attr "mode" "RVVMF2x6SF") (const_int 64)
672 (eq_attr "mode" "RVVM1x5SF") (const_int 32)
673 (eq_attr "mode" "RVVMF2x5SF") (const_int 64)
674 (eq_attr "mode" "RVVM2x4SF") (const_int 16)
675 (eq_attr "mode" "RVVM1x4SF") (const_int 32)
676 (eq_attr "mode" "RVVMF2x4SF") (const_int 64)
677 (eq_attr "mode" "RVVM2x3SF") (const_int 16)
678 (eq_attr "mode" "RVVM1x3SF") (const_int 32)
679 (eq_attr "mode" "RVVMF2x3SF") (const_int 64)
680 (eq_attr "mode" "RVVM4x2SF") (const_int 8)
681 (eq_attr "mode" "RVVM2x2SF") (const_int 16)
682 (eq_attr "mode" "RVVM1x2SF") (const_int 32)
683 (eq_attr "mode" "RVVMF2x2SF") (const_int 64)
684 (eq_attr "mode" "RVVM1x8DI") (const_int 64)
685 (eq_attr "mode" "RVVM1x7DI") (const_int 64)
686 (eq_attr "mode" "RVVM1x6DI") (const_int 64)
687 (eq_attr "mode" "RVVM1x5DI") (const_int 64)
688 (eq_attr "mode" "RVVM2x4DI") (const_int 32)
689 (eq_attr "mode" "RVVM1x4DI") (const_int 64)
690 (eq_attr "mode" "RVVM2x3DI") (const_int 32)
691 (eq_attr "mode" "RVVM1x3DI") (const_int 64)
692 (eq_attr "mode" "RVVM4x2DI") (const_int 16)
693 (eq_attr "mode" "RVVM2x2DI") (const_int 32)
694 (eq_attr "mode" "RVVM1x2DI") (const_int 64)
695 (eq_attr "mode" "RVVM1x8DF") (const_int 64)
696 (eq_attr "mode" "RVVM1x7DF") (const_int 64)
697 (eq_attr "mode" "RVVM1x6DF") (const_int 64)
698 (eq_attr "mode" "RVVM1x5DF") (const_int 64)
699 (eq_attr "mode" "RVVM2x4DF") (const_int 32)
700 (eq_attr "mode" "RVVM1x4DF") (const_int 64)
701 (eq_attr "mode" "RVVM2x3DF") (const_int 32)
702 (eq_attr "mode" "RVVM1x3DF") (const_int 64)
703 (eq_attr "mode" "RVVM4x2DF") (const_int 16)
704 (eq_attr "mode" "RVVM2x2DF") (const_int 32)
705 (eq_attr "mode" "RVVM1x2DF") (const_int 64)
707 ;; VLS modes.
708 (eq_attr "mode" "V1QI,V1BI") (symbol_ref "riscv_vector::get_ratio(E_V1QImode)")
709 (eq_attr "mode" "V2QI,V2BI") (symbol_ref "riscv_vector::get_ratio(E_V2QImode)")
710 (eq_attr "mode" "V4QI,V4BI") (symbol_ref "riscv_vector::get_ratio(E_V4QImode)")
711 (eq_attr "mode" "V8QI,V8BI") (symbol_ref "riscv_vector::get_ratio(E_V8QImode)")
712 (eq_attr "mode" "V16QI,V16BI") (symbol_ref "riscv_vector::get_ratio(E_V16QImode)")
713 (eq_attr "mode" "V32QI,V32BI") (symbol_ref "riscv_vector::get_ratio(E_V32QImode)")
714 (eq_attr "mode" "V64QI,V64BI") (symbol_ref "riscv_vector::get_ratio(E_V64QImode)")
715 (eq_attr "mode" "V128QI,V128BI") (symbol_ref "riscv_vector::get_ratio(E_V128QImode)")
716 (eq_attr "mode" "V256QI,V256BI") (symbol_ref "riscv_vector::get_ratio(E_V256QImode)")
717 (eq_attr "mode" "V512QI,V512BI") (symbol_ref "riscv_vector::get_ratio(E_V512QImode)")
718 (eq_attr "mode" "V1024QI,V1024BI") (symbol_ref "riscv_vector::get_ratio(E_V1024QImode)")
719 (eq_attr "mode" "V2048QI,V2048BI") (symbol_ref "riscv_vector::get_ratio(E_V2048QImode)")
720 (eq_attr "mode" "V4096QI,V4096BI") (symbol_ref "riscv_vector::get_ratio(E_V4096QImode)")
721 (eq_attr "mode" "V1HI") (symbol_ref "riscv_vector::get_ratio(E_V1HImode)")
722 (eq_attr "mode" "V2HI") (symbol_ref "riscv_vector::get_ratio(E_V2HImode)")
723 (eq_attr "mode" "V4HI") (symbol_ref "riscv_vector::get_ratio(E_V4HImode)")
724 (eq_attr "mode" "V8HI") (symbol_ref "riscv_vector::get_ratio(E_V8HImode)")
725 (eq_attr "mode" "V16HI") (symbol_ref "riscv_vector::get_ratio(E_V16HImode)")
726 (eq_attr "mode" "V32HI") (symbol_ref "riscv_vector::get_ratio(E_V32HImode)")
727 (eq_attr "mode" "V64HI") (symbol_ref "riscv_vector::get_ratio(E_V64HImode)")
728 (eq_attr "mode" "V128HI") (symbol_ref "riscv_vector::get_ratio(E_V128HImode)")
729 (eq_attr "mode" "V256HI") (symbol_ref "riscv_vector::get_ratio(E_V256HImode)")
730 (eq_attr "mode" "V512HI") (symbol_ref "riscv_vector::get_ratio(E_V512HImode)")
731 (eq_attr "mode" "V1024HI") (symbol_ref "riscv_vector::get_ratio(E_V1024HImode)")
732 (eq_attr "mode" "V2048HI") (symbol_ref "riscv_vector::get_ratio(E_V2048HImode)")
733 (eq_attr "mode" "V1SI") (symbol_ref "riscv_vector::get_ratio(E_V1SImode)")
734 (eq_attr "mode" "V2SI") (symbol_ref "riscv_vector::get_ratio(E_V2SImode)")
735 (eq_attr "mode" "V4SI") (symbol_ref "riscv_vector::get_ratio(E_V4SImode)")
736 (eq_attr "mode" "V8SI") (symbol_ref "riscv_vector::get_ratio(E_V8SImode)")
737 (eq_attr "mode" "V16SI") (symbol_ref "riscv_vector::get_ratio(E_V16SImode)")
738 (eq_attr "mode" "V32SI") (symbol_ref "riscv_vector::get_ratio(E_V32SImode)")
739 (eq_attr "mode" "V64SI") (symbol_ref "riscv_vector::get_ratio(E_V64SImode)")
740 (eq_attr "mode" "V128SI") (symbol_ref "riscv_vector::get_ratio(E_V128SImode)")
741 (eq_attr "mode" "V256SI") (symbol_ref "riscv_vector::get_ratio(E_V256SImode)")
742 (eq_attr "mode" "V512SI") (symbol_ref "riscv_vector::get_ratio(E_V512SImode)")
743 (eq_attr "mode" "V1024SI") (symbol_ref "riscv_vector::get_ratio(E_V1024SImode)")
744 (eq_attr "mode" "V1DI") (symbol_ref "riscv_vector::get_ratio(E_V1DImode)")
745 (eq_attr "mode" "V2DI") (symbol_ref "riscv_vector::get_ratio(E_V2DImode)")
746 (eq_attr "mode" "V4DI") (symbol_ref "riscv_vector::get_ratio(E_V4DImode)")
747 (eq_attr "mode" "V8DI") (symbol_ref "riscv_vector::get_ratio(E_V8DImode)")
748 (eq_attr "mode" "V16DI") (symbol_ref "riscv_vector::get_ratio(E_V16DImode)")
749 (eq_attr "mode" "V32DI") (symbol_ref "riscv_vector::get_ratio(E_V32DImode)")
750 (eq_attr "mode" "V64DI") (symbol_ref "riscv_vector::get_ratio(E_V64DImode)")
751 (eq_attr "mode" "V128DI") (symbol_ref "riscv_vector::get_ratio(E_V128DImode)")
752 (eq_attr "mode" "V256DI") (symbol_ref "riscv_vector::get_ratio(E_V256DImode)")
753 (eq_attr "mode" "V512DI") (symbol_ref "riscv_vector::get_ratio(E_V512DImode)")
754 (eq_attr "mode" "V1HF") (symbol_ref "riscv_vector::get_ratio(E_V1HFmode)")
755 (eq_attr "mode" "V2HF") (symbol_ref "riscv_vector::get_ratio(E_V2HFmode)")
756 (eq_attr "mode" "V4HF") (symbol_ref "riscv_vector::get_ratio(E_V4HFmode)")
757 (eq_attr "mode" "V8HF") (symbol_ref "riscv_vector::get_ratio(E_V8HFmode)")
758 (eq_attr "mode" "V16HF") (symbol_ref "riscv_vector::get_ratio(E_V16HFmode)")
759 (eq_attr "mode" "V32HF") (symbol_ref "riscv_vector::get_ratio(E_V32HFmode)")
760 (eq_attr "mode" "V64HF") (symbol_ref "riscv_vector::get_ratio(E_V64HFmode)")
761 (eq_attr "mode" "V128HF") (symbol_ref "riscv_vector::get_ratio(E_V128HFmode)")
762 (eq_attr "mode" "V256HF") (symbol_ref "riscv_vector::get_ratio(E_V256HFmode)")
763 (eq_attr "mode" "V512HF") (symbol_ref "riscv_vector::get_ratio(E_V512HFmode)")
764 (eq_attr "mode" "V1024HF") (symbol_ref "riscv_vector::get_ratio(E_V1024HFmode)")
765 (eq_attr "mode" "V2048HF") (symbol_ref "riscv_vector::get_ratio(E_V2048HFmode)")
766 (eq_attr "mode" "V1SF") (symbol_ref "riscv_vector::get_ratio(E_V1SFmode)")
767 (eq_attr "mode" "V2SF") (symbol_ref "riscv_vector::get_ratio(E_V2SFmode)")
768 (eq_attr "mode" "V4SF") (symbol_ref "riscv_vector::get_ratio(E_V4SFmode)")
769 (eq_attr "mode" "V8SF") (symbol_ref "riscv_vector::get_ratio(E_V8SFmode)")
770 (eq_attr "mode" "V16SF") (symbol_ref "riscv_vector::get_ratio(E_V16SFmode)")
771 (eq_attr "mode" "V32SF") (symbol_ref "riscv_vector::get_ratio(E_V32SFmode)")
772 (eq_attr "mode" "V64SF") (symbol_ref "riscv_vector::get_ratio(E_V64SFmode)")
773 (eq_attr "mode" "V128SF") (symbol_ref "riscv_vector::get_ratio(E_V128SFmode)")
774 (eq_attr "mode" "V256SF") (symbol_ref "riscv_vector::get_ratio(E_V256SFmode)")
775 (eq_attr "mode" "V512SF") (symbol_ref "riscv_vector::get_ratio(E_V512SFmode)")
776 (eq_attr "mode" "V1024SF") (symbol_ref "riscv_vector::get_ratio(E_V1024SFmode)")
777 (eq_attr "mode" "V1DF") (symbol_ref "riscv_vector::get_ratio(E_V1DFmode)")
778 (eq_attr "mode" "V2DF") (symbol_ref "riscv_vector::get_ratio(E_V2DFmode)")
779 (eq_attr "mode" "V4DF") (symbol_ref "riscv_vector::get_ratio(E_V4DFmode)")
780 (eq_attr "mode" "V8DF") (symbol_ref "riscv_vector::get_ratio(E_V8DFmode)")
781 (eq_attr "mode" "V16DF") (symbol_ref "riscv_vector::get_ratio(E_V16DFmode)")
782 (eq_attr "mode" "V32DF") (symbol_ref "riscv_vector::get_ratio(E_V32DFmode)")
783 (eq_attr "mode" "V64DF") (symbol_ref "riscv_vector::get_ratio(E_V64DFmode)")
784 (eq_attr "mode" "V128DF") (symbol_ref "riscv_vector::get_ratio(E_V128DFmode)")
785 (eq_attr "mode" "V256DF") (symbol_ref "riscv_vector::get_ratio(E_V256DFmode)")
786 (eq_attr "mode" "V512DF") (symbol_ref "riscv_vector::get_ratio(E_V512DFmode)")]
787 (const_int INVALID_ATTRIBUTE)))
789 ;; The index of operand[] to get the merge op.
790 (define_attr "merge_op_idx" ""
791 (cond [(eq_attr "type" "vlde,vimov,vfmov,vldm,vlds,vmalu,vldux,vldox,vicmp,\
792 vialu,vshift,viminmax,vimul,vidiv,vsalu,vext,viwalu,\
793 viwmul,vnshift,vaalu,vsmul,vsshift,vnclip,vmsfs,\
794 vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
795 vfsqrt,vfrecp,vfsgnj,vfcmp,vfcvtitof,vfcvtftoi,vfwcvtitof,\
796 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,\
797 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vimovxv,vfmovfv,\
798 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
799 vgather,vldff,viwmuladd,vfwmuladd,vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
800 vandn,vbrev,vbrev8,vrev8,vrol,vror,vwsll,vclmul,vclmulh,\
801 vfncvtbf16,vfwcvtbf16,vfwmaccbf16")
802 (const_int 2)
804 (eq_attr "type" "vimerge,vfmerge,vcompress,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
805 vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c")
806 (const_int 1)
808 (eq_attr "type" "vimuladd,vfmuladd")
809 (const_int 2)]
810 (const_int INVALID_ATTRIBUTE)))
812 ;; The index of operand[] represents the machine mode of the instruction.
813 (define_attr "mode_idx" ""
814 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,vldux,vldox,vldff,vldr,vstr,\
815 vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,vialu,vext,vicalu,\
816 vshift,vicmp,viminmax,vimul,vidiv,vimuladd,vimerge,vimov,\
817 vsalu,vaalu,vsmul,vsshift,vfalu,vfmul,vfdiv,vfmuladd,vfsqrt,vfrecp,\
818 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
819 vfcvtitof,vfncvtitof,vfncvtftoi,vfncvtftof,vmalu,vmiota,vmidx,\
820 vimovxv,vfmovfv,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
821 vgather,vcompress,vmov,vnclip,vnshift,vandn,vcpop,vclz,vctz,vrol,vror")
822 (const_int 0)
824 (eq_attr "type" "vimovvx,vfmovvf")
825 (const_int 1)
827 (eq_attr "type" "vssegte,vmpop,vmffs")
828 (const_int 2)
830 (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox,vfcvtftoi,vfwcvtitof,vfwcvtftoi,
831 vfwcvtftof,vmsfs,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vwsll")
832 (const_int 3)
834 (eq_attr "type" "viwalu,viwmul,viwmuladd,vfwalu,vfwmul,vfwmuladd")
835 (const_int 4)]
836 (const_int INVALID_ATTRIBUTE)))
838 ;; The index of operand[] to get the avl op.
839 (define_attr "vl_op_idx" ""
840 (cond [(eq_attr "type" "vlde,vste,vimov,vfmov,vldm,vstm,vmalu,vsts,vstux,\
841 vstox,vext,vmsfs,vmiota,vfsqrt,vfrecp,vfcvtitof,vldff,\
842 vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
843 vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,vcompress,\
844 vlsegde,vssegts,vssegtux,vssegtox,vlsegdff,vbrev,vbrev8,vrev8,\
845 vghsh,vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c,\
846 vfncvtbf16,vfwcvtbf16")
847 (const_int 4)
849 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
850 ;; whereas it is pred_strided_load if operands[3] is vector mode.
851 (eq_attr "type" "vlds")
852 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
853 (const_int 5)
854 (const_int 4))
856 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
857 viwalu,viwmul,vnshift,vimerge,vaalu,vsmul,\
858 vsshift,vnclip,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
859 vfsgnj,vfmerge,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
860 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
861 vgather,viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox,vandn,vrol,\
862 vror,vwsll,vclmul,vclmulh,vfwmaccbf16")
863 (const_int 5)
865 (eq_attr "type" "vicmp,vimuladd,vfcmp,vfmuladd")
866 (const_int 6)
868 (eq_attr "type" "vmpop,vmffs,vmidx,vssegte,vcpop,vclz,vctz,vgmul,vaesef,vaesem,vaesdf,\
869 vaesdm,vaesz,vsm4r")
870 (const_int 3)]
871 (const_int INVALID_ATTRIBUTE)))
873 ;; The tail policy op value.
874 (define_attr "ta" ""
875 (cond [(eq_attr "type" "vlde,vimov,vfmov,vext,vmiota,vfsqrt,vfrecp,\
876 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,\
877 vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,\
878 vcompress,vldff,vlsegde,vlsegdff,vbrev,vbrev8,vrev8,vghsh,\
879 vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c,\
880 vfncvtbf16,vfwcvtbf16")
881 (symbol_ref "riscv_vector::get_ta(operands[5])")
883 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
884 ;; whereas it is pred_strided_load if operands[3] is vector mode.
885 (eq_attr "type" "vlds")
886 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
887 (symbol_ref "riscv_vector::get_ta(operands[6])")
888 (symbol_ref "riscv_vector::get_ta(operands[5])"))
890 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
891 viwalu,viwmul,vnshift,vimerge,vaalu,vsmul,\
892 vsshift,vnclip,vfalu,vfmul,vfminmax,vfdiv,\
893 vfwalu,vfwmul,vfsgnj,vfmerge,vired,viwred,vfredu,\
894 vfredo,vfwredu,vfwredo,vslideup,vslidedown,vislide1up,\
895 vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
896 vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vwsll,vclmul,vclmulh,\
897 vfwmaccbf16,sf_vqmacc,sf_vfnrclip")
898 (symbol_ref "riscv_vector::get_ta(operands[6])")
900 (eq_attr "type" "vimuladd,vfmuladd")
901 (symbol_ref "riscv_vector::get_ta(operands[7])")
903 (eq_attr "type" "vmidx,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaesz,vsm4r")
904 (symbol_ref "riscv_vector::get_ta(operands[4])")]
905 (const_int INVALID_ATTRIBUTE)))
907 ;; The mask policy op value.
908 (define_attr "ma" ""
909 (cond [(eq_attr "type" "vlde,vext,vmiota,vfsqrt,vfrecp,vfcvtitof,vfcvtftoi,\
910 vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,\
911 vfncvtftof,vfclass,vldff,vlsegde,vlsegdff,vbrev,vbrev8,vrev8,\
912 vfncvtbf16,vfwcvtbf16")
913 (symbol_ref "riscv_vector::get_ma(operands[6])")
915 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
916 ;; whereas it is pred_strided_load if operands[3] is vector mode.
917 (eq_attr "type" "vlds")
918 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
919 (symbol_ref "riscv_vector::get_ma(operands[7])")
920 (symbol_ref "riscv_vector::get_ma(operands[6])"))
922 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
923 viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
924 vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,\
925 vfwalu,vfwmul,vfsgnj,vfcmp,vslideup,vslidedown,\
926 vislide1up,vislide1down,vfslide1up,vfslide1down,vgather,\
927 viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox,vandn,vrol,\
928 vror,vwsll,vclmul,vclmulh,vfwmaccbf16,sf_vqmacc,sf_vfnrclip")
929 (symbol_ref "riscv_vector::get_ma(operands[7])")
931 (eq_attr "type" "vimuladd,vfmuladd")
932 (symbol_ref "riscv_vector::get_ma(operands[8])")
934 (eq_attr "type" "vmsfs,vmidx")
935 (symbol_ref "riscv_vector::get_ma(operands[5])")]
936 (const_int INVALID_ATTRIBUTE)))
938 ;; The avl type value.
939 (define_attr "avl_type_idx" ""
940 (cond [(eq_attr "type" "vlde,vldff,vste,vimov,vfmov,vext,vimerge,\
941 vfsqrt,vfrecp,vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\
942 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
943 vfclass,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
944 vimovxv,vfmovfv,vlsegde,vlsegdff,vmiota,vbrev,vbrev8,vrev8,\
945 vfncvtbf16,vfwcvtbf16")
946 (const_int 7)
947 (eq_attr "type" "vldm,vstm,vmalu,vmalu,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaesz,\
948 vsm4r")
949 (const_int 5)
951 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
952 ;; whereas it is pred_strided_load if operands[3] is vector mode.
953 (eq_attr "type" "vlds")
954 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
955 (const_int 8)
956 (const_int 7))
958 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
959 viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
960 vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
961 vfsgnj,vfcmp,vslideup,vslidedown,vislide1up,\
962 vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
963 vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vclmul,vclmulh,vwsll,\
964 vfwmaccbf16")
965 (const_int 8)
966 (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox")
967 (const_int 5)
969 (eq_attr "type" "vimuladd,vfmuladd")
970 (const_int 9)
972 (eq_attr "type" "vmsfs,vmidx,vcompress,vghsh,vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,\
973 vsm4k,vsm3me,vsm3c")
974 (const_int 6)
976 (eq_attr "type" "vmpop,vmffs,vssegte,vcpop,vclz,vctz")
977 (const_int 4)]
978 (const_int INVALID_ATTRIBUTE)))
980 ;; Defines rounding mode of an fixed-point operation.
982 (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
983 (cond [(eq_attr "type" "vaalu,vsmul,vsshift,vnclip")
984 (cond
985 [(match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNU")
986 (const_string "rnu")
988 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNE")
989 (const_string "rne")
991 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RDN")
992 (const_string "rdn")
994 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_ROD")
995 (const_string "rod")]
996 (const_string "none"))]
997 (const_string "none")))
999 ;; Defines rounding mode of an floating-point operation.
1000 (define_attr "frm_mode" ""
1001 (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
1002 (symbol_ref "riscv_vector::FRM_DYN")]
1003 (symbol_ref "riscv_vector::FRM_NONE")))
1005 (include "thead-vector.md")
1007 ;; -----------------------------------------------------------------
1008 ;; ---- Miscellaneous Operations
1009 ;; -----------------------------------------------------------------
1011 (define_insn "@vundefined<mode>"
1012 [(set (match_operand:V 0 "register_operand" "=vr")
1013 (unspec:V [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
1014 "TARGET_VECTOR"
1015 ""
1016 [(set_attr "type" "vector")])
1018 (define_insn "@vundefined<mode>"
1019 [(set (match_operand:VB 0 "register_operand" "=vr")
1020 (unspec:VB [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
1021 "TARGET_VECTOR"
1022 ""
1023 [(set_attr "type" "vector")])
1025 (define_insn "@vundefined<mode>"
1026 [(set (match_operand:VT 0 "register_operand" "=vr")
1027 (unspec:VT [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
1028 "TARGET_VECTOR"
1029 ""
1030 [(set_attr "type" "vector")])
1032 (define_expand "@vreinterpret<mode>"
1033 [(set (match_operand:V 0 "register_operand")
1034 (match_operand 1 "vector_any_register_operand"))]
1035 "TARGET_VECTOR"
1036 {
1037 emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1]));
1038 DONE;
1039 }
1040 )
1042 (define_expand "@vreinterpret<mode>"
1043 [(set (match_operand:VB 0 "register_operand")
1044 (match_operand 1 "vector_any_register_operand"))]
1045 "TARGET_VECTOR"
1046 {
1047 emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1]));
1048 DONE;
1049 }
1050 )
1052 ;; This pattern is used to hold the AVL operand for
1053 ;; RVV instructions that implicitly use VLMAX AVL.
1054 ;; RVV instruction implicitly use GPR that is ultimately
1055 ;; defined by this pattern is safe for VSETVL pass emit
1056 ;; a vsetvl instruction modify this register after RA.
1057 ;; Case 1:
1058 ;; vlmax_avl a5
1059 ;; ... (across many blocks)
1060 ;; vadd (implicit use a5) ====> emit: vsetvl a5,zero
1061 ;; Case 2:
1062 ;; vlmax_avl a5
1063 ;; ... (across many blocks)
1064 ;; mv a6,a5
1065 ;; ... (across many blocks)
1066 ;; vadd (implicit use a6) ====> emit: vsetvl a6,zero
1067 ;; Case 3:
1068 ;; vlmax_avl a5
1069 ;; ... (across many blocks)
1070 ;; store mem,a5 (spill)
1071 ;; ... (across many blocks)
1072 ;; load a7,mem (spill)
1073 ;; ... (across many blocks)
1074 ;; vadd (implicit use a7) ====> emit: vsetvl a7,zero
1075 ;; Such cases are all safe for VSETVL PASS to emit a vsetvl
1076 ;; instruction that modifies the AVL operand.
1077 (define_insn "@vlmax_avl<mode>"
1078 [(set (match_operand:P 0 "register_operand" "=r")
1079 (unspec:P [(match_operand:P 1 "const_int_operand" "i")] UNSPEC_VLMAX))]
1080 "TARGET_VECTOR"
1081 ""
1082 [(set_attr "type" "vsetvl_pre")]
1083 )
1085 ;; Set VXRM
1086 (define_insn "vxrmsi"
1087 [(set (reg:SI VXRM_REGNUM)
1088 (match_operand:SI 0 "const_int_operand" "i"))]
1089 "TARGET_VECTOR"
1090 "csrwi\tvxrm,%0"
1091 [(set_attr "type" "wrvxrm")
1092 (set_attr "mode" "SI")])
1094 ;; Set FRM
1095 (define_insn "fsrmsi_backup"
1096 [(set (match_operand:SI 0 "register_operand" "=r,r")
1097 (reg:SI FRM_REGNUM))
1098 (set (reg:SI FRM_REGNUM)
1099 (match_operand:SI 1 "reg_or_int_operand" "r,i"))]
1100 "TARGET_VECTOR"
1101 "@
1102 fsrm\t%0,%1
1103 fsrmi\t%0,%1"
1104 [(set_attr "type" "wrfrm,wrfrm")
1105 (set_attr "mode" "SI")]
1106 )
1108 (define_insn "fsrmsi_restore"
1109 [(set (reg:SI FRM_REGNUM)
1110 (match_operand:SI 0 "reg_or_int_operand" "r,i"))]
1111 "TARGET_VECTOR"
1112 "@
1113 fsrm\t%0
1114 fsrmi\t%0"
1115 [(set_attr "type" "wrfrm,wrfrm")
1116 (set_attr "mode" "SI")]
1117 )
1119 ;; The volatile fsrmsi restore is used for the exit point for the
1120 ;; dynamic mode switching. It will generate one volatile fsrm a5
1121 ;; which won't be eliminated.
1122 (define_insn "fsrmsi_restore_volatile"
1123 [(set (reg:SI FRM_REGNUM)
1124 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
1125 UNSPECV_FRM_RESTORE_EXIT))]
1126 "TARGET_VECTOR"
1127 "fsrm\t%0"
1128 [(set_attr "type" "wrfrm")
1129 (set_attr "mode" "SI")]
1130 )
1132 ;; Read FRM
1133 (define_insn "frrmsi"
1134 [(set (match_operand:SI 0 "register_operand" "=r")
1135 (reg:SI FRM_REGNUM))]
1136 "TARGET_VECTOR"
1137 "frrm\t%0"
1138 [(set_attr "type" "fmove")
1139 (set_attr "mode" "SI")]
1140 )
1142 ;; -----------------------------------------------------------------
1143 ;; ---- Moves Operations
1144 ;; -----------------------------------------------------------------
1146 (define_expand "mov<mode>"
1147 [(set (match_operand:V 0 "reg_or_mem_operand")
1148 (match_operand:V 1 "general_operand"))]
1149 "TARGET_VECTOR"
1150 {
1151 /* For whole register move, we transform the pattern into the format
1152 that excludes the clobber of scratch register.
1154 We include clobber of a scalar scratch register which is going to be
1155 used for emit of vsetvl instruction after reload_completed since we
1156 need vsetvl instruction to set VL/VTYPE global status for fractional
1157 vector load/store.
1159 For example:
1160 [(set (match_operand:RVVMF8QI v24)
1161 (match_operand:RVVMF8QI (mem: a4)))
1162 (clobber (scratch:SI a5))]
1163 ====>> vsetvl a5,zero,e8,mf8
1164 ====>> vle8.v v24,(a4)
1166 Philosophy:
1168 - Clobber a scalar scratch register for each mov<mode>.
1170 - Classify the machine_mode mode = <MODE>mode into 2 class:
1171 Whole register move and fractional register move.
1173 - Transform and remove scratch clobber register for whole
1174 register move so that we can avoid occupying the scalar
1175 registers.
1177 - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
1178 before spilling. The clobber scratch is used by spilling fractional
1179 registers in IRA/LRA so it's too early. */
1180 if (TARGET_XTHEADVECTOR && reg_or_mem_operand (operands[1], <MODE>mode))
1181 {
1182 emit_insn (gen_pred_th_whole_mov (<MODE>mode, operands[0], operands[1],
1183 RVV_VLMAX, GEN_INT(riscv_vector::VLMAX)));
1184 DONE;
1185 }
1187 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1188 DONE;
1189 })
1191 ;; This pattern is used for code-gen for whole register load/stores.
1192 ;; Also applicable for all register moves.
1193 ;; Fractional vector modes load/store are not allowed to match this pattern.
1194 ;; Mask modes load/store are not allowed to match this pattern.
1195 ;; We separate "*mov<mode>" into "*mov<mode>_whole" and "*mov<mode>_fract" because
1196 ;; we don't want to include fractional load/store in "*mov<mode>" which will
1197 ;; create unexpected patterns in LRA.
1198 ;; For example:
1199 ;; ira rtl:
1200 ;; (insn 20 19 9 2 (set (reg/v:RVVMF4QI 97 v1 [ v1 ])
1201 ;; (reg:RVVMF4QI 134 [ _1 ])) "rvv.c":9:22 571 {*movvnx2qi_fract}
1202 ;; (nil))
1203 ;; When the value of pseudo register 134 of the insn above is discovered already
1204 ;; spilled in the memory during LRA.
1205 ;; LRA will reload this pattern into a memory load instruction pattern.
1206 ;; Because RVVMF4QI is a fractional vector, we want LRA reload this pattern into
1207 ;; (insn 20 19 9 2 (parallel [
1208 ;; (set (reg:RVVMF4QI 98 v2 [orig:134 _1 ] [134])
1209 ;; (mem/c:RVVMF4QI (reg:SI 13 a3 [155]) [1 %sfp+[-2, -2] S[2, 2] A8]))
1210 ;; (clobber (reg:SI 14 a4 [149]))])
1211 ;; So that we could be able to emit vsetvl instruction using clobber scratch a4.
1212 ;; To let LRA generate the expected pattern, we should exclude fractional vector
1213 ;; load/store in "*mov<mode>_whole". Otherwise, it will reload this pattern into:
1214 ;; (insn 20 19 9 2 (set (reg:RVVMF4QI 98 v2 [orig:134 _1 ] [134])
1215 ;; (mem/c:RVVMF4QI (reg:SI 13 a3 [155]) [1 %sfp+[-2, -2] S[2, 2] A8])))
1216 ;; which is not the pattern we want.
1217 ;; According the facts above, we make "*mov<mode>_whole" includes load/store/move for whole
1218 ;; vector modes according to '-march' and "*mov<mode>_fract" only include fractional vector modes.
1219 (define_insn_and_split "*mov<mode>_whole"
1220 [(set (match_operand:V_WHOLE 0 "reg_or_mem_operand" "=vr, m,vr")
1221 (match_operand:V_WHOLE 1 "reg_or_mem_operand" " m,vr,vr"))]
1222 "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
1223 "@
1224 vl%m1re<sew>.v\t%0,%1
1225 vs%m1r.v\t%1,%0
1226 #"
1227 "&& !memory_operand (operands[0], <MODE>mode)
1228 && !memory_operand (operands[1], <MODE>mode)"
1229 [(parallel [(set (match_dup 0) (match_dup 1))
1230 (use (reg:SI VTYPE_REGNUM))])]
1231 ""
1232 [(set_attr "type" "vldr,vstr,vmov")
1233 (set_attr "mode" "<MODE>")])
1235 ;; Full-register moves like vmv1r.v require a valid vtype.
1236 ;; The ABI does not guarantee that the vtype is valid after a function
1237 ;; call so we need to make it dependent on the vtype and have
1238 ;; the vsetvl pass insert a vsetvl if necessary.
1239 ;; To facilitate optimization we keep the reg-reg move patterns "regular"
1240 ;; until split time and only then switch to a pattern like below that
1241 ;; uses the vtype register.
1242 ;; As the use of these patterns is limited (in the general context)
1243 ;; there is no need for helper functions and we can just create the RTX
1244 ;; directly.
1245 (define_insn "*mov<mode>_reg_whole_vtype"
1246 [(set (match_operand:V_WHOLE 0 "reg_or_mem_operand" "=vr")
1247 (match_operand:V_WHOLE 1 "reg_or_mem_operand" " vr"))
1248 (use (reg:SI VTYPE_REGNUM))]
1249 "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
1250 "vmv%m1r.v\t%0,%1"
1251 [(set_attr "type" "vmov")
1252 (set_attr "mode" "<MODE>")])
1254 (define_insn_and_split "*mov<mode>_fract"
1255 [(set (match_operand:V_FRACT 0 "register_operand" "=vr")
1256 (match_operand:V_FRACT 1 "register_operand" " vr"))]
1257 "TARGET_VECTOR"
1258 "#"
1259 "&& 1"
1260 [(parallel [(set (match_dup 0) (match_dup 1))
1261 (use (reg:SI VTYPE_REGNUM))])]
1262 ""
1263 [(set_attr "type" "vmov")
1264 (set_attr "mode" "<MODE>")])
1266 (define_insn "*mov<mode>_fract_vtype"
1267 [(set (match_operand:V_FRACT 0 "register_operand" "=vr")
1268 (match_operand:V_FRACT 1 "register_operand" " vr"))
1269 (use (reg:SI VTYPE_REGNUM))]
1270 "TARGET_VECTOR"
1271 "vmv1r.v\t%0,%1"
1272 [(set_attr "type" "vmov")
1273 (set_attr "mode" "<MODE>")])
1275 (define_expand "mov<mode>"
1276 [(set (match_operand:VB 0 "reg_or_mem_operand")
1277 (match_operand:VB 1 "general_operand"))]
1278 "TARGET_VECTOR"
1279 {
1280 if (TARGET_XTHEADVECTOR && reg_or_mem_operand (operands[1], <MODE>mode))
1281 {
1282 emit_insn (gen_pred_th_whole_mov (<MODE>mode, operands[0], operands[1],
1283 RVV_VLMAX, GEN_INT(riscv_vector::VLMAX)));
1284 DONE;
1285 }
1287 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1288 DONE;
1289 })
1291 (define_insn_and_split "*mov<mode>"
1292 [(set (match_operand:VB 0 "register_operand" "=vr")
1293 (match_operand:VB 1 "register_operand" " vr"))]
1294 "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
1295 "#"
1296 "&& 1"
1297 [(parallel [(set (match_dup 0) (match_dup 1))
1298 (use (reg:SI VTYPE_REGNUM))])]
1299 ""
1300 [(set_attr "type" "vmov")
1301 (set_attr "mode" "<MODE>")])
1303 (define_insn "*mov<mode>_vtype"
1304 [(set (match_operand:VB 0 "register_operand" "=vr")
1305 (match_operand:VB 1 "register_operand" " vr"))
1306 (use (reg:SI VTYPE_REGNUM))]
1307 "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
1308 "vmv1r.v\t%0,%1"
1309 [(set_attr "type" "vmov")
1310 (set_attr "mode" "<MODE>")])
1312 (define_expand "@mov<V_FRACT:mode><P:mode>_lra"
1313 [(parallel
1314 [(set (match_operand:V_FRACT 0 "reg_or_mem_operand")
1315 (match_operand:V_FRACT 1 "reg_or_mem_operand"))
1316 (clobber (match_scratch:P 2))])]
1317 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1318 {})
1320 (define_expand "@mov<VB:mode><P:mode>_lra"
1321 [(parallel
1322 [(set (match_operand:VB 0 "reg_or_mem_operand")
1323 (match_operand:VB 1 "reg_or_mem_operand"))
1324 (clobber (match_scratch:P 2))])]
1325 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1326 {})
1328 (define_insn_and_split "*mov<V_FRACT:mode><P:mode>_lra"
1329 [(set (match_operand:V_FRACT 0 "reg_or_mem_operand" "=vr, m,vr")
1330 (match_operand:V_FRACT 1 "reg_or_mem_operand" " m,vr,vr"))
1331 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1332 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1333 "#"
1334 "&& reload_completed"
1335 [(const_int 0)]
1336 {
1337 if (REG_P (operands[0]) && REG_P (operands[1]))
1338 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1339 else
1340 {
1341 riscv_vector::emit_vlmax_vsetvl (<V_FRACT:MODE>mode, operands[2]);
1342 riscv_vector::emit_vlmax_insn_lra (code_for_pred_mov (<V_FRACT:MODE>mode),
1343 riscv_vector::UNARY_OP, operands, operands[2]);
1344 }
1345 DONE;
1346 }
1347 [(set_attr "type" "vector")]
1348 )
1350 (define_insn_and_split "*mov<VB:mode><P:mode>_lra"
1351 [(set (match_operand:VB 0 "reg_or_mem_operand" "=vr, m,vr")
1352 (match_operand:VB 1 "reg_or_mem_operand" " m,vr,vr"))
1353 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1354 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1355 "#"
1356 "&& reload_completed"
1357 [(const_int 0)]
1358 {
1359 if (REG_P (operands[0]) && REG_P (operands[1]))
1360 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1361 else
1362 {
1363 riscv_vector::emit_vlmax_vsetvl (<VB:MODE>mode, operands[2]);
1364 riscv_vector::emit_vlmax_insn_lra (code_for_pred_mov (<VB:MODE>mode),
1365 riscv_vector::UNARY_MASK_OP, operands, operands[2]);
1366 }
1367 DONE;
1368 }
1369 [(set_attr "type" "vector")]
1370 )
1372 ;; Define tuple modes data movement.
1373 ;; operands[2] is used to save the offset of each subpart.
1374 ;; operands[3] is used to calculate the address for each subpart.
1375 ;; operands[4] is VL of vsetvli instruction.
1376 (define_expand "mov<mode>"
1377 [(parallel [(set (match_operand:VT 0 "reg_or_mem_operand")
1378 (match_operand:VT 1 "general_operand"))
1379 (clobber (match_dup 2))
1380 (clobber (match_dup 3))
1381 (clobber (match_dup 4))])]
1382 "TARGET_VECTOR"
1383 {
1384 /* Need to force register if mem <- !reg. */
1385 if (MEM_P (operands[0]) && !REG_P (operands[1]))
1386 operands[1] = force_reg (<MODE>mode, operands[1]);
1388 if (GET_CODE (operands[1]) == CONST_VECTOR)
1389 {
1390 riscv_vector::expand_tuple_move (operands);
1391 DONE;
1392 }
1394 operands[2] = gen_rtx_SCRATCH (Pmode);
1395 operands[3] = gen_rtx_SCRATCH (Pmode);
1396 operands[4] = gen_rtx_SCRATCH (Pmode);
1397 })
1399 (define_insn_and_split "*mov<VT:mode>_<P:mode>"
1400 [(set (match_operand:VT 0 "reg_or_mem_operand" "=vr,vr, m")
1401 (match_operand:VT 1 "reg_or_mem_operand" " vr, m,vr"))
1402 (clobber (match_scratch:P 2 "=X,&r,&r"))
1403 (clobber (match_scratch:P 3 "=X,&r,&r"))
1404 (clobber (match_scratch:P 4 "=X,&r,&r"))]
1405 "TARGET_VECTOR"
1406 "#"
1407 "&& reload_completed"
1408 [(const_int 0)]
1409 {
1410 riscv_vector::expand_tuple_move (operands);
1411 DONE;
1412 }
1413 [(set_attr "type" "vmov,vlde,vste")
1414 (set_attr "mode" "<VT:MODE>")
1415 (set (attr "avl_type_idx") (const_int INVALID_ATTRIBUTE))
1416 (set (attr "mode_idx") (const_int INVALID_ATTRIBUTE))])
1418 ;; -----------------------------------------------------------------
1419 ;; ---- VLS Moves Operations
1420 ;; -----------------------------------------------------------------
1422 (define_expand "mov<mode>"
1423 [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand")
1424 (match_operand:VLS_AVL_IMM 1 "general_operand"))]
1425 "TARGET_VECTOR"
1426 {
1427 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1428 DONE;
1429 })
1431 (define_insn_and_split "*mov<mode>"
1432 [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
1433 (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
1434 "TARGET_VECTOR
1435 && (register_operand (operands[0], <MODE>mode)
1436 || register_operand (operands[1], <MODE>mode))"
1437 "@
1438 #
1439 #
1440 vmv%m1r.v\t%0,%1"
1441 "&& reload_completed
1442 && (!register_operand (operands[0], <MODE>mode)
1443 || !register_operand (operands[1], <MODE>mode))"
1444 [(const_int 0)]
1445 {
1446 bool ok_p = riscv_vector::legitimize_move (operands[0], &operands[1]);
1447 gcc_assert (ok_p);
1448 DONE;
1449 }
1450 [(set_attr "type" "vlde,vste,vmov")
1451 (set_attr "mode" "<MODE>")
1452 (set (attr "avl_type_idx") (const_int INVALID_ATTRIBUTE))
1453 (set (attr "mode_idx") (const_int INVALID_ATTRIBUTE))]
1454 )
1456 (define_expand "mov<mode>"
1457 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
1458 (match_operand:VLS_AVL_REG 1 "general_operand"))]
1459 "TARGET_VECTOR"
1460 {
1461 bool ok_p = riscv_vector::legitimize_move (operands[0], &operands[1]);
1462 gcc_assert (ok_p);
1463 DONE;
1464 })
1466 (define_expand "@mov<VLS_AVL_REG:mode><P:mode>_lra"
1467 [(parallel
1468 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
1469 (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand"))
1470 (clobber (match_scratch:P 2))])]
1471 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1472 {})
1474 (define_insn_and_split "*mov<VLS_AVL_REG:mode><P:mode>_lra"
1475 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr")
1476 (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr"))
1477 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1478 "TARGET_VECTOR && (lra_in_progress || reload_completed)
1479 && (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
1480 || register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"
1481 "#"
1482 "&& reload_completed"
1483 [(const_int 0)]
1484 {
1485 if (REG_P (operands[0]) && REG_P (operands[1]))
1486 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1487 else
1488 {
1489 emit_move_insn (operands[2], gen_int_mode (GET_MODE_NUNITS (<VLS_AVL_REG:MODE>mode),
1490 Pmode));
1491 unsigned insn_flags
1492 = GET_MODE_CLASS (<VLS_AVL_REG:MODE>mode) == MODE_VECTOR_BOOL
1493 ? riscv_vector::UNARY_MASK_OP
1494 : riscv_vector::UNARY_OP;
1495 riscv_vector::emit_nonvlmax_insn (code_for_pred_mov (<VLS_AVL_REG:MODE>mode),
1496 insn_flags, operands, operands[2]);
1497 }
1498 DONE;
1499 }
1500 [(set_attr "type" "vlde,vste,vmov")
1501 (set_attr "mode" "<VLS_AVL_REG:MODE>")
1502 (set (attr "avl_type_idx") (const_int INVALID_ATTRIBUTE))
1503 (set (attr "mode_idx") (const_int INVALID_ATTRIBUTE))]
1504 )
1506 (define_insn_and_split "*mov<mode>_vls"
1507 [(set (match_operand:VLS 0 "register_operand" "=vr")
1508 (match_operand:VLS 1 "register_operand" " vr"))]
1509 "TARGET_VECTOR"
1510 "#"
1511 "&& 1"
1512 [(parallel [(set (match_dup 0) (match_dup 1))
1513 (use (reg:SI VTYPE_REGNUM))])]
1514 ""
1515 [(set_attr "type" "vmov")
1516 (set_attr "mode" "<MODE>")])
1518 (define_insn "*mov<mode>_vls_vtype"
1519 [(set (match_operand:VLS 0 "register_operand" "=vr")
1520 (match_operand:VLS 1 "register_operand" " vr"))
1521 (use (reg:SI VTYPE_REGNUM))]
1522 "TARGET_VECTOR"
1523 "vmv%m1r.v\t%0,%1"
1524 [(set_attr "type" "vmov")
1525 (set_attr "mode" "<MODE>")])
1527 (define_insn_and_split "*mov<mode>_vls"
1528 [(set (match_operand:VLSB 0 "register_operand" "=vr")
1529 (match_operand:VLSB 1 "register_operand" " vr"))]
1530 "TARGET_VECTOR"
1531 "#"
1532 "&& 1"
1533 [(parallel [(set (match_dup 0) (match_dup 1))
1534 (use (reg:SI VTYPE_REGNUM))])]
1535 ""
1536 [(set_attr "type" "vmov")
1537 (set_attr "mode" "<MODE>")])
1539 (define_insn "*mov<mode>_vls_vtype"
1540 [(set (match_operand:VLSB 0 "register_operand" "=vr")
1541 (match_operand:VLSB 1 "register_operand" " vr"))
1542 (use (reg:SI VTYPE_REGNUM))]
1543 "TARGET_VECTOR"
1544 "vmv1r.v\t%0,%1"
1545 [(set_attr "type" "vmov")
1546 (set_attr "mode" "<MODE>")])
1548 ;; According to RVV ISA:
1549 ;; If an element accessed by a vector memory instruction is not naturally aligned to the size of the element,
1550 ;; either the element is transferred successfully or an address misaligned exception is raised on that element.
1551 (define_expand "movmisalign<mode>"
1552 [(set (match_operand:V_VLS 0 "nonimmediate_operand")
1553 (match_operand:V_VLS 1 "general_operand"))]
1554 "TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED"
1555 {
1556 emit_move_insn (operands[0], operands[1]);
1557 DONE;
1558 }
1559 )
1561 ;; -----------------------------------------------------------------
1562 ;; ---- Duplicate Operations
1563 ;; -----------------------------------------------------------------
1565 (define_expand "vec_duplicate<mode>"
1566 [(set (match_operand:V_VLS 0 "register_operand")
1567 (vec_duplicate:V_VLS
1568 (match_operand:<VEL> 1 "direct_broadcast_operand")))]
1569 "TARGET_VECTOR"
1570 {
1571 /* Early expand DImode broadcast in RV32 system to avoid RA reload
1572 generate (set (reg) (vec_duplicate:DI)). */
1573 bool gt_p = maybe_gt (GET_MODE_SIZE (<VEL>mode), GET_MODE_SIZE (Pmode));
1574 if (!FLOAT_MODE_P (<VEL>mode) && gt_p)
1575 {
1576 riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode),
1577 riscv_vector::UNARY_OP, operands);
1578 DONE;
1579 }
1580 /* Otherwise, allow it fall into general vec_duplicate pattern
1581 which allow us to have vv->vx combine optimization in later pass. */
1582 })
1584 ;; According to GCC internal:
1585 ;; This pattern only handles duplicates of non-constant inputs.
1586 ;; Constant vectors go through the movm pattern instead.
1587 ;; So "direct_broadcast_operand" can only be mem or reg, no CONSTANT.
1588 (define_insn_and_split "*vec_duplicate<mode>"
1589 [(set (match_operand:V_VLS 0 "register_operand")
1590 (vec_duplicate:V_VLS
1591 (match_operand:<VEL> 1 "direct_broadcast_operand")))]
1592 "TARGET_VECTOR && can_create_pseudo_p ()"
1593 "#"
1594 "&& 1"
1595 [(const_int 0)]
1596 {
1597 riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode),
1598 riscv_vector::UNARY_OP, operands);
1599 DONE;
1600 }
1601 [(set_attr "type" "vector")]
1602 )
1604 ;; -----------------------------------------------------------------
1605 ;; ---- 6. Configuration-Setting Instructions
1606 ;; -----------------------------------------------------------------
1607 ;; Includes:
1608 ;; - 6.1 vsetvli/vsetivli/vsetvl instructions
1609 ;; -----------------------------------------------------------------
1611 ;; we don't define vsetvli as unspec_volatile which has side effects.
1612 ;; This instruction can be scheduled by the instruction scheduler.
1613 ;; This means these instructions will be deleted when
1614 ;; there is no instructions using vl or vtype in the following.
1615 ;; rd | rs1 | AVL value | Effect on vl
1616 ;; - | !x0 | x[rs1] | Normal stripmining
1617 ;; !x0 | x0 | ~0 | Set vl to VLMAX
1618 ;; operands[0]: VL.
1619 ;; operands[1]: AVL.
1620 ;; operands[2]: SEW
1621 ;; operands[3]: LMUL
1622 ;; operands[4]: Tail policy 0 or 1 (undisturbed/agnostic)
1623 ;; operands[5]: Mask policy 0 or 1 (undisturbed/agnostic)
1625 ;; We define 2 types of "vsetvl*" instruction patterns:
1627 ;; - "@vsetvl<mode>" is a parallel format which has side effects.
1629 ;; - "@vsetvl<mode>_no_side_effects" has no side effects.
1631 ;; - "@vsetvl<mode>" is used by "vsetvl" intrinsics and "insert-vsetvl" PASS.
1633 ;; - "@vsetvl<mode>_no_side_effects" is used by GCC standard patterns.
1635 ;; - "@vsetvl<mode>" includes VL/VTYPE global registers status (define set)
1636 ;; and each RVV instruction includes VL/VTYPE global registers status (use)
1637 ;; so that we can guarantee each RVV instruction can execute with correct
1638 ;; VL/VTYPE global registers status after "insert-vsetvl" PASS.
1640 ;; - "@vsetvl<mode>_no_side_effects" has no side effects and excludes VL/VTYPE
1641 ;; global registers status (define set). It's only used by GCC standard pattern
1642 ;; expansion. For example: "mov<mode>" pattern for fractional vector modes which
1643 ;; need to set VL/VTYPE. Then we could manually call this pattern to gain benefits
1644 ;; from the optimization of each GCC internal PASS.
1646 ;; 1. void foo (float *in, float *out)
1647 ;; {
1648 ;; vfloat32mf2_t v = *(vfloat32mf2_t*)in;
1649 ;; *(vfloat32mf2_t*)out = v;
1650 ;; }
1651 ;; We could eliminate the second "vsetvl" by calling "@vsetvl<mode>_no_side_effects".
1652 ;;
1653 ;; "@vsetvl<mode>": ;; "@vsetvl<mode>_no_side_effects":
1654 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; vsetvli a4,zero,e32,mf2,ta,ma
1655 ;; vle32.v v24,(a0) ;; vle32.v v24,(a0)
1656 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; --
1657 ;; vse32.v v24,(a1) ;; vse32.v v24,(a1)
1658 ;; ret ;; ret
1660 ;; 2. void foo (int8_t *in, int8_t *out, int M)
1661 ;; {
1662 ;; for (int i = 0; i < M; i++){
1663 ;; vint8mf2_t v = *(vint8mf2_t*)(in + i);
1664 ;; *(vint8mf2_t*)(out + i) = v;
1665 ;; }
1666 ;; }
1667 ;;
1668 ;; Hoist "vsetvl" instruction in LICM:
1669 ;; "@vsetvl<mode>": ;; "@vsetvl<mode>_no_side_effects":
1670 ;; - ;; vsetvli a4,zero,e32,mf2,ta,ma
1671 ;; LOOP: ;; LOOP:
1672 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; -
1673 ;; vle32.v v24,(a0) ;; vle32.v v24,(a0)
1674 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; -
1675 ;; vse32.v v24,(a1) ;; vse32.v v24,(a1)
1677 ;; However, it may produce wrong codegen if we exclude VL/VTYPE in "vsetvl<mode>".
1678 ;; 3. void foo (int8_t *in, int8_t *out, int32_t *in2, int32_t *out2, int M)
1679 ;; {
1680 ;; for (int i = 0; i < M; i++){
1681 ;; vint8mf2_t v = *(vint8mf2_t*)(in + i);
1682 ;; vint32mf2_t v2 = *(vint32mf2_t*)(in + i + i);
1683 ;; *(vint8mf2_t*)(out + i) = v;
1684 ;; *(vint32mf2_t*)(out + i + i) = v2;
1685 ;; }
1686 ;; }
1687 ;;
1688 ;; vsetvli a6,zero,e8,mf2,ta,ma
1689 ;; vsetvli a2,zero,e32,mf2,ta,ma
1690 ;; LOOP:
1691 ;; vle8.v v25,(a0)
1692 ;; vle32.v v24,(a5)
1693 ;; addi a0,a0,1
1694 ;; vse8.v v25,(a1)
1695 ;; vse32.v v24,(a3)
1696 ;;
1697 ;; Both vle8.v and vle32.v are using the wrong VL/VTYPE status.
1698 ;; We leave it to "insert-vsetvl" PASS to correct this situation.
1700 ;; The "insert-vsetvl" PASS mechanism:
1701 ;; 1. Before "insert-vsetvl" PASS, only RVV instructions are generated
1702 ;; by GCC standard pattern expansion has the corresponding "vsetvl".
1703 ;; We exploit each GCC internal optimization pass to optimize the "vsetvl".
1704 ;; 2. Correct the VL/VTYPE status for each GCC standard pattern RVV instructions.
1705 ;; Insert vsetvl for each RVV instructions that has no VL/VTYPE status if necessary.
1706 ;; For example: RVV intrinsics.
1707 ;; 3. Optimize "vsetvl" instructions.
1709 (define_insn "@vsetvl<mode>"
1710 [(set (match_operand:P 0 "register_operand" "=r")
1711 (unspec:P [(match_operand:P 1 "vector_length_operand" "rvl")
1712 (match_operand 2 "const_int_operand" "i")
1713 (match_operand 3 "const_int_operand" "i")
1714 (match_operand 4 "const_int_operand" "i")
1715 (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))
1716 (set (reg:SI VL_REGNUM)
1717 (unspec:SI [(match_dup 1)
1718 (match_dup 2)
1719 (match_dup 3)] UNSPEC_VSETVL))
1720 (set (reg:SI VTYPE_REGNUM)
1721 (unspec:SI [(match_dup 2)
1722 (match_dup 3)
1723 (match_dup 4)
1724 (match_dup 5)] UNSPEC_VSETVL))]
1725 "TARGET_VECTOR"
1726 "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
1727 [(set_attr "type" "vsetvl")
1728 (set_attr "mode" "<MODE>")
1729 (set (attr "sew") (symbol_ref "INTVAL (operands[2])"))
1730 (set (attr "vlmul") (symbol_ref "INTVAL (operands[3])"))
1731 (set (attr "ta") (symbol_ref "INTVAL (operands[4])"))
1732 (set (attr "ma") (symbol_ref "INTVAL (operands[5])"))])
1734 ;; vsetvl zero,zero,vtype instruction.
1735 ;; This pattern has no side effects and does not set X0 register.
1736 (define_insn "vsetvl_vtype_change_only"
1737 [(set (reg:SI VTYPE_REGNUM)
1738 (unspec:SI
1739 [(match_operand 0 "const_int_operand" "i")
1740 (match_operand 1 "const_int_operand" "i")
1741 (match_operand 2 "const_int_operand" "i")
1742 (match_operand 3 "const_int_operand" "i")] UNSPEC_VSETVL))]
1743 "TARGET_VECTOR"
1744 "vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3"
1745 [(set_attr "type" "vsetvl")
1746 (set_attr "mode" "SI")
1747 (set (attr "sew") (symbol_ref "INTVAL (operands[0])"))
1748 (set (attr "vlmul") (symbol_ref "INTVAL (operands[1])"))
1749 (set (attr "ta") (symbol_ref "INTVAL (operands[2])"))
1750 (set (attr "ma") (symbol_ref "INTVAL (operands[3])"))])
1752 ;; vsetvl zero,rs1,vtype instruction.
1753 ;; The reason we need this pattern since we should avoid setting X0 register
1754 ;; in vsetvl instruction pattern.
1755 (define_insn "@vsetvl_discard_result<mode>"
1756 [(set (reg:SI VL_REGNUM)
1757 (unspec:SI [(match_operand:P 0 "vector_length_operand" "rvl")
1758 (match_operand 1 "const_int_operand" "i")
1759 (match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL))
1760 (set (reg:SI VTYPE_REGNUM)
1761 (unspec:SI [(match_dup 1)
1762 (match_dup 2)
1763 (match_operand 3 "const_int_operand" "i")
1764 (match_operand 4 "const_int_operand" "i")] UNSPEC_VSETVL))]
1765 "TARGET_VECTOR"
1766 "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4"
1767 [(set_attr "type" "vsetvl")
1768 (set_attr "mode" "<MODE>")
1769 (set (attr "sew") (symbol_ref "INTVAL (operands[1])"))
1770 (set (attr "vlmul") (symbol_ref "INTVAL (operands[2])"))
1771 (set (attr "ta") (symbol_ref "INTVAL (operands[3])"))
1772 (set (attr "ma") (symbol_ref "INTVAL (operands[4])"))])
1774 ;; It's emit by vsetvl/vsetvlmax intrinsics with no side effects.
1775 ;; Since we have many optimization passes from "expand" to "reload_completed",
1776 ;; such pattern can allow us gain benefits of these optimizations.
1777 (define_insn_and_split "@vsetvl<mode>_no_side_effects"
1778 [(set (match_operand:P 0 "register_operand" "=r")
1779 (unspec:P [(match_operand:P 1 "vector_length_operand" "rvl")
1780 (match_operand 2 "const_int_operand" "i")
1781 (match_operand 3 "const_int_operand" "i")
1782 (match_operand 4 "const_int_operand" "i")
1783 (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))]
1784 "TARGET_VECTOR"
1785 "#"
1786 "&& epilogue_completed"
1787 [(parallel
1788 [(set (match_dup 0)
1789 (unspec:P [(match_dup 1) (match_dup 2) (match_dup 3)
1790 (match_dup 4) (match_dup 5)] UNSPEC_VSETVL))
1791 (set (reg:SI VL_REGNUM)
1792 (unspec:SI [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_VSETVL))
1793 (set (reg:SI VTYPE_REGNUM)
1794 (unspec:SI [(match_dup 2) (match_dup 3) (match_dup 4)
1795 (match_dup 5)] UNSPEC_VSETVL))])]
1796 ""
1797 [(set_attr "type" "vsetvl")
1798 (set_attr "mode" "SI")])
1800 ;; This pattern use to combine bellow two insns and then further remove
1801 ;; unnecessary sign_extend operations:
1802 ;; (set (reg:DI 134 [ _1 ])
1803 ;; (unspec:DI [
1804 ;; (const_int 19 [0x13])
1805 ;; (const_int 8 [0x8])
1806 ;; (const_int 5 [0x5])
1807 ;; (const_int 2 [0x2]) repeated x2
1808 ;; ] UNSPEC_VSETVL))
1809 ;; (set (reg/v:DI 135 [ <retval> ])
1810 ;; (sign_extend:DI (subreg:SI (reg:DI 134 [ _1 ]) 0)))
1811 ;;
1812 ;; The reason we can remove signe_extend is because currently the vl value
1813 ;; returned by the vsetvl instruction ranges from 0 to 65536 (uint16_t), and
1814 ;; bits 17 to 63 (including 31) are always 0, so there is no change after
1815 ;; sign_extend. Note that for HI and QI modes we cannot do this.
1816 ;; Of course, if the range of instructions returned by vsetvl later expands
1817 ;; to 32bits, then this combine pattern needs to be removed. But that could be
1818 ;; a long time from now.
1819 (define_insn_and_split "*vsetvldi_no_side_effects_si_extend"
1820 [(set (match_operand:DI 0 "register_operand")
1821 (sign_extend:DI
1822 (subreg:SI
1823 (unspec:DI [(match_operand:P 1 "vector_length_operand")
1824 (match_operand 2 "const_int_operand")
1825 (match_operand 3 "const_int_operand")
1826 (match_operand 4 "const_int_operand")
1827 (match_operand 5 "const_int_operand")] UNSPEC_VSETVL) 0)))]
1828 "TARGET_VECTOR && TARGET_64BIT"
1829 "#"
1830 "&& 1"
1831 [(set (match_dup 0)
1832 (unspec:DI [(match_dup 1)
1833 (match_dup 2)
1834 (match_dup 3)
1835 (match_dup 4)
1836 (match_dup 5)] UNSPEC_VSETVL))]
1837 ""
1838 [(set_attr "type" "vsetvl")
1839 (set_attr "mode" "SI")])
1841 ;; RVV machine description matching format
1842 ;; (define_insn ""
1843 ;; [(set (match_operand:MODE 0)
1844 ;; (if_then_else:MODE
1845 ;; (unspec:<MODE:VM>
1846 ;; [(match_operand:<VM> 1 "vector_mask_operand")
1847 ;; (match_operand N + 4 "vector_length_operand")
1848 ;; (match_operand N + 5 "const_int_operand")
1849 ;; (match_operand N + 6 "const_int_operand")
1850 ;; (reg:SI VL_REGNUM)
1851 ;; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1852 ;; (instruction operation:MODE
1853 ;; (match_operand 3
1854 ;; (match_operand 4
1855 ;; (match_operand 5
1856 ;; ................
1857 ;; (match_operand N + 3)
1858 ;; (match_operand:MODE 2 "vector_reg_or_const0_operand")))]
1859 ;;
1860 ;; (unspec:[........] UNSPEC_VPREDICATE) is a predicate wrapper.
1861 ;; Include mask predicate && length predicate && vector policy.
1863 ;; -------------------------------------------------------------------------------
1864 ;; ---- Predicated Mov
1865 ;; -------------------------------------------------------------------------------
1866 ;; Includes:
1867 ;; - 7.4. Vector Unit-Stride Instructions
1868 ;; - 11.15 Vector Integer Merge Instructions
1869 ;; - 11.16 Vector Integer Move Instructions
1870 ;; - 13.16 Vector Floating-Point Move Instruction
1871 ;; - 15.1 Vector Mask-Register Logical Instructions
1872 ;; -------------------------------------------------------------------------------
1874 ;; vle.v/vse.v/vmv.v.v.
1875 ;; For vle.v/vmv.v.v, we may need merge and mask operand.
1876 ;; For vse.v, we don't need merge operand, so it should always match "vu".
1877 ;; constraint alternative 0 ~ 1 match vle.v.
1878 ;; constraint alternative 2 match vse.v.
1879 ;; constraint alternative 3 match vmv.v.v.
1881 ;; If operand 3 is a const_vector, then it is left to pred_broadcast patterns.
1882 (define_expand "@pred_mov<mode>"
1883 [(set (match_operand:V_VLS 0 "nonimmediate_operand")
1884 (if_then_else:V_VLS
1885 (unspec:<VM>
1886 [(match_operand:<VM> 1 "vector_mask_operand")
1887 (match_operand 4 "vector_length_operand")
1888 (match_operand 5 "const_int_operand")
1889 (match_operand 6 "const_int_operand")
1890 (match_operand 7 "const_int_operand")
1891 (reg:SI VL_REGNUM)
1892 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1893 (match_operand:V_VLS 3 "vector_move_operand")
1894 (match_operand:V_VLS 2 "vector_merge_operand")))]
1895 "TARGET_VECTOR"
1896 {})
1898 ;; vle.v/vse.v,vmv.v.v
1899 (define_insn_and_split "*pred_mov<mode>"
1900 [(set (match_operand:V_VLS 0 "nonimmediate_operand" "=vr, vr, vd, m, vr, vr")
1901 (if_then_else:V_VLS
1902 (unspec:<VM>
1903 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm, vmWc1, Wc1, Wc1")
1904 (match_operand 4 "vector_length_operand" " rvl, rvl, rvl, rvl, rvl, rvl")
1905 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
1906 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
1907 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
1908 (reg:SI VL_REGNUM)
1909 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1910 (match_operand:V_VLS 3 "reg_or_mem_operand" " m, m, m, vr, vr, vr")
1911 (match_operand:V_VLS 2 "vector_merge_operand" " 0, vu, vu, vu, vu, 0")))]
1912 "(TARGET_VECTOR
1913 && (register_operand (operands[0], <MODE>mode)
1914 || register_operand (operands[3], <MODE>mode)))"
1915 "@
1916 vle<sew>.v\t%0,%3%p1
1917 vle<sew>.v\t%0,%3
1918 vle<sew>.v\t%0,%3,%1.t
1919 vse<sew>.v\t%3,%0%p1
1920 vmv.v.v\t%0,%3
1921 vmv.v.v\t%0,%3"
1922 "&& riscv_vector::whole_reg_to_reg_move_p (operands, <MODE>mode, 7)"
1923 [(set (match_dup 0) (match_dup 3))]
1924 ""
1925 [(set_attr "type" "vlde,vlde,vlde,vste,vimov,vimov")
1926 (set_attr "mode" "<MODE>")])
1928 ;; Dedicated pattern for vse.v instruction since we can't reuse pred_mov pattern to include
1929 ;; memory operand as input which will produce inferior codegen.
1930 (define_insn "@pred_store<mode>"
1931 [(set (match_operand:V 0 "memory_operand" "+m")
1932 (if_then_else:V
1933 (unspec:<VM>
1934 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
1935 (match_operand 3 "vector_length_operand" " rvl")
1936 (match_operand 4 "const_int_operand" " i")
1937 (reg:SI VL_REGNUM)
1938 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1939 (match_operand:V 2 "register_operand" " vr")
1940 (match_dup 0)))]
1941 "TARGET_VECTOR"
1942 "vse<sew>.v\t%2,%0%p1"
1943 [(set_attr "type" "vste")
1944 (set_attr "mode" "<MODE>")
1945 (set (attr "avl_type_idx") (const_int 4))
1946 (set_attr "vl_op_idx" "3")])
1948 ;; vlm.v/vsm.v/vmclr.m/vmset.m.
1949 ;; constraint alternative 0 match vlm.v.
1950 ;; constraint alternative 1 match vsm.v.
1951 ;; constraint alternative 3 match vmclr.m.
1952 ;; constraint alternative 4 match vmset.m.
1953 (define_insn_and_split "@pred_mov<mode>"
1954 [(set (match_operand:VB_VLS 0 "nonimmediate_operand" "=vr, m, vr, vr, vr")
1955 (if_then_else:VB_VLS
1956 (unspec:VB_VLS
1957 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1")
1958 (match_operand 4 "vector_length_operand" "rvl, rvl, rvl, rvl, rvl")
1959 (match_operand 5 "const_int_operand" " i, i, i, i, i")
1960 (reg:SI VL_REGNUM)
1961 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1962 (match_operand:VB_VLS 3 "vector_move_operand" " m, vr, vr, Wc0, Wc1")
1963 (match_operand:VB_VLS 2 "vector_undef_operand" " vu, vu, vu, vu, vu")))]
1964 "TARGET_VECTOR"
1965 "@
1966 vlm.v\t%0,%3
1967 vsm.v\t%3,%0
1968 vmmv.m\t%0,%3
1969 vmclr.m\t%0
1970 vmset.m\t%0"
1971 "&& riscv_vector::whole_reg_to_reg_move_p (operands, <MODE>mode, 5)"
1972 [(set (match_dup 0) (match_dup 3))]
1973 ""
1974 [(set_attr "type" "vldm,vstm,vmalu,vmalu,vmalu")
1975 (set_attr "mode" "<MODE>")])
1977 ;; Dedicated pattern for vsm.v instruction since we can't reuse pred_mov pattern to include
1978 ;; memory operand as input which will produce inferior codegen.
1979 (define_insn "@pred_store<mode>"
1980 [(set (match_operand:VB 0 "memory_operand" "+m")
1981 (if_then_else:VB
1982 (unspec:VB
1983 [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
1984 (match_operand 3 "vector_length_operand" "rvl")
1985 (match_operand 4 "const_int_operand" " i")
1986 (reg:SI VL_REGNUM)
1987 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1988 (match_operand:VB 2 "register_operand" " vr")
1989 (match_dup 0)))]
1990 "TARGET_VECTOR"
1991 "vsm.v\t%2,%0"
1992 [(set_attr "type" "vstm")
1993 (set_attr "mode" "<MODE>")
1994 (set (attr "avl_type_idx") (const_int 4))
1995 (set_attr "vl_op_idx" "3")])
1997 (define_insn "@pred_merge<mode>"
1998 [(set (match_operand:V_VLS 0 "register_operand" "=vd,vd,vd,vd")
1999 (if_then_else:V_VLS
2000 (unspec:<VM>
2001 [(match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
2002 (match_operand 6 "const_int_operand" " i, i, i, i")
2003 (match_operand 7 "const_int_operand" " i, i, i, i")
2004 (reg:SI VL_REGNUM)
2005 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2006 (vec_merge:V_VLS
2007 (match_operand:V_VLS 3 "vector_arith_operand" " vr,vr,vi,vi")
2008 (match_operand:V_VLS 2 "register_operand" " vr,vr,vr,vr")
2009 (match_operand:<VM> 4 "register_operand" " vm,vm,vm,vm"))
2010 (match_operand:V_VLS 1 "vector_merge_operand" " vu, 0,vu, 0")))]
2011 "TARGET_VECTOR"
2012 "vmerge.v%o3m\t%0,%2,%v3,%4"
2013 [(set_attr "type" "vimerge")
2014 (set_attr "mode" "<MODE>")])
2016 (define_insn "@pred_merge<mode>_scalar"
2017 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd")
2018 (if_then_else:V_VLSI_QHS
2019 (unspec:<VM>
2020 [(match_operand 5 "vector_length_operand" "rvl,rvl")
2021 (match_operand 6 "const_int_operand" " i, i")
2022 (match_operand 7 "const_int_operand" " i, i")
2023 (reg:SI VL_REGNUM)
2024 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2025 (vec_merge:V_VLSI_QHS
2026 (vec_duplicate:V_VLSI_QHS
2027 (match_operand:<VEL> 3 "register_operand" " r, r"))
2028 (match_operand:V_VLSI_QHS 2 "register_operand" " vr,vr")
2029 (match_operand:<VM> 4 "register_operand" " vm,vm"))
2030 (match_operand:V_VLSI_QHS 1 "vector_merge_operand" " vu, 0")))]
2031 "TARGET_VECTOR"
2032 "vmerge.vxm\t%0,%2,%3,%4"
2033 [(set_attr "type" "vimerge")
2034 (set_attr "mode" "<MODE>")])
2036 (define_expand "@pred_merge<mode>_scalar"
2037 [(set (match_operand:V_VLSI_D 0 "register_operand")
2038 (if_then_else:V_VLSI_D
2039 (unspec:<VM>
2040 [(match_operand 5 "vector_length_operand")
2041 (match_operand 6 "const_int_operand")
2042 (match_operand 7 "const_int_operand")
2043 (reg:SI VL_REGNUM)
2044 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2045 (vec_merge:V_VLSI_D
2046 (vec_duplicate:V_VLSI_D
2047 (match_operand:<VEL> 3 "reg_or_int_operand"))
2048 (match_operand:V_VLSI_D 2 "register_operand")
2049 (match_operand:<VM> 4 "register_operand"))
2050 (match_operand:V_VLSI_D 1 "vector_merge_operand")))]
2051 "TARGET_VECTOR"
2052 {
2053 if (riscv_vector::sew64_scalar_helper (
2054 operands,
2055 /* scalar op */&operands[3],
2056 /* vl */operands[5],
2057 <MODE>mode,
2058 riscv_vector::simm5_p (operands[3]),
2059 [] (rtx *operands, rtx broadcast_scalar) {
2060 emit_insn (gen_pred_merge<mode> (operands[0], operands[1],
2061 operands[2], broadcast_scalar, operands[4], operands[5],
2062 operands[6], operands[7]));
2063 },
2064 (riscv_vector::avl_type) INTVAL (operands[7])))
2065 DONE;
2066 })
2068 (define_insn "*pred_merge<mode>_scalar"
2069 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd")
2070 (if_then_else:V_VLSI_D
2071 (unspec:<VM>
2072 [(match_operand 5 "vector_length_operand" "rvl,rvl")
2073 (match_operand 6 "const_int_operand" " i, i")
2074 (match_operand 7 "const_int_operand" " i, i")
2075 (reg:SI VL_REGNUM)
2076 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2077 (vec_merge:V_VLSI_D
2078 (vec_duplicate:V_VLSI_D
2079 (match_operand:<VEL> 3 "register_operand" " r, r"))
2080 (match_operand:V_VLSI_D 2 "register_operand" " vr,vr")
2081 (match_operand:<VM> 4 "register_operand" " vm,vm"))
2082 (match_operand:V_VLSI_D 1 "vector_merge_operand" " vu, 0")))]
2083 "TARGET_VECTOR"
2084 "vmerge.vxm\t%0,%2,%3,%4"
2085 [(set_attr "type" "vimerge")
2086 (set_attr "mode" "<MODE>")])
2088 (define_insn "*pred_merge<mode>_extended_scalar"
2089 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd")
2090 (if_then_else:V_VLSI_D
2091 (unspec:<VM>
2092 [(match_operand 5 "vector_length_operand" "rvl,rvl")
2093 (match_operand 6 "const_int_operand" " i, i")
2094 (match_operand 7 "const_int_operand" " i, i")
2095 (reg:SI VL_REGNUM)
2096 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2097 (vec_merge:V_VLSI_D
2098 (vec_duplicate:V_VLSI_D
2099 (sign_extend:<VEL>
2100 (match_operand:<VSUBEL> 3 "register_operand" " r, r")))
2101 (match_operand:V_VLSI_D 2 "register_operand" " vr,vr")
2102 (match_operand:<VM> 4 "register_operand" " vm,vm"))
2103 (match_operand:V_VLSI_D 1 "vector_merge_operand" " vu, 0")))]
2104 "TARGET_VECTOR && !TARGET_64BIT"
2105 "vmerge.vxm\t%0,%2,%3,%4"
2106 [(set_attr "type" "vimerge")
2107 (set_attr "mode" "<MODE>")])
2109 ;; -------------------------------------------------------------------------------
2110 ;; ---- Predicated Broadcast
2111 ;; -------------------------------------------------------------------------------
2112 ;; Includes:
2113 ;; - 7.5. Vector Strided Instructions (zero stride)
2114 ;; - 11.16 Vector Integer Move Instructions (vmv.v.x)
2115 ;; - 13.16 Vector Floating-Point Move Instruction (vfmv.v.f)
2116 ;; - 16.1 Integer Scalar Move Instructions (vmv.s.x)
2117 ;; - 16.2 Floating-Point Scalar Move Instructions (vfmv.s.f)
2118 ;; -------------------------------------------------------------------------------
2120 ;; According to RVV ISA, vector-scalar instruction doesn't support
2121 ;; operand fetched from 2 consecutive registers, so we should use
2122 ;; vlse.v which is a memory access to broadcast a DImode scalar into a vector.
2123 ;;
2124 ;; Since the optimization flow in GCC is as follows:
2125 ;; expand --> LICM (Loop invariant) --> split.
2126 ;; To use LICM optimization, we postpone generation of vlse.v to split stage since
2127 ;; a memory access instruction can not be optimized by LICM (Loop invariant).
2128 (define_expand "@pred_broadcast<mode>"
2129 [(set (match_operand:V_VLS 0 "register_operand")
2130 (if_then_else:V_VLS
2131 (unspec:<VM>
2132 [(match_operand:<VM> 1 "vector_broadcast_mask_operand")
2133 (match_operand 4 "vector_length_operand")
2134 (match_operand 5 "const_int_operand")
2135 (match_operand 6 "const_int_operand")
2136 (match_operand 7 "const_int_operand")
2137 (reg:SI VL_REGNUM)
2138 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2139 (vec_duplicate:V_VLS
2140 (match_operand:<VEL> 3 "direct_broadcast_operand"))
2141 (match_operand:V_VLS 2 "vector_merge_operand")))]
2142 "TARGET_VECTOR"
2143 {
2144 /* Transform vmv.v.x/vfmv.v.f (avl = 1) into vmv.s.x since vmv.s.x/vfmv.s.f
2145 has better chances to do vsetvl fusion in vsetvl pass. */
2146 if (riscv_vector::splat_to_scalar_move_p (operands))
2147 {
2148 operands[1] = riscv_vector::gen_scalar_move_mask (<VM>mode);
2149 operands[3] = force_reg (<VEL>mode, operands[3]);
2150 }
2151 /* Handle vmv.s.x instruction (Wb1 mask) which has memory scalar. */
2152 else if (satisfies_constraint_Wdm (operands[3]))
2153 {
2154 if (satisfies_constraint_Wb1 (operands[1]))
2155 {
2156 /* Case 1: vmv.s.x (TA, x == memory) ==> vlse.v (TA) */
2157 if (satisfies_constraint_vu (operands[2]))
2158 operands[1] = CONSTM1_RTX (<VM>mode);
2159 else if (GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode))
2160 {
2161 /* Case 2: vmv.s.x (TU, x == memory) ==>
2162 vl = 0 or 1; + vlse.v (TU) in RV32 system */
2163 operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
2164 operands[1] = CONSTM1_RTX (<VM>mode);
2165 }
2166 else
2167 /* Case 3: load x (memory) to register. */
2168 operands[3] = force_reg (<VEL>mode, operands[3]);
2169 }
2170 }
2171 else if (GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode)
2172 && (immediate_operand (operands[3], Pmode)
2173 || (CONST_POLY_INT_P (operands[3])
2174 && known_ge (rtx_to_poly_int64 (operands[3]), 0U)
2175 && known_le (rtx_to_poly_int64 (operands[3]), GET_MODE_SIZE (<MODE>mode)))))
2176 {
2177 rtx tmp = gen_reg_rtx (Pmode);
2178 poly_int64 value = rtx_to_poly_int64 (operands[3]);
2179 emit_move_insn (tmp, gen_int_mode (value, Pmode));
2180 operands[3] = gen_rtx_SIGN_EXTEND (<VEL>mode, tmp);
2181 }
2182 /* Never load (const_int 0) into a register, that's silly. */
2183 else if (operands[3] == CONST0_RTX (<VEL>mode))
2184 ;
2185 /* If we're broadcasting [-16..15] across more than just
2186 element 0, then we can use vmv.v.i directly, thus avoiding
2187 the load of the constant into a GPR. */
2188 else if (CONST_INT_P (operands[3])
2189 && IN_RANGE (INTVAL (operands[3]), -16, 15)
2190 && !satisfies_constraint_Wb1 (operands[1]))
2191 ;
2192 else
2193 operands[3] = force_reg (<VEL>mode, operands[3]);
2194 })
2196 (define_insn_and_split "*pred_broadcast<mode>"
2197 [(set (match_operand:V_VLSI 0 "register_operand" "=vr, vr, vd, vd, vr, vr, vr, vr")
2198 (if_then_else:V_VLSI
2199 (unspec:<VM>
2200 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1, vm, vm,Wc1,Wc1,Wb1,Wb1")
2201 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl,rvl,rvl,rvl,rvl")
2202 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
2203 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
2204 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
2205 (reg:SI VL_REGNUM)
2206 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2207 (vec_duplicate:V_VLSI
2208 (match_operand:<VEL> 3 "direct_broadcast_operand" "rP,rP,Wdm,Wdm,Wdm,Wdm, rJ, rJ"))
2209 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
2210 "TARGET_VECTOR"
2211 "@
2212 vmv.v.%o3\t%0,%3
2213 vmv.v.%o3\t%0,%3
2214 vlse<sew>.v\t%0,%3,zero,%1.t
2215 vlse<sew>.v\t%0,%3,zero,%1.t
2216 vlse<sew>.v\t%0,%3,zero
2217 vlse<sew>.v\t%0,%3,zero
2218 vmv.s.x\t%0,%z3
2219 vmv.s.x\t%0,%z3"
2220 "(register_operand (operands[3], <VEL>mode)
2221 || CONST_POLY_INT_P (operands[3]))
2222 && GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode)"
2223 [(set (match_dup 0)
2224 (if_then_else:V_VLSI (unspec:<VM> [(match_dup 1) (match_dup 4)
2225 (match_dup 5) (match_dup 6) (match_dup 7)
2226 (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2227 (vec_duplicate:V_VLSI (match_dup 3))
2228 (match_dup 2)))]
2229 {
2230 gcc_assert (can_create_pseudo_p ());
2231 if (CONST_POLY_INT_P (operands[3]))
2232 {
2233 rtx tmp = gen_reg_rtx (<VEL>mode);
2234 emit_move_insn (tmp, operands[3]);
2235 operands[3] = tmp;
2236 }
2237 rtx m = assign_stack_local (<VEL>mode, GET_MODE_SIZE (<VEL>mode),
2238 GET_MODE_ALIGNMENT (<VEL>mode));
2239 m = validize_mem (m);
2240 emit_move_insn (m, operands[3]);
2241 m = gen_rtx_MEM (<VEL>mode, force_reg (Pmode, XEXP (m, 0)));
2242 operands[3] = m;
2244 /* For SEW = 64 in RV32 system, we expand vmv.s.x:
2245 andi a2,a2,1
2246 vsetvl zero,a2,e64
2247 vlse64.v */
2248 if (satisfies_constraint_Wb1 (operands[1]))
2249 {
2250 operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
2251 operands[1] = CONSTM1_RTX (<VM>mode);
2252 }
2253 }
2254 [(set_attr "type" "vimov,vimov,vlds,vlds,vlds,vlds,vimovxv,vimovxv")
2255 (set_attr "mode" "<MODE>")])
2257 (define_insn "*pred_broadcast<mode>_zvfh"
2258 [(set (match_operand:V_VLSF 0 "register_operand" "=vr, vr, vr, vr")
2259 (if_then_else:V_VLSF
2260 (unspec:<VM>
2261 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1, Wc1, Wb1, Wb1")
2262 (match_operand 4 "vector_length_operand" "rvl, rvl, rvl, rvl")
2263 (match_operand 5 "const_int_operand" " i, i, i, i")
2264 (match_operand 6 "const_int_operand" " i, i, i, i")
2265 (match_operand 7 "const_int_operand" " i, i, i, i")
2266 (reg:SI VL_REGNUM)
2267 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2268 (vec_duplicate:V_VLSF
2269 (match_operand:<VEL> 3 "direct_broadcast_operand" " f, f, f, f"))
2270 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
2271 "TARGET_VECTOR"
2272 "@
2273 vfmv.v.f\t%0,%3
2274 vfmv.v.f\t%0,%3
2275 vfmv.s.f\t%0,%3
2276 vfmv.s.f\t%0,%3"
2277 [(set_attr "type" "vfmov,vfmov,vfmovfv,vfmovfv")
2278 (set_attr "mode" "<MODE>")])
2280 (define_insn "*pred_broadcast<mode>_zvfhmin"
2281 [(set (match_operand:V_VLSF_ZVFHMIN 0 "register_operand" "=vr, vr, vr, vr")
2282 (if_then_else:V_VLSF_ZVFHMIN
2283 (unspec:<VM>
2284 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" " vm, vm, Wc1, Wc1")
2285 (match_operand 4 "vector_length_operand" "rvl, rvl, rvl, rvl")
2286 (match_operand 5 "const_int_operand" " i, i, i, i")
2287 (match_operand 6 "const_int_operand" " i, i, i, i")
2288 (match_operand 7 "const_int_operand" " i, i, i, i")
2289 (reg:SI VL_REGNUM)
2290 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2291 (vec_duplicate:V_VLSF_ZVFHMIN
2292 (match_operand:<VEL> 3 "direct_broadcast_operand" "Wdm, Wdm, Wdm, Wdm"))
2293 (match_operand:V_VLSF_ZVFHMIN 2 "vector_merge_operand" " vu, 0, vu, 0")))]
2294 "TARGET_VECTOR"
2295 "@
2296 vlse<sew>.v\t%0,%3,zero,%1.t
2297 vlse<sew>.v\t%0,%3,zero,%1.t
2298 vlse<sew>.v\t%0,%3,zero
2299 vlse<sew>.v\t%0,%3,zero"
2300 [(set_attr "type" "vlds,vlds,vlds,vlds")
2301 (set_attr "mode" "<MODE>")])
2303 (define_insn "*pred_broadcast<mode>_extended_scalar"
2304 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vr, vr, vr, vr")
2305 (if_then_else:V_VLSI_D
2306 (unspec:<VM>
2307 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1,Wb1,Wb1")
2308 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
2309 (match_operand 5 "const_int_operand" " i, i, i, i")
2310 (match_operand 6 "const_int_operand" " i, i, i, i")
2311 (match_operand 7 "const_int_operand" " i, i, i, i")
2312 (reg:SI VL_REGNUM)
2313 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2314 (vec_duplicate:V_VLSI_D
2315 (sign_extend:<VEL>
2316 (match_operand:<VSUBEL> 3 "register_operand" " r, r, r, r")))
2317 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2318 "TARGET_VECTOR && !TARGET_64BIT"
2319 "@
2320 vmv.v.x\t%0,%3
2321 vmv.v.x\t%0,%3
2322 vmv.s.x\t%0,%3
2323 vmv.s.x\t%0,%3"
2324 [(set_attr "type" "vimov,vimov,vimovxv,vimovxv")
2325 (set_attr "mode" "<MODE>")])
2327 (define_insn "*pred_broadcast<mode>_zero"
2328 [(set (match_operand:V_VLS 0 "register_operand" "=vr, vr")
2329 (if_then_else:V_VLS
2330 (unspec:<VM>
2331 [(match_operand:<VM> 1 "vector_least_significant_set_mask_operand" "Wb1, Wb1")
2332 (match_operand 4 "vector_length_operand" "rvl, rvl")
2333 (match_operand 5 "const_int_operand" " i, i")
2334 (match_operand 6 "const_int_operand" " i, i")
2335 (match_operand 7 "const_int_operand" " i, i")
2336 (reg:SI VL_REGNUM)
2337 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2338 (match_operand:V_VLS 3 "vector_const_0_operand" "Wc0, Wc0")
2339 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
2340 "TARGET_VECTOR"
2341 "vmv.s.x\t%0,zero"
2342 [(set_attr "type" "vimovxv,vimovxv")
2343 (set_attr "mode" "<MODE>")])
2345 ;; Because (vec_duplicate imm) will be converted to (const_vector imm),
2346 ;; This pattern is used to handle this case.
2347 (define_insn "*pred_broadcast<mode>_imm"
2348 [(set (match_operand:V_VLS 0 "register_operand" "=vr, vr")
2349 (if_then_else:V_VLS
2350 (unspec:<VM>
2351 [(match_operand:<VM> 1 "vector_all_trues_mask_operand" " Wc1, Wc1")
2352 (match_operand 4 "vector_length_operand" " rvl, rvl")
2353 (match_operand 5 "const_int_operand" " i, i")
2354 (match_operand 6 "const_int_operand" " i, i")
2355 (match_operand 7 "const_int_operand" " i, i")
2356 (reg:SI VL_REGNUM)
2357 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2358 (match_operand:V_VLS 3 "vector_const_int_or_double_0_operand" "viWc0, viWc0")
2359 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
2360 "TARGET_VECTOR"
2361 "vmv.v.i\t%0,%v3"
2362 [(set_attr "type" "vimov,vimov")
2363 (set_attr "mode" "<MODE>")])
2365 ;; -------------------------------------------------------------------------------
2366 ;; ---- Predicated Strided loads/stores
2367 ;; -------------------------------------------------------------------------------
2368 ;; Includes:
2369 ;; - 7.5. Vector Strided Instructions
2370 ;; -------------------------------------------------------------------------------
2372 (define_insn "@pred_strided_load<mode>"
2373 [(set (match_operand:V_VLS 0 "register_operand" "=vr, vr, vd, vr, vr, vd")
2374 (if_then_else:V_VLS
2375 (unspec:<VM>
2376 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm, vmWc1, Wc1, vm")
2377 (match_operand 5 "vector_length_operand" " rvl, rvl, rvl, rvl, rvl, rvl")
2378 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2379 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2380 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2381 (reg:SI VL_REGNUM)
2382 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2383 (unspec:V_VLS
2384 [(match_operand:V_VLS 3 "memory_operand" " m, m, m, m, m, m")
2385 (mem:BLK (scratch))
2386 (match_operand 4 "<V_VLS:stride_predicate>" "<V_VLS:stride_load_constraint>")] UNSPEC_STRIDED)
2387 (match_operand:V_VLS 2 "vector_merge_operand" " 0, vu, vu, 0, vu, vu")))]
2388 "TARGET_VECTOR"
2389 "@
2390 vlse<sew>.v\t%0,%3,%z4%p1
2391 vlse<sew>.v\t%0,%3,%z4
2392 vlse<sew>.v\t%0,%3,%z4,%1.t
2393 vle<sew>.v\t%0,%3%p1
2394 vle<sew>.v\t%0,%3
2395 vle<sew>.v\t%0,%3,%1.t"
2396 [(set_attr "type" "vlds")
2397 (set_attr "mode" "<MODE>")])
2399 (define_insn "@pred_strided_store<mode>"
2400 [(set (mem:BLK (scratch))
2401 (unspec:BLK
2402 [(match_operand:V_VLS 0 "memory_operand" " +m, m")
2403 (unspec:<VM>
2404 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1")
2405 (match_operand 4 "vector_length_operand" " rvl, rvl")
2406 (match_operand 5 "const_int_operand" " i, i")
2407 (reg:SI VL_REGNUM)
2408 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2409 (match_operand 2 "<V_VLS:stride_predicate>" "<V_VLS:stride_store_constraint>")
2410 (match_operand:V_VLS 3 "register_operand" " vr, vr")] UNSPEC_STRIDED))]
2411 "TARGET_VECTOR"
2412 "@
2413 vsse<sew>.v\t%3,%0,%z2%p1
2414 vse<sew>.v\t%3,%0%p1"
2415 [(set_attr "type" "vsts")
2416 (set_attr "mode" "<MODE>")
2417 (set (attr "avl_type_idx") (const_int 5))])
2419 ;; -------------------------------------------------------------------------------
2420 ;; ---- Predicated indexed loads/stores
2421 ;; -------------------------------------------------------------------------------
2422 ;; Includes:
2423 ;; - 7.6. Vector Indexed Instructions
2424 ;; -------------------------------------------------------------------------------
2426 ;; DEST eew is same as SOURCE eew, DEST register can overlap SOURCE.
2427 (define_insn "@pred_indexed_<order>load<mode>_same_eew"
2428 [(set (match_operand:VINDEXED 0 "register_operand" "=vd, vr,vd, vr")
2429 (if_then_else:VINDEXED
2430 (unspec:<VM>
2431 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1,vm,Wc1")
2432 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
2433 (match_operand 6 "const_int_operand" " i, i, i, i")
2434 (match_operand 7 "const_int_operand" " i, i, i, i")
2435 (match_operand 8 "const_int_operand" " i, i, i, i")
2436 (reg:SI VL_REGNUM)
2437 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2438 (unspec:VINDEXED
2439 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ,rJ, rJ")
2440 (mem:BLK (scratch))
2441 (match_operand:<VINDEX> 4 "register_operand" " vr, vr,vr, vr")] ORDER)
2442 (match_operand:VINDEXED 2 "vector_merge_operand" " vu, vu, 0, 0")))]
2443 "TARGET_VECTOR"
2444 "vl<order>xei<sew>.v\t%0,(%z3),%4%p1"
2445 [(set_attr "type" "vld<order>x")
2446 (set_attr "mode" "<MODE>")])
2448 ;; DEST eew is greater than SOURCE eew.
2449 (define_insn "@pred_indexed_<order>load<mode>_x2_greater_eew"
2450 [(set (match_operand:VEEWEXT2 0 "register_operand" "=&vr, &vr")
2451 (if_then_else:VEEWEXT2
2452 (unspec:<VM>
2453 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
2454 (match_operand 5 "vector_length_operand" " rvl, rvl")
2455 (match_operand 6 "const_int_operand" " i, i")
2456 (match_operand 7 "const_int_operand" " i, i")
2457 (match_operand 8 "const_int_operand" " i, i")
2458 (reg:SI VL_REGNUM)
2459 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2460 (unspec:VEEWEXT2
2461 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
2462 (mem:BLK (scratch))
2463 (match_operand:<VINDEX_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")] ORDER)
2464 (match_operand:VEEWEXT2 2 "vector_merge_operand" " vu, 0")))]
2465 "TARGET_VECTOR"
2466 "vl<order>xei<double_trunc_sew>.v\t%0,(%z3),%4%p1"
2467 [(set_attr "type" "vld<order>x")
2468 (set_attr "mode" "<MODE>")])
2470 (define_insn "@pred_indexed_<order>load<mode>_x4_greater_eew"
2471 [(set (match_operand:VEEWEXT4 0 "register_operand" "=&vr, &vr")
2472 (if_then_else:VEEWEXT4
2473 (unspec:<VM>
2474 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
2475 (match_operand 5 "vector_length_operand" " rvl, rvl")
2476 (match_operand 6 "const_int_operand" " i, i")
2477 (match_operand 7 "const_int_operand" " i, i")
2478 (match_operand 8 "const_int_operand" " i, i")
2479 (reg:SI VL_REGNUM)
2480 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2481 (unspec:VEEWEXT4
2482 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
2483 (mem:BLK (scratch))
2484 (match_operand:<VINDEX_QUAD_TRUNC> 4 "register_operand" " vr, vr")] ORDER)
2485 (match_operand:VEEWEXT4 2 "vector_merge_operand" " vu, 0")))]
2486 "TARGET_VECTOR"
2487 "vl<order>xei<quad_trunc_sew>.v\t%0,(%z3),%4%p1"
2488 [(set_attr "type" "vld<order>x")
2489 (set_attr "mode" "<MODE>")])
2491 (define_insn "@pred_indexed_<order>load<mode>_x8_greater_eew"
2492 [(set (match_operand:VEEWEXT8 0 "register_operand" "=&vr, &vr")
2493 (if_then_else:VEEWEXT8
2494 (unspec:<VM>
2495 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
2496 (match_operand 5 "vector_length_operand" " rvl, rvl")
2497 (match_operand 6 "const_int_operand" " i, i")
2498 (match_operand 7 "const_int_operand" " i, i")
2499 (match_operand 8 "const_int_operand" " i, i")
2500 (reg:SI VL_REGNUM)
2501 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2502 (unspec:VEEWEXT8
2503 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
2504 (mem:BLK (scratch))
2505 (match_operand:<VINDEX_OCT_TRUNC> 4 "register_operand" " vr, vr")] ORDER)
2506 (match_operand:VEEWEXT8 2 "vector_merge_operand" " vu, 0")))]
2507 "TARGET_VECTOR"
2508 "vl<order>xei<oct_trunc_sew>.v\t%0,(%z3),%4%p1"
2509 [(set_attr "type" "vld<order>x")
2510 (set_attr "mode" "<MODE>")])
2512 ;; DEST eew is smaller than SOURCE eew.
2513 (define_insn "@pred_indexed_<order>load<mode>_x2_smaller_eew"
2514 [(set (match_operand:VEEWTRUNC2 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2515 (if_then_else:VEEWTRUNC2
2516 (unspec:<VM>
2517 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2518 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl, rvl, rvl")
2519 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2520 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2521 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2522 (reg:SI VL_REGNUM)
2523 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2524 (unspec:VEEWTRUNC2
2525 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2526 (mem:BLK (scratch))
2527 (match_operand:<VINDEX_DOUBLE_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2528 (match_operand:VEEWTRUNC2 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2529 "TARGET_VECTOR"
2530 "vl<order>xei<double_ext_sew>.v\t%0,(%z3),%4%p1"
2531 [(set_attr "type" "vld<order>x")
2532 (set_attr "mode" "<MODE>")])
2534 (define_insn "@pred_indexed_<order>load<mode>_x4_smaller_eew"
2535 [(set (match_operand:VEEWTRUNC4 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2536 (if_then_else:VEEWTRUNC4
2537 (unspec:<VM>
2538 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2539 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl, rvl, rvl")
2540 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2541 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2542 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2543 (reg:SI VL_REGNUM)
2544 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2545 (unspec:VEEWTRUNC4
2546 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2547 (mem:BLK (scratch))
2548 (match_operand:<VINDEX_QUAD_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2549 (match_operand:VEEWTRUNC4 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2550 "TARGET_VECTOR"
2551 "vl<order>xei<quad_ext_sew>.v\t%0,(%z3),%4%p1"
2552 [(set_attr "type" "vld<order>x")
2553 (set_attr "mode" "<MODE>")])
2555 (define_insn "@pred_indexed_<order>load<mode>_x8_smaller_eew"
2556 [(set (match_operand:VEEWTRUNC8 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2557 (if_then_else:VEEWTRUNC8
2558 (unspec:<VM>
2559 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2560 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl, rvl, rvl")
2561 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2562 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2563 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2564 (reg:SI VL_REGNUM)
2565 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2566 (unspec:VEEWTRUNC8
2567 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2568 (mem:BLK (scratch))
2569 (match_operand:<VINDEX_OCT_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2570 (match_operand:VEEWTRUNC8 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2571 "TARGET_VECTOR"
2572 "vl<order>xei<oct_ext_sew>.v\t%0,(%z3),%4%p1"
2573 [(set_attr "type" "vld<order>x")
2574 (set_attr "mode" "<MODE>")])
2576 (define_insn "@pred_indexed_<order>store<RATIO64:mode><RATIO64I:mode>"
2577 [(set (mem:BLK (scratch))
2578 (unspec:BLK
2579 [(unspec:<VM>
2580 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2581 (match_operand 4 "vector_length_operand" " rvl")
2582 (match_operand 5 "const_int_operand" " i")
2583 (reg:SI VL_REGNUM)
2584 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2585 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2586 (match_operand:RATIO64I 2 "register_operand" " vr")
2587 (match_operand:RATIO64 3 "register_operand" " vr")] ORDER))]
2588 "TARGET_VECTOR"
2589 "vs<order>xei<RATIO64I:sew>.v\t%3,(%z1),%2%p0"
2590 [(set_attr "type" "vst<order>x")
2591 (set_attr "mode" "<RATIO64:MODE>")])
2593 (define_insn "@pred_indexed_<order>store<RATIO32:mode><RATIO32I:mode>"
2594 [(set (mem:BLK (scratch))
2595 (unspec:BLK
2596 [(unspec:<VM>
2597 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2598 (match_operand 4 "vector_length_operand" " rvl")
2599 (match_operand 5 "const_int_operand" " i")
2600 (reg:SI VL_REGNUM)
2601 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2602 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2603 (match_operand:RATIO32I 2 "register_operand" " vr")
2604 (match_operand:RATIO32 3 "register_operand" " vr")] ORDER))]
2605 "TARGET_VECTOR"
2606 "vs<order>xei<RATIO32I:sew>.v\t%3,(%z1),%2%p0"
2607 [(set_attr "type" "vst<order>x")
2608 (set_attr "mode" "<RATIO32:MODE>")])
2610 (define_insn "@pred_indexed_<order>store<RATIO16:mode><RATIO16I:mode>"
2611 [(set (mem:BLK (scratch))
2612 (unspec:BLK
2613 [(unspec:<VM>
2614 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2615 (match_operand 4 "vector_length_operand" " rvl")
2616 (match_operand 5 "const_int_operand" " i")
2617 (reg:SI VL_REGNUM)
2618 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2619 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2620 (match_operand:RATIO16I 2 "register_operand" " vr")
2621 (match_operand:RATIO16 3 "register_operand" " vr")] ORDER))]
2622 "TARGET_VECTOR"
2623 "vs<order>xei<RATIO16I:sew>.v\t%3,(%z1),%2%p0"
2624 [(set_attr "type" "vst<order>x")
2625 (set_attr "mode" "<RATIO16:MODE>")])
2627 (define_insn "@pred_indexed_<order>store<RATIO8:mode><RATIO8I:mode>"
2628 [(set (mem:BLK (scratch))
2629 (unspec:BLK
2630 [(unspec:<VM>
2631 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2632 (match_operand 4 "vector_length_operand" " rvl")
2633 (match_operand 5 "const_int_operand" " i")
2634 (reg:SI VL_REGNUM)
2635 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2636 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2637 (match_operand:RATIO8I 2 "register_operand" " vr")
2638 (match_operand:RATIO8 3 "register_operand" " vr")] ORDER))]
2639 "TARGET_VECTOR"
2640 "vs<order>xei<RATIO8I:sew>.v\t%3,(%z1),%2%p0"
2641 [(set_attr "type" "vst<order>x")
2642 (set_attr "mode" "<RATIO8:MODE>")])
2644 (define_insn "@pred_indexed_<order>store<RATIO4:mode><RATIO4I:mode>"
2645 [(set (mem:BLK (scratch))
2646 (unspec:BLK
2647 [(unspec:<VM>
2648 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2649 (match_operand 4 "vector_length_operand" " rvl")
2650 (match_operand 5 "const_int_operand" " i")
2651 (reg:SI VL_REGNUM)
2652 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2653 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2654 (match_operand:RATIO4I 2 "register_operand" " vr")
2655 (match_operand:RATIO4 3 "register_operand" " vr")] ORDER))]
2656 "TARGET_VECTOR"
2657 "vs<order>xei<RATIO4I:sew>.v\t%3,(%z1),%2%p0"
2658 [(set_attr "type" "vst<order>x")
2659 (set_attr "mode" "<RATIO4:MODE>")])
2661 (define_insn "@pred_indexed_<order>store<RATIO2:mode><RATIO2I:mode>"
2662 [(set (mem:BLK (scratch))
2663 (unspec:BLK
2664 [(unspec:<VM>
2665 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2666 (match_operand 4 "vector_length_operand" " rvl")
2667 (match_operand 5 "const_int_operand" " i")
2668 (reg:SI VL_REGNUM)
2669 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2670 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2671 (match_operand:RATIO2I 2 "register_operand" " vr")
2672 (match_operand:RATIO2 3 "register_operand" " vr")] ORDER))]
2673 "TARGET_VECTOR"
2674 "vs<order>xei<RATIO2I:sew>.v\t%3,(%z1),%2%p0"
2675 [(set_attr "type" "vst<order>x")
2676 (set_attr "mode" "<RATIO2:MODE>")])
2678 (define_insn "@pred_indexed_<order>store<RATIO1:mode><RATIO1:mode>"
2679 [(set (mem:BLK (scratch))
2680 (unspec:BLK
2681 [(unspec:<VM>
2682 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2683 (match_operand 4 "vector_length_operand" " rvl")
2684 (match_operand 5 "const_int_operand" " i")
2685 (reg:SI VL_REGNUM)
2686 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2687 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2688 (match_operand:RATIO1 2 "register_operand" " vr")
2689 (match_operand:RATIO1 3 "register_operand" " vr")] ORDER))]
2690 "TARGET_VECTOR"
2691 "vs<order>xei<RATIO1:sew>.v\t%3,(%z1),%2%p0"
2692 [(set_attr "type" "vst<order>x")
2693 (set_attr "mode" "<RATIO1:MODE>")])
2695 ;; -------------------------------------------------------------------------------
2696 ;; ---- Predicated integer binary operations
2697 ;; -------------------------------------------------------------------------------
2698 ;; Includes:
2699 ;; - 11.1 Vector Single-Width Integer Add and Subtract
2700 ;; - 11.4 Vector Integer Add-with-Carry/Subtract-with-Borrow Instructions
2701 ;; - 11.5 Vector Bitwise Logical Instructions
2702 ;; - 11.6 Vector Single-Width Bit Shift Instructions
2703 ;; - 11.9 Vector Integer Min/Max Instructions
2704 ;; - 11.10 Vector Single-Width Integer Multiply Instructions
2705 ;; - 11.11 Vector Integer Divide Instructions
2706 ;; -------------------------------------------------------------------------------
2708 (define_insn "@pred_<optab><mode>"
2709 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr, vd, vd, vr, vr, vd, vd, vr, vr")
2710 (if_then_else:V_VLSI
2711 (unspec:<VM>
2712 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1, vm, vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
2713 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl, rvl,rvl,rvl,rvl,rvl,rvl,rvl,rvl,rvl")
2714 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2715 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2716 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2717 (reg:SI VL_REGNUM)
2718 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2719 (any_int_binop:V_VLSI
2720 (match_operand:V_VLSI 3 "<binop_rhs1_predicate>" "<binop_rhs1_constraint>")
2721 (match_operand:V_VLSI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
2722 (match_operand:V_VLSI 2 "vector_merge_operand" "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0")))]
2723 "TARGET_VECTOR"
2724 "@
2725 v<insn>.vv\t%0,%3,%4%p1
2726 v<insn>.vv\t%0,%3,%4%p1
2727 v<insn>.vv\t%0,%3,%4%p1
2728 v<insn>.vv\t%0,%3,%4%p1
2729 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2730 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2731 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2732 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2733 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2734 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2735 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2736 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1"
2737 [(set_attr "type" "<int_binop_insn_type>")
2738 (set_attr "mode" "<MODE>")])
2740 ;; vx instructions patterns.
2741 ;; Note: Unlike vv patterns, we should split them since they are variant.
2742 ;; For vsll.vx/vsra.vx/vsrl.vx the scalar mode should be Pmode whereas the
2743 ;; scalar mode is inner mode of the RVV mode for other vx patterns.
2744 (define_insn "@pred_<optab><mode>_scalar"
2745 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr,vd,vd, vr, vr")
2746 (if_then_else:V_VLSI
2747 (unspec:<VM>
2748 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1")
2749 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl,rvl,rvl,rvl,rvl")
2750 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
2751 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
2752 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
2753 (reg:SI VL_REGNUM)
2754 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2755 (any_shift:V_VLSI
2756 (match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr,vr,vr, vr, vr")
2757 (match_operand 4 "pmode_reg_or_uimm5_operand" " r, r, r, r, K, K, K, K"))
2758 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0,vu, 0, vu, 0")))]
2759 "TARGET_VECTOR"
2760 "v<insn>.v%o4\t%0,%3,%4%p1"
2761 [(set_attr "type" "vshift")
2762 (set_attr "mode" "<MODE>")])
2764 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
2765 (define_insn "@pred_<optab><mode>_scalar"
2766 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2767 (if_then_else:V_VLSI_QHS
2768 (unspec:<VM>
2769 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2770 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
2771 (match_operand 6 "const_int_operand" " i, i, i, i")
2772 (match_operand 7 "const_int_operand" " i, i, i, i")
2773 (match_operand 8 "const_int_operand" " i, i, i, i")
2774 (reg:SI VL_REGNUM)
2775 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2776 (any_commutative_binop:V_VLSI_QHS
2777 (vec_duplicate:V_VLSI_QHS
2778 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2779 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr"))
2780 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2781 "TARGET_VECTOR"
2782 "v<insn>.vx\t%0,%3,%z4%p1"
2783 [(set_attr "type" "<int_binop_insn_type>")
2784 (set_attr "mode" "<MODE>")])
2786 (define_insn "@pred_<optab><mode>_scalar"
2787 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2788 (if_then_else:V_VLSI_QHS
2789 (unspec:<VM>
2790 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2791 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
2792 (match_operand 6 "const_int_operand" " i, i, i, i")
2793 (match_operand 7 "const_int_operand" " i, i, i, i")
2794 (match_operand 8 "const_int_operand" " i, i, i, i")
2795 (reg:SI VL_REGNUM)
2796 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2797 (any_non_commutative_binop:V_VLSI_QHS
2798 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr")
2799 (vec_duplicate:V_VLSI_QHS
2800 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2801 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2802 "TARGET_VECTOR"
2803 "v<insn>.vx\t%0,%3,%z4%p1"
2804 [(set_attr "type" "<int_binop_insn_type>")
2805 (set_attr "mode" "<MODE>")])
2807 (define_insn "@pred_sub<mode>_reverse_scalar"
2808 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2809 (if_then_else:V_VLSI_QHS
2810 (unspec:<VM>
2811 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2812 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
2813 (match_operand 6 "const_int_operand" " i, i, i, i")
2814 (match_operand 7 "const_int_operand" " i, i, i, i")
2815 (match_operand 8 "const_int_operand" " i, i, i, i")
2816 (reg:SI VL_REGNUM)
2817 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2818 (minus:V_VLSI_QHS
2819 (vec_duplicate:V_VLSI_QHS
2820 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2821 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr"))
2822 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2823 "TARGET_VECTOR"
2824 "vrsub.vx\t%0,%3,%z4%p1"
2825 [(set_attr "type" "vialu")
2826 (set_attr "mode" "<MODE>")])
2828 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
2829 ;; we need to deal with SEW = 64 in RV32 system.
2830 (define_expand "@pred_<optab><mode>_scalar"
2831 [(set (match_operand:V_VLSI_D 0 "register_operand")
2832 (if_then_else:V_VLSI_D
2833 (unspec:<VM>
2834 [(match_operand:<VM> 1 "vector_mask_operand")
2835 (match_operand 5 "vector_length_operand")
2836 (match_operand 6 "const_int_operand")
2837 (match_operand 7 "const_int_operand")
2838 (match_operand 8 "const_int_operand")
2839 (reg:SI VL_REGNUM)
2840 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2841 (any_commutative_binop:V_VLSI_D
2842 (vec_duplicate:V_VLSI_D
2843 (match_operand:<VEL> 4 "reg_or_int_operand"))
2844 (match_operand:V_VLSI_D 3 "register_operand"))
2845 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2846 "TARGET_VECTOR"
2847 {
2848 if (riscv_vector::sew64_scalar_helper (
2849 operands,
2850 /* scalar op */&operands[4],
2851 /* vl */operands[5],
2852 <MODE>mode,
2853 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
2854 [] (rtx *operands, rtx broadcast_scalar) {
2855 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
2856 operands[2], operands[3], broadcast_scalar, operands[5],
2857 operands[6], operands[7], operands[8]));
2858 },
2859 (riscv_vector::avl_type) INTVAL (operands[8])))
2860 DONE;
2861 })
2863 (define_insn "*pred_<optab><mode>_scalar"
2864 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2865 (if_then_else:V_VLSI_D
2866 (unspec:<VM>
2867 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2868 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
2869 (match_operand 6 "const_int_operand" " i, i, i, i")
2870 (match_operand 7 "const_int_operand" " i, i, i, i")
2871 (match_operand 8 "const_int_operand" " i, i, i, i")
2872 (reg:SI VL_REGNUM)
2873 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2874 (any_commutative_binop:V_VLSI_D
2875 (vec_duplicate:V_VLSI_D
2876 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2877 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2878 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2879 "TARGET_VECTOR"
2880 "v<insn>.vx\t%0,%3,%z4%p1"
2881 [(set_attr "type" "<int_binop_insn_type>")
2882 (set_attr "mode" "<MODE>")])
2884 (define_insn "*pred_<optab><mode>_extended_scalar"
2885 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2886 (if_then_else:V_VLSI_D
2887 (unspec:<VM>
2888 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2889 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
2890 (match_operand 6 "const_int_operand" " i, i, i, i")
2891 (match_operand 7 "const_int_operand" " i, i, i, i")
2892 (match_operand 8 "const_int_operand" " i, i, i, i")
2893 (reg:SI VL_REGNUM)
2894 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2895 (any_commutative_binop:V_VLSI_D
2896 (vec_duplicate:V_VLSI_D
2897 (sign_extend:<VEL>
2898 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2899 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2900 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2901 "TARGET_VECTOR && !TARGET_64BIT"
2902 "v<insn>.vx\t%0,%3,%z4%p1"
2903 [(set_attr "type" "<int_binop_insn_type>")
2904 (set_attr "mode" "<MODE>")])
2906 (define_expand "@pred_<optab><mode>_scalar"
2907 [(set (match_operand:V_VLSI_D 0 "register_operand")
2908 (if_then_else:V_VLSI_D
2909 (unspec:<VM>
2910 [(match_operand:<VM> 1 "vector_mask_operand")
2911 (match_operand 5 "vector_length_operand")
2912 (match_operand 6 "const_int_operand")
2913 (match_operand 7 "const_int_operand")
2914 (match_operand 8 "const_int_operand")
2915 (reg:SI VL_REGNUM)
2916 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2917 (any_non_commutative_binop:V_VLSI_D
2918 (match_operand:V_VLSI_D 3 "register_operand")
2919 (vec_duplicate:V_VLSI_D
2920 (match_operand:<VEL> 4 "reg_or_int_operand")))
2921 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2922 "TARGET_VECTOR"
2923 {
2924 if (riscv_vector::sew64_scalar_helper (
2925 operands,
2926 /* scalar op */&operands[4],
2927 /* vl */operands[5],
2928 <MODE>mode,
2929 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
2930 [] (rtx *operands, rtx broadcast_scalar) {
2931 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
2932 operands[2], operands[3], broadcast_scalar, operands[5],
2933 operands[6], operands[7], operands[8]));
2934 },
2935 (riscv_vector::avl_type) INTVAL (operands[8])))
2936 DONE;
2937 })
2939 (define_insn "*pred_<optab><mode>_scalar"
2940 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2941 (if_then_else:V_VLSI_D
2942 (unspec:<VM>
2943 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2944 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
2945 (match_operand 6 "const_int_operand" " i, i, i, i")
2946 (match_operand 7 "const_int_operand" " i, i, i, i")
2947 (match_operand 8 "const_int_operand" " i, i, i, i")
2948 (reg:SI VL_REGNUM)
2949 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2950 (any_non_commutative_binop:V_VLSI_D
2951 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr")
2952 (vec_duplicate:V_VLSI_D
2953 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2954 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2955 "TARGET_VECTOR"
2956 "v<insn>.vx\t%0,%3,%z4%p1"
2957 [(set_attr "type" "<int_binop_insn_type>")
2958 (set_attr "mode" "<MODE>")])
2960 (define_insn "*pred_<optab><mode>_extended_scalar"
2961 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2962 (if_then_else:V_VLSI_D
2963 (unspec:<VM>
2964 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2965 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
2966 (match_operand 6 "const_int_operand" " i, i, i, i")
2967 (match_operand 7 "const_int_operand" " i, i, i, i")
2968 (match_operand 8 "const_int_operand" " i, i, i, i")
2969 (reg:SI VL_REGNUM)
2970 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2971 (any_non_commutative_binop:V_VLSI_D
2972 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr")
2973 (vec_duplicate:V_VLSI_D
2974 (sign_extend:<VEL>
2975 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))))
2976 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2977 "TARGET_VECTOR && !TARGET_64BIT"
2978 "v<insn>.vx\t%0,%3,%z4%p1"
2979 [(set_attr "type" "<int_binop_insn_type>")
2980 (set_attr "mode" "<MODE>")])
2982 (define_expand "@pred_sub<mode>_reverse_scalar"
2983 [(set (match_operand:V_VLSI_D 0 "register_operand")
2984 (if_then_else:V_VLSI_D
2985 (unspec:<VM>
2986 [(match_operand:<VM> 1 "vector_mask_operand")
2987 (match_operand 5 "vector_length_operand")
2988 (match_operand 6 "const_int_operand")
2989 (match_operand 7 "const_int_operand")
2990 (match_operand 8 "const_int_operand")
2991 (reg:SI VL_REGNUM)
2992 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2993 (minus:V_VLSI_D
2994 (vec_duplicate:V_VLSI_D
2995 (match_operand:<VEL> 4 "reg_or_int_operand"))
2996 (match_operand:V_VLSI_D 3 "register_operand"))
2997 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2998 "TARGET_VECTOR"
2999 {
3000 if (riscv_vector::sew64_scalar_helper (
3001 operands,
3002 /* scalar op */&operands[4],
3003 /* vl */operands[5],
3004 <MODE>mode,
3005 riscv_vector::neg_simm5_p (operands[4]),
3006 [] (rtx *operands, rtx broadcast_scalar) {
3007 emit_insn (gen_pred_sub<mode> (operands[0], operands[1],
3008 operands[2], broadcast_scalar, operands[3], operands[5],
3009 operands[6], operands[7], operands[8]));
3010 },
3011 (riscv_vector::avl_type) INTVAL (operands[8])))
3012 DONE;
3013 })
3015 (define_insn "*pred_sub<mode>_reverse_scalar"
3016 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
3017 (if_then_else:V_VLSI_D
3018 (unspec:<VM>
3019 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
3020 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
3021 (match_operand 6 "const_int_operand" " i, i, i, i")
3022 (match_operand 7 "const_int_operand" " i, i, i, i")
3023 (match_operand 8 "const_int_operand" " i, i, i, i")
3024 (reg:SI VL_REGNUM)
3025 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3026 (minus:V_VLSI_D
3027 (vec_duplicate:V_VLSI_D
3028 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
3029 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
3030 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
3031 "TARGET_VECTOR"
3032 "vrsub.vx\t%0,%3,%z4%p1"
3033 [(set_attr "type" "vialu")
3034 (set_attr "mode" "<MODE>")])
3036 (define_insn "*pred_sub<mode>_extended_reverse_scalar"
3037 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
3038 (if_then_else:V_VLSI_D
3039 (unspec:<VM>
3040 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
3041 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
3042 (match_operand 6 "const_int_operand" " i, i, i, i")
3043 (match_operand 7 "const_int_operand" " i, i, i, i")
3044 (match_operand 8 "const_int_operand" " i, i, i, i")
3045 (reg:SI VL_REGNUM)
3046 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3047 (minus:V_VLSI_D
3048 (vec_duplicate:V_VLSI_D
3049 (sign_extend:<VEL>
3050 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
3051 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
3052 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
3053 "TARGET_VECTOR && !TARGET_64BIT"
3054 "vrsub.vx\t%0,%3,%z4%p1"
3055 [(set_attr "type" "vialu")
3056 (set_attr "mode" "<MODE>")])
3058 ;; Multiply High instructions.
3059 (define_insn "@pred_mulh<v_su><mode>"
3060 [(set (match_operand:VFULLI 0 "register_operand" "=vd,vd, vr, vr")
3061 (if_then_else:VFULLI
3062 (unspec:<VM>
3063 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
3064 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
3065 (match_operand 6 "const_int_operand" " i, i, i, i")
3066 (match_operand 7 "const_int_operand" " i, i, i, i")
3067 (match_operand 8 "const_int_operand" " i, i, i, i")
3068 (reg:SI VL_REGNUM)
3069 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3070 (unspec:VFULLI
3071 [(match_operand:VFULLI 3 "register_operand" "vr,vr, vr, vr")
3072 (match_operand:VFULLI 4 "register_operand" "vr,vr, vr, vr")] VMULH)
3073 (match_operand:VFULLI 2 "vector_merge_operand" "vu, 0, vu, 0")))]
3074 "TARGET_VECTOR"
3075 "vmulh<v_su>.vv\t%0,%3,%4%p1"
3076 [(set_attr "type" "vimul")
3077 (set_attr "mode" "<MODE>")])
3079 (define_insn "@pred_mulh<v_su><mode>_scalar"
3080 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd, vr, vr")
3081 (if_then_else:VI_QHS
3082 (unspec:<VM>
3083 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
3084 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
3085 (match_operand 6 "const_int_operand" " i, i, i, i")
3086 (match_operand 7 "const_int_operand" " i, i, i, i")
3087 (match_operand 8 "const_int_operand" " i, i, i, i")
3088 (reg:SI VL_REGNUM)
3089 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3090 (unspec:VI_QHS
3091 [(vec_duplicate:VI_QHS
3092 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
3093 (match_operand:VI_QHS 3 "register_operand" "vr,vr, vr, vr")] VMULH)
3094 (match_operand:VI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
3095 "TARGET_VECTOR"
3096 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
3097 [(set_attr "type" "vimul")
3098 (set_attr "mode" "<MODE>")])
3100 (define_expand "@pred_mulh<v_su><mode>_scalar"
3101 [(set (match_operand:VFULLI_D 0 "register_operand")
3102 (if_then_else:VFULLI_D
3103 (unspec:<VM>
3104 [(match_operand:<VM> 1 "vector_mask_operand")
3105 (match_operand 5 "vector_length_operand")
3106 (match_operand 6 "const_int_operand")
3107 (match_operand 7 "const_int_operand")
3108 (match_operand 8 "const_int_operand")
3109 (reg:SI VL_REGNUM)
3110 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3111 (unspec:VFULLI_D
3112 [(vec_duplicate:VFULLI_D
3113 (match_operand:<VEL> 4 "reg_or_int_operand"))
3114 (match_operand:VFULLI_D 3 "register_operand")] VMULH)
3115 (match_operand:VFULLI_D 2 "vector_merge_operand")))]
3116 "TARGET_VECTOR"
3117 {
3118 if (riscv_vector::sew64_scalar_helper (
3119 operands,
3120 /* scalar op */&operands[4],
3121 /* vl */operands[5],
3122 <MODE>mode,
3123 false,
3124 [] (rtx *operands, rtx broadcast_scalar) {
3125 emit_insn (gen_pred_mulh<v_su><mode> (operands[0], operands[1],
3126 operands[2], operands[3], broadcast_scalar, operands[5],
3127 operands[6], operands[7], operands[8]));
3128 },
3129 (riscv_vector::avl_type) INTVAL (operands[8])))
3130 DONE;
3131 })
3133 (define_insn "*pred_mulh<v_su><mode>_scalar"
3134 [(set (match_operand:VFULLI_D 0 "register_operand" "=vd,vd, vr, vr")
3135 (if_then_else:VFULLI_D
3136 (unspec:<VM>
3137 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
3138 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
3139 (match_operand 6 "const_int_operand" " i, i, i, i")
3140 (match_operand 7 "const_int_operand" " i, i, i, i")
3141 (match_operand 8 "const_int_operand" " i, i, i, i")
3142 (reg:SI VL_REGNUM)
3143 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3144 (unspec:VFULLI_D
3145 [(vec_duplicate:VFULLI_D
3146 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
3147 (match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr")] VMULH)
3148 (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
3149 "TARGET_VECTOR"
3150 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
3151 [(set_attr "type" "vimul")
3152 (set_attr "mode" "<MODE>")])
3154 (define_insn "*pred_mulh<v_su><mode>_extended_scalar"
3155 [(set (match_operand:VFULLI_D 0 "register_operand" "=vd,vd, vr, vr")
3156 (if_then_else:VFULLI_D
3157 (unspec:<VM>
3158 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
3159 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
3160 (match_operand 6 "const_int_operand" " i, i, i, i")
3161 (match_operand 7 "const_int_operand" " i, i, i, i")
3162 (match_operand 8 "const_int_operand" " i, i, i, i")
3163 (reg:SI VL_REGNUM)
3164 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3165 (unspec:VFULLI_D
3166 [(vec_duplicate:VFULLI_D
3167 (sign_extend:<VEL>
3168 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
3169 (match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr")] VMULH)
3170 (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
3171 "TARGET_VECTOR && !TARGET_64BIT"
3172 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
3173 [(set_attr "type" "vimul")
3174 (set_attr "mode" "<MODE>")])
3176 ;; Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
3177 (define_insn "@pred_adc<mode>"
3178 [(set (match_operand:VI 0 "register_operand" "=vd,vd,vd,vd")
3179 (if_then_else:VI
3180 (unspec:<VM>
3181 [(match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
3182 (match_operand 6 "const_int_operand" " i, i, i, i")
3183 (match_operand 7 "const_int_operand" " i, i, i, i")
3184 (reg:SI VL_REGNUM)
3185 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3186 (unspec:VI
3187 [(plus:VI
3188 (match_operand:VI 2 "register_operand" "vr,vr,vr,vr")
3189 (match_operand:VI 3 "vector_arith_operand" "vr,vr,vi,vi"))
3190 (match_operand:<VM> 4 "register_operand" "vm,vm,vm,vm")] UNSPEC_VADC)
3191 (match_operand:VI 1 "vector_merge_operand" "vu, 0,vu, 0")))]
3192 "TARGET_VECTOR"
3193 "vadc.v%o3m\t%0,%2,%v3,%4"
3194 [(set_attr "type" "vicalu")
3195 (set_attr "mode" "<MODE>")
3196 (set_attr "merge_op_idx" "1")
3197 (set_attr "vl_op_idx" "5")
3198 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3199 (set (attr "avl_type_idx") (const_int 7))])
3201 (define_insn "@pred_sbc<mode>"
3202 [(set (match_operand:VI 0 "register_operand" "=vd,vd")
3203 (if_then_else:VI
3204 (unspec:<VM>
3205 [(match_operand 5 "vector_length_operand" "rvl,rvl")
3206 (match_operand 6 "const_int_operand" " i, i")
3207 (match_operand 7 "const_int_operand" " i, i")
3208 (reg:SI VL_REGNUM)
3209 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3210 (unspec:VI
3211 [(minus:VI
3212 (match_operand:VI 2 "register_operand" "vr,vr")
3213 (match_operand:VI 3 "register_operand" "vr,vr"))
3214 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3215 (match_operand:VI 1 "vector_merge_operand" "vu, 0")))]
3216 "TARGET_VECTOR"
3217 "vsbc.vvm\t%0,%2,%3,%4"
3218 [(set_attr "type" "vicalu")
3219 (set_attr "mode" "<MODE>")
3220 (set_attr "merge_op_idx" "1")
3221 (set_attr "vl_op_idx" "5")
3222 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3223 (set (attr "avl_type_idx") (const_int 7))])
3225 (define_insn "@pred_adc<mode>_scalar"
3226 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
3227 (if_then_else:VI_QHS
3228 (unspec:<VM>
3229 [(match_operand 5 "vector_length_operand" "rvl,rvl")
3230 (match_operand 6 "const_int_operand" " i, i")
3231 (match_operand 7 "const_int_operand" " i, i")
3232 (reg:SI VL_REGNUM)
3233 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3234 (unspec:VI_QHS
3235 [(plus:VI_QHS
3236 (vec_duplicate:VI_QHS
3237 (match_operand:<VEL> 3 "register_operand" " r, r"))
3238 (match_operand:VI_QHS 2 "register_operand" "vr,vr"))
3239 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3240 (match_operand:VI_QHS 1 "vector_merge_operand" "vu, 0")))]
3241 "TARGET_VECTOR"
3242 "vadc.vxm\t%0,%2,%3,%4"
3243 [(set_attr "type" "vicalu")
3244 (set_attr "mode" "<MODE>")
3245 (set_attr "merge_op_idx" "1")
3246 (set_attr "vl_op_idx" "5")
3247 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3248 (set (attr "avl_type_idx") (const_int 7))])
3250 (define_insn "@pred_sbc<mode>_scalar"
3251 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
3252 (if_then_else:VI_QHS
3253 (unspec:<VM>
3254 [(match_operand 5 "vector_length_operand" "rvl,rvl")
3255 (match_operand 6 "const_int_operand" " i, i")
3256 (match_operand 7 "const_int_operand" " i, i")
3257 (reg:SI VL_REGNUM)
3258 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3259 (unspec:VI_QHS
3260 [(minus:VI_QHS
3261 (match_operand:VI_QHS 2 "register_operand" "vr,vr")
3262 (vec_duplicate:VI_QHS
3263 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ")))
3264 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3265 (match_operand:VI_QHS 1 "vector_merge_operand" "vu, 0")))]
3266 "TARGET_VECTOR"
3267 "vsbc.vxm\t%0,%2,%z3,%4"
3268 [(set_attr "type" "vicalu")
3269 (set_attr "mode" "<MODE>")
3270 (set_attr "merge_op_idx" "1")
3271 (set_attr "vl_op_idx" "5")
3272 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3273 (set (attr "avl_type_idx") (const_int 7))])
3275 (define_expand "@pred_adc<mode>_scalar"
3276 [(set (match_operand:VI_D 0 "register_operand")
3277 (if_then_else:VI_D
3278 (unspec:<VM>
3279 [(match_operand 5 "vector_length_operand")
3280 (match_operand 6 "const_int_operand")
3281 (match_operand 7 "const_int_operand")
3282 (reg:SI VL_REGNUM)
3283 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3284 (unspec:VI_D
3285 [(plus:VI_D
3286 (vec_duplicate:VI_D
3287 (match_operand:<VEL> 3 "reg_or_int_operand"))
3288 (match_operand:VI_D 2 "register_operand"))
3289 (match_operand:<VM> 4 "register_operand")] UNSPEC_VADC)
3290 (match_operand:VI_D 1 "vector_merge_operand")))]
3291 "TARGET_VECTOR"
3292 {
3293 if (riscv_vector::sew64_scalar_helper (
3294 operands,
3295 /* scalar op */&operands[3],
3296 /* vl */operands[5],
3297 <MODE>mode,
3298 riscv_vector::simm5_p (operands[3]),
3299 [] (rtx *operands, rtx broadcast_scalar) {
3300 emit_insn (gen_pred_adc<mode> (operands[0], operands[1],
3301 operands[2], broadcast_scalar, operands[4], operands[5],
3302 operands[6], operands[7]));
3303 },
3304 (riscv_vector::avl_type) INTVAL (operands[7])))
3305 DONE;
3306 })
3308 (define_insn "*pred_adc<mode>_scalar"
3309 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3310 (if_then_else:VI_D
3311 (unspec:<VM>
3312 [(match_operand 5 "vector_length_operand" "rvl,rvl")
3313 (match_operand 6 "const_int_operand" " i, i")
3314 (match_operand 7 "const_int_operand" " i, i")
3315 (reg:SI VL_REGNUM)
3316 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3317 (unspec:VI_D
3318 [(plus:VI_D
3319 (vec_duplicate:VI_D
3320 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ"))
3321 (match_operand:VI_D 2 "register_operand" "vr,vr"))
3322 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3323 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3324 "TARGET_VECTOR"
3325 "vadc.vxm\t%0,%2,%z3,%4"
3326 [(set_attr "type" "vicalu")
3327 (set_attr "mode" "<MODE>")
3328 (set_attr "merge_op_idx" "1")
3329 (set_attr "vl_op_idx" "5")
3330 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3331 (set (attr "avl_type_idx") (const_int 7))])
3333 (define_insn "*pred_adc<mode>_extended_scalar"
3334 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3335 (if_then_else:VI_D
3336 (unspec:<VM>
3337 [(match_operand 5 "vector_length_operand" "rvl,rvl")
3338 (match_operand 6 "const_int_operand" " i, i")
3339 (match_operand 7 "const_int_operand" " i, i")
3340 (reg:SI VL_REGNUM)
3341 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3342 (unspec:VI_D
3343 [(plus:VI_D
3344 (vec_duplicate:VI_D
3345 (sign_extend:<VEL>
3346 (match_operand:<VSUBEL> 3 "reg_or_0_operand" "rJ,rJ")))
3347 (match_operand:VI_D 2 "register_operand" "vr,vr"))
3348 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3349 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3350 "TARGET_VECTOR && !TARGET_64BIT"
3351 "vadc.vxm\t%0,%2,%z3,%4"
3352 [(set_attr "type" "vicalu")
3353 (set_attr "mode" "<MODE>")
3354 (set_attr "merge_op_idx" "1")
3355 (set_attr "vl_op_idx" "5")
3356 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3357 (set (attr "avl_type_idx") (const_int 7))])
3359 (define_expand "@pred_sbc<mode>_scalar"
3360 [(set (match_operand:VI_D 0 "register_operand")
3361 (if_then_else:VI_D
3362 (unspec:<VM>
3363 [(match_operand 5 "vector_length_operand")
3364 (match_operand 6 "const_int_operand")
3365 (match_operand 7 "const_int_operand")
3366 (reg:SI VL_REGNUM)
3367 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3368 (unspec:VI_D
3369 [(minus:VI_D
3370 (match_operand:VI_D 2 "register_operand")
3371 (vec_duplicate:VI_D
3372 (match_operand:<VEL> 3 "reg_or_int_operand")))
3373 (match_operand:<VM> 4 "register_operand")] UNSPEC_VSBC)
3374 (match_operand:VI_D 1 "vector_merge_operand")))]
3375 "TARGET_VECTOR"
3376 {
3377 if (riscv_vector::sew64_scalar_helper (
3378 operands,
3379 /* scalar op */&operands[3],
3380 /* vl */operands[5],
3381 <MODE>mode,
3382 false,
3383 [] (rtx *operands, rtx broadcast_scalar) {
3384 emit_insn (gen_pred_sbc<mode> (operands[0], operands[1],
3385 operands[2], broadcast_scalar, operands[4], operands[5],
3386 operands[6], operands[7]));
3387 },
3388 (riscv_vector::avl_type) INTVAL (operands[7])))
3389 DONE;
3390 })
3392 (define_insn "*pred_sbc<mode>_scalar"
3393 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3394 (if_then_else:VI_D
3395 (unspec:<VM>
3396 [(match_operand 5 "vector_length_operand" "rvl,rvl")
3397 (match_operand 6 "const_int_operand" " i, i")
3398 (match_operand 7 "const_int_operand" " i, i")
3399 (reg:SI VL_REGNUM)
3400 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3401 (unspec:VI_D
3402 [(minus:VI_D
3403 (match_operand:VI_D 2 "register_operand" "vr,vr")
3404 (vec_duplicate:VI_D
3405 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ")))
3406 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3407 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3408 "TARGET_VECTOR"
3409 "vsbc.vxm\t%0,%2,%z3,%4"
3410 [(set_attr "type" "vicalu")
3411 (set_attr "mode" "<MODE>")
3412 (set_attr "merge_op_idx" "1")
3413 (set_attr "vl_op_idx" "5")
3414 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3415 (set (attr "avl_type_idx") (const_int 7))])
3417 (define_insn "*pred_sbc<mode>_extended_scalar"
3418 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3419 (if_then_else:VI_D
3420 (unspec:<VM>
3421 [(match_operand 5 "vector_length_operand" "rvl,rvl")
3422 (match_operand 6 "const_int_operand" " i, i")
3423 (match_operand 7 "const_int_operand" " i, i")
3424 (reg:SI VL_REGNUM)
3425 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3426 (unspec:VI_D
3427 [(minus:VI_D
3428 (match_operand:VI_D 2 "register_operand" "vr,vr")
3429 (vec_duplicate:VI_D
3430 (sign_extend:<VEL>
3431 (match_operand:<VSUBEL> 3 "reg_or_0_operand" "rJ,rJ"))))
3432 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3433 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3434 "TARGET_VECTOR && !TARGET_64BIT"
3435 "vsbc.vxm\t%0,%2,%z3,%4"
3436 [(set_attr "type" "vicalu")
3437 (set_attr "mode" "<MODE>")
3438 (set_attr "merge_op_idx" "1")
3439 (set_attr "vl_op_idx" "5")
3440 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3441 (set (attr "avl_type_idx") (const_int 7))])
3443 (define_insn "@pred_madc<mode>"
3444 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr, &vr")
3445 (unspec:<VM>
3446 [(plus:VI
3447 (match_operand:VI 1 "register_operand" " %0, vr, vr")
3448 (match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi"))
3449 (match_operand:<VM> 3 "register_operand" " vm, vm, vm")
3450 (unspec:<VM>
3451 [(match_operand 4 "vector_length_operand" " rvl, rvl, rvl")
3452 (match_operand 5 "const_int_operand" " i, i, i")
3453 (reg:SI VL_REGNUM)
3454 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3455 "TARGET_VECTOR"
3456 "vmadc.v%o2m\t%0,%1,%v2,%3"
3457 [(set_attr "type" "vicalu")
3458 (set_attr "mode" "<MODE>")
3459 (set_attr "vl_op_idx" "4")
3460 (set (attr "avl_type_idx") (const_int 5))
3461 (set_attr "spec_restriction" "thv,none,none")])
3463 (define_insn "@pred_msbc<mode>"
3464 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr")
3465 (unspec:<VM>
3466 [(minus:VI
3467 (match_operand:VI 1 "register_operand" " 0, vr, vr")
3468 (match_operand:VI 2 "register_operand" " vr, 0, vr"))
3469 (match_operand:<VM> 3 "register_operand" " vm, vm, vm")
3470 (unspec:<VM>
3471 [(match_operand 4 "vector_length_operand" "rvl,rvl, rvl")
3472 (match_operand 5 "const_int_operand" " i, i, i")
3473 (reg:SI VL_REGNUM)
3474 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3475 "TARGET_VECTOR"
3476 "vmsbc.vvm\t%0,%1,%2,%3"
3477 [(set_attr "type" "vicalu")
3478 (set_attr "mode" "<MODE>")
3479 (set_attr "vl_op_idx" "4")
3480 (set (attr "avl_type_idx") (const_int 5))
3481 (set_attr "spec_restriction" "thv,thv,none")])
3483 (define_insn "@pred_madc<mode>_scalar"
3484 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3485 (unspec:<VM>
3486 [(plus:VI_QHS
3487 (vec_duplicate:VI_QHS
3488 (match_operand:<VEL> 2 "register_operand" " r, r"))
3489 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3490 (match_operand:<VM> 3 "register_operand" " vm, vm")
3491 (unspec:<VM>
3492 [(match_operand 4 "vector_length_operand" "rvl, rvl")
3493 (match_operand 5 "const_int_operand" " i, i")
3494 (reg:SI VL_REGNUM)
3495 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3496 "TARGET_VECTOR"
3497 "vmadc.vxm\t%0,%1,%2,%3"
3498 [(set_attr "type" "vicalu")
3499 (set_attr "mode" "<MODE>")
3500 (set_attr "vl_op_idx" "4")
3501 (set (attr "avl_type_idx") (const_int 5))
3502 (set_attr "spec_restriction" "thv,none")])
3504 (define_insn "@pred_msbc<mode>_scalar"
3505 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3506 (unspec:<VM>
3507 [(minus:VI_QHS
3508 (vec_duplicate:VI_QHS
3509 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3510 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3511 (match_operand:<VM> 3 "register_operand" " vm, vm")
3512 (unspec:<VM>
3513 [(match_operand 4 "vector_length_operand" "rvl, rvl")
3514 (match_operand 5 "const_int_operand" " i, i")
3515 (reg:SI VL_REGNUM)
3516 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3517 "TARGET_VECTOR"
3518 "vmsbc.vxm\t%0,%1,%z2,%3"
3519 [(set_attr "type" "vicalu")
3520 (set_attr "mode" "<MODE>")
3521 (set_attr "vl_op_idx" "4")
3522 (set (attr "avl_type_idx") (const_int 5))
3523 (set_attr "spec_restriction" "thv,none")])
3525 (define_expand "@pred_madc<mode>_scalar"
3526 [(set (match_operand:<VM> 0 "register_operand")
3527 (unspec:<VM>
3528 [(plus:VI_D
3529 (vec_duplicate:VI_D
3530 (match_operand:<VEL> 2 "reg_or_int_operand"))
3531 (match_operand:VI_D 1 "register_operand"))
3532 (match_operand:<VM> 3 "register_operand")
3533 (unspec:<VM>
3534 [(match_operand 4 "vector_length_operand")
3535 (match_operand 5 "const_int_operand")
3536 (reg:SI VL_REGNUM)
3537 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3538 "TARGET_VECTOR"
3539 {
3540 if (riscv_vector::sew64_scalar_helper (
3541 operands,
3542 /* scalar op */&operands[2],
3543 /* vl */operands[4],
3544 <MODE>mode,
3545 riscv_vector::simm5_p (operands[2]),
3546 [] (rtx *operands, rtx broadcast_scalar) {
3547 emit_insn (gen_pred_madc<mode> (operands[0], operands[1],
3548 broadcast_scalar, operands[3], operands[4], operands[5]));
3549 },
3550 (riscv_vector::avl_type) INTVAL (operands[5])))
3551 DONE;
3552 })
3554 (define_insn "*pred_madc<mode>_scalar"
3555 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3556 (unspec:<VM>
3557 [(plus:VI_D
3558 (vec_duplicate:VI_D
3559 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3560 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3561 (match_operand:<VM> 3 "register_operand" " vm, vm")
3562 (unspec:<VM>
3563 [(match_operand 4 "vector_length_operand" "rvl, rvl")
3564 (match_operand 5 "const_int_operand" " i, i")
3565 (reg:SI VL_REGNUM)
3566 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3567 "TARGET_VECTOR"
3568 "vmadc.vxm\t%0,%1,%z2,%3"
3569 [(set_attr "type" "vicalu")
3570 (set_attr "mode" "<MODE>")
3571 (set_attr "vl_op_idx" "4")
3572 (set (attr "avl_type_idx") (const_int 5))
3573 (set_attr "spec_restriction" "thv,none")])
3575 (define_insn "*pred_madc<mode>_extended_scalar"
3576 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3577 (unspec:<VM>
3578 [(plus:VI_D
3579 (vec_duplicate:VI_D
3580 (sign_extend:<VEL>
3581 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3582 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3583 (match_operand:<VM> 3 "register_operand" " vm, vm")
3584 (unspec:<VM>
3585 [(match_operand 4 "vector_length_operand" "rvl, rvl")
3586 (match_operand 5 "const_int_operand" " i, i")
3587 (reg:SI VL_REGNUM)
3588 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3589 "TARGET_VECTOR && !TARGET_64BIT"
3590 "vmadc.vxm\t%0,%1,%z2,%3"
3591 [(set_attr "type" "vicalu")
3592 (set_attr "mode" "<MODE>")
3593 (set_attr "vl_op_idx" "4")
3594 (set (attr "avl_type_idx") (const_int 5))
3595 (set_attr "spec_restriction" "thv,none")])
3597 (define_expand "@pred_msbc<mode>_scalar"
3598 [(set (match_operand:<VM> 0 "register_operand")
3599 (unspec:<VM>
3600 [(minus:VI_D
3601 (vec_duplicate:VI_D
3602 (match_operand:<VEL> 2 "reg_or_int_operand"))
3603 (match_operand:VI_D 1 "register_operand"))
3604 (match_operand:<VM> 3 "register_operand")
3605 (unspec:<VM>
3606 [(match_operand 4 "vector_length_operand")
3607 (match_operand 5 "const_int_operand")
3608 (reg:SI VL_REGNUM)
3609 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3610 "TARGET_VECTOR"
3611 {
3612 if (riscv_vector::sew64_scalar_helper (
3613 operands,
3614 /* scalar op */&operands[2],
3615 /* vl */operands[4],
3616 <MODE>mode,
3617 false,
3618 [] (rtx *operands, rtx broadcast_scalar) {
3619 emit_insn (gen_pred_msbc<mode> (operands[0], operands[1],
3620 broadcast_scalar, operands[3], operands[4], operands[5]));
3621 },
3622 (riscv_vector::avl_type) INTVAL (operands[5])))
3623 DONE;
3624 })
3626 (define_insn "*pred_msbc<mode>_scalar"
3627 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3628 (unspec:<VM>
3629 [(minus:VI_D
3630 (vec_duplicate:VI_D
3631 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3632 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3633 (match_operand:<VM> 3 "register_operand" " vm, vm")
3634 (unspec:<VM>
3635 [(match_operand 4 "vector_length_operand" "rvl, rvl")
3636 (match_operand 5 "const_int_operand" " i, i")
3637 (reg:SI VL_REGNUM)
3638 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3639 "TARGET_VECTOR"
3640 "vmsbc.vxm\t%0,%1,%z2,%3"
3641 [(set_attr "type" "vicalu")
3642 (set_attr "mode" "<MODE>")
3643 (set_attr "vl_op_idx" "4")
3644 (set (attr "avl_type_idx") (const_int 5))
3645 (set_attr "spec_restriction" "thv,none")])
3647 (define_insn "*pred_msbc<mode>_extended_scalar"
3648 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3649 (unspec:<VM>
3650 [(minus:VI_D
3651 (vec_duplicate:VI_D
3652 (sign_extend:<VEL>
3653 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3654 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3655 (match_operand:<VM> 3 "register_operand" " vm, vm")
3656 (unspec:<VM>
3657 [(match_operand 4 "vector_length_operand" "rvl, rvl")
3658 (match_operand 5 "const_int_operand" " i, i")
3659 (reg:SI VL_REGNUM)
3660 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3661 "TARGET_VECTOR && !TARGET_64BIT"
3662 "vmsbc.vxm\t%0,%1,%z2,%3"
3663 [(set_attr "type" "vicalu")
3664 (set_attr "mode" "<MODE>")
3665 (set_attr "vl_op_idx" "4")
3666 (set (attr "avl_type_idx") (const_int 5))
3667 (set_attr "spec_restriction" "thv,none")])
3669 (define_insn "@pred_madc<mode>_overflow"
3670 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr, &vr")
3671 (unspec:<VM>
3672 [(plus:VI
3673 (match_operand:VI 1 "register_operand" " %0, vr, vr")
3674 (match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi"))
3675 (unspec:<VM>
3676 [(match_operand 3 "vector_length_operand" " rvl, rvl, rvl")
3677 (match_operand 4 "const_int_operand" " i, i, i")
3678 (reg:SI VL_REGNUM)
3679 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3680 "TARGET_VECTOR"
3681 "vmadc.v%o2\t%0,%1,%v2"
3682 [(set_attr "type" "vicalu")
3683 (set_attr "mode" "<MODE>")
3684 (set_attr "vl_op_idx" "3")
3685 (set (attr "avl_type_idx") (const_int 4))
3686 (set_attr "spec_restriction" "thv,none,none")])
3688 (define_insn "@pred_msbc<mode>_overflow"
3689 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
3690 (unspec:<VM>
3691 [(minus:VI
3692 (match_operand:VI 1 "register_operand" " 0, vr, vr, vr")
3693 (match_operand:VI 2 "register_operand" " vr, 0, vr, vi"))
3694 (unspec:<VM>
3695 [(match_operand 3 "vector_length_operand" " rvl, rvl, rvl, rvl")
3696 (match_operand 4 "const_int_operand" " i, i, i, i")
3697 (reg:SI VL_REGNUM)
3698 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3699 "TARGET_VECTOR"
3700 "vmsbc.vv\t%0,%1,%2"
3701 [(set_attr "type" "vicalu")
3702 (set_attr "mode" "<MODE>")
3703 (set_attr "vl_op_idx" "3")
3704 (set (attr "avl_type_idx") (const_int 4))
3705 (set_attr "spec_restriction" "thv,thv,none,none")])
3707 (define_insn "@pred_madc<mode>_overflow_scalar"
3708 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3709 (unspec:<VM>
3710 [(plus:VI_QHS
3711 (vec_duplicate:VI_QHS
3712 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3713 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3714 (unspec:<VM>
3715 [(match_operand 3 "vector_length_operand" "rvl, rvl")
3716 (match_operand 4 "const_int_operand" " i, i")
3717 (reg:SI VL_REGNUM)
3718 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3719 "TARGET_VECTOR"
3720 "vmadc.vx\t%0,%1,%z2"
3721 [(set_attr "type" "vicalu")
3722 (set_attr "mode" "<MODE>")
3723 (set_attr "vl_op_idx" "3")
3724 (set (attr "avl_type_idx") (const_int 4))
3725 (set_attr "spec_restriction" "thv,none")])
3727 (define_insn "@pred_msbc<mode>_overflow_scalar"
3728 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3729 (unspec:<VM>
3730 [(minus:VI_QHS
3731 (vec_duplicate:VI_QHS
3732 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3733 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3734 (unspec:<VM>
3735 [(match_operand 3 "vector_length_operand" "rvl, rvl")
3736 (match_operand 4 "const_int_operand" " i, i")
3737 (reg:SI VL_REGNUM)
3738 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3739 "TARGET_VECTOR"
3740 "vmsbc.vx\t%0,%1,%z2"
3741 [(set_attr "type" "vicalu")
3742 (set_attr "mode" "<MODE>")
3743 (set_attr "vl_op_idx" "3")
3744 (set (attr "avl_type_idx") (const_int 4))
3745 (set_attr "spec_restriction" "thv,none")])
3747 (define_expand "@pred_madc<mode>_overflow_scalar"
3748 [(set (match_operand:<VM> 0 "register_operand")
3749 (unspec:<VM>
3750 [(plus:VI_D
3751 (vec_duplicate:VI_D
3752 (match_operand:<VEL> 2 "reg_or_int_operand"))
3753 (match_operand:VI_D 1 "register_operand"))
3754 (unspec:<VM>
3755 [(match_operand 3 "vector_length_operand")
3756 (match_operand 4 "const_int_operand")
3757 (reg:SI VL_REGNUM)
3758 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3759 "TARGET_VECTOR"
3760 {
3761 if (riscv_vector::sew64_scalar_helper (
3762 operands,
3763 /* scalar op */&operands[2],
3764 /* vl */operands[3],
3765 <MODE>mode,
3766 riscv_vector::simm5_p (operands[2]),
3767 [] (rtx *operands, rtx broadcast_scalar) {
3768 emit_insn (gen_pred_madc<mode>_overflow (operands[0], operands[1],
3769 broadcast_scalar, operands[3], operands[4]));
3770 },
3771 (riscv_vector::avl_type) INTVAL (operands[4])))
3772 DONE;
3773 })
3775 (define_insn "*pred_madc<mode>_overflow_scalar"
3776 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3777 (unspec:<VM>
3778 [(plus:VI_D
3779 (vec_duplicate:VI_D
3780 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3781 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3782 (unspec:<VM>
3783 [(match_operand 3 "vector_length_operand" "rvl, rvl")
3784 (match_operand 4 "const_int_operand" " i, i")
3785 (reg:SI VL_REGNUM)
3786 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3787 "TARGET_VECTOR"
3788 "vmadc.vx\t%0,%1,%z2"
3789 [(set_attr "type" "vicalu")
3790 (set_attr "mode" "<MODE>")
3791 (set_attr "vl_op_idx" "3")
3792 (set (attr "avl_type_idx") (const_int 4))
3793 (set_attr "spec_restriction" "thv,none")])
3795 (define_insn "*pred_madc<mode>_overflow_extended_scalar"
3796 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3797 (unspec:<VM>
3798 [(plus:VI_D
3799 (vec_duplicate:VI_D
3800 (sign_extend:<VEL>
3801 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3802 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3803 (unspec:<VM>
3804 [(match_operand 3 "vector_length_operand" "rvl, rvl")
3805 (match_operand 4 "const_int_operand" " i, i")
3806 (reg:SI VL_REGNUM)
3807 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3808 "TARGET_VECTOR && !TARGET_64BIT"
3809 "vmadc.vx\t%0,%1,%z2"
3810 [(set_attr "type" "vicalu")
3811 (set_attr "mode" "<MODE>")
3812 (set_attr "vl_op_idx" "3")
3813 (set (attr "avl_type_idx") (const_int 4))
3814 (set_attr "spec_restriction" "thv,none")])
3816 (define_expand "@pred_msbc<mode>_overflow_scalar"
3817 [(set (match_operand:<VM> 0 "register_operand")
3818 (unspec:<VM>
3819 [(minus:VI_D
3820 (vec_duplicate:VI_D
3821 (match_operand:<VEL> 2 "reg_or_int_operand"))
3822 (match_operand:VI_D 1 "register_operand"))
3823 (unspec:<VM>
3824 [(match_operand 3 "vector_length_operand")
3825 (match_operand 4 "const_int_operand")
3826 (reg:SI VL_REGNUM)
3827 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3828 "TARGET_VECTOR"
3829 {
3830 if (riscv_vector::sew64_scalar_helper (
3831 operands,
3832 /* scalar op */&operands[2],
3833 /* vl */operands[3],
3834 <MODE>mode,
3835 false,
3836 [] (rtx *operands, rtx broadcast_scalar) {
3837 emit_insn (gen_pred_msbc<mode>_overflow (operands[0], operands[1],
3838 broadcast_scalar, operands[3], operands[4]));
3839 },
3840 (riscv_vector::avl_type) INTVAL (operands[4])))
3841 DONE;
3842 })
3844 (define_insn "*pred_msbc<mode>_overflow_scalar"
3845 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3846 (unspec:<VM>
3847 [(minus:VI_D
3848 (vec_duplicate:VI_D
3849 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3850 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3851 (unspec:<VM>
3852 [(match_operand 3 "vector_length_operand" "rvl, rvl")
3853 (match_operand 4 "const_int_operand" " i, i")
3854 (reg:SI VL_REGNUM)
3855 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3856 "TARGET_VECTOR"
3857 "vmsbc.vx\t%0,%1,%z2"
3858 [(set_attr "type" "vicalu")
3859 (set_attr "mode" "<MODE>")
3860 (set_attr "vl_op_idx" "3")
3861 (set (attr "avl_type_idx") (const_int 4))
3862 (set_attr "spec_restriction" "thv,none")])
3864 (define_insn "*pred_msbc<mode>_overflow_extended_scalar"
3865 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3866 (unspec:<VM>
3867 [(minus:VI_D
3868 (vec_duplicate:VI_D
3869 (sign_extend:<VEL>
3870 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3871 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3872 (unspec:<VM>
3873 [(match_operand 3 "vector_length_operand" "rvl, rvl")
3874 (match_operand 4 "const_int_operand" " i, i")
3875 (reg:SI VL_REGNUM)
3876 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3877 "TARGET_VECTOR && !TARGET_64BIT"
3878 "vmsbc.vx\t%0,%1,%z2"
3879 [(set_attr "type" "vicalu")
3880 (set_attr "mode" "<MODE>")
3881 (set_attr "vl_op_idx" "3")
3882 (set (attr "avl_type_idx") (const_int 4))
3883 (set_attr "spec_restriction" "thv,none")])
3885 ;; -------------------------------------------------------------------------------
3886 ;; ---- Predicated integer unary operations
3887 ;; -------------------------------------------------------------------------------
3888 ;; Includes:
3889 ;; - vneg.v/vnot.v
3890 ;; -------------------------------------------------------------------------------
3892 (define_insn "@pred_<optab><mode>"
3893 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr")
3894 (if_then_else:V_VLSI
3895 (unspec:<VM>
3896 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
3897 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
3898 (match_operand 5 "const_int_operand" " i, i, i, i")
3899 (match_operand 6 "const_int_operand" " i, i, i, i")
3900 (match_operand 7 "const_int_operand" " i, i, i, i")
3901 (reg:SI VL_REGNUM)
3902 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3903 (any_int_unop:V_VLSI
3904 (match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr"))
3905 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0")))]
3906 "TARGET_VECTOR"
3907 "v<insn>.v\t%0,%3%p1"
3908 [(set_attr "type" "vialu")
3909 (set_attr "mode" "<MODE>")
3910 (set_attr "vl_op_idx" "4")
3911 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
3912 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
3913 (set (attr "avl_type_idx") (const_int 7))])
3915 ;; -------------------------------------------------------------------------------
3916 ;; ---- Predicated integer widening binary operations
3917 ;; -------------------------------------------------------------------------------
3918 ;; Includes:
3919 ;; - 11.2 Vector Widening Integer Add/Subtract
3920 ;; - 11.3 Vector Integer Extension
3921 ;; - 11.12 Vector Widening Integer Multiply Instructions
3922 ;; -------------------------------------------------------------------------------
3924 ;; Vector Double-Widening Sign-extend and Zero-extend.
3925 (define_insn "@pred_<optab><mode>_vf2"
3926 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3927 (if_then_else:VWEXTI
3928 (unspec:<VM>
3929 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3930 (match_operand 4 "vector_length_operand" " rvl, rvl")
3931 (match_operand 5 "const_int_operand" " i, i")
3932 (match_operand 6 "const_int_operand" " i, i")
3933 (match_operand 7 "const_int_operand" " i, i")
3934 (reg:SI VL_REGNUM)
3935 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3936 (any_extend:VWEXTI
3937 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3938 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3939 "TARGET_VECTOR"
3940 "v<sz>ext.vf2\t%0,%3%p1"
3941 [(set_attr "type" "vext")
3942 (set_attr "mode" "<MODE>")])
3944 ;; Vector Quad-Widening Sign-extend and Zero-extend.
3945 (define_insn "@pred_<optab><mode>_vf4"
3946 [(set (match_operand:VQEXTI 0 "register_operand" "=&vr,&vr")
3947 (if_then_else:VQEXTI
3948 (unspec:<VM>
3949 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3950 (match_operand 4 "vector_length_operand" " rvl, rvl")
3951 (match_operand 5 "const_int_operand" " i, i")
3952 (match_operand 6 "const_int_operand" " i, i")
3953 (match_operand 7 "const_int_operand" " i, i")
3954 (reg:SI VL_REGNUM)
3955 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3956 (any_extend:VQEXTI
3957 (match_operand:<V_QUAD_TRUNC> 3 "register_operand" " vr, vr"))
3958 (match_operand:VQEXTI 2 "vector_merge_operand" " vu, 0")))]
3959 "TARGET_VECTOR"
3960 "v<sz>ext.vf4\t%0,%3%p1"
3961 [(set_attr "type" "vext")
3962 (set_attr "mode" "<MODE>")])
3964 ;; Vector Oct-Widening Sign-extend and Zero-extend.
3965 (define_insn "@pred_<optab><mode>_vf8"
3966 [(set (match_operand:VOEXTI 0 "register_operand" "=&vr,&vr")
3967 (if_then_else:VOEXTI
3968 (unspec:<VM>
3969 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3970 (match_operand 4 "vector_length_operand" " rvl, rvl")
3971 (match_operand 5 "const_int_operand" " i, i")
3972 (match_operand 6 "const_int_operand" " i, i")
3973 (match_operand 7 "const_int_operand" " i, i")
3974 (reg:SI VL_REGNUM)
3975 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3976 (any_extend:VOEXTI
3977 (match_operand:<V_OCT_TRUNC> 3 "register_operand" " vr, vr"))
3978 (match_operand:VOEXTI 2 "vector_merge_operand" " vu, 0")))]
3979 "TARGET_VECTOR"
3980 "v<sz>ext.vf8\t%0,%3%p1"
3981 [(set_attr "type" "vext")
3982 (set_attr "mode" "<MODE>")])
3984 ;; Vector Widening Add/Subtract/Multiply.
3985 (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>"
3986 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3987 (if_then_else:VWEXTI
3988 (unspec:<VM>
3989 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3990 (match_operand 5 "vector_length_operand" " rvl, rvl")
3991 (match_operand 6 "const_int_operand" " i, i")
3992 (match_operand 7 "const_int_operand" " i, i")
3993 (match_operand 8 "const_int_operand" " i, i")
3994 (reg:SI VL_REGNUM)
3995 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3996 (any_widen_binop:VWEXTI
3997 (any_extend:VWEXTI
3998 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3999 (any_extend:VWEXTI
4000 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
4001 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
4002 "TARGET_VECTOR"
4003 "vw<any_widen_binop:insn><any_extend:u>.vv\t%0,%3,%4%p1"
4004 [(set_attr "type" "vi<widen_binop_insn_type>")
4005 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4007 (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>_scalar"
4008 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
4009 (if_then_else:VWEXTI
4010 (unspec:<VM>
4011 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4012 (match_operand 5 "vector_length_operand" " rvl, rvl")
4013 (match_operand 6 "const_int_operand" " i, i")
4014 (match_operand 7 "const_int_operand" " i, i")
4015 (match_operand 8 "const_int_operand" " i, i")
4016 (reg:SI VL_REGNUM)
4017 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4018 (any_widen_binop:VWEXTI
4019 (any_extend:VWEXTI
4020 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
4021 (any_extend:VWEXTI
4022 (vec_duplicate:<V_DOUBLE_TRUNC>
4023 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))))
4024 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
4025 "TARGET_VECTOR"
4026 "vw<any_widen_binop:insn><any_extend:u>.vx\t%0,%3,%z4%p1"
4027 [(set_attr "type" "vi<widen_binop_insn_type>")
4028 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4030 (define_insn "@pred_single_widen_sub<any_extend:su><mode>"
4031 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
4032 (if_then_else:VWEXTI
4033 (unspec:<VM>
4034 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4035 (match_operand 5 "vector_length_operand" " rvl, rvl")
4036 (match_operand 6 "const_int_operand" " i, i")
4037 (match_operand 7 "const_int_operand" " i, i")
4038 (match_operand 8 "const_int_operand" " i, i")
4039 (reg:SI VL_REGNUM)
4040 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4041 (minus:VWEXTI
4042 (match_operand:VWEXTI 3 "register_operand" " vr, vr")
4043 (any_extend:VWEXTI
4044 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
4045 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
4046 "TARGET_VECTOR"
4047 "vwsub<any_extend:u>.wv\t%0,%3,%4%p1"
4048 [(set_attr "type" "viwalu")
4049 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4051 (define_insn "@pred_single_widen_add<any_extend:su><mode>"
4052 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
4053 (if_then_else:VWEXTI
4054 (unspec:<VM>
4055 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4056 (match_operand 5 "vector_length_operand" " rvl, rvl")
4057 (match_operand 6 "const_int_operand" " i, i")
4058 (match_operand 7 "const_int_operand" " i, i")
4059 (match_operand 8 "const_int_operand" " i, i")
4060 (reg:SI VL_REGNUM)
4061 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4062 (plus:VWEXTI
4063 (any_extend:VWEXTI
4064 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr"))
4065 (match_operand:VWEXTI 3 "register_operand" " vr, vr"))
4066 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
4067 "TARGET_VECTOR"
4068 "vwadd<any_extend:u>.wv\t%0,%3,%4%p1"
4069 [(set_attr "type" "viwalu")
4070 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4072 (define_insn "@pred_single_widen_<plus_minus:optab><any_extend:su><mode>_scalar"
4073 [(set (match_operand:VWEXTI 0 "register_operand" "=vd,vd, vr, vr")
4074 (if_then_else:VWEXTI
4075 (unspec:<VM>
4076 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
4077 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
4078 (match_operand 6 "const_int_operand" " i, i, i, i")
4079 (match_operand 7 "const_int_operand" " i, i, i, i")
4080 (match_operand 8 "const_int_operand" " i, i, i, i")
4081 (reg:SI VL_REGNUM)
4082 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4083 (plus_minus:VWEXTI
4084 (match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr")
4085 (any_extend:VWEXTI
4086 (vec_duplicate:<V_DOUBLE_TRUNC>
4087 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ,rJ, rJ, rJ"))))
4088 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4089 "TARGET_VECTOR"
4090 "vw<plus_minus:insn><any_extend:u>.wx\t%0,%3,%z4%p1"
4091 [(set_attr "type" "vi<widen_binop_insn_type>")
4092 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4094 (define_insn "@pred_single_widen_add<any_extend:su><mode>_extended_scalar"
4095 [(set (match_operand:VWEXTI 0 "register_operand" "=vd,vd, vr, vr")
4096 (if_then_else:VWEXTI
4097 (unspec:<VM>
4098 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
4099 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
4100 (match_operand 6 "const_int_operand" " i, i, i, i")
4101 (match_operand 7 "const_int_operand" " i, i, i, i")
4102 (match_operand 8 "const_int_operand" " i, i, i, i")
4103 (reg:SI VL_REGNUM)
4104 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4105 (plus:VWEXTI
4106 (vec_duplicate:VWEXTI
4107 (any_extend:<VEL>
4108 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ,rJ, rJ, rJ")))
4109 (match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr"))
4110 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4111 "TARGET_VECTOR"
4112 "vwadd<any_extend:u>.wx\t%0,%3,%z4%p1"
4113 [(set_attr "type" "viwalu")
4114 (set_attr "mode_idx" "3")
4115 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4117 (define_insn "@pred_single_widen_sub<any_extend:su><mode>_extended_scalar"
4118 [(set (match_operand:VWEXTI 0 "register_operand" "=vd,vd, vr, vr")
4119 (if_then_else:VWEXTI
4120 (unspec:<VM>
4121 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
4122 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
4123 (match_operand 6 "const_int_operand" " i, i, i, i")
4124 (match_operand 7 "const_int_operand" " i, i, i, i")
4125 (match_operand 8 "const_int_operand" " i, i, i, i")
4126 (reg:SI VL_REGNUM)
4127 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4128 (minus:VWEXTI
4129 (match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr")
4130 (vec_duplicate:VWEXTI
4131 (any_extend:<VEL>
4132 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ,rJ, rJ, rJ"))))
4133 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4134 "TARGET_VECTOR"
4135 "vwsub<any_extend:u>.wx\t%0,%3,%z4%p1"
4136 [(set_attr "type" "viwalu")
4137 (set_attr "mode_idx" "3")
4138 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4140 (define_insn "@pred_widen_mulsu<mode>"
4141 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
4142 (if_then_else:VWEXTI
4143 (unspec:<VM>
4144 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4145 (match_operand 5 "vector_length_operand" " rvl, rvl")
4146 (match_operand 6 "const_int_operand" " i, i")
4147 (match_operand 7 "const_int_operand" " i, i")
4148 (match_operand 8 "const_int_operand" " i, i")
4149 (reg:SI VL_REGNUM)
4150 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4151 (mult:VWEXTI
4152 (sign_extend:VWEXTI
4153 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
4154 (zero_extend:VWEXTI
4155 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
4156 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
4157 "TARGET_VECTOR"
4158 "vwmulsu.vv\t%0,%3,%4%p1"
4159 [(set_attr "type" "viwmul")
4160 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4162 (define_insn "@pred_widen_mulsu<mode>_scalar"
4163 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
4164 (if_then_else:VWEXTI
4165 (unspec:<VM>
4166 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4167 (match_operand 5 "vector_length_operand" " rvl, rvl")
4168 (match_operand 6 "const_int_operand" " i, i")
4169 (match_operand 7 "const_int_operand" " i, i")
4170 (match_operand 8 "const_int_operand" " i, i")
4171 (reg:SI VL_REGNUM)
4172 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4173 (mult:VWEXTI
4174 (sign_extend:VWEXTI
4175 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
4176 (zero_extend:VWEXTI
4177 (vec_duplicate:<V_DOUBLE_TRUNC>
4178 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))))
4179 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
4180 "TARGET_VECTOR"
4181 "vwmulsu.vx\t%0,%3,%z4%p1"
4182 [(set_attr "type" "viwmul")
4183 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4185 ;; vwcvt<u>.x.x.v
4186 (define_insn "@pred_<optab><mode>"
4187 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
4188 (if_then_else:VWEXTI
4189 (unspec:<VM>
4190 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4191 (match_operand 4 "vector_length_operand" " rvl, rvl")
4192 (match_operand 5 "const_int_operand" " i, i")
4193 (match_operand 6 "const_int_operand" " i, i")
4194 (match_operand 7 "const_int_operand" " i, i")
4195 (reg:SI VL_REGNUM)
4196 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4197 (plus:VWEXTI
4198 (any_extend:VWEXTI
4199 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
4200 (vec_duplicate:VWEXTI
4201 (reg:<VEL> X0_REGNUM)))
4202 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
4203 "TARGET_VECTOR"
4204 "vwcvt<u>.x.x.v\t%0,%3%p1"
4205 [(set_attr "type" "viwalu")
4206 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4207 (set_attr "vl_op_idx" "4")
4208 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
4209 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4210 (set (attr "avl_type_idx") (const_int 7))])
4212 ;; -------------------------------------------------------------------------------
4213 ;; ---- Predicated integer Narrowing operations
4214 ;; -------------------------------------------------------------------------------
4215 ;; Includes:
4216 ;; - 11.7 Vector Narrowing Integer Right Shift Instructions
4217 ;; -------------------------------------------------------------------------------
4219 ;; The destination EEW is smaller than the source EEW and the overlap is in the
4220 ;; lowest-numbered part of the source register group
4221 ;; e.g, when LMUL = 1, vnsrl.wi v0,v0,3 is legal but a destination of v1 is not.
4222 (define_insn "@pred_narrow_<optab><mode>"
4223 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd,vd, vr, vr,vd, vr, &vr, &vr, vd, vr, &vr, &vr")
4224 (if_then_else:<V_DOUBLE_TRUNC>
4225 (unspec:<VM>
4226 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1, vm,Wc1,vmWc1,vmWc1")
4227 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl,rvl,rvl, rvl, rvl,rvl,rvl, rvl, rvl")
4228 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4229 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4230 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4231 (reg:SI VL_REGNUM)
4232 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4233 (truncate:<V_DOUBLE_TRUNC>
4234 (any_shiftrt:VWEXTI
4235 (match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr, 0, 0, vr, vr, 0, 0, vr, vr")
4236 (match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand" " 0, 0, 0, 0,vr, vr, vr, vr, vk, vk, vk, vk")))
4237 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " 0,vu, 0, vu,vu, vu, vu, 0, vu, vu, vu, 0")))]
4238 "TARGET_VECTOR"
4239 "vn<insn>.w%o4\t%0,%3,%v4%p1"
4240 [(set_attr "type" "vnshift")
4241 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4242 (set_attr "spec_restriction" "none,none,thv,thv,none,thv,none,none,none,thv,none,none")])
4244 (define_insn "@pred_narrow_<optab><mode>_scalar"
4245 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
4246 (if_then_else:<V_DOUBLE_TRUNC>
4247 (unspec:<VM>
4248 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
4249 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl, rvl, rvl")
4250 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
4251 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
4252 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
4253 (reg:SI VL_REGNUM)
4254 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4255 (truncate:<V_DOUBLE_TRUNC>
4256 (any_shiftrt:VWEXTI
4257 (match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr")
4258 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK, rK, rK")))
4259 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
4260 "TARGET_VECTOR"
4261 "vn<insn>.w%o4\t%0,%3,%4%p1"
4262 [(set_attr "type" "vnshift")
4263 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4264 (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
4266 ;; vncvt.x.x.w
4267 (define_insn "@pred_trunc<mode>"
4268 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
4269 (if_then_else:<V_DOUBLE_TRUNC>
4270 (unspec:<VM>
4271 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
4272 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl, rvl, rvl")
4273 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
4274 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
4275 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
4276 (reg:SI VL_REGNUM)
4277 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4278 (truncate:<V_DOUBLE_TRUNC>
4279 (match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
4280 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
4281 "TARGET_VECTOR"
4282 "vncvt.x.x.w\t%0,%3%p1"
4283 [(set_attr "type" "vnshift")
4284 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4285 (set_attr "vl_op_idx" "4")
4286 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
4287 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4288 (set (attr "avl_type_idx") (const_int 7))
4289 (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
4291 ;; -------------------------------------------------------------------------------
4292 ;; ---- Predicated fixed-point operations
4293 ;; -------------------------------------------------------------------------------
4294 ;; Includes:
4295 ;; - 12.1 Vector Single-Width Saturating Add and Subtract
4296 ;; - 12.2 Vector Single-Width Averaging Add and Subtract
4297 ;; - 12.3 Vector Single-Width Fractional Multiply with Rounding and Saturation
4298 ;; - 12.4 Vector Single-Width Scaling Shift Instructions
4299 ;; - 12.5 Vector Narrowing Fixed-Point Clip Instructions
4300 ;; -------------------------------------------------------------------------------
4302 ;; Saturating Add and Subtract
4303 (define_insn "@pred_<optab><mode>"
4304 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr, vd, vd, vr, vr")
4305 (if_then_else:V_VLSI
4306 (unspec:<VM>
4307 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
4308 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl,rvl,rvl,rvl,rvl")
4309 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
4310 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
4311 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
4312 (reg:SI VL_REGNUM)
4313 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4314 (any_sat_int_binop:V_VLSI
4315 (match_operand:V_VLSI 3 "<binop_rhs1_predicate>" " vr, vr, vr, vr, vr, vr, vr, vr")
4316 (match_operand:V_VLSI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
4317 (match_operand:V_VLSI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
4318 "TARGET_VECTOR"
4319 "@
4320 v<insn>.vv\t%0,%3,%4%p1
4321 v<insn>.vv\t%0,%3,%4%p1
4322 v<insn>.vv\t%0,%3,%4%p1
4323 v<insn>.vv\t%0,%3,%4%p1
4324 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4325 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4326 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4327 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1"
4328 [(set_attr "type" "<int_binop_insn_type>")
4329 (set_attr "mode" "<MODE>")])
4331 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
4332 (define_insn "@pred_<optab><mode>_scalar"
4333 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vd, vr, vr")
4334 (if_then_else:VI_QHS
4335 (unspec:<VM>
4336 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4337 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
4338 (match_operand 6 "const_int_operand" " i, i, i, i")
4339 (match_operand 7 "const_int_operand" " i, i, i, i")
4340 (match_operand 8 "const_int_operand" " i, i, i, i")
4341 (reg:SI VL_REGNUM)
4342 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4343 (sat_int_plus_binop:VI_QHS
4344 (vec_duplicate:VI_QHS
4345 (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))
4346 (match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr"))
4347 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4348 "TARGET_VECTOR"
4349 "v<insn>.vx\t%0,%3,%4%p1"
4350 [(set_attr "type" "<int_binop_insn_type>")
4351 (set_attr "mode" "<MODE>")])
4353 (define_insn "@pred_<optab><mode>_scalar"
4354 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vd, vr, vr")
4355 (if_then_else:VI_QHS
4356 (unspec:<VM>
4357 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4358 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
4359 (match_operand 6 "const_int_operand" " i, i, i, i")
4360 (match_operand 7 "const_int_operand" " i, i, i, i")
4361 (match_operand 8 "const_int_operand" " i, i, i, i")
4362 (reg:SI VL_REGNUM)
4363 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4364 (sat_int_minus_binop:VI_QHS
4365 (match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr")
4366 (vec_duplicate:VI_QHS
4367 (match_operand:<VEL> 4 "register_operand" " r, r, r, r")))
4368 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4369 "TARGET_VECTOR"
4370 "v<insn>.vx\t%0,%3,%4%p1"
4371 [(set_attr "type" "<int_binop_insn_type>")
4372 (set_attr "mode" "<MODE>")])
4374 (define_expand "@pred_<optab><mode>_scalar"
4375 [(set (match_operand:VI_D 0 "register_operand")
4376 (if_then_else:VI_D
4377 (unspec:<VM>
4378 [(match_operand:<VM> 1 "vector_mask_operand")
4379 (match_operand 5 "vector_length_operand")
4380 (match_operand 6 "const_int_operand")
4381 (match_operand 7 "const_int_operand")
4382 (match_operand 8 "const_int_operand")
4383 (reg:SI VL_REGNUM)
4384 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4385 (sat_int_plus_binop:VI_D
4386 (vec_duplicate:VI_D
4387 (match_operand:<VEL> 4 "reg_or_int_operand"))
4388 (match_operand:VI_D 3 "register_operand"))
4389 (match_operand:VI_D 2 "vector_merge_operand")))]
4390 "TARGET_VECTOR"
4391 {
4392 if (riscv_vector::sew64_scalar_helper (
4393 operands,
4394 /* scalar op */&operands[4],
4395 /* vl */operands[5],
4396 <MODE>mode,
4397 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
4398 [] (rtx *operands, rtx broadcast_scalar) {
4399 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
4400 operands[2], operands[3], broadcast_scalar, operands[5],
4401 operands[6], operands[7], operands[8]));
4402 },
4403 (riscv_vector::avl_type) INTVAL (operands[8])))
4404 DONE;
4405 })
4407 (define_insn "*pred_<optab><mode>_scalar"
4408 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4409 (if_then_else:VI_D
4410 (unspec:<VM>
4411 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4412 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
4413 (match_operand 6 "const_int_operand" " i, i, i, i")
4414 (match_operand 7 "const_int_operand" " i, i, i, i")
4415 (match_operand 8 "const_int_operand" " i, i, i, i")
4416 (reg:SI VL_REGNUM)
4417 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4418 (sat_int_plus_binop:VI_D
4419 (vec_duplicate:VI_D
4420 (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))
4421 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))
4422 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4423 "TARGET_VECTOR"
4424 "v<insn>.vx\t%0,%3,%4%p1"
4425 [(set_attr "type" "<int_binop_insn_type>")
4426 (set_attr "mode" "<MODE>")])
4428 (define_insn "*pred_<optab><mode>_extended_scalar"
4429 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4430 (if_then_else:VI_D
4431 (unspec:<VM>
4432 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4433 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
4434 (match_operand 6 "const_int_operand" " i, i, i, i")
4435 (match_operand 7 "const_int_operand" " i, i, i, i")
4436 (match_operand 8 "const_int_operand" " i, i, i, i")
4437 (reg:SI VL_REGNUM)
4438 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4439 (sat_int_plus_binop:VI_D
4440 (vec_duplicate:VI_D
4441 (sign_extend:<VEL>
4442 (match_operand:<VSUBEL> 4 "register_operand" " r, r, r, r")))
4443 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))
4444 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4445 "TARGET_VECTOR && !TARGET_64BIT"
4446 "v<insn>.vx\t%0,%3,%4%p1"
4447 [(set_attr "type" "<int_binop_insn_type>")
4448 (set_attr "mode" "<MODE>")])
4450 (define_expand "@pred_<optab><mode>_scalar"
4451 [(set (match_operand:VI_D 0 "register_operand")
4452 (if_then_else:VI_D
4453 (unspec:<VM>
4454 [(match_operand:<VM> 1 "vector_mask_operand")
4455 (match_operand 5 "vector_length_operand")
4456 (match_operand 6 "const_int_operand")
4457 (match_operand 7 "const_int_operand")
4458 (match_operand 8 "const_int_operand")
4459 (reg:SI VL_REGNUM)
4460 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4461 (sat_int_minus_binop:VI_D
4462 (match_operand:VI_D 3 "register_operand")
4463 (vec_duplicate:VI_D
4464 (match_operand:<VEL> 4 "reg_or_int_operand")))
4465 (match_operand:VI_D 2 "vector_merge_operand")))]
4466 "TARGET_VECTOR"
4467 {
4468 if (riscv_vector::sew64_scalar_helper (
4469 operands,
4470 /* scalar op */&operands[4],
4471 /* vl */operands[5],
4472 <MODE>mode,
4473 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
4474 [] (rtx *operands, rtx broadcast_scalar) {
4475 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
4476 operands[2], operands[3], broadcast_scalar, operands[5],
4477 operands[6], operands[7], operands[8]));
4478 },
4479 (riscv_vector::avl_type) INTVAL (operands[8])))
4480 DONE;
4481 })
4483 (define_insn "*pred_<optab><mode>_scalar"
4484 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4485 (if_then_else:VI_D
4486 (unspec:<VM>
4487 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4488 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
4489 (match_operand 6 "const_int_operand" " i, i, i, i")
4490 (match_operand 7 "const_int_operand" " i, i, i, i")
4491 (match_operand 8 "const_int_operand" " i, i, i, i")
4492 (reg:SI VL_REGNUM)
4493 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4494 (sat_int_minus_binop:VI_D
4495 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4496 (vec_duplicate:VI_D
4497 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")))
4498 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4499 "TARGET_VECTOR"
4500 "v<insn>.vx\t%0,%3,%z4%p1"
4501 [(set_attr "type" "<int_binop_insn_type>")
4502 (set_attr "mode" "<MODE>")])
4504 (define_insn "*pred_<optab><mode>_extended_scalar"
4505 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4506 (if_then_else:VI_D
4507 (unspec:<VM>
4508 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4509 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
4510 (match_operand 6 "const_int_operand" " i, i, i, i")
4511 (match_operand 7 "const_int_operand" " i, i, i, i")
4512 (match_operand 8 "const_int_operand" " i, i, i, i")
4513 (reg:SI VL_REGNUM)
4514 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4515 (sat_int_minus_binop:VI_D
4516 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4517 (vec_duplicate:VI_D
4518 (sign_extend:<VEL>
4519 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))))
4520 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4521 "TARGET_VECTOR && !TARGET_64BIT"
4522 "v<insn>.vx\t%0,%3,%z4%p1"
4523 [(set_attr "type" "<int_binop_insn_type>")
4524 (set_attr "mode" "<MODE>")])
4526 (define_insn "@pred_<sat_op><mode>"
4527 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr")
4528 (if_then_else:V_VLSI
4529 (unspec:<VM>
4530 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4531 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
4532 (match_operand 6 "const_int_operand" " i, i, i, i")
4533 (match_operand 7 "const_int_operand" " i, i, i, i")
4534 (match_operand 8 "const_int_operand" " i, i, i, i")
4535 (match_operand 9 "const_int_operand" " i, i, i, i")
4536 (reg:SI VL_REGNUM)
4537 (reg:SI VTYPE_REGNUM)
4538 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4539 (unspec:V_VLSI
4540 [(match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")
4541 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")] VSAT_OP)
4542 (match_operand:V_VLSI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4543 "TARGET_VECTOR"
4544 "v<sat_op>.vv\t%0,%3,%4%p1"
4545 [(set_attr "type" "<sat_insn_type>")
4546 (set_attr "mode" "<MODE>")])
4548 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
4549 (define_insn "@pred_<sat_op><mode>_scalar"
4550 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr, vd, vr")
4551 (if_then_else:VI_QHS
4552 (unspec:<VM>
4553 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4554 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
4555 (match_operand 6 "const_int_operand" " i, i, i, i")
4556 (match_operand 7 "const_int_operand" " i, i, i, i")
4557 (match_operand 8 "const_int_operand" " i, i, i, i")
4558 (match_operand 9 "const_int_operand" " i, i, i, i")
4559 (reg:SI VL_REGNUM)
4560 (reg:SI VTYPE_REGNUM)
4561 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4562 (unspec:VI_QHS
4563 [(match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr")
4564 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
4565 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4566 "TARGET_VECTOR"
4567 "v<sat_op>.vx\t%0,%3,%z4%p1"
4568 [(set_attr "type" "<sat_insn_type>")
4569 (set_attr "mode" "<MODE>")])
4571 (define_insn "@pred_<sat_op><mode>_scalar"
4572 [(set (match_operand:VI 0 "register_operand" "=vd, vr, vd, vr")
4573 (if_then_else:VI
4574 (unspec:<VM>
4575 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4576 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
4577 (match_operand 6 "const_int_operand" " i, i, i, i")
4578 (match_operand 7 "const_int_operand" " i, i, i, i")
4579 (match_operand 8 "const_int_operand" " i, i, i, i")
4580 (match_operand 9 "const_int_operand" " i, i, i, i")
4581 (reg:SI VL_REGNUM)
4582 (reg:SI VTYPE_REGNUM)
4583 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4584 (unspec:VI
4585 [(match_operand:VI 3 "register_operand" " vr, vr, vr, vr")
4586 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSAT_SHIFT_OP)
4587 (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4588 "TARGET_VECTOR"
4589 "v<sat_op>.v%o4\t%0,%3,%4%p1"
4590 [(set_attr "type" "<sat_insn_type>")
4591 (set_attr "mode" "<MODE>")])
4593 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
4594 ;; we need to deal with SEW = 64 in RV32 system.
4595 (define_expand "@pred_<sat_op><mode>_scalar"
4596 [(set (match_operand:VI_D 0 "register_operand")
4597 (if_then_else:VI_D
4598 (unspec:<VM>
4599 [(match_operand:<VM> 1 "vector_mask_operand")
4600 (match_operand 5 "vector_length_operand")
4601 (match_operand 6 "const_int_operand")
4602 (match_operand 7 "const_int_operand")
4603 (match_operand 8 "const_int_operand")
4604 (match_operand 9 "const_int_operand")
4605 (reg:SI VL_REGNUM)
4606 (reg:SI VTYPE_REGNUM)
4607 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4608 (unspec:VI_D
4609 [(match_operand:VI_D 3 "register_operand")
4610 (match_operand:<VEL> 4 "reg_or_int_operand")] VSAT_ARITH_OP)
4611 (match_operand:VI_D 2 "vector_merge_operand")))]
4612 "TARGET_VECTOR"
4613 {
4614 if (riscv_vector::sew64_scalar_helper (
4615 operands,
4616 /* scalar op */&operands[4],
4617 /* vl */operands[5],
4618 <MODE>mode,
4619 false,
4620 [] (rtx *operands, rtx broadcast_scalar) {
4621 emit_insn (gen_pred_<sat_op><mode> (operands[0], operands[1],
4622 operands[2], operands[3], broadcast_scalar, operands[5],
4623 operands[6], operands[7], operands[8], operands[9]));
4624 },
4625 (riscv_vector::avl_type) INTVAL (operands[8])))
4626 DONE;
4627 })
4629 (define_insn "*pred_<sat_op><mode>_scalar"
4630 [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, vd, vr")
4631 (if_then_else:VI_D
4632 (unspec:<VM>
4633 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4634 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
4635 (match_operand 6 "const_int_operand" " i, i, i, i")
4636 (match_operand 7 "const_int_operand" " i, i, i, i")
4637 (match_operand 8 "const_int_operand" " i, i, i, i")
4638 (match_operand 9 "const_int_operand" " i, i, i, i")
4639 (reg:SI VL_REGNUM)
4640 (reg:SI VTYPE_REGNUM)
4641 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4642 (unspec:VI_D
4643 [(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4644 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
4645 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4646 "TARGET_VECTOR"
4647 "v<sat_op>.vx\t%0,%3,%z4%p1"
4648 [(set_attr "type" "<sat_insn_type>")
4649 (set_attr "mode" "<MODE>")])
4651 (define_insn "*pred_<sat_op><mode>_extended_scalar"
4652 [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, vd, vr")
4653 (if_then_else:VI_D
4654 (unspec:<VM>
4655 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4656 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
4657 (match_operand 6 "const_int_operand" " i, i, i, i")
4658 (match_operand 7 "const_int_operand" " i, i, i, i")
4659 (match_operand 8 "const_int_operand" " i, i, i, i")
4660 (match_operand 9 "const_int_operand" " i, i, i, i")
4661 (reg:SI VL_REGNUM)
4662 (reg:SI VTYPE_REGNUM)
4663 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4664 (unspec:VI_D
4665 [(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4666 (sign_extend:<VEL>
4667 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSAT_ARITH_OP)
4668 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4669 "TARGET_VECTOR && !TARGET_64BIT"
4670 "v<sat_op>.vx\t%0,%3,%z4%p1"
4671 [(set_attr "type" "<sat_insn_type>")
4672 (set_attr "mode" "<MODE>")])
4674 ;; CLIP
4675 (define_insn "@pred_narrow_clip<v_su><mode>"
4676 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd,vd, vr, vr,vd, vr, &vr, &vr, vd, vr, &vr, &vr")
4677 (if_then_else:<V_DOUBLE_TRUNC>
4678 (unspec:<VM>
4679 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1, vm,Wc1,vmWc1,vmWc1")
4680 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl,rvl,rvl, rvl, rvl,rvl,rvl, rvl, rvl")
4681 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4682 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4683 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4684 (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4685 (reg:SI VL_REGNUM)
4686 (reg:SI VTYPE_REGNUM)
4687 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4688 (unspec:<V_DOUBLE_TRUNC>
4689 [(match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr, 0, 0, vr, vr, 0, 0, vr, vr")
4690 (match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand" " 0, 0, 0, 0,vr, vr, vr, vr, vk, vk, vk, vk")] VNCLIP)
4691 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " 0,vu, 0, vu,vu, vu, vu, 0, vu, vu, vu, 0")))]
4692 "TARGET_VECTOR"
4693 "vnclip<v_su>.w%o4\t%0,%3,%v4%p1"
4694 [(set_attr "type" "vnclip")
4695 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4696 (set_attr "spec_restriction" "thv,thv,thv,thv,thv,thv,none,none,thv,thv,none,none")])
4698 (define_insn "@pred_narrow_clip<v_su><mode>_scalar"
4699 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
4700 (if_then_else:<V_DOUBLE_TRUNC>
4701 (unspec:<VM>
4702 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
4703 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl, rvl, rvl")
4704 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
4705 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
4706 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
4707 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
4708 (reg:SI VL_REGNUM)
4709 (reg:SI VTYPE_REGNUM)
4710 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4711 (unspec:<V_DOUBLE_TRUNC>
4712 [(match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr")
4713 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK, rK, rK")] VNCLIP)
4714 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
4715 "TARGET_VECTOR"
4716 "vnclip<v_su>.w%o4\t%0,%3,%4%p1"
4717 [(set_attr "type" "vnclip")
4718 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4719 (set_attr "spec_restriction" "thv,thv,thv,thv,none,none")])
4721 ;; -------------------------------------------------------------------------------
4722 ;; ---- Predicated integer comparison operations
4723 ;; -------------------------------------------------------------------------------
4724 ;; Includes:
4725 ;; - 11.8 Vector Integer Comparison Instructions
4726 ;; -------------------------------------------------------------------------------
4728 (define_expand "@pred_cmp<mode>"
4729 [(set (match_operand:<VM> 0 "register_operand")
4730 (if_then_else:<VM>
4731 (unspec:<VM>
4732 [(match_operand:<VM> 1 "vector_mask_operand")
4733 (match_operand 6 "vector_length_operand")
4734 (match_operand 7 "const_int_operand")
4735 (match_operand 8 "const_int_operand")
4736 (reg:SI VL_REGNUM)
4737 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4738 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4739 [(match_operand:V_VLSI 4 "register_operand")
4740 (match_operand:V_VLSI 5 "vector_arith_operand")])
4741 (match_operand:<VM> 2 "vector_merge_operand")))]
4742 "TARGET_VECTOR"
4743 {})
4745 (define_insn "*pred_cmp<mode>_merge_tie_mask"
4746 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4747 (if_then_else:<VM>
4748 (unspec:<VM>
4749 [(match_operand:<VM> 1 "register_operand" " 0")
4750 (match_operand 5 "vector_length_operand" " rvl")
4751 (match_operand 6 "const_int_operand" " i")
4752 (match_operand 7 "const_int_operand" " i")
4753 (reg:SI VL_REGNUM)
4754 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4755 (match_operator:<VM> 2 "comparison_except_ltge_operator"
4756 [(match_operand:V_VLSI 3 "register_operand" " vr")
4757 (match_operand:V_VLSI 4 "vector_arith_operand" "vrvi")])
4758 (match_dup 1)))]
4759 "TARGET_VECTOR"
4760 "vms%B2.v%o4\t%0,%3,%v4,v0.t"
4761 [(set_attr "type" "vicmp")
4762 (set_attr "mode" "<MODE>")
4763 (set_attr "merge_op_idx" "1")
4764 (set_attr "vl_op_idx" "5")
4765 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4766 (set (attr "avl_type_idx") (const_int 7))])
4768 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4769 (define_insn "*pred_cmp<mode>"
4770 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, vr, vr, &vr, &vr, &vr, &vr")
4771 (if_then_else:<VM>
4772 (unspec:<VM>
4773 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4774 (match_operand 6 "vector_length_operand" " rvl, rvl, rvl, rvl, rvl, rvl, rvl, rvl")
4775 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
4776 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
4777 (reg:SI VL_REGNUM)
4778 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4779 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4780 [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr")
4781 (match_operand:V_VLSI 5 "vector_arith_operand" " vr, vr, vi, vi, vr, vr, vi, vi")])
4782 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
4783 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4784 "vms%B3.v%o5\t%0,%4,%v5%p1"
4785 [(set_attr "type" "vicmp")
4786 (set_attr "mode" "<MODE>")
4787 (set_attr "spec_restriction" "thv,thv,thv,thv,rvv,rvv,rvv,rvv")])
4789 ;; We use early-clobber for source LMUL > dest LMUL.
4790 (define_insn "*pred_cmp<mode>_narrow"
4791 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
4792 (if_then_else:<VM>
4793 (unspec:<VM>
4794 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4795 (match_operand 6 "vector_length_operand" " rvl, rvl, rvl, rvl, rvl, rvl, rvl, rvl, rvl")
4796 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4797 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4798 (reg:SI VL_REGNUM)
4799 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4800 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4801 [(match_operand:V_VLSI 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
4802 (match_operand:V_VLSI 5 "vector_arith_operand" " vrvi, vrvi, 0, 0, vrvi, 0, 0, vrvi, vrvi")])
4803 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
4804 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4805 "vms%B3.v%o5\t%0,%4,%v5%p1"
4806 [(set_attr "type" "vicmp")
4807 (set_attr "mode" "<MODE>")
4808 (set_attr "spec_restriction" "none,thv,thv,thv,thv,thv,thv,none,none")])
4810 (define_expand "@pred_ltge<mode>"
4811 [(set (match_operand:<VM> 0 "register_operand")
4812 (if_then_else:<VM>
4813 (unspec:<VM>
4814 [(match_operand:<VM> 1 "vector_mask_operand")
4815 (match_operand 6 "vector_length_operand")
4816 (match_operand 7 "const_int_operand")
4817 (match_operand 8 "const_int_operand")
4818 (reg:SI VL_REGNUM)
4819 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4820 (match_operator:<VM> 3 "ltge_operator"
4821 [(match_operand:V_VLSI 4 "register_operand")
4822 (match_operand:V_VLSI 5 "vector_neg_arith_operand")])
4823 (match_operand:<VM> 2 "vector_merge_operand")))]
4824 "TARGET_VECTOR"
4825 {})
4827 (define_insn "*pred_ltge<mode>_merge_tie_mask"
4828 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4829 (if_then_else:<VM>
4830 (unspec:<VM>
4831 [(match_operand:<VM> 1 "register_operand" " 0")
4832 (match_operand 5 "vector_length_operand" " rvl")
4833 (match_operand 6 "const_int_operand" " i")
4834 (match_operand 7 "const_int_operand" " i")
4835 (reg:SI VL_REGNUM)
4836 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4837 (match_operator:<VM> 2 "ltge_operator"
4838 [(match_operand:V_VLSI 3 "register_operand" " vr")
4839 (match_operand:V_VLSI 4 "vector_neg_arith_operand" "vrvj")])
4840 (match_dup 1)))]
4841 "TARGET_VECTOR"
4842 "vms%B2.v%o4\t%0,%3,%v4,v0.t"
4843 [(set_attr "type" "vicmp")
4844 (set_attr "mode" "<MODE>")
4845 (set_attr "merge_op_idx" "1")
4846 (set_attr "vl_op_idx" "5")
4847 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4848 (set (attr "avl_type_idx") (const_int 7))])
4850 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4851 (define_insn "*pred_ltge<mode>"
4852 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, vr, vr, &vr, &vr, &vr, &vr")
4853 (if_then_else:<VM>
4854 (unspec:<VM>
4855 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4856 (match_operand 6 "vector_length_operand" " rvl, rvl, rvl, rvl, rvl, rvl, rvl, rvl")
4857 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
4858 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
4859 (reg:SI VL_REGNUM)
4860 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4861 (match_operator:<VM> 3 "ltge_operator"
4862 [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr")
4863 (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vr, vr, vj, vj, vr, vr, vj, vj")])
4864 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
4865 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4866 "vms%B3.v%o5\t%0,%4,%v5%p1"
4867 [(set_attr "type" "vicmp")
4868 (set_attr "mode" "<MODE>")
4869 (set_attr "spec_restriction" "thv,thv,thv,thv,rvv,rvv,rvv,rvv")])
4871 ;; We use early-clobber for source LMUL > dest LMUL.
4872 (define_insn "*pred_ltge<mode>_narrow"
4873 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
4874 (if_then_else:<VM>
4875 (unspec:<VM>
4876 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4877 (match_operand 6 "vector_length_operand" " rvl, rvl, rvl, rvl, rvl, rvl, rvl, rvl, rvl")
4878 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4879 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4880 (reg:SI VL_REGNUM)
4881 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4882 (match_operator:<VM> 3 "ltge_operator"
4883 [(match_operand:V_VLSI 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
4884 (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vrvj, vrvj, 0, 0, vrvj, 0, 0, vrvj, vrvj")])
4885 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
4886 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4887 "vms%B3.v%o5\t%0,%4,%v5%p1"
4888 [(set_attr "type" "vicmp")
4889 (set_attr "mode" "<MODE>")
4890 (set_attr "spec_restriction" "none,thv,thv,thv,thv,thv,thv,none,none")])
4892 (define_expand "@pred_cmp<mode>_scalar"
4893 [(set (match_operand:<VM> 0 "register_operand")
4894 (if_then_else:<VM>
4895 (unspec:<VM>
4896 [(match_operand:<VM> 1 "vector_mask_operand")
4897 (match_operand 6 "vector_length_operand")
4898 (match_operand 7 "const_int_operand")
4899 (match_operand 8 "const_int_operand")
4900 (reg:SI VL_REGNUM)
4901 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4902 (match_operator:<VM> 3 "comparison_except_ge_operator"
4903 [(match_operand:V_VLSI_QHS 4 "register_operand")
4904 (vec_duplicate:V_VLSI_QHS
4905 (match_operand:<VEL> 5 "register_operand"))])
4906 (match_operand:<VM> 2 "vector_merge_operand")))]
4907 "TARGET_VECTOR"
4908 {})
4910 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
4911 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4912 (if_then_else:<VM>
4913 (unspec:<VM>
4914 [(match_operand:<VM> 1 "register_operand" " 0")
4915 (match_operand 5 "vector_length_operand" "rvl")
4916 (match_operand 6 "const_int_operand" " i")
4917 (match_operand 7 "const_int_operand" " i")
4918 (reg:SI VL_REGNUM)
4919 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4920 (match_operator:<VM> 2 "comparison_except_ge_operator"
4921 [(match_operand:V_VLSI_QHS 3 "register_operand" " vr")
4922 (vec_duplicate:V_VLSI_QHS
4923 (match_operand:<VEL> 4 "register_operand" " r"))])
4924 (match_dup 1)))]
4925 "TARGET_VECTOR"
4926 "vms%B2.vx\t%0,%3,%4,v0.t"
4927 [(set_attr "type" "vicmp")
4928 (set_attr "mode" "<MODE>")
4929 (set_attr "merge_op_idx" "1")
4930 (set_attr "vl_op_idx" "5")
4931 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4932 (set (attr "avl_type_idx") (const_int 7))])
4934 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4935 (define_insn "*pred_cmp<mode>_scalar"
4936 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
4937 (if_then_else:<VM>
4938 (unspec:<VM>
4939 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
4940 (match_operand 6 "vector_length_operand" " rvl, rvl, rvl, rvl")
4941 (match_operand 7 "const_int_operand" " i, i, i, i")
4942 (match_operand 8 "const_int_operand" " i, i, i, i")
4943 (reg:SI VL_REGNUM)
4944 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4945 (match_operator:<VM> 3 "comparison_except_ge_operator"
4946 [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr")
4947 (vec_duplicate:V_VLSI_QHS
4948 (match_operand:<VEL> 5 "register_operand" " r, r, r, r"))])
4949 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4950 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4951 "vms%B3.vx\t%0,%4,%5%p1"
4952 [(set_attr "type" "vicmp")
4953 (set_attr "mode" "<MODE>")
4954 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
4956 ;; We use early-clobber for source LMUL > dest LMUL.
4957 (define_insn "*pred_cmp<mode>_scalar_narrow"
4958 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4959 (if_then_else:<VM>
4960 (unspec:<VM>
4961 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4962 (match_operand 6 "vector_length_operand" " rvl, rvl, rvl, rvl, rvl")
4963 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4964 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4965 (reg:SI VL_REGNUM)
4966 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4967 (match_operator:<VM> 3 "comparison_except_ge_operator"
4968 [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")
4969 (vec_duplicate:V_VLSI_QHS
4970 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))])
4971 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4972 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4973 "vms%B3.vx\t%0,%4,%5%p1"
4974 [(set_attr "type" "vicmp")
4975 (set_attr "mode" "<MODE>")
4976 (set_attr "spec_restriction" "none,thv,thv,none,none")])
4978 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
4979 ;; we need to deal with SEW = 64 in RV32 system.
4980 (define_expand "@pred_cmp<mode>_scalar"
4981 [(set (match_operand:<VM> 0 "register_operand")
4982 (if_then_else:<VM>
4983 (unspec:<VM>
4984 [(match_operand:<VM> 1 "vector_mask_operand")
4985 (match_operand 6 "vector_length_operand")
4986 (match_operand 7 "const_int_operand")
4987 (match_operand 8 "const_int_operand")
4988 (reg:SI VL_REGNUM)
4989 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4990 (match_operator:<VM> 3 "comparison_except_ge_operator"
4991 [(match_operand:V_VLSI_D 4 "register_operand")
4992 (vec_duplicate:V_VLSI_D
4993 (match_operand:<VEL> 5 "reg_or_int_operand"))])
4994 (match_operand:<VM> 2 "vector_merge_operand")))]
4995 "TARGET_VECTOR"
4996 {
4997 enum rtx_code code = GET_CODE (operands[3]);
4998 if (riscv_vector::sew64_scalar_helper (
4999 operands,
5000 /* scalar op */&operands[5],
5001 /* vl */operands[6],
5002 <MODE>mode,
5003 riscv_vector::has_vi_variant_p (code, operands[5]),
5004 code == LT || code == LTU ?
5005 [] (rtx *operands, rtx broadcast_scalar) {
5006 emit_insn (gen_pred_ltge<mode> (operands[0], operands[1],
5007 operands[2], operands[3], operands[4], broadcast_scalar,
5008 operands[6], operands[7], operands[8]));
5009 }
5010 :
5011 [] (rtx *operands, rtx broadcast_scalar) {
5012 emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
5013 operands[2], operands[3], operands[4], broadcast_scalar,
5014 operands[6], operands[7], operands[8]));
5015 },
5016 (riscv_vector::avl_type) INTVAL (operands[8])))
5017 DONE;
5018 })
5020 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
5021 [(set (match_operand:<VM> 0 "register_operand" "=vm")
5022 (if_then_else:<VM>
5023 (unspec:<VM>
5024 [(match_operand:<VM> 1 "register_operand" " 0")
5025 (match_operand 5 "vector_length_operand" "rvl")
5026 (match_operand 6 "const_int_operand" " i")
5027 (match_operand 7 "const_int_operand" " i")
5028 (reg:SI VL_REGNUM)
5029 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5030 (match_operator:<VM> 2 "comparison_except_ge_operator"
5031 [(match_operand:V_VLSI_D 3 "register_operand" " vr")
5032 (vec_duplicate:V_VLSI_D
5033 (match_operand:<VEL> 4 "register_operand" " r"))])
5034 (match_dup 1)))]
5035 "TARGET_VECTOR"
5036 "vms%B2.vx\t%0,%3,%4,v0.t"
5037 [(set_attr "type" "vicmp")
5038 (set_attr "mode" "<MODE>")
5039 (set_attr "merge_op_idx" "1")
5040 (set_attr "vl_op_idx" "5")
5041 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
5042 (set (attr "avl_type_idx") (const_int 7))])
5044 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
5045 (define_insn "*pred_cmp<mode>_scalar"
5046 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
5047 (if_then_else:<VM>
5048 (unspec:<VM>
5049 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
5050 (match_operand 6 "vector_length_operand" " rvl, rvl, rvl, rvl")
5051 (match_operand 7 "const_int_operand" " i, i, i, i")
5052 (match_operand 8 "const_int_operand" " i, i, i, i")
5053 (reg:SI VL_REGNUM)
5054 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5055 (match_operator:<VM> 3 "comparison_except_ge_operator"
5056 [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
5057 (vec_duplicate:V_VLSI_D
5058 (match_operand:<VEL> 5 "register_operand" " r, r, r, r"))])
5059 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
5060 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
5061 "vms%B3.vx\t%0,%4,%5%p1"
5062 [(set_attr "type" "vicmp")
5063 (set_attr "mode" "<MODE>")
5064 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
5066 ;; We use early-clobber for source LMUL > dest LMUL.
5067 (define_insn "*pred_cmp<mode>_scalar_narrow"
5068 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
5069 (if_then_else:<VM>
5070 (unspec:<VM>
5071 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
5072 (match_operand 6 "vector_length_operand" " rvl, rvl, rvl, rvl, rvl")
5073 (match_operand 7 "const_int_operand" " i, i, i, i, i")
5074 (match_operand 8 "const_int_operand" " i, i, i, i, i")
5075 (reg:SI VL_REGNUM)
5076 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5077 (match_operator:<VM> 3 "comparison_except_ge_operator"
5078 [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")
5079 (vec_duplicate:V_VLSI_D
5080 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))])
5081 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
5082 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
5083 "vms%B3.vx\t%0,%4,%5%p1"
5084 [(set_attr "type" "vicmp")
5085 (set_attr "mode" "<MODE>")
5086 (set_attr "spec_restriction" "none,thv,thv,none,none")])
5088 (define_insn "*pred_cmp<mode>_extended_scalar_merge_tie_mask"
5089 [(set (match_operand:<VM> 0 "register_operand" "=vm")
5090 (if_then_else:<VM>
5091 (unspec:<VM>
5092 [(match_operand:<VM> 1 "register_operand" " 0")
5093 (match_operand 5 "vector_length_operand" "rvl")
5094 (match_operand 6 "const_int_operand" " i")
5095 (match_operand 7 "const_int_operand" " i")
5096 (reg:SI VL_REGNUM)
5097 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5098 (match_operator:<VM> 2 "comparison_except_ge_operator"
5099 [(match_operand:V_VLSI_D 3 "register_operand" " vr")
5100 (vec_duplicate:V_VLSI_D
5101 (sign_extend:<VEL>
5102 (match_operand:<VSUBEL> 4 "register_operand" " r")))])
5103 (match_dup 1)))]
5104 "TARGET_VECTOR && !TARGET_64BIT"
5105 "vms%B2.vx\t%0,%3,%4,v0.t"
5106 [(set_attr "type" "vicmp")
5107 (set_attr "mode" "<MODE>")
5108 (set_attr "merge_op_idx" "1")
5109 (set_attr "vl_op_idx" "5")
5110 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
5111 (set (attr "avl_type_idx") (const_int 7))])
5113 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
5114 (define_insn "*pred_cmp<mode>_extended_scalar"
5115 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
5116 (if_then_else:<VM>
5117 (unspec:<VM>
5118 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
5119 (match_operand 6 "vector_length_operand" " rvl, rvl, rvl, rvl")
5120 (match_operand 7 "const_int_operand" " i, i, i, i")
5121 (match_operand 8 "const_int_operand" " i, i, i, i")
5122 (reg:SI VL_REGNUM)
5123 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5124 (match_operator:<VM> 3 "comparison_except_ge_operator"
5125 [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
5126 (vec_duplicate:V_VLSI_D
5127 (sign_extend:<VEL>
5128 (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r")))])
5129 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
5130 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode) && !TARGET_64BIT"
5131 "vms%B3.vx\t%0,%4,%5%p1"
5132 [(set_attr "type" "vicmp")
5133 (set_attr "mode" "<MODE>")
5134 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
5136 (define_insn "*pred_cmp<mode>_extended_scalar_narrow"
5137 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
5138 (if_then_else:<VM>
5139 (unspec:<VM>
5140 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
5141 (match_operand 6 "vector_length_operand" " rvl, rvl, rvl, rvl, rvl")
5142 (match_operand 7 "const_int_operand" " i, i, i, i, i")
5143 (match_operand 8 "const_int_operand" " i, i, i, i, i")
5144 (reg:SI VL_REGNUM)
5145 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5146 (match_operator:<VM> 3 "comparison_except_ge_operator"
5147 [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")
5148 (vec_duplicate:V_VLSI_D
5149 (sign_extend:<VEL>
5150 (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r, r")))])
5151 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
5152 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode) && !TARGET_64BIT"
5153 "vms%B3.vx\t%0,%4,%5%p1"
5154 [(set_attr "type" "vicmp")
5155 (set_attr "mode" "<MODE>")
5156 (set_attr "spec_restriction" "none,thv,thv,none,none")])
5158 ;; GE, vmsge.vx/vmsgeu.vx
5159 ;;
5160 ;; unmasked va >= x
5161 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x
5162 ;; - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd
5163 ;;
5164 ;; masked va >= x, vd != v0
5165 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
5166 ;; - expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
5167 ;;
5168 ;; masked va >= x, vd == v0
5169 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
5170 ;; - expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt
5171 (define_expand "@pred_ge<mode>_scalar"
5172 [(set (match_operand:<VM> 0 "register_operand")
5173 (if_then_else:<VM>
5174 (unspec:<VM>
5175 [(match_operand:<VM> 1 "vector_mask_operand")
5176 (match_operand 6 "vector_length_operand")
5177 (match_operand 7 "const_int_operand")
5178 (match_operand 8 "const_int_operand")
5179 (reg:SI VL_REGNUM)
5180 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5181 (match_operator:<VM> 3 "ge_operator"
5182 [(match_operand:V_VLSI 4 "register_operand")
5183 (vec_duplicate:V_VLSI
5184 (match_operand:<VEL> 5 "reg_or_int_operand"))])
5185 (match_operand:<VM> 2 "vector_merge_operand")))]
5186 "TARGET_VECTOR"
5187 {
5188 enum rtx_code code = GET_CODE (operands[3]);
5189 rtx undef = RVV_VUNDEF (<VM>mode);
5190 rtx tmp = gen_reg_rtx (<VM>mode);
5191 if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
5192 {
5193 /* If vmsgeu with 0 immediate, expand it to vmset. */
5194 if (satisfies_constraint_Wc1 (operands[1]))
5195 emit_insn (
5196 gen_pred_mov (<VM>mode, operands[0], CONSTM1_RTX (<VM>mode), undef,
5197 CONSTM1_RTX (<VM>mode), operands[6], operands[8]));
5198 else
5199 {
5200 /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
5201 */
5202 if (rtx_equal_p (operands[1], operands[2]))
5203 emit_move_insn (operands[0], operands[1]);
5204 else if (register_operand (operands[2], <VM>mode))
5205 emit_insn (gen_pred (IOR, <VM>mode, operands[0],
5206 CONSTM1_RTX (<VM>mode), undef, operands[1],
5207 operands[2], operands[6], operands[8]));
5208 else
5209 emit_insn (gen_pred (IOR, <VM>mode, operands[0],
5210 CONSTM1_RTX (<VM>mode), undef, operands[1],
5211 operands[1], operands[6], operands[8]));
5212 }
5213 }
5214 else if (riscv_vector::neg_simm5_p (operands[5]))
5215 emit_insn (
5216 gen_pred_ltge<mode> (operands[0], operands[1], operands[2], operands[3],
5217 operands[4],
5218 gen_const_vec_duplicate (<MODE>mode, operands[5]),
5219 operands[6], operands[7], operands[8]));
5220 else
5221 {
5222 if (code == GE)
5223 operands[3] = gen_rtx_fmt_ee (LT, <VM>mode, XEXP (operands[3], 0),
5224 XEXP (operands[3], 1));
5225 else
5226 operands[3] = gen_rtx_fmt_ee (LTU, <VM>mode, XEXP (operands[3], 0),
5227 XEXP (operands[3], 1));
5228 if (GET_MODE_BITSIZE (<VEL>mode) <= GET_MODE_BITSIZE (Pmode))
5229 operands[5] = force_reg (<VEL>mode, operands[5]);
5231 if (satisfies_constraint_Wc1 (operands[1]))
5232 {
5233 /* unmasked va >= x
5234 - pseudoinstruction: vmsge{u}.vx vd, va, x
5235 - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd. */
5236 emit_insn (
5237 gen_pred_cmp<mode>_scalar (tmp, operands[1], operands[2],
5238 operands[3], operands[4], operands[5],
5239 operands[6], operands[7], operands[8]));
5240 emit_insn (gen_pred_nand<vm> (operands[0], CONSTM1_RTX (<VM>mode),
5241 undef, tmp, tmp, operands[6], operands[8]));
5242 }
5243 else
5244 {
5245 if (rtx_equal_p (operands[1], operands[2]))
5246 {
5247 /* masked va >= x, vd == v0
5248 - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
5249 - expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt. */
5250 emit_insn (gen_pred_cmp<mode>_scalar (
5251 tmp, CONSTM1_RTX (<VM>mode), undef, operands[3], operands[4],
5252 operands[5], operands[6], operands[7], operands[8]));
5253 emit_insn (
5254 gen_pred_andnot<vm> (operands[0], CONSTM1_RTX (<VM>mode), undef,
5255 operands[1], tmp, operands[6], operands[8]));
5256 }
5257 else
5258 {
5259 /* masked va >= x, vd != v0
5260 - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
5261 - expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
5262 */
5263 emit_insn (gen_pred_cmp<mode>_scalar (
5264 tmp, operands[1], operands[2], operands[3], operands[4],
5265 operands[5], operands[6], operands[7], operands[8]));
5266 emit_insn (gen_pred (XOR, <VM>mode, operands[0],
5267 CONSTM1_RTX (<VM>mode), undef, tmp,
5268 operands[1], operands[6], operands[8]));
5269 }
5270 }
5271 }
5272 DONE;
5273 })
5275 ;; -------------------------------------------------------------------------------
5276 ;; ---- Predicated integer ternary operations
5277 ;; -------------------------------------------------------------------------------
5278 ;; Includes:
5279 ;; - 11.13 Vector Single-Width Integer Multiply-Add Instructions
5280 ;; -------------------------------------------------------------------------------
5282 (define_expand "@pred_mul_plus<mode>"
5283 [(set (match_operand:V_VLSI 0 "register_operand")
5284 (if_then_else:V_VLSI
5285 (unspec:<VM>
5286 [(match_operand:<VM> 1 "vector_mask_operand")
5287 (match_operand 6 "vector_length_operand")
5288 (match_operand 7 "const_int_operand")
5289 (match_operand 8 "const_int_operand")
5290 (match_operand 9 "const_int_operand")
5291 (reg:SI VL_REGNUM)
5292 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5293 (plus:V_VLSI
5294 (mult:V_VLSI
5295 (match_operand:V_VLSI 2 "register_operand")
5296 (match_operand:V_VLSI 3 "register_operand"))
5297 (match_operand:V_VLSI 4 "register_operand"))
5298 (match_operand:V_VLSI 5 "vector_merge_operand")))]
5299 "TARGET_VECTOR"
5300 {
5301 riscv_vector::prepare_ternary_operands (operands);
5302 })
5304 (define_insn "*pred_mul_plus<mode>_undef"
5305 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr")
5306 (if_then_else:V_VLSI
5307 (unspec:<VM>
5308 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, Wc1,Wc1")
5309 (match_operand 6 "vector_length_operand" "rvl,rvl, rvl,rvl")
5310 (match_operand 7 "const_int_operand" " i, i, i, i")
5311 (match_operand 8 "const_int_operand" " i, i, i, i")
5312 (match_operand 9 "const_int_operand" " i, i, i, i")
5313 (reg:SI VL_REGNUM)
5314 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5315 (plus:V_VLSI
5316 (mult:V_VLSI
5317 (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr")
5318 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr"))
5319 (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, 0"))
5320 (match_operand:V_VLSI 2 "vector_undef_operand")))]
5321 "TARGET_VECTOR"
5322 "@
5323 vmadd.vv\t%0,%4,%5%p1
5324 vmacc.vv\t%0,%3,%4%p1
5325 vmadd.vv\t%0,%4,%5%p1
5326 vmacc.vv\t%0,%3,%4%p1"
5327 [(set_attr "type" "vimuladd")
5328 (set_attr "mode" "<MODE>")])
5330 (define_insn "*pred_madd<mode>"
5331 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr")
5332 (if_then_else:V_VLSI
5333 (unspec:<VM>
5334 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
5335 (match_operand 5 "vector_length_operand" "rvl,rvl")
5336 (match_operand 6 "const_int_operand" " i, i")
5337 (match_operand 7 "const_int_operand" " i, i")
5338 (match_operand 8 "const_int_operand" " i, i")
5339 (reg:SI VL_REGNUM)
5340 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5341 (plus:V_VLSI
5342 (mult:V_VLSI
5343 (match_operand:V_VLSI 2 "register_operand" " 0, 0")
5344 (match_operand:V_VLSI 3 "register_operand" " vr, vr"))
5345 (match_operand:V_VLSI 4 "register_operand" " vr, vr"))
5346 (match_dup 2)))]
5347 "TARGET_VECTOR"
5348 "@
5349 vmadd.vv\t%0,%3,%4%p1
5350 vmadd.vv\t%0,%3,%4%p1"
5351 [(set_attr "type" "vimuladd")
5352 (set_attr "mode" "<MODE>")
5353 (set_attr "merge_op_idx" "2")
5354 (set_attr "vl_op_idx" "5")
5355 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5356 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5357 (set (attr "avl_type_idx") (const_int 8))])
5359 (define_insn "*pred_macc<mode>"
5360 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr")
5361 (if_then_else:V_VLSI
5362 (unspec:<VM>
5363 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
5364 (match_operand 5 "vector_length_operand" "rvl,rvl")
5365 (match_operand 6 "const_int_operand" " i, i")
5366 (match_operand 7 "const_int_operand" " i, i")
5367 (match_operand 8 "const_int_operand" " i, i")
5368 (reg:SI VL_REGNUM)
5369 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5370 (plus:V_VLSI
5371 (mult:V_VLSI
5372 (match_operand:V_VLSI 2 "register_operand" " vr, vr")
5373 (match_operand:V_VLSI 3 "register_operand" " vr, vr"))
5374 (match_operand:V_VLSI 4 "register_operand" " 0, 0"))
5375 (match_dup 4)))]
5376 "TARGET_VECTOR"
5377 "vmacc.vv\t%0,%2,%3%p1"
5378 [(set_attr "type" "vimuladd")
5379 (set_attr "mode" "<MODE>")
5380 (set_attr "merge_op_idx" "4")
5381 (set_attr "vl_op_idx" "5")
5382 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5383 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5384 (set (attr "avl_type_idx") (const_int 8))])
5386 (define_expand "@pred_mul_plus<mode>_scalar"
5387 [(set (match_operand:V_VLSI_QHS 0 "register_operand")
5388 (if_then_else:V_VLSI_QHS
5389 (unspec:<VM>
5390 [(match_operand:<VM> 1 "vector_mask_operand")
5391 (match_operand 6 "vector_length_operand")
5392 (match_operand 7 "const_int_operand")
5393 (match_operand 8 "const_int_operand")
5394 (match_operand 9 "const_int_operand")
5395 (reg:SI VL_REGNUM)
5396 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5397 (plus:V_VLSI_QHS
5398 (mult:V_VLSI_QHS
5399 (vec_duplicate:V_VLSI_QHS
5400 (match_operand:<VEL> 2 "register_operand"))
5401 (match_operand:V_VLSI_QHS 3 "register_operand"))
5402 (match_operand:V_VLSI_QHS 4 "register_operand"))
5403 (match_operand:V_VLSI_QHS 5 "register_operand")))]
5404 "TARGET_VECTOR"
5405 {})
5407 (define_insn "*pred_madd<mode>_scalar"
5408 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr")
5409 (if_then_else:V_VLSI
5410 (unspec:<VM>
5411 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
5412 (match_operand 5 "vector_length_operand" "rvl,rvl")
5413 (match_operand 6 "const_int_operand" " i, i")
5414 (match_operand 7 "const_int_operand" " i, i")
5415 (match_operand 8 "const_int_operand" " i, i")
5416 (reg:SI VL_REGNUM)
5417 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5418 (plus:V_VLSI
5419 (mult:V_VLSI
5420 (vec_duplicate:V_VLSI
5421 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
5422 (match_operand:V_VLSI 3 "register_operand" " 0, 0"))
5423 (match_operand:V_VLSI 4 "register_operand" " vr, vr"))
5424 (match_dup 3)))]
5425 "TARGET_VECTOR"
5426 "@
5427 vmadd.vx\t%0,%z2,%4%p1
5428 vmadd.vx\t%0,%z2,%4%p1"
5429 [(set_attr "type" "vimuladd")
5430 (set_attr "mode" "<MODE>")
5431 (set_attr "merge_op_idx" "3")
5432 (set_attr "vl_op_idx" "5")
5433 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5434 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5435 (set (attr "avl_type_idx") (const_int 8))])
5437 (define_insn "*pred_macc<mode>_scalar"
5438 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr")
5439 (if_then_else:V_VLSI
5440 (unspec:<VM>
5441 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
5442 (match_operand 5 "vector_length_operand" "rvl,rvl")
5443 (match_operand 6 "const_int_operand" " i, i")
5444 (match_operand 7 "const_int_operand" " i, i")
5445 (match_operand 8 "const_int_operand" " i, i")
5446 (reg:SI VL_REGNUM)
5447 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5448 (plus:V_VLSI
5449 (mult:V_VLSI
5450 (vec_duplicate:V_VLSI
5451 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
5452 (match_operand:V_VLSI 3 "register_operand" " vr, vr"))
5453 (match_operand:V_VLSI 4 "register_operand" " 0, 0"))
5454 (match_dup 4)))]
5455 "TARGET_VECTOR"
5456 "@
5457 vmacc.vx\t%0,%z2,%3%p1
5458 vmacc.vx\t%0,%z2,%3%p1"
5459 [(set_attr "type" "vimuladd")
5460 (set_attr "mode" "<MODE>")
5461 (set_attr "merge_op_idx" "4")
5462 (set_attr "vl_op_idx" "5")
5463 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5464 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5465 (set (attr "avl_type_idx") (const_int 8))])
5467 (define_expand "@pred_mul_plus<mode>_scalar"
5468 [(set (match_operand:V_VLSI_D 0 "register_operand")
5469 (if_then_else:V_VLSI_D
5470 (unspec:<VM>
5471 [(match_operand:<VM> 1 "vector_mask_operand")
5472 (match_operand 6 "vector_length_operand")
5473 (match_operand 7 "const_int_operand")
5474 (match_operand 8 "const_int_operand")
5475 (match_operand 9 "const_int_operand")
5476 (reg:SI VL_REGNUM)
5477 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5478 (plus:V_VLSI_D
5479 (mult:V_VLSI_D
5480 (vec_duplicate:V_VLSI_D
5481 (match_operand:<VEL> 2 "reg_or_int_operand"))
5482 (match_operand:V_VLSI_D 3 "register_operand"))
5483 (match_operand:V_VLSI_D 4 "register_operand"))
5484 (match_operand:V_VLSI_D 5 "register_operand")))]
5485 "TARGET_VECTOR"
5486 {
5487 if (riscv_vector::sew64_scalar_helper (
5488 operands,
5489 /* scalar op */&operands[2],
5490 /* vl */operands[6],
5491 <MODE>mode,
5492 false,
5493 [] (rtx *operands, rtx broadcast_scalar) {
5494 emit_insn (gen_pred_mul_plus<mode> (operands[0], operands[1],
5495 broadcast_scalar, operands[3], operands[4], operands[5],
5496 operands[6], operands[7], operands[8], operands[9]));
5497 },
5498 (riscv_vector::avl_type) INTVAL (operands[9])))
5499 DONE;
5500 })
5502 (define_insn "*pred_madd<mode>_extended_scalar"
5503 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd, vr")
5504 (if_then_else:V_VLSI_D
5505 (unspec:<VM>
5506 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
5507 (match_operand 5 "vector_length_operand" "rvl,rvl")
5508 (match_operand 6 "const_int_operand" " i, i")
5509 (match_operand 7 "const_int_operand" " i, i")
5510 (match_operand 8 "const_int_operand" " i, i")
5511 (reg:SI VL_REGNUM)
5512 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5513 (plus:V_VLSI_D
5514 (mult:V_VLSI_D
5515 (vec_duplicate:V_VLSI_D
5516 (sign_extend:<VEL>
5517 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
5518 (match_operand:V_VLSI_D 3 "register_operand" " 0, 0"))
5519 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr"))
5520 (match_dup 3)))]
5521 "TARGET_VECTOR && !TARGET_64BIT"
5522 "@
5523 vmadd.vx\t%0,%z2,%4%p1
5524 vmadd.vx\t%0,%z2,%4%p1"
5525 [(set_attr "type" "vimuladd")
5526 (set_attr "mode" "<MODE>")
5527 (set_attr "merge_op_idx" "3")
5528 (set_attr "vl_op_idx" "5")
5529 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5530 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5531 (set (attr "avl_type_idx") (const_int 8))])
5533 (define_insn "*pred_macc<mode>_extended_scalar"
5534 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd, vr")
5535 (if_then_else:V_VLSI_D
5536 (unspec:<VM>
5537 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
5538 (match_operand 5 "vector_length_operand" "rvl,rvl")
5539 (match_operand 6 "const_int_operand" " i, i")
5540 (match_operand 7 "const_int_operand" " i, i")
5541 (match_operand 8 "const_int_operand" " i, i")
5542 (reg:SI VL_REGNUM)
5543 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5544 (plus:V_VLSI_D
5545 (mult:V_VLSI_D
5546 (vec_duplicate:V_VLSI_D
5547 (sign_extend:<VEL>
5548 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
5549 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr"))
5550 (match_operand:V_VLSI_D 4 "register_operand" " 0, 0"))
5551 (match_dup 4)))]
5552 "TARGET_VECTOR && !TARGET_64BIT"
5553 "@
5554 vmacc.vx\t%0,%z2,%3%p1
5555 vmacc.vx\t%0,%z2,%3%p1"
5556 [(set_attr "type" "vimuladd")
5557 (set_attr "mode" "<MODE>")
5558 (set_attr "merge_op_idx" "4")
5559 (set_attr "vl_op_idx" "5")
5560 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5561 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5562 (set (attr "avl_type_idx") (const_int 8))])
5564 (define_expand "@pred_minus_mul<mode>"
5565 [(set (match_operand:V_VLSI 0 "register_operand")
5566 (if_then_else:V_VLSI
5567 (unspec:<VM>
5568 [(match_operand:<VM> 1 "vector_mask_operand")
5569 (match_operand 6 "vector_length_operand")
5570 (match_operand 7 "const_int_operand")
5571 (match_operand 8 "const_int_operand")
5572 (match_operand 9 "const_int_operand")
5573 (reg:SI VL_REGNUM)
5574 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5575 (minus:V_VLSI
5576 (match_operand:V_VLSI 4 "register_operand")
5577 (mult:V_VLSI
5578 (match_operand:V_VLSI 2 "register_operand")
5579 (match_operand:V_VLSI 3 "register_operand")))
5580 (match_operand:V_VLSI 5 "vector_merge_operand")))]
5581 "TARGET_VECTOR"
5582 {
5583 riscv_vector::prepare_ternary_operands (operands);
5584 })
5586 (define_insn "*pred_minus_mul<mode>_undef"
5587 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr")
5588 (if_then_else:V_VLSI
5589 (unspec:<VM>
5590 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
5591 (match_operand 6 "vector_length_operand" "rvl,rvl,rvl,rvl")
5592 (match_operand 7 "const_int_operand" " i, i, i, i")
5593 (match_operand 8 "const_int_operand" " i, i, i, i")
5594 (match_operand 9 "const_int_operand" " i, i, i, i")
5595 (reg:SI VL_REGNUM)
5596 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5597 (minus:V_VLSI
5598 (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, 0")
5599 (mult:V_VLSI
5600 (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr")
5601 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")))
5602 (match_operand:V_VLSI 2 "vector_undef_operand")))]
5603 "TARGET_VECTOR"
5604 "@
5605 vnmsub.vv\t%0,%4,%5%p1
5606 vnmsac.vv\t%0,%3,%4%p1
5607 vnmsub.vv\t%0,%4,%5%p1
5608 vnmsac.vv\t%0,%3,%4%p1"
5609 [(set_attr "type" "vimuladd")
5610 (set_attr "mode" "<MODE>")])
5612 (define_insn "*pred_nmsub<mode>"
5613 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr")
5614 (if_then_else:V_VLSI
5615 (unspec:<VM>
5616 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
5617 (match_operand 5 "vector_length_operand" "rvl,rvl")
5618 (match_operand 6 "const_int_operand" " i, i")
5619 (match_operand 7 "const_int_operand" " i, i")
5620 (match_operand 8 "const_int_operand" " i, i")
5621 (reg:SI VL_REGNUM)
5622 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5623 (minus:V_VLSI
5624 (match_operand:V_VLSI 4 "register_operand" " vr, vr")
5625 (mult:V_VLSI
5626 (match_operand:V_VLSI 2 "register_operand" " 0, 0")
5627 (match_operand:V_VLSI 3 "register_operand" " vr, vr")))
5628 (match_dup 2)))]
5629 "TARGET_VECTOR"
5630 "@
5631 vnmsub.vv\t%0,%3,%4%p1
5632 vnmsub.vv\t%0,%3,%4%p1"
5633 [(set_attr "type" "vimuladd")
5634 (set_attr "mode" "<MODE>")
5635 (set_attr "merge_op_idx" "2")
5636 (set_attr "vl_op_idx" "5")
5637 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5638 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5639 (set (attr "avl_type_idx") (const_int 8))])
5641 (define_insn "*pred_nmsac<mode>"
5642 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr")
5643 (if_then_else:V_VLSI
5644 (unspec:<VM>
5645 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
5646 (match_operand 5 "vector_length_operand" "rvl,rvl")
5647 (match_operand 6 "const_int_operand" " i, i")
5648 (match_operand 7 "const_int_operand" " i, i")
5649 (match_operand 8 "const_int_operand" " i, i")
5650 (reg:SI VL_REGNUM)
5651 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5652 (minus:V_VLSI
5653 (match_operand:V_VLSI 4 "register_operand" " 0, 0")
5654 (mult:V_VLSI
5655 (match_operand:V_VLSI 2 "register_operand" " vr, vr")
5656 (match_operand:V_VLSI 3 "register_operand" " vr, vr")))
5657 (match_dup 4)))]
5658 "TARGET_VECTOR"
5659 "@
5660 vnmsac.vv\t%0,%2,%3%p1
5661 vnmsac.vv\t%0,%2,%3%p1"
5662 [(set_attr "type" "vimuladd")
5663 (set_attr "mode" "<MODE>")
5664 (set_attr "merge_op_idx" "4")
5665 (set_attr "vl_op_idx" "5")
5666 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5667 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5668 (set (attr "avl_type_idx") (const_int 8))])
5670 (define_expand "@pred_minus_mul<mode>_scalar"
5671 [(set (match_operand:V_VLSI_QHS 0 "register_operand")
5672 (if_then_else:V_VLSI_QHS
5673 (unspec:<VM>
5674 [(match_operand:<VM> 1 "vector_mask_operand")
5675 (match_operand 6 "vector_length_operand")
5676 (match_operand 7 "const_int_operand")
5677 (match_operand 8 "const_int_operand")
5678 (match_operand 9 "const_int_operand")
5679 (reg:SI VL_REGNUM)
5680 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5681 (minus:V_VLSI_QHS
5682 (match_operand:V_VLSI_QHS 4 "register_operand")
5683 (mult:V_VLSI_QHS
5684 (vec_duplicate:V_VLSI_QHS
5685 (match_operand:<VEL> 2 "register_operand"))
5686 (match_operand:V_VLSI_QHS 3 "register_operand")))
5687 (match_operand:V_VLSI_QHS 5 "register_operand")))]
5688 "TARGET_VECTOR"
5689 {})
5691 (define_insn "*pred_nmsub<mode>_scalar"
5692 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr")
5693 (if_then_else:V_VLSI
5694 (unspec:<VM>
5695 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
5696 (match_operand 5 "vector_length_operand" "rvl,rvl")
5697 (match_operand 6 "const_int_operand" " i, i")
5698 (match_operand 7 "const_int_operand" " i, i")
5699 (match_operand 8 "const_int_operand" " i, i")
5700 (reg:SI VL_REGNUM)
5701 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5702 (minus:V_VLSI
5703 (match_operand:V_VLSI 4 "register_operand" " vr, vr")
5704 (mult:V_VLSI
5705 (vec_duplicate:V_VLSI
5706 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
5707 (match_operand:V_VLSI 3 "register_operand" " 0, 0")))
5708 (match_dup 3)))]
5709 "TARGET_VECTOR"
5710 "@
5711 vnmsub.vx\t%0,%z2,%4%p1
5712 vnmsub.vx\t%0,%z2,%4%p1"
5713 [(set_attr "type" "vimuladd")
5714 (set_attr "mode" "<MODE>")
5715 (set_attr "merge_op_idx" "3")
5716 (set_attr "vl_op_idx" "5")
5717 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5718 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5719 (set (attr "avl_type_idx") (const_int 8))])
5721 (define_insn "*pred_nmsac<mode>_scalar"
5722 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr")
5723 (if_then_else:V_VLSI
5724 (unspec:<VM>
5725 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
5726 (match_operand 5 "vector_length_operand" "rvl,rvl")
5727 (match_operand 6 "const_int_operand" " i, i")
5728 (match_operand 7 "const_int_operand" " i, i")
5729 (match_operand 8 "const_int_operand" " i, i")
5730 (reg:SI VL_REGNUM)
5731 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5732 (minus:V_VLSI
5733 (match_operand:V_VLSI 4 "register_operand" " 0, 0")
5734 (mult:V_VLSI
5735 (vec_duplicate:V_VLSI
5736 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
5737 (match_operand:V_VLSI 3 "register_operand" " vr, vr")))
5738 (match_dup 4)))]
5739 "TARGET_VECTOR"
5740 "@
5741 vnmsac.vx\t%0,%z2,%3%p1
5742 vnmsac.vx\t%0,%z2,%3%p1"
5743 [(set_attr "type" "vimuladd")
5744 (set_attr "mode" "<MODE>")
5745 (set_attr "merge_op_idx" "4")
5746 (set_attr "vl_op_idx" "5")
5747 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5748 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5749 (set (attr "avl_type_idx") (const_int 8))])
5751 (define_expand "@pred_minus_mul<mode>_scalar"
5752 [(set (match_operand:V_VLSI_D 0 "register_operand")
5753 (if_then_else:V_VLSI_D
5754 (unspec:<VM>
5755 [(match_operand:<VM> 1 "vector_mask_operand")
5756 (match_operand 6 "vector_length_operand")
5757 (match_operand 7 "const_int_operand")
5758 (match_operand 8 "const_int_operand")
5759 (match_operand 9 "const_int_operand")
5760 (reg:SI VL_REGNUM)
5761 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5762 (minus:V_VLSI_D
5763 (match_operand:V_VLSI_D 4 "register_operand")
5764 (mult:V_VLSI_D
5765 (vec_duplicate:V_VLSI_D
5766 (match_operand:<VEL> 2 "reg_or_int_operand"))
5767 (match_operand:V_VLSI_D 3 "register_operand")))
5768 (match_operand:V_VLSI_D 5 "register_operand")))]
5769 "TARGET_VECTOR"
5770 {
5771 if (riscv_vector::sew64_scalar_helper (
5772 operands,
5773 /* scalar op */&operands[2],
5774 /* vl */operands[6],
5775 <MODE>mode,
5776 false,
5777 [] (rtx *operands, rtx broadcast_scalar) {
5778 emit_insn (gen_pred_minus_mul<mode> (operands[0], operands[1],
5779 broadcast_scalar, operands[3], operands[4], operands[5],
5780 operands[6], operands[7], operands[8], operands[9]));
5781 },
5782 (riscv_vector::avl_type) INTVAL (operands[9])))
5783 DONE;
5784 })
5786 (define_insn "*pred_nmsub<mode>_extended_scalar"
5787 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd, vr")
5788 (if_then_else:V_VLSI_D
5789 (unspec:<VM>
5790 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
5791 (match_operand 5 "vector_length_operand" "rvl,rvl")
5792 (match_operand 6 "const_int_operand" " i, i")
5793 (match_operand 7 "const_int_operand" " i, i")
5794 (match_operand 8 "const_int_operand" " i, i")
5795 (reg:SI VL_REGNUM)
5796 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5797 (minus:V_VLSI_D
5798 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr")
5799 (mult:V_VLSI_D
5800 (vec_duplicate:V_VLSI_D
5801 (sign_extend:<VEL>
5802 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
5803 (match_operand:V_VLSI_D 3 "register_operand" " 0, 0")))
5804 (match_dup 3)))]
5805 "TARGET_VECTOR && !TARGET_64BIT"
5806 "@
5807 vnmsub.vx\t%0,%z2,%4%p1
5808 vnmsub.vx\t%0,%z2,%4%p1"
5809 [(set_attr "type" "vimuladd")
5810 (set_attr "mode" "<MODE>")
5811 (set_attr "merge_op_idx" "3")
5812 (set_attr "vl_op_idx" "5")
5813 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5814 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5815 (set (attr "avl_type_idx") (const_int 8))])
5817 (define_insn "*pred_nmsac<mode>_extended_scalar"
5818 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd, vr")
5819 (if_then_else:V_VLSI_D
5820 (unspec:<VM>
5821 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
5822 (match_operand 5 "vector_length_operand" "rvl,rvl")
5823 (match_operand 6 "const_int_operand" " i, i")
5824 (match_operand 7 "const_int_operand" " i, i")
5825 (match_operand 8 "const_int_operand" " i, i")
5826 (reg:SI VL_REGNUM)
5827 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5828 (minus:V_VLSI_D
5829 (match_operand:V_VLSI_D 4 "register_operand" " 0, 0")
5830 (mult:V_VLSI_D
5831 (vec_duplicate:V_VLSI_D
5832 (sign_extend:<VEL>
5833 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
5834 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr")))
5835 (match_dup 4)))]
5836 "TARGET_VECTOR && !TARGET_64BIT"
5837 "@
5838 vnmsac.vx\t%0,%z2,%3%p1
5839 vnmsac.vx\t%0,%z2,%3%p1"
5840 [(set_attr "type" "vimuladd")
5841 (set_attr "mode" "<MODE>")
5842 (set_attr "merge_op_idx" "4")
5843 (set_attr "vl_op_idx" "5")
5844 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5845 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5846 (set (attr "avl_type_idx") (const_int 8))])
5848 ;; -------------------------------------------------------------------------------
5849 ;; ---- Predicated widen integer ternary operations
5850 ;; -------------------------------------------------------------------------------
5851 ;; Includes:
5852 ;; - 11.14 Vector Widening Integer Multiply-Add Instructions
5853 ;; -------------------------------------------------------------------------------
5855 (define_insn "@pred_widen_mul_plus<su><mode>"
5856 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5857 (if_then_else:VWEXTI
5858 (unspec:<VM>
5859 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5860 (match_operand 5 "vector_length_operand" " rvl")
5861 (match_operand 6 "const_int_operand" " i")
5862 (match_operand 7 "const_int_operand" " i")
5863 (match_operand 8 "const_int_operand" " i")
5864 (reg:SI VL_REGNUM)
5865 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5866 (plus:VWEXTI
5867 (mult:VWEXTI
5868 (any_extend:VWEXTI
5869 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
5870 (any_extend:VWEXTI
5871 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5872 (match_operand:VWEXTI 2 "register_operand" " 0"))
5873 (match_dup 2)))]
5874 "TARGET_VECTOR"
5875 "vwmacc<u>.vv\t%0,%3,%4%p1"
5876 [(set_attr "type" "viwmuladd")
5877 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5879 (define_insn "@pred_widen_mul_plus<su><mode>_scalar"
5880 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5881 (if_then_else:VWEXTI
5882 (unspec:<VM>
5883 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5884 (match_operand 5 "vector_length_operand" " rvl")
5885 (match_operand 6 "const_int_operand" " i")
5886 (match_operand 7 "const_int_operand" " i")
5887 (match_operand 8 "const_int_operand" " i")
5888 (reg:SI VL_REGNUM)
5889 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5890 (plus:VWEXTI
5891 (mult:VWEXTI
5892 (any_extend:VWEXTI
5893 (vec_duplicate:<V_DOUBLE_TRUNC>
5894 (match_operand:<VSUBEL> 3 "register_operand" " r")))
5895 (any_extend:VWEXTI
5896 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5897 (match_operand:VWEXTI 2 "register_operand" " 0"))
5898 (match_dup 2)))]
5899 "TARGET_VECTOR"
5900 "vwmacc<u>.vx\t%0,%3,%4%p1"
5901 [(set_attr "type" "viwmuladd")
5902 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5904 (define_insn "@pred_widen_mul_plussu<mode>"
5905 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5906 (if_then_else:VWEXTI
5907 (unspec:<VM>
5908 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5909 (match_operand 5 "vector_length_operand" " rvl")
5910 (match_operand 6 "const_int_operand" " i")
5911 (match_operand 7 "const_int_operand" " i")
5912 (match_operand 8 "const_int_operand" " i")
5913 (reg:SI VL_REGNUM)
5914 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5915 (plus:VWEXTI
5916 (mult:VWEXTI
5917 (sign_extend:VWEXTI
5918 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
5919 (zero_extend:VWEXTI
5920 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5921 (match_operand:VWEXTI 2 "register_operand" " 0"))
5922 (match_dup 2)))]
5923 "TARGET_VECTOR"
5924 "vwmaccsu.vv\t%0,%3,%4%p1"
5925 [(set_attr "type" "viwmuladd")
5926 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5928 (define_insn "@pred_widen_mul_plussu<mode>_scalar"
5929 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5930 (if_then_else:VWEXTI
5931 (unspec:<VM>
5932 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5933 (match_operand 5 "vector_length_operand" " rvl")
5934 (match_operand 6 "const_int_operand" " i")
5935 (match_operand 7 "const_int_operand" " i")
5936 (match_operand 8 "const_int_operand" " i")
5937 (reg:SI VL_REGNUM)
5938 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5939 (plus:VWEXTI
5940 (mult:VWEXTI
5941 (sign_extend:VWEXTI
5942 (vec_duplicate:<V_DOUBLE_TRUNC>
5943 (match_operand:<VSUBEL> 3 "register_operand" " r")))
5944 (zero_extend:VWEXTI
5945 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5946 (match_operand:VWEXTI 2 "register_operand" " 0"))
5947 (match_dup 2)))]
5948 "TARGET_VECTOR"
5949 "vwmaccsu.vx\t%0,%3,%4%p1"
5950 [(set_attr "type" "viwmuladd")
5951 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5953 (define_insn "@pred_widen_mul_plusus<mode>_scalar"
5954 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5955 (if_then_else:VWEXTI
5956 (unspec:<VM>
5957 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5958 (match_operand 5 "vector_length_operand" " rvl")
5959 (match_operand 6 "const_int_operand" " i")
5960 (match_operand 7 "const_int_operand" " i")
5961 (match_operand 8 "const_int_operand" " i")
5962 (reg:SI VL_REGNUM)
5963 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5964 (plus:VWEXTI
5965 (mult:VWEXTI
5966 (zero_extend:VWEXTI
5967 (vec_duplicate:<V_DOUBLE_TRUNC>
5968 (match_operand:<VSUBEL> 3 "register_operand" " r")))
5969 (sign_extend:VWEXTI
5970 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5971 (match_operand:VWEXTI 2 "register_operand" " 0"))
5972 (match_dup 2)))]
5973 "TARGET_VECTOR"
5974 "vwmaccus.vx\t%0,%3,%4%p1"
5975 [(set_attr "type" "viwmuladd")
5976 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5978 ;; -------------------------------------------------------------------------------
5979 ;; ---- Predicated BOOL mask operations
5980 ;; -------------------------------------------------------------------------------
5981 ;; Includes:
5982 ;; - 15.1 Vector Mask-Register Logical Instructions
5983 ;; - 15.2 Vector count population in mask vcpop.m
5984 ;; - 15.3 vfirst find-first-set mask bit
5985 ;; - 15.4 vmsbf.m set-before-first mask bit
5986 ;; - 15.5 vmsif.m set-including-first mask bit
5987 ;; - 15.6 vmsof.m set-only-first mask bit
5988 ;; - 15.8 Vector Iota Instruction
5989 ;; - 15.9 Vector Element Index Instruction
5990 ;; -------------------------------------------------------------------------------
5992 ;; We keep this pattern same as pred_mov so that we can gain more optimizations.
5993 ;; For example, if we have vmxor.mm v1,v1,v1. It will be optimized as vmclr.m which
5994 ;; is generated by pred_mov.
5995 (define_insn "@pred_<optab><mode>"
5996 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
5997 (if_then_else:VB_VLS
5998 (unspec:VB_VLS
5999 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6000 (match_operand 5 "vector_length_operand" "rvl")
6001 (match_operand 6 "const_int_operand" " i")
6002 (reg:SI VL_REGNUM)
6003 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6004 (any_bitwise:VB_VLS
6005 (match_operand:VB_VLS 3 "register_operand" " vr")
6006 (match_operand:VB_VLS 4 "register_operand" " vr"))
6007 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6008 "TARGET_VECTOR"
6009 "vm<insn>.mm\t%0,%3,%4"
6010 [(set_attr "type" "vmalu")
6011 (set_attr "mode" "<MODE>")
6012 (set_attr "vl_op_idx" "5")
6013 (set (attr "avl_type_idx") (const_int 6))])
6015 (define_insn "@pred_n<optab><mode>"
6016 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
6017 (if_then_else:VB_VLS
6018 (unspec:VB_VLS
6019 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6020 (match_operand 5 "vector_length_operand" "rvl")
6021 (match_operand 6 "const_int_operand" " i")
6022 (reg:SI VL_REGNUM)
6023 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6024 (not:VB_VLS
6025 (any_bitwise:VB_VLS
6026 (match_operand:VB_VLS 3 "register_operand" " vr")
6027 (match_operand:VB_VLS 4 "register_operand" " vr")))
6028 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6029 "TARGET_VECTOR"
6030 "vm<ninsn>.mm\t%0,%3,%4"
6031 [(set_attr "type" "vmalu")
6032 (set_attr "mode" "<MODE>")
6033 (set_attr "vl_op_idx" "5")
6034 (set (attr "avl_type_idx") (const_int 6))])
6036 (define_insn "@pred_<optab>not<mode>"
6037 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
6038 (if_then_else:VB_VLS
6039 (unspec:VB_VLS
6040 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6041 (match_operand 5 "vector_length_operand" "rvl")
6042 (match_operand 6 "const_int_operand" " i")
6043 (reg:SI VL_REGNUM)
6044 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6045 (and_ior:VB_VLS
6046 (match_operand:VB_VLS 3 "register_operand" " vr")
6047 (not:VB_VLS
6048 (match_operand:VB_VLS 4 "register_operand" " vr")))
6049 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6050 "TARGET_VECTOR"
6051 "vm<insn>n.mm\t%0,%3,%4"
6052 [(set_attr "type" "vmalu")
6053 (set_attr "mode" "<MODE>")
6054 (set_attr "vl_op_idx" "5")
6055 (set (attr "avl_type_idx") (const_int 6))])
6057 (define_insn "@pred_not<mode>"
6058 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
6059 (if_then_else:VB_VLS
6060 (unspec:VB_VLS
6061 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6062 (match_operand 4 "vector_length_operand" "rvl")
6063 (match_operand 5 "const_int_operand" " i")
6064 (reg:SI VL_REGNUM)
6065 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6066 (not:VB_VLS
6067 (match_operand:VB_VLS 3 "register_operand" " vr"))
6068 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6069 "TARGET_VECTOR"
6070 "vmnot.m\t%0,%3"
6071 [(set_attr "type" "vmalu")
6072 (set_attr "mode" "<MODE>")
6073 (set_attr "vl_op_idx" "4")
6074 (set (attr "avl_type_idx") (const_int 5))])
6076 (define_insn "@pred_popcount<VB_VLS:mode><P:mode>"
6077 [(set (match_operand:P 0 "register_operand" "=r")
6078 (popcount:P
6079 (unspec:VB_VLS
6080 [(and:VB_VLS
6081 (match_operand:VB_VLS 1 "vector_mask_operand" "vmWc1")
6082 (match_operand:VB_VLS 2 "register_operand" " vr"))
6083 (match_operand 3 "vector_length_operand" " rvl")
6084 (match_operand 4 "const_int_operand" " i")
6085 (reg:SI VL_REGNUM)
6086 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))]
6087 "TARGET_VECTOR"
6088 "vcpop.m\t%0,%2%p1"
6089 [(set_attr "type" "vmpop")
6090 (set_attr "mode" "<VB_VLS:MODE>")])
6092 (define_insn "@pred_ffs<VB:mode><P:mode>"
6093 [(set (match_operand:P 0 "register_operand" "=r")
6094 (plus:P
6095 (ffs:P
6096 (unspec:VB
6097 [(and:VB
6098 (match_operand:VB 1 "vector_mask_operand" "vmWc1")
6099 (match_operand:VB 2 "register_operand" " vr"))
6100 (match_operand 3 "vector_length_operand" " rvl")
6101 (match_operand 4 "const_int_operand" " i")
6102 (reg:SI VL_REGNUM)
6103 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))
6104 (const_int -1)))]
6105 "TARGET_VECTOR"
6106 "vfirst.m\t%0,%2%p1"
6107 [(set_attr "type" "vmffs")
6108 (set_attr "mode" "<VB:MODE>")])
6110 (define_insn "@pred_<misc_op><mode>"
6111 [(set (match_operand:VB 0 "register_operand" "=&vr, &vr")
6112 (if_then_else:VB
6113 (unspec:VB
6114 [(match_operand:VB 1 "vector_mask_operand" "vmWc1,vmWc1")
6115 (match_operand 4 "vector_length_operand" " rvl, rvl")
6116 (match_operand 5 "const_int_operand" " i, i")
6117 (match_operand 6 "const_int_operand" " i, i")
6118 (reg:SI VL_REGNUM)
6119 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6120 (unspec:VB
6121 [(match_operand:VB 3 "register_operand" " vr, vr")] VMISC)
6122 (match_operand:VB 2 "vector_merge_operand" " vu, 0")))]
6123 "TARGET_VECTOR"
6124 "vm<misc_op>.m\t%0,%3%p1"
6125 [(set_attr "type" "vmsfs")
6126 (set_attr "mode" "<MODE>")])
6128 (define_insn "@pred_iota<mode>"
6129 [(set (match_operand:VI 0 "register_operand" "=&vr, &vr")
6130 (if_then_else:VI
6131 (unspec:<VM>
6132 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
6133 (match_operand 4 "vector_length_operand" " rvl, rvl")
6134 (match_operand 5 "const_int_operand" " i, i")
6135 (match_operand 6 "const_int_operand" " i, i")
6136 (match_operand 7 "const_int_operand" " i, i")
6137 (reg:SI VL_REGNUM)
6138 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6139 (unspec:VI
6140 [(match_operand:<VM> 3 "register_operand" " vr, vr")] UNSPEC_VIOTA)
6141 (match_operand:VI 2 "vector_merge_operand" " vu, 0")))]
6142 "TARGET_VECTOR"
6143 "viota.m\t%0,%3%p1"
6144 [(set_attr "type" "vmiota")
6145 (set_attr "mode" "<MODE>")])
6147 (define_insn "@pred_series<mode>"
6148 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr")
6149 (if_then_else:V_VLSI
6150 (unspec:<VM>
6151 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6152 (match_operand 3 "vector_length_operand" "rvl,rvl,rvl,rvl")
6153 (match_operand 4 "const_int_operand" " i, i, i, i")
6154 (match_operand 5 "const_int_operand" " i, i, i, i")
6155 (match_operand 6 "const_int_operand" " i, i, i, i")
6156 (reg:SI VL_REGNUM)
6157 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6158 (vec_series:V_VLSI (const_int 0) (const_int 1))
6159 (match_operand:V_VLSI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6160 "TARGET_VECTOR"
6161 "vid.v\t%0%p1"
6162 [(set_attr "type" "vmidx")
6163 (set_attr "mode" "<MODE>")])
6165 ;; -------------------------------------------------------------------------------
6166 ;; ---- Predicated floating-point binary operations
6167 ;; -------------------------------------------------------------------------------
6168 ;; Includes:
6169 ;; - 13.2 Vector Single-Width Floating-Point Add/Subtract Instructions
6170 ;; - 13.4 Vector Single-Width Floating-Point Multiply/Divide Instructions
6171 ;; - 13.11 Vector Floating-Point MIN/MAX Instructions
6172 ;; - 13.12 Vector Floating-Point Sign-Injection Instructions
6173 ;; -------------------------------------------------------------------------------
6175 (define_insn "@pred_<optab><mode>"
6176 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6177 (if_then_else:V_VLSF
6178 (unspec:<VM>
6179 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6180 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
6181 (match_operand 6 "const_int_operand" " i, i, i, i")
6182 (match_operand 7 "const_int_operand" " i, i, i, i")
6183 (match_operand 8 "const_int_operand" " i, i, i, i")
6184 (match_operand 9 "const_int_operand" " i, i, i, i")
6185 (reg:SI VL_REGNUM)
6186 (reg:SI VTYPE_REGNUM)
6187 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6188 (any_float_binop:V_VLSF
6189 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6190 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6191 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6192 "TARGET_VECTOR"
6193 "vf<insn>.vv\t%0,%3,%4%p1"
6194 [(set_attr "type" "<float_insn_type>")
6195 (set_attr "mode" "<MODE>")
6196 (set (attr "frm_mode")
6197 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6199 (define_insn "@pred_<optab><mode>"
6200 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6201 (if_then_else:V_VLSF
6202 (unspec:<VM>
6203 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6204 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
6205 (match_operand 6 "const_int_operand" " i, i, i, i")
6206 (match_operand 7 "const_int_operand" " i, i, i, i")
6207 (match_operand 8 "const_int_operand" " i, i, i, i")
6208 (reg:SI VL_REGNUM)
6209 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6210 (any_float_binop_nofrm:V_VLSF
6211 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6212 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6213 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6214 "TARGET_VECTOR"
6215 "vf<insn>.vv\t%0,%3,%4%p1"
6216 [(set_attr "type" "<float_insn_type>")
6217 (set_attr "mode" "<MODE>")])
6219 (define_insn "@pred_<ieee_fmaxmin_op><mode>"
6220 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6221 (if_then_else:V_VLSF
6222 (unspec:<VM>
6223 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6224 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
6225 (match_operand 6 "const_int_operand" " i, i, i, i")
6226 (match_operand 7 "const_int_operand" " i, i, i, i")
6227 (match_operand 8 "const_int_operand" " i, i, i, i")
6228 (reg:SI VL_REGNUM)
6229 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6230 (unspec:V_VLSF
6231 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6232 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")]
6233 UNSPEC_VFMAXMIN)
6234 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6235 "TARGET_VECTOR"
6236 "v<ieee_fmaxmin_op>.vv\t%0,%3,%4%p1"
6237 [(set_attr "type" "vfminmax")
6238 (set_attr "mode" "<MODE>")])
6240 (define_insn "@pred_<optab><mode>_scalar"
6241 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6242 (if_then_else:VF
6243 (unspec:<VM>
6244 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6245 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
6246 (match_operand 6 "const_int_operand" " i, i, i, i")
6247 (match_operand 7 "const_int_operand" " i, i, i, i")
6248 (match_operand 8 "const_int_operand" " i, i, i, i")
6249 (match_operand 9 "const_int_operand" " i, i, i, i")
6250 (reg:SI VL_REGNUM)
6251 (reg:SI VTYPE_REGNUM)
6252 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6253 (commutative_float_binop:VF
6254 (vec_duplicate:VF
6255 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6256 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6257 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6258 "TARGET_VECTOR"
6259 "vf<insn>.vf\t%0,%3,%4%p1"
6260 [(set_attr "type" "<float_insn_type>")
6261 (set_attr "mode" "<MODE>")
6262 (set (attr "frm_mode")
6263 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6265 (define_insn "@pred_<optab><mode>_scalar"
6266 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6267 (if_then_else:VF
6268 (unspec:<VM>
6269 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6270 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
6271 (match_operand 6 "const_int_operand" " i, i, i, i")
6272 (match_operand 7 "const_int_operand" " i, i, i, i")
6273 (match_operand 8 "const_int_operand" " i, i, i, i")
6274 (reg:SI VL_REGNUM)
6275 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6276 (commutative_float_binop_nofrm:VF
6277 (vec_duplicate:VF
6278 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6279 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6280 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6281 "TARGET_VECTOR"
6282 "vf<insn>.vf\t%0,%3,%4%p1"
6283 [(set_attr "type" "<float_insn_type>")
6284 (set_attr "mode" "<MODE>")])
6286 (define_insn "@pred_<ieee_fmaxmin_op><mode>_scalar"
6287 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6288 (if_then_else:VF
6289 (unspec:<VM>
6290 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6291 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
6292 (match_operand 6 "const_int_operand" " i, i, i, i")
6293 (match_operand 7 "const_int_operand" " i, i, i, i")
6294 (match_operand 8 "const_int_operand" " i, i, i, i")
6295 (reg:SI VL_REGNUM)
6296 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6297 (unspec:VF
6298 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6299 (vec_duplicate:VF
6300 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))]
6301 UNSPEC_VFMAXMIN)
6302 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6303 "TARGET_VECTOR"
6304 "v<ieee_fmaxmin_op>.vf\t%0,%3,%4%p1"
6305 [(set_attr "type" "vfminmax")
6306 (set_attr "mode" "<MODE>")])
6308 (define_insn "@pred_<optab><mode>_scalar"
6309 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6310 (if_then_else:VF
6311 (unspec:<VM>
6312 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6313 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
6314 (match_operand 6 "const_int_operand" " i, i, i, i")
6315 (match_operand 7 "const_int_operand" " i, i, i, i")
6316 (match_operand 8 "const_int_operand" " i, i, i, i")
6317 (match_operand 9 "const_int_operand" " i, i, i, i")
6318 (reg:SI VL_REGNUM)
6319 (reg:SI VTYPE_REGNUM)
6320 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6321 (non_commutative_float_binop:VF
6322 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6323 (vec_duplicate:VF
6324 (match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
6325 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6326 "TARGET_VECTOR"
6327 "vf<insn>.vf\t%0,%3,%4%p1"
6328 [(set_attr "type" "<float_insn_type>")
6329 (set_attr "mode" "<MODE>")
6330 (set (attr "frm_mode")
6331 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6333 (define_insn "@pred_<optab><mode>_reverse_scalar"
6334 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6335 (if_then_else:VF
6336 (unspec:<VM>
6337 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6338 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
6339 (match_operand 6 "const_int_operand" " i, i, i, i")
6340 (match_operand 7 "const_int_operand" " i, i, i, i")
6341 (match_operand 8 "const_int_operand" " i, i, i, i")
6342 (match_operand 9 "const_int_operand" " i, i, i, i")
6343 (reg:SI VL_REGNUM)
6344 (reg:SI VTYPE_REGNUM)
6345 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6346 (non_commutative_float_binop:VF
6347 (vec_duplicate:VF
6348 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6349 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6350 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6351 "TARGET_VECTOR"
6352 "vfr<insn>.vf\t%0,%3,%4%p1"
6353 [(set_attr "type" "<float_insn_type>")
6354 (set_attr "mode" "<MODE>")
6355 (set (attr "frm_mode")
6356 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6358 (define_insn "@pred_<copysign><mode>"
6359 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6360 (if_then_else:V_VLSF
6361 (unspec:<VM>
6362 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6363 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
6364 (match_operand 6 "const_int_operand" " i, i, i, i")
6365 (match_operand 7 "const_int_operand" " i, i, i, i")
6366 (match_operand 8 "const_int_operand" " i, i, i, i")
6367 (reg:SI VL_REGNUM)
6368 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6369 (unspec:V_VLSF
6370 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6371 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
6372 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6373 "TARGET_VECTOR"
6374 "vfsgnj<nx>.vv\t%0,%3,%4%p1"
6375 [(set_attr "type" "vfsgnj")
6376 (set_attr "mode" "<MODE>")])
6378 (define_insn "@pred_ncopysign<mode>"
6379 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6380 (if_then_else:VF
6381 (unspec:<VM>
6382 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6383 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
6384 (match_operand 6 "const_int_operand" " i, i, i, i")
6385 (match_operand 7 "const_int_operand" " i, i, i, i")
6386 (match_operand 8 "const_int_operand" " i, i, i, i")
6387 (reg:SI VL_REGNUM)
6388 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6389 (neg:VF
6390 (unspec:VF
6391 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6392 (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] UNSPEC_VCOPYSIGN))
6393 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6394 "TARGET_VECTOR"
6395 "vfsgnjn.vv\t%0,%3,%4%p1"
6396 [(set_attr "type" "vfsgnj")
6397 (set_attr "mode" "<MODE>")])
6399 (define_insn "@pred_<copysign><mode>_scalar"
6400 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6401 (if_then_else:V_VLSF
6402 (unspec:<VM>
6403 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6404 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
6405 (match_operand 6 "const_int_operand" " i, i, i, i")
6406 (match_operand 7 "const_int_operand" " i, i, i, i")
6407 (match_operand 8 "const_int_operand" " i, i, i, i")
6408 (reg:SI VL_REGNUM)
6409 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6410 (unspec:V_VLSF
6411 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6412 (vec_duplicate:V_VLSF
6413 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
6414 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6415 "TARGET_VECTOR"
6416 "vfsgnj<nx>.vf\t%0,%3,%4%p1"
6417 [(set_attr "type" "vfsgnj")
6418 (set_attr "mode" "<MODE>")])
6420 (define_insn "@pred_ncopysign<mode>_scalar"
6421 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6422 (if_then_else:VF
6423 (unspec:<VM>
6424 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6425 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
6426 (match_operand 6 "const_int_operand" " i, i, i, i")
6427 (match_operand 7 "const_int_operand" " i, i, i, i")
6428 (match_operand 8 "const_int_operand" " i, i, i, i")
6429 (reg:SI VL_REGNUM)
6430 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6431 (neg:VF
6432 (unspec:VF
6433 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6434 (vec_duplicate:VF
6435 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] UNSPEC_VCOPYSIGN))
6436 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6437 "TARGET_VECTOR"
6438 "vfsgnjn.vf\t%0,%3,%4%p1"
6439 [(set_attr "type" "vfsgnj")
6440 (set_attr "mode" "<MODE>")])
6442 ;; -------------------------------------------------------------------------------
6443 ;; ---- Predicated floating-point ternary operations
6444 ;; -------------------------------------------------------------------------------
6445 ;; Includes:
6446 ;; - 13.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions
6447 ;; -------------------------------------------------------------------------------
6449 (define_expand "@pred_mul_<optab><mode>"
6450 [(set (match_operand:V_VLSF 0 "register_operand")
6451 (if_then_else:V_VLSF
6452 (unspec:<VM>
6453 [(match_operand:<VM> 1 "vector_mask_operand")
6454 (match_operand 6 "vector_length_operand")
6455 (match_operand 7 "const_int_operand")
6456 (match_operand 8 "const_int_operand")
6457 (match_operand 9 "const_int_operand")
6458 (match_operand 10 "const_int_operand")
6459 (reg:SI VL_REGNUM)
6460 (reg:SI VTYPE_REGNUM)
6461 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6462 (plus_minus:V_VLSF
6463 (mult:V_VLSF
6464 (match_operand:V_VLSF 2 "register_operand")
6465 (match_operand:V_VLSF 3 "register_operand"))
6466 (match_operand:V_VLSF 4 "register_operand"))
6467 (match_operand:V_VLSF 5 "vector_merge_operand")))]
6468 "TARGET_VECTOR"
6469 {
6470 riscv_vector::prepare_ternary_operands (operands);
6471 })
6473 (define_insn "*pred_mul_<optab><mode>_undef"
6474 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd, vr, vr")
6475 (if_then_else:V_VLSF
6476 (unspec:<VM>
6477 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
6478 (match_operand 6 "vector_length_operand" "rvl,rvl,rvl,rvl")
6479 (match_operand 7 "const_int_operand" " i, i, i, i")
6480 (match_operand 8 "const_int_operand" " i, i, i, i")
6481 (match_operand 9 "const_int_operand" " i, i, i, i")
6482 (match_operand 10 "const_int_operand" " i, i, i, i")
6483 (reg:SI VL_REGNUM)
6484 (reg:SI VTYPE_REGNUM)
6485 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6486 (plus_minus:V_VLSF
6487 (mult:V_VLSF
6488 (match_operand:V_VLSF 3 "register_operand" " 0,vr, 0, vr")
6489 (match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr"))
6490 (match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, 0"))
6491 (match_operand:V_VLSF 2 "vector_undef_operand")))]
6492 "TARGET_VECTOR"
6493 "@
6494 vf<madd_msub>.vv\t%0,%4,%5%p1
6495 vf<macc_msac>.vv\t%0,%3,%4%p1
6496 vf<madd_msub>.vv\t%0,%4,%5%p1
6497 vf<macc_msac>.vv\t%0,%3,%4%p1"
6498 [(set_attr "type" "vfmuladd")
6499 (set_attr "mode" "<MODE>")
6500 (set (attr "frm_mode")
6501 (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
6503 (define_insn "*pred_<madd_msub><mode>"
6504 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr")
6505 (if_then_else:V_VLSF
6506 (unspec:<VM>
6507 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
6508 (match_operand 5 "vector_length_operand" "rvl,rvl")
6509 (match_operand 6 "const_int_operand" " i, i")
6510 (match_operand 7 "const_int_operand" " i, i")
6511 (match_operand 8 "const_int_operand" " i, i")
6512 (match_operand 9 "const_int_operand" " i, i")
6513 (reg:SI VL_REGNUM)
6514 (reg:SI VTYPE_REGNUM)
6515 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6516 (plus_minus:V_VLSF
6517 (mult:V_VLSF
6518 (match_operand:V_VLSF 2 "register_operand" " 0, 0")
6519 (match_operand:V_VLSF 3 "register_operand" " vr, vr"))
6520 (match_operand:V_VLSF 4 "register_operand" " vr, vr"))
6521 (match_dup 2)))]
6522 "TARGET_VECTOR"
6523 "@
6524 vf<madd_msub>.vv\t%0,%3,%4%p1
6525 vf<madd_msub>.vv\t%0,%3,%4%p1"
6526 [(set_attr "type" "vfmuladd")
6527 (set_attr "mode" "<MODE>")
6528 (set_attr "merge_op_idx" "2")
6529 (set_attr "vl_op_idx" "5")
6530 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6531 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6532 (set (attr "avl_type_idx") (const_int 8))
6533 (set (attr "frm_mode")
6534 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6536 (define_insn "*pred_<macc_msac><mode>"
6537 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr")
6538 (if_then_else:V_VLSF
6539 (unspec:<VM>
6540 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
6541 (match_operand 5 "vector_length_operand" "rvl,rvl")
6542 (match_operand 6 "const_int_operand" " i, i")
6543 (match_operand 7 "const_int_operand" " i, i")
6544 (match_operand 8 "const_int_operand" " i, i")
6545 (match_operand 9 "const_int_operand" " i, i")
6546 (reg:SI VL_REGNUM)
6547 (reg:SI VTYPE_REGNUM)
6548 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6549 (plus_minus:V_VLSF
6550 (mult:V_VLSF
6551 (match_operand:V_VLSF 2 "register_operand" " vr, vr")
6552 (match_operand:V_VLSF 3 "register_operand" " vr, vr"))
6553 (match_operand:V_VLSF 4 "register_operand" " 0, 0"))
6554 (match_dup 4)))]
6555 "TARGET_VECTOR"
6556 "@
6557 vf<macc_msac>.vv\t%0,%2,%3%p1
6558 vf<macc_msac>.vv\t%0,%2,%3%p1"
6559 [(set_attr "type" "vfmuladd")
6560 (set_attr "mode" "<MODE>")
6561 (set_attr "merge_op_idx" "4")
6562 (set_attr "vl_op_idx" "5")
6563 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6564 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6565 (set (attr "avl_type_idx") (const_int 8))
6566 (set (attr "frm_mode")
6567 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6569 (define_expand "@pred_mul_<optab><mode>_scalar"
6570 [(set (match_operand:V_VLSF 0 "register_operand")
6571 (if_then_else:V_VLSF
6572 (unspec:<VM>
6573 [(match_operand:<VM> 1 "vector_mask_operand")
6574 (match_operand 6 "vector_length_operand")
6575 (match_operand 7 "const_int_operand")
6576 (match_operand 8 "const_int_operand")
6577 (match_operand 9 "const_int_operand")
6578 (match_operand 10 "const_int_operand")
6579 (reg:SI VL_REGNUM)
6580 (reg:SI VTYPE_REGNUM)
6581 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6582 (plus_minus:V_VLSF
6583 (mult:V_VLSF
6584 (vec_duplicate:V_VLSF
6585 (match_operand:<VEL> 2 "register_operand"))
6586 (match_operand:V_VLSF 3 "register_operand"))
6587 (match_operand:V_VLSF 4 "register_operand"))
6588 (match_operand:V_VLSF 5 "register_operand")))]
6589 "TARGET_VECTOR"
6590 {})
6592 (define_insn "*pred_<madd_msub><mode>_scalar"
6593 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr")
6594 (if_then_else:V_VLSF
6595 (unspec:<VM>
6596 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
6597 (match_operand 5 "vector_length_operand" "rvl,rvl")
6598 (match_operand 6 "const_int_operand" " i, i")
6599 (match_operand 7 "const_int_operand" " i, i")
6600 (match_operand 8 "const_int_operand" " i, i")
6601 (match_operand 9 "const_int_operand" " i, i")
6602 (reg:SI VL_REGNUM)
6603 (reg:SI VTYPE_REGNUM)
6604 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6605 (plus_minus:V_VLSF
6606 (mult:V_VLSF
6607 (vec_duplicate:V_VLSF
6608 (match_operand:<VEL> 2 "register_operand" " f, f"))
6609 (match_operand:V_VLSF 3 "register_operand" " 0, 0"))
6610 (match_operand:V_VLSF 4 "register_operand" " vr, vr"))
6611 (match_dup 3)))]
6612 "TARGET_VECTOR"
6613 "@
6614 vf<madd_msub>.vf\t%0,%2,%4%p1
6615 vf<madd_msub>.vf\t%0,%2,%4%p1"
6616 [(set_attr "type" "vfmuladd")
6617 (set_attr "mode" "<MODE>")
6618 (set_attr "merge_op_idx" "3")
6619 (set_attr "vl_op_idx" "5")
6620 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6621 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6622 (set (attr "avl_type_idx") (const_int 8))
6623 (set (attr "frm_mode")
6624 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6626 (define_insn "*pred_<macc_msac><mode>_scalar"
6627 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr")
6628 (if_then_else:V_VLSF
6629 (unspec:<VM>
6630 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
6631 (match_operand 5 "vector_length_operand" "rvl,rvl")
6632 (match_operand 6 "const_int_operand" " i, i")
6633 (match_operand 7 "const_int_operand" " i, i")
6634 (match_operand 8 "const_int_operand" " i, i")
6635 (match_operand 9 "const_int_operand" " i, i")
6636 (reg:SI VL_REGNUM)
6637 (reg:SI VTYPE_REGNUM)
6638 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6639 (plus_minus:V_VLSF
6640 (mult:V_VLSF
6641 (vec_duplicate:V_VLSF
6642 (match_operand:<VEL> 2 "register_operand" " f, f"))
6643 (match_operand:V_VLSF 3 "register_operand" "vr, vr"))
6644 (match_operand:V_VLSF 4 "register_operand" " 0, 0"))
6645 (match_dup 4)))]
6646 "TARGET_VECTOR"
6647 "@
6648 vf<macc_msac>.vf\t%0,%2,%3%p1
6649 vf<macc_msac>.vf\t%0,%2,%3%p1"
6650 [(set_attr "type" "vfmuladd")
6651 (set_attr "mode" "<MODE>")
6652 (set_attr "merge_op_idx" "4")
6653 (set_attr "vl_op_idx" "5")
6654 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6655 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6656 (set (attr "avl_type_idx") (const_int 8))
6657 (set (attr "frm_mode")
6658 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6660 (define_expand "@pred_mul_neg_<optab><mode>"
6661 [(set (match_operand:V_VLSF 0 "register_operand")
6662 (if_then_else:V_VLSF
6663 (unspec:<VM>
6664 [(match_operand:<VM> 1 "vector_mask_operand")
6665 (match_operand 6 "vector_length_operand")
6666 (match_operand 7 "const_int_operand")
6667 (match_operand 8 "const_int_operand")
6668 (match_operand 9 "const_int_operand")
6669 (match_operand 10 "const_int_operand")
6670 (reg:SI VL_REGNUM)
6671 (reg:SI VTYPE_REGNUM)
6672 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6673 (plus_minus:V_VLSF
6674 (neg:V_VLSF
6675 (mult:V_VLSF
6676 (match_operand:V_VLSF 2 "register_operand")
6677 (match_operand:V_VLSF 3 "register_operand")))
6678 (match_operand:V_VLSF 4 "register_operand"))
6679 (match_operand:V_VLSF 5 "vector_merge_operand")))]
6680 "TARGET_VECTOR"
6681 {
6682 riscv_vector::prepare_ternary_operands (operands);
6683 })
6685 (define_insn "*pred_mul_neg_<optab><mode>_undef"
6686 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd,vr, vr")
6687 (if_then_else:V_VLSF
6688 (unspec:<VM>
6689 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
6690 (match_operand 6 "vector_length_operand" "rvl,rvl,rvl,rvl")
6691 (match_operand 7 "const_int_operand" " i, i, i, i")
6692 (match_operand 8 "const_int_operand" " i, i, i, i")
6693 (match_operand 9 "const_int_operand" " i, i, i, i")
6694 (match_operand 10 "const_int_operand" " i, i, i, i")
6695 (reg:SI VL_REGNUM)
6696 (reg:SI VTYPE_REGNUM)
6697 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6698 (plus_minus:V_VLSF
6699 (neg:V_VLSF
6700 (mult:V_VLSF
6701 (match_operand:V_VLSF 3 "register_operand" " 0,vr, 0, vr")
6702 (match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr")))
6703 (match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, 0"))
6704 (match_operand:V_VLSF 2 "vector_undef_operand")))]
6705 "TARGET_VECTOR"
6706 "@
6707 vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6708 vf<nmsac_nmacc>.vv\t%0,%3,%4%p1
6709 vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6710 vf<nmsac_nmacc>.vv\t%0,%3,%4%p1"
6711 [(set_attr "type" "vfmuladd")
6712 (set_attr "mode" "<MODE>")
6713 (set (attr "frm_mode")
6714 (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
6716 (define_insn "*pred_<nmsub_nmadd><mode>"
6717 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr")
6718 (if_then_else:V_VLSF
6719 (unspec:<VM>
6720 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
6721 (match_operand 5 "vector_length_operand" "rvl,rvl")
6722 (match_operand 6 "const_int_operand" " i, i")
6723 (match_operand 7 "const_int_operand" " i, i")
6724 (match_operand 8 "const_int_operand" " i, i")
6725 (match_operand 9 "const_int_operand" " i, i")
6726 (reg:SI VL_REGNUM)
6727 (reg:SI VTYPE_REGNUM)
6728 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6729 (plus_minus:V_VLSF
6730 (neg:V_VLSF
6731 (mult:V_VLSF
6732 (match_operand:V_VLSF 2 "register_operand" " 0, 0")
6733 (match_operand:V_VLSF 3 "register_operand" " vr, vr")))
6734 (match_operand:V_VLSF 4 "register_operand" " vr, vr"))
6735 (match_dup 2)))]
6736 "TARGET_VECTOR"
6737 "@
6738 vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
6739 vf<nmsub_nmadd>.vv\t%0,%3,%4%p1"
6740 [(set_attr "type" "vfmuladd")
6741 (set_attr "mode" "<MODE>")
6742 (set_attr "merge_op_idx" "2")
6743 (set_attr "vl_op_idx" "5")
6744 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6745 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6746 (set (attr "avl_type_idx") (const_int 8))
6747 (set (attr "frm_mode")
6748 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6750 (define_insn "*pred_<nmsac_nmacc><mode>"
6751 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr")
6752 (if_then_else:V_VLSF
6753 (unspec:<VM>
6754 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
6755 (match_operand 5 "vector_length_operand" "rvl,rvl")
6756 (match_operand 6 "const_int_operand" " i, i")
6757 (match_operand 7 "const_int_operand" " i, i")
6758 (match_operand 8 "const_int_operand" " i, i")
6759 (match_operand 9 "const_int_operand" " i, i")
6760 (reg:SI VL_REGNUM)
6761 (reg:SI VTYPE_REGNUM)
6762 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6763 (plus_minus:V_VLSF
6764 (neg:V_VLSF
6765 (mult:V_VLSF
6766 (match_operand:V_VLSF 2 "register_operand" " vr, vr")
6767 (match_operand:V_VLSF 3 "register_operand" " vr, vr")))
6768 (match_operand:V_VLSF 4 "register_operand" " 0, 0"))
6769 (match_dup 4)))]
6770 "TARGET_VECTOR"
6771 "@
6772 vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
6773 vf<nmsac_nmacc>.vv\t%0,%2,%3%p1"
6774 [(set_attr "type" "vfmuladd")
6775 (set_attr "mode" "<MODE>")
6776 (set_attr "merge_op_idx" "4")
6777 (set_attr "vl_op_idx" "5")
6778 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6779 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6780 (set (attr "avl_type_idx") (const_int 8))
6781 (set (attr "frm_mode")
6782 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6784 (define_expand "@pred_mul_neg_<optab><mode>_scalar"
6785 [(set (match_operand:V_VLSF 0 "register_operand")
6786 (if_then_else:V_VLSF
6787 (unspec:<VM>
6788 [(match_operand:<VM> 1 "vector_mask_operand")
6789 (match_operand 6 "vector_length_operand")
6790 (match_operand 7 "const_int_operand")
6791 (match_operand 8 "const_int_operand")
6792 (match_operand 9 "const_int_operand")
6793 (match_operand 10 "const_int_operand")
6794 (reg:SI VL_REGNUM)
6795 (reg:SI VTYPE_REGNUM)
6796 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6797 (plus_minus:V_VLSF
6798 (neg:V_VLSF
6799 (mult:V_VLSF
6800 (vec_duplicate:V_VLSF
6801 (match_operand:<VEL> 2 "register_operand"))
6802 (match_operand:V_VLSF 3 "register_operand")))
6803 (match_operand:V_VLSF 4 "register_operand"))
6804 (match_operand:V_VLSF 5 "register_operand")))]
6805 "TARGET_VECTOR"
6806 {})
6808 (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
6809 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr")
6810 (if_then_else:V_VLSF
6811 (unspec:<VM>
6812 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
6813 (match_operand 5 "vector_length_operand" "rvl,rvl")
6814 (match_operand 6 "const_int_operand" " i, i")
6815 (match_operand 7 "const_int_operand" " i, i")
6816 (match_operand 8 "const_int_operand" " i, i")
6817 (match_operand 9 "const_int_operand" " i, i")
6818 (reg:SI VL_REGNUM)
6819 (reg:SI VTYPE_REGNUM)
6820 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6821 (plus_minus:V_VLSF
6822 (neg:V_VLSF
6823 (mult:V_VLSF
6824 (vec_duplicate:V_VLSF
6825 (match_operand:<VEL> 2 "register_operand" " f, f"))
6826 (match_operand:V_VLSF 3 "register_operand" " 0, 0")))
6827 (match_operand:V_VLSF 4 "register_operand" " vr, vr"))
6828 (match_dup 3)))]
6829 "TARGET_VECTOR"
6830 "@
6831 vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
6832 vf<nmsub_nmadd>.vf\t%0,%2,%4%p1"
6833 [(set_attr "type" "vfmuladd")
6834 (set_attr "mode" "<MODE>")
6835 (set_attr "merge_op_idx" "3")
6836 (set_attr "vl_op_idx" "5")
6837 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6838 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6839 (set (attr "avl_type_idx") (const_int 8))
6840 (set (attr "frm_mode")
6841 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6843 (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
6844 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr")
6845 (if_then_else:V_VLSF
6846 (unspec:<VM>
6847 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
6848 (match_operand 5 "vector_length_operand" "rvl,rvl")
6849 (match_operand 6 "const_int_operand" " i, i")
6850 (match_operand 7 "const_int_operand" " i, i")
6851 (match_operand 8 "const_int_operand" " i, i")
6852 (match_operand 9 "const_int_operand" " i, i")
6853 (reg:SI VL_REGNUM)
6854 (reg:SI VTYPE_REGNUM)
6855 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6856 (plus_minus:V_VLSF
6857 (neg:V_VLSF
6858 (mult:V_VLSF
6859 (vec_duplicate:V_VLSF
6860 (match_operand:<VEL> 2 "register_operand" " f, f"))
6861 (match_operand:V_VLSF 3 "register_operand" " vr, vr")))
6862 (match_operand:V_VLSF 4 "register_operand" " 0, 0"))
6863 (match_dup 4)))]
6864 "TARGET_VECTOR"
6865 "@
6866 vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
6867 vf<nmsac_nmacc>.vf\t%0,%2,%3%p1"
6868 [(set_attr "type" "vfmuladd")
6869 (set_attr "mode" "<MODE>")
6870 (set_attr "merge_op_idx" "4")
6871 (set_attr "vl_op_idx" "5")
6872 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6873 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6874 (set (attr "avl_type_idx") (const_int 8))
6875 (set (attr "frm_mode")
6876 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6878 ;; -------------------------------------------------------------------------------
6879 ;; ---- Predicated floating-point unary operations
6880 ;; -------------------------------------------------------------------------------
6881 ;; Includes:
6882 ;; - 13.8 Vector Floating-Point Square-Root Instruction
6883 ;; - 13.9 Vector Floating-Point Reciprocal Square-Root Estimate Instruction
6884 ;; - 13.10 Vector Floating-Point Reciprocal Estimate Instruction
6885 ;; - 13.12 Vector Floating-Point Sign-Injection Instructions (vfneg.v/vfabs.v)
6886 ;; - 13.14 Vector Floating-Point Classify Instruction
6887 ;; -------------------------------------------------------------------------------
6889 (define_insn "@pred_<optab><mode>"
6890 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6891 (if_then_else:V_VLSF
6892 (unspec:<VM>
6893 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6894 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
6895 (match_operand 5 "const_int_operand" " i, i, i, i")
6896 (match_operand 6 "const_int_operand" " i, i, i, i")
6897 (match_operand 7 "const_int_operand" " i, i, i, i")
6898 (match_operand 8 "const_int_operand" " i, i, i, i")
6899 (reg:SI VL_REGNUM)
6900 (reg:SI VTYPE_REGNUM)
6901 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6902 (any_float_unop:V_VLSF
6903 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6904 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6905 "TARGET_VECTOR"
6906 "vf<insn>.v\t%0,%3%p1"
6907 [(set_attr "type" "<float_insn_type>")
6908 (set_attr "mode" "<MODE>")
6909 (set_attr "vl_op_idx" "4")
6910 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
6911 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
6912 (set (attr "avl_type_idx") (const_int 7))
6913 (set (attr "frm_mode")
6914 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
6916 (define_insn "@pred_<optab><mode>"
6917 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6918 (if_then_else:V_VLSF
6919 (unspec:<VM>
6920 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6921 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
6922 (match_operand 5 "const_int_operand" " i, i, i, i")
6923 (match_operand 6 "const_int_operand" " i, i, i, i")
6924 (match_operand 7 "const_int_operand" " i, i, i, i")
6925 (reg:SI VL_REGNUM)
6926 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6927 (any_float_unop_nofrm:V_VLSF
6928 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6929 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6930 "TARGET_VECTOR"
6931 "vf<insn>.v\t%0,%3%p1"
6932 [(set_attr "type" "<float_insn_type>")
6933 (set_attr "mode" "<MODE>")
6934 (set_attr "vl_op_idx" "4")
6935 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
6936 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
6937 (set (attr "avl_type_idx") (const_int 7))])
6939 (define_insn "@pred_<misc_op><mode>"
6940 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6941 (if_then_else:VF
6942 (unspec:<VM>
6943 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6944 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
6945 (match_operand 5 "const_int_operand" " i, i, i, i")
6946 (match_operand 6 "const_int_operand" " i, i, i, i")
6947 (match_operand 7 "const_int_operand" " i, i, i, i")
6948 (reg:SI VL_REGNUM)
6949 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6950 (unspec:VF
6951 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
6952 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6953 "TARGET_VECTOR"
6954 "vf<misc_op>.v\t%0,%3%p1"
6955 [(set_attr "type" "<float_insn_type>")
6956 (set_attr "mode" "<MODE>")])
6958 (define_insn "@pred_<misc_frm_op><mode>"
6959 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6960 (if_then_else:VF
6961 (unspec:<VM>
6962 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6963 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
6964 (match_operand 5 "const_int_operand" " i, i, i, i")
6965 (match_operand 6 "const_int_operand" " i, i, i, i")
6966 (match_operand 7 "const_int_operand" " i, i, i, i")
6967 (match_operand 8 "const_int_operand" " i, i, i, i")
6968 (reg:SI VL_REGNUM)
6969 (reg:SI VTYPE_REGNUM)
6970 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6971 (unspec:VF
6972 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC_FRM)
6973 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6974 "TARGET_VECTOR"
6975 "vf<misc_frm_op>.v\t%0,%3%p1"
6976 [(set_attr "type" "<float_frm_insn_type>")
6977 (set_attr "mode" "<MODE>")
6978 (set (attr "frm_mode")
6979 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
6981 (define_insn "@pred_class<mode>"
6982 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
6983 (if_then_else:<VCONVERT>
6984 (unspec:<VM>
6985 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6986 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
6987 (match_operand 5 "const_int_operand" " i, i, i, i")
6988 (match_operand 6 "const_int_operand" " i, i, i, i")
6989 (match_operand 7 "const_int_operand" " i, i, i, i")
6990 (reg:SI VL_REGNUM)
6991 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6992 (unspec:<VCONVERT>
6993 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
6994 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6995 "TARGET_VECTOR"
6996 "vfclass.v\t%0,%3%p1"
6997 [(set_attr "type" "vfclass")
6998 (set_attr "mode" "<MODE>")])
7000 ;; -------------------------------------------------------------------------------
7001 ;; ---- Predicated floating-point widen binary operations
7002 ;; -------------------------------------------------------------------------------
7003 ;; Includes:
7004 ;; - 13.3 Vector Widening Floating-Point Add/Subtract Instructions
7005 ;; - 13.5 Vector Widening Floating-Point Multiply
7006 ;; -------------------------------------------------------------------------------
7008 ;; Vector Widening Add/Subtract/Multiply.
7009 (define_insn "@pred_dual_widen_<optab><mode>"
7010 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
7011 (if_then_else:VWEXTF
7012 (unspec:<VM>
7013 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7014 (match_operand 5 "vector_length_operand" " rvl, rvl")
7015 (match_operand 6 "const_int_operand" " i, i")
7016 (match_operand 7 "const_int_operand" " i, i")
7017 (match_operand 8 "const_int_operand" " i, i")
7018 (match_operand 9 "const_int_operand" " i, i")
7019 (reg:SI VL_REGNUM)
7020 (reg:SI VTYPE_REGNUM)
7021 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7022 (any_widen_binop:VWEXTF
7023 (float_extend:VWEXTF
7024 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
7025 (float_extend:VWEXTF
7026 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
7027 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7028 "TARGET_VECTOR"
7029 "vfw<insn>.vv\t%0,%3,%4%p1"
7030 [(set_attr "type" "vf<widen_binop_insn_type>")
7031 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7032 (set (attr "frm_mode")
7033 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7035 (define_insn "@pred_dual_widen_<optab><mode>_scalar"
7036 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
7037 (if_then_else:VWEXTF
7038 (unspec:<VM>
7039 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7040 (match_operand 5 "vector_length_operand" " rvl, rvl")
7041 (match_operand 6 "const_int_operand" " i, i")
7042 (match_operand 7 "const_int_operand" " i, i")
7043 (match_operand 8 "const_int_operand" " i, i")
7044 (match_operand 9 "const_int_operand" " i, i")
7045 (reg:SI VL_REGNUM)
7046 (reg:SI VTYPE_REGNUM)
7047 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7048 (any_widen_binop:VWEXTF
7049 (float_extend:VWEXTF
7050 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
7051 (float_extend:VWEXTF
7052 (vec_duplicate:<V_DOUBLE_TRUNC>
7053 (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
7054 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7055 "TARGET_VECTOR"
7056 "vfw<insn>.vf\t%0,%3,%4%p1"
7057 [(set_attr "type" "vf<widen_binop_insn_type>")
7058 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7059 (set (attr "frm_mode")
7060 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7062 (define_insn "@pred_single_widen_add<mode>"
7063 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
7064 (if_then_else:VWEXTF
7065 (unspec:<VM>
7066 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7067 (match_operand 5 "vector_length_operand" " rvl, rvl")
7068 (match_operand 6 "const_int_operand" " i, i")
7069 (match_operand 7 "const_int_operand" " i, i")
7070 (match_operand 8 "const_int_operand" " i, i")
7071 (match_operand 9 "const_int_operand" " i, i")
7072 (reg:SI VL_REGNUM)
7073 (reg:SI VTYPE_REGNUM)
7074 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7075 (plus:VWEXTF
7076 (float_extend:VWEXTF
7077 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr"))
7078 (match_operand:VWEXTF 3 "register_operand" " vr, vr"))
7079 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7080 "TARGET_VECTOR"
7081 "vfwadd.wv\t%0,%3,%4%p1"
7082 [(set_attr "type" "vfwalu")
7083 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7084 (set (attr "frm_mode")
7085 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7087 (define_insn "@pred_single_widen_sub<mode>"
7088 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
7089 (if_then_else:VWEXTF
7090 (unspec:<VM>
7091 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7092 (match_operand 5 "vector_length_operand" " rvl, rvl")
7093 (match_operand 6 "const_int_operand" " i, i")
7094 (match_operand 7 "const_int_operand" " i, i")
7095 (match_operand 8 "const_int_operand" " i, i")
7096 (match_operand 9 "const_int_operand" " i, i")
7097 (reg:SI VL_REGNUM)
7098 (reg:SI VTYPE_REGNUM)
7099 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7100 (minus:VWEXTF
7101 (match_operand:VWEXTF 3 "register_operand" " vr, vr")
7102 (float_extend:VWEXTF
7103 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
7104 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7105 "TARGET_VECTOR"
7106 "vfwsub.wv\t%0,%3,%4%p1"
7107 [(set_attr "type" "vfwalu")
7108 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7109 (set (attr "frm_mode")
7110 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7112 (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
7113 [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vd, vr, vr")
7114 (if_then_else:VWEXTF
7115 (unspec:<VM>
7116 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7117 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
7118 (match_operand 6 "const_int_operand" " i, i, i, i")
7119 (match_operand 7 "const_int_operand" " i, i, i, i")
7120 (match_operand 8 "const_int_operand" " i, i, i, i")
7121 (match_operand 9 "const_int_operand" " i, i, i, i")
7122 (reg:SI VL_REGNUM)
7123 (reg:SI VTYPE_REGNUM)
7124 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7125 (plus_minus:VWEXTF
7126 (match_operand:VWEXTF 3 "register_operand" " vr, vr, vr, vr")
7127 (float_extend:VWEXTF
7128 (vec_duplicate:<V_DOUBLE_TRUNC>
7129 (match_operand:<VSUBEL> 4 "register_operand" " f, f, f, f"))))
7130 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7131 "TARGET_VECTOR"
7132 "vfw<insn>.wf\t%0,%3,%4%p1"
7133 [(set_attr "type" "vf<widen_binop_insn_type>")
7134 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7135 (set (attr "frm_mode")
7136 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7138 ;; -------------------------------------------------------------------------------
7139 ;; ---- Predicated widen floating-point ternary operations
7140 ;; -------------------------------------------------------------------------------
7141 ;; Includes:
7142 ;; - 13.7 Vector Widening Floating-Point Fused Multiply-Add Instructions
7143 ;; -------------------------------------------------------------------------------
7145 (define_insn "@pred_widen_mul_<optab><mode>"
7146 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7147 (if_then_else:VWEXTF
7148 (unspec:<VM>
7149 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7150 (match_operand 5 "vector_length_operand" " rvl")
7151 (match_operand 6 "const_int_operand" " i")
7152 (match_operand 7 "const_int_operand" " i")
7153 (match_operand 8 "const_int_operand" " i")
7154 (match_operand 9 "const_int_operand" " i")
7155 (reg:SI VL_REGNUM)
7156 (reg:SI VTYPE_REGNUM)
7157 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7158 (plus_minus:VWEXTF
7159 (mult:VWEXTF
7160 (float_extend:VWEXTF
7161 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
7162 (float_extend:VWEXTF
7163 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
7164 (match_operand:VWEXTF 2 "register_operand" " 0"))
7165 (match_dup 2)))]
7166 "TARGET_VECTOR"
7167 "vfw<macc_msac>.vv\t%0,%3,%4%p1"
7168 [(set_attr "type" "vfwmuladd")
7169 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7170 (set (attr "frm_mode")
7171 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7173 (define_insn "@pred_widen_mul_<optab><mode>_scalar"
7174 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7175 (if_then_else:VWEXTF
7176 (unspec:<VM>
7177 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7178 (match_operand 5 "vector_length_operand" " rvl")
7179 (match_operand 6 "const_int_operand" " i")
7180 (match_operand 7 "const_int_operand" " i")
7181 (match_operand 8 "const_int_operand" " i")
7182 (match_operand 9 "const_int_operand" " i")
7183 (reg:SI VL_REGNUM)
7184 (reg:SI VTYPE_REGNUM)
7185 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7186 (plus_minus:VWEXTF
7187 (mult:VWEXTF
7188 (float_extend:VWEXTF
7189 (vec_duplicate:<V_DOUBLE_TRUNC>
7190 (match_operand:<VSUBEL> 3 "register_operand" " f")))
7191 (float_extend:VWEXTF
7192 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
7193 (match_operand:VWEXTF 2 "register_operand" " 0"))
7194 (match_dup 2)))]
7195 "TARGET_VECTOR"
7196 "vfw<macc_msac>.vf\t%0,%3,%4%p1"
7197 [(set_attr "type" "vfwmuladd")
7198 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7199 (set (attr "frm_mode")
7200 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7202 (define_insn "@pred_widen_mul_neg_<optab><mode>"
7203 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7204 (if_then_else:VWEXTF
7205 (unspec:<VM>
7206 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7207 (match_operand 5 "vector_length_operand" " rvl")
7208 (match_operand 6 "const_int_operand" " i")
7209 (match_operand 7 "const_int_operand" " i")
7210 (match_operand 8 "const_int_operand" " i")
7211 (match_operand 9 "const_int_operand" " i")
7212 (reg:SI VL_REGNUM)
7213 (reg:SI VTYPE_REGNUM)
7214 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7215 (plus_minus:VWEXTF
7216 (neg:VWEXTF
7217 (mult:VWEXTF
7218 (float_extend:VWEXTF
7219 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
7220 (float_extend:VWEXTF
7221 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
7222 (match_operand:VWEXTF 2 "register_operand" " 0"))
7223 (match_dup 2)))]
7224 "TARGET_VECTOR"
7225 "vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
7226 [(set_attr "type" "vfwmuladd")
7227 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7228 (set (attr "frm_mode")
7229 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7231 (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
7232 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7233 (if_then_else:VWEXTF
7234 (unspec:<VM>
7235 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7236 (match_operand 5 "vector_length_operand" " rvl")
7237 (match_operand 6 "const_int_operand" " i")
7238 (match_operand 7 "const_int_operand" " i")
7239 (match_operand 8 "const_int_operand" " i")
7240 (match_operand 9 "const_int_operand" " i")
7241 (reg:SI VL_REGNUM)
7242 (reg:SI VTYPE_REGNUM)
7243 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7244 (plus_minus:VWEXTF
7245 (neg:VWEXTF
7246 (mult:VWEXTF
7247 (float_extend:VWEXTF
7248 (vec_duplicate:<V_DOUBLE_TRUNC>
7249 (match_operand:<VSUBEL> 3 "register_operand" " f")))
7250 (float_extend:VWEXTF
7251 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
7252 (match_operand:VWEXTF 2 "register_operand" " 0"))
7253 (match_dup 2)))]
7254 "TARGET_VECTOR"
7255 "vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
7256 [(set_attr "type" "vfwmuladd")
7257 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7258 (set (attr "frm_mode")
7259 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7261 ;; -------------------------------------------------------------------------------
7262 ;; ---- Predicated floating-point comparison operations
7263 ;; -------------------------------------------------------------------------------
7264 ;; Includes:
7265 ;; - 13.13 Vector Floating-Point Compare Instructions
7266 ;; -------------------------------------------------------------------------------
7268 (define_expand "@pred_cmp<mode>"
7269 [(set (match_operand:<VM> 0 "register_operand")
7270 (if_then_else:<VM>
7271 (unspec:<VM>
7272 [(match_operand:<VM> 1 "vector_mask_operand")
7273 (match_operand 6 "vector_length_operand")
7274 (match_operand 7 "const_int_operand")
7275 (match_operand 8 "const_int_operand")
7276 (reg:SI VL_REGNUM)
7277 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7278 (match_operator:<VM> 3 "signed_order_operator"
7279 [(match_operand:V_VLSF 4 "register_operand")
7280 (match_operand:V_VLSF 5 "register_operand")])
7281 (match_operand:<VM> 2 "vector_merge_operand")))]
7282 "TARGET_VECTOR"
7283 {})
7285 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
7286 (define_insn "*pred_cmp<mode>"
7287 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
7288 (if_then_else:<VM>
7289 (unspec:<VM>
7290 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
7291 (match_operand 6 "vector_length_operand" " rvl, rvl, rvl, rvl")
7292 (match_operand 7 "const_int_operand" " i, i, i, i")
7293 (match_operand 8 "const_int_operand" " i, i, i, i")
7294 (reg:SI VL_REGNUM)
7295 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7296 (match_operator:<VM> 3 "signed_order_operator"
7297 [(match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")
7298 (match_operand:V_VLSF 5 "register_operand" " vr, vr, vr, vr")])
7299 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7300 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
7301 "vmf%B3.vv\t%0,%4,%5%p1"
7302 [(set_attr "type" "vfcmp")
7303 (set_attr "mode" "<MODE>")
7304 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
7306 (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
7307 [(set (match_operand:<VM> 0 "register_operand" "=vm")
7308 (if_then_else:<VM>
7309 (unspec:<VM>
7310 [(match_operand:<VM> 1 "register_operand" " 0")
7311 (match_operand 5 "vector_length_operand" "rvl")
7312 (match_operand 6 "const_int_operand" " i")
7313 (match_operand 7 "const_int_operand" " i")
7314 (reg:SI VL_REGNUM)
7315 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7316 (match_operator:<VM> 2 "signed_order_operator"
7317 [(match_operand:V_VLSF 3 "register_operand" " vr")
7318 (match_operand:V_VLSF 4 "register_operand" " vr")])
7319 (match_dup 1)))]
7320 "TARGET_VECTOR"
7321 "vmf%B2.vv\t%0,%3,%4,v0.t"
7322 [(set_attr "type" "vfcmp")
7323 (set_attr "mode" "<MODE>")
7324 (set_attr "merge_op_idx" "1")
7325 (set_attr "vl_op_idx" "5")
7326 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7327 (set (attr "avl_type_idx") (const_int 7))])
7329 ;; We use early-clobber for source LMUL > dest LMUL.
7330 (define_insn "*pred_cmp<mode>_narrow"
7331 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
7332 (if_then_else:<VM>
7333 (unspec:<VM>
7334 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
7335 (match_operand 6 "vector_length_operand" " rvl, rvl, rvl, rvl, rvl, rvl, rvl, rvl, rvl")
7336 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
7337 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
7338 (reg:SI VL_REGNUM)
7339 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7340 (match_operator:<VM> 3 "signed_order_operator"
7341 [(match_operand:V_VLSF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
7342 (match_operand:V_VLSF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
7343 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
7344 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
7345 "vmf%B3.vv\t%0,%4,%5%p1"
7346 [(set_attr "type" "vfcmp")
7347 (set_attr "mode" "<MODE>")
7348 (set_attr "spec_restriction" "none,thv,thv,thv,thv,thv,thv,none,none")])
7350 (define_expand "@pred_cmp<mode>_scalar"
7351 [(set (match_operand:<VM> 0 "register_operand")
7352 (if_then_else:<VM>
7353 (unspec:<VM>
7354 [(match_operand:<VM> 1 "vector_mask_operand")
7355 (match_operand 6 "vector_length_operand")
7356 (match_operand 7 "const_int_operand")
7357 (match_operand 8 "const_int_operand")
7358 (reg:SI VL_REGNUM)
7359 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7360 (match_operator:<VM> 3 "signed_order_operator"
7361 [(match_operand:V_VLSF 4 "register_operand")
7362 (vec_duplicate:V_VLSF
7363 (match_operand:<VEL> 5 "register_operand"))])
7364 (match_operand:<VM> 2 "vector_merge_operand")))]
7365 "TARGET_VECTOR"
7366 {})
7368 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
7369 [(set (match_operand:<VM> 0 "register_operand" "=vm")
7370 (if_then_else:<VM>
7371 (unspec:<VM>
7372 [(match_operand:<VM> 1 "register_operand" " 0")
7373 (match_operand 5 "vector_length_operand" "rvl")
7374 (match_operand 6 "const_int_operand" " i")
7375 (match_operand 7 "const_int_operand" " i")
7376 (reg:SI VL_REGNUM)
7377 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7378 (match_operator:<VM> 2 "signed_order_operator"
7379 [(match_operand:V_VLSF 3 "register_operand" " vr")
7380 (vec_duplicate:V_VLSF
7381 (match_operand:<VEL> 4 "register_operand" " f"))])
7382 (match_dup 1)))]
7383 "TARGET_VECTOR"
7384 "vmf%B2.vf\t%0,%3,%4,v0.t"
7385 [(set_attr "type" "vfcmp")
7386 (set_attr "mode" "<MODE>")
7387 (set_attr "merge_op_idx" "1")
7388 (set_attr "vl_op_idx" "5")
7389 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7390 (set (attr "avl_type_idx") (const_int 7))])
7392 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
7393 (define_insn "*pred_cmp<mode>_scalar"
7394 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
7395 (if_then_else:<VM>
7396 (unspec:<VM>
7397 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
7398 (match_operand 6 "vector_length_operand" " rvl, rvl, rvl, rvl")
7399 (match_operand 7 "const_int_operand" " i, i, i, i")
7400 (match_operand 8 "const_int_operand" " i, i, i, i")
7401 (reg:SI VL_REGNUM)
7402 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7403 (match_operator:<VM> 3 "signed_order_operator"
7404 [(match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")
7405 (vec_duplicate:V_VLSF
7406 (match_operand:<VEL> 5 "register_operand" " f, f, f, f"))])
7407 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7408 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
7409 "vmf%B3.vf\t%0,%4,%5%p1"
7410 [(set_attr "type" "vfcmp")
7411 (set_attr "mode" "<MODE>")
7412 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
7414 ;; We use early-clobber for source LMUL > dest LMUL.
7415 (define_insn "*pred_cmp<mode>_scalar_narrow"
7416 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
7417 (if_then_else:<VM>
7418 (unspec:<VM>
7419 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
7420 (match_operand 6 "vector_length_operand" " rvl, rvl, rvl, rvl, rvl")
7421 (match_operand 7 "const_int_operand" " i, i, i, i, i")
7422 (match_operand 8 "const_int_operand" " i, i, i, i, i")
7423 (reg:SI VL_REGNUM)
7424 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7425 (match_operator:<VM> 3 "signed_order_operator"
7426 [(match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")
7427 (vec_duplicate:V_VLSF
7428 (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
7429 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
7430 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
7431 "vmf%B3.vf\t%0,%4,%5%p1"
7432 [(set_attr "type" "vfcmp")
7433 (set_attr "mode" "<MODE>")
7434 (set_attr "spec_restriction" "none,thv,thv,none,none")])
7436 ;; -------------------------------------------------------------------------------
7437 ;; ---- Predicated floating-point merge
7438 ;; -------------------------------------------------------------------------------
7439 ;; Includes:
7440 ;; - 13.15 Vector Floating-Point Merge Instruction
7441 ;; -------------------------------------------------------------------------------
7443 (define_insn "@pred_merge<mode>_scalar"
7444 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd")
7445 (if_then_else:V_VLSF
7446 (unspec:<VM>
7447 [(match_operand 5 "vector_length_operand" "rvl,rvl")
7448 (match_operand 6 "const_int_operand" " i, i")
7449 (match_operand 7 "const_int_operand" " i, i")
7450 (reg:SI VL_REGNUM)
7451 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7452 (vec_merge:V_VLSF
7453 (vec_duplicate:V_VLSF
7454 (match_operand:<VEL> 3 "register_operand" " f, f"))
7455 (match_operand:V_VLSF 2 "register_operand" " vr,vr")
7456 (match_operand:<VM> 4 "register_operand" " vm,vm"))
7457 (match_operand:V_VLSF 1 "vector_merge_operand" " vu, 0")))]
7458 "TARGET_VECTOR"
7459 "vfmerge.vfm\t%0,%2,%3,%4"
7460 [(set_attr "type" "vfmerge")
7461 (set_attr "mode" "<MODE>")])
7463 ;; -------------------------------------------------------------------------------
7464 ;; ---- Predicated floating-point conversions
7465 ;; -------------------------------------------------------------------------------
7466 ;; Includes:
7467 ;; - 13.17 Single-Width Floating-Point/Integer Type-Convert Instructions
7468 ;; -------------------------------------------------------------------------------
7470 (define_insn "@pred_fcvt_x<v_su>_f<mode>"
7471 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
7472 (if_then_else:<VCONVERT>
7473 (unspec:<VM>
7474 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7475 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
7476 (match_operand 5 "const_int_operand" " i, i, i, i")
7477 (match_operand 6 "const_int_operand" " i, i, i, i")
7478 (match_operand 7 "const_int_operand" " i, i, i, i")
7479 (match_operand 8 "const_int_operand" " i, i, i, i")
7480 (reg:SI VL_REGNUM)
7481 (reg:SI VTYPE_REGNUM)
7482 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7483 (unspec:<VCONVERT>
7484 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
7485 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7486 "TARGET_VECTOR"
7487 "vfcvt.x<v_su>.f.v\t%0,%3%p1"
7488 [(set_attr "type" "vfcvtftoi")
7489 (set_attr "mode" "<MODE>")
7490 (set (attr "frm_mode")
7491 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7493 (define_insn "@pred_<fix_cvt><mode>"
7494 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
7495 (if_then_else:<VCONVERT>
7496 (unspec:<VM>
7497 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7498 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
7499 (match_operand 5 "const_int_operand" " i, i, i, i")
7500 (match_operand 6 "const_int_operand" " i, i, i, i")
7501 (match_operand 7 "const_int_operand" " i, i, i, i")
7502 (reg:SI VL_REGNUM)
7503 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7504 (any_fix:<VCONVERT>
7505 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
7506 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7507 "TARGET_VECTOR"
7508 "vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
7509 [(set_attr "type" "vfcvtftoi")
7510 (set_attr "mode" "<MODE>")])
7512 (define_insn "@pred_<float_cvt><mode>"
7513 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
7514 (if_then_else:V_VLSF
7515 (unspec:<VM>
7516 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7517 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
7518 (match_operand 5 "const_int_operand" " i, i, i, i")
7519 (match_operand 6 "const_int_operand" " i, i, i, i")
7520 (match_operand 7 "const_int_operand" " i, i, i, i")
7521 (match_operand 8 "const_int_operand" " i, i, i, i")
7522 (reg:SI VL_REGNUM)
7523 (reg:SI VTYPE_REGNUM)
7524 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7525 (any_float:V_VLSF
7526 (match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
7527 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7528 "TARGET_VECTOR"
7529 "vfcvt.f.x<u>.v\t%0,%3%p1"
7530 [(set_attr "type" "vfcvtitof")
7531 (set_attr "mode" "<MODE>")
7532 (set (attr "frm_mode")
7533 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7535 ;; -------------------------------------------------------------------------------
7536 ;; ---- Predicated floating-point widen conversions
7537 ;; -------------------------------------------------------------------------------
7538 ;; Includes:
7539 ;; - 13.18 Widening Floating-Point/Integer Type-Convert Instructions
7540 ;; -------------------------------------------------------------------------------
7542 (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
7543 [(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
7544 (if_then_else:VWCONVERTI
7545 (unspec:<VM>
7546 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7547 (match_operand 4 "vector_length_operand" " rvl, rvl")
7548 (match_operand 5 "const_int_operand" " i, i")
7549 (match_operand 6 "const_int_operand" " i, i")
7550 (match_operand 7 "const_int_operand" " i, i")
7551 (match_operand 8 "const_int_operand" " i, i")
7552 (reg:SI VL_REGNUM)
7553 (reg:SI VTYPE_REGNUM)
7554 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7555 (unspec:VWCONVERTI
7556 [(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")] VFCVTS)
7557 (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
7558 "TARGET_VECTOR"
7559 "vfwcvt.x<v_su>.f.v\t%0,%3%p1"
7560 [(set_attr "type" "vfwcvtftoi")
7561 (set_attr "mode" "<VNCONVERT>")
7562 (set (attr "frm_mode")
7563 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7565 (define_insn "@pred_widen_<fix_cvt><mode>"
7566 [(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
7567 (if_then_else:VWCONVERTI
7568 (unspec:<VM>
7569 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7570 (match_operand 4 "vector_length_operand" " rvl, rvl")
7571 (match_operand 5 "const_int_operand" " i, i")
7572 (match_operand 6 "const_int_operand" " i, i")
7573 (match_operand 7 "const_int_operand" " i, i")
7574 (reg:SI VL_REGNUM)
7575 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7576 (any_fix:VWCONVERTI
7577 (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
7578 (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
7579 "TARGET_VECTOR"
7580 "vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
7581 [(set_attr "type" "vfwcvtftoi")
7582 (set_attr "mode" "<VNCONVERT>")])
7584 (define_insn "@pred_widen_<float_cvt><mode>"
7585 [(set (match_operand:V_VLSF 0 "register_operand" "=&vr, &vr")
7586 (if_then_else:V_VLSF
7587 (unspec:<VM>
7588 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7589 (match_operand 4 "vector_length_operand" " rvl, rvl")
7590 (match_operand 5 "const_int_operand" " i, i")
7591 (match_operand 6 "const_int_operand" " i, i")
7592 (match_operand 7 "const_int_operand" " i, i")
7593 (reg:SI VL_REGNUM)
7594 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7595 (any_float:V_VLSF
7596 (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
7597 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0")))]
7598 "TARGET_VECTOR"
7599 "vfwcvt.f.x<u>.v\t%0,%3%p1"
7600 [(set_attr "type" "vfwcvtitof")
7601 (set_attr "mode" "<VNCONVERT>")])
7603 (define_insn "@pred_extend<mode>"
7604 [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand" "=&vr, &vr")
7605 (if_then_else:VWEXTF_ZVFHMIN
7606 (unspec:<VM>
7607 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7608 (match_operand 4 "vector_length_operand" " rvl, rvl")
7609 (match_operand 5 "const_int_operand" " i, i")
7610 (match_operand 6 "const_int_operand" " i, i")
7611 (match_operand 7 "const_int_operand" " i, i")
7612 (reg:SI VL_REGNUM)
7613 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7614 (float_extend:VWEXTF_ZVFHMIN
7615 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
7616 (match_operand:VWEXTF_ZVFHMIN 2 "vector_merge_operand" " vu, 0")))]
7617 "TARGET_VECTOR"
7618 "vfwcvt.f.f.v\t%0,%3%p1"
7619 [(set_attr "type" "vfwcvtftof")
7620 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
7622 ;; -------------------------------------------------------------------------------
7623 ;; ---- Predicated floating-point narrow conversions
7624 ;; -------------------------------------------------------------------------------
7625 ;; Includes:
7626 ;; - 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions
7627 ;; -------------------------------------------------------------------------------
7629 (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
7630 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7631 (if_then_else:<VNCONVERT>
7632 (unspec:<VM>
7633 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7634 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl, rvl, rvl")
7635 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7636 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7637 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7638 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7639 (reg:SI VL_REGNUM)
7640 (reg:SI VTYPE_REGNUM)
7641 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7642 (unspec:<VNCONVERT>
7643 [(match_operand:V_VLSF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
7644 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7645 "TARGET_VECTOR"
7646 "vfncvt.x<v_su>.f.w\t%0,%3%p1"
7647 [(set_attr "type" "vfncvtftoi")
7648 (set_attr "mode" "<VNCONVERT>")
7649 (set (attr "frm_mode")
7650 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
7651 (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
7653 (define_insn "@pred_narrow_<fix_cvt><mode>"
7654 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7655 (if_then_else:<VNCONVERT>
7656 (unspec:<VM>
7657 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7658 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl, rvl, rvl")
7659 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7660 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7661 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7662 (reg:SI VL_REGNUM)
7663 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7664 (any_fix:<VNCONVERT>
7665 (match_operand:V_VLSF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7666 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7667 "TARGET_VECTOR"
7668 "vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
7669 [(set_attr "type" "vfncvtftoi")
7670 (set_attr "mode" "<VNCONVERT>")])
7672 (define_insn "@pred_narrow_<float_cvt><mode>"
7673 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7674 (if_then_else:<VNCONVERT>
7675 (unspec:<VM>
7676 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7677 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl, rvl, rvl")
7678 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7679 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7680 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7681 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7682 (reg:SI VL_REGNUM)
7683 (reg:SI VTYPE_REGNUM)
7684 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7685 (any_float:<VNCONVERT>
7686 (match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7687 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7688 "TARGET_VECTOR"
7689 "vfncvt.f.x<u>.w\t%0,%3%p1"
7690 [(set_attr "type" "vfncvtitof")
7691 (set_attr "mode" "<VNCONVERT>")
7692 (set (attr "frm_mode")
7693 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
7694 (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
7696 (define_insn "@pred_trunc<mode>"
7697 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7698 (if_then_else:<V_DOUBLE_TRUNC>
7699 (unspec:<VM>
7700 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7701 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl, rvl, rvl")
7702 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7703 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7704 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7705 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7706 (reg:SI VL_REGNUM)
7707 (reg:SI VTYPE_REGNUM)
7708 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7709 (float_truncate:<V_DOUBLE_TRUNC>
7710 (match_operand:VWEXTF_ZVFHMIN 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7711 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7712 "TARGET_VECTOR"
7713 "vfncvt.f.f.w\t%0,%3%p1"
7714 [(set_attr "type" "vfncvtftof")
7715 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7716 (set (attr "frm_mode")
7717 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
7718 (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
7720 (define_insn "@pred_rod_trunc<mode>"
7721 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7722 (if_then_else:<V_DOUBLE_TRUNC>
7723 (unspec:<VM>
7724 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7725 (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl, rvl, rvl")
7726 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7727 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7728 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7729 (reg:SI VL_REGNUM)
7730 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7731 (unspec:<V_DOUBLE_TRUNC>
7732 [(float_truncate:<V_DOUBLE_TRUNC>
7733 (match_operand:VWEXTF_ZVFHMIN 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
7734 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7735 "TARGET_VECTOR"
7736 "vfncvt.rod.f.f.w\t%0,%3%p1"
7737 [(set_attr "type" "vfncvtftof")
7738 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
7740 ;; -------------------------------------------------------------------------------
7741 ;; ---- Predicated reduction operations
7742 ;; -------------------------------------------------------------------------------
7743 ;; Includes:
7744 ;; - 14.1 Vector Single-Width Integer Reduction Instructions
7745 ;; - 14.2 Vector Widening Integer Reduction Instructions
7746 ;; - 14.3 Vector Single-Width Floating-Point Reduction Instructions
7747 ;; - 14.4 Vector Widening Floating-Point Reduction Instructions
7748 ;; -------------------------------------------------------------------------------
7749 ;;
7750 ;; NOTE for VL0 safe variantreduction:
7751 ;; The VL0 safe variantis used by the auto vectorizer to generate vectorized code
7752 ;; only, because the auto vectorizer expect reduction should propgat the start
7753 ;; value to dest even VL=0, the only way is force vd=vs1 by constraint.
7755 ;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs)
7756 (define_insn "@pred_<reduc_op_pat_name><mode>"
7757 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
7758 (unspec:<V_LMUL1>
7759 [(unspec:<VM>
7760 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7761 (match_operand 5 "vector_length_operand" " rvl, rvl")
7762 (match_operand 6 "const_int_operand" " i, i")
7763 (match_operand 7 "const_int_operand" " i, i")
7764 (reg:SI VL_REGNUM)
7765 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7766 (unspec:<V_LMUL1> [
7767 (match_operand:V_VLSI 3 "register_operand" " vr, vr")
7768 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7769 ] ANY_REDUC)
7770 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7771 "TARGET_VECTOR"
7772 "v<reduc_op>.vs\t%0,%3,%4%p1"
7773 [(set_attr "type" "vired")
7774 (set_attr "mode" "<MODE>")])
7776 ;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs)
7777 ;; but for auto vectorizer (see "NOTE for VL0 safe variantreduction" for detail)
7778 (define_insn "@pred_<reduc_op_pat_name><mode>"
7779 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr")
7780 (unspec:<V_LMUL1>
7781 [(unspec:<VM>
7782 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7783 (match_operand 5 "vector_length_operand" " rvl")
7784 (match_operand 6 "const_int_operand" " i")
7785 (match_operand 7 "const_int_operand" " i")
7786 (reg:SI VL_REGNUM)
7787 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7788 (unspec:<V_LMUL1> [
7789 (match_operand:V_VLSI 3 "register_operand" " vr")
7790 (match_operand:<V_LMUL1> 4 "register_operand" " 0")
7791 ] ANY_REDUC_VL0_SAFE)
7792 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu")] UNSPEC_REDUC))]
7793 "TARGET_VECTOR"
7794 "v<reduc_op>.vs\t%0,%3,%4%p1"
7795 [(set_attr "type" "vired")
7796 (set_attr "mode" "<MODE>")])
7798 ;; Integer Widen Reduction Sum (vwredsum[u].vs)
7799 (define_insn "@pred_<reduc_op_pat_name><mode>"
7800 [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=vr, vr")
7801 (unspec:<V_EXT_LMUL1>
7802 [(unspec:<VM>
7803 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7804 (match_operand 5 "vector_length_operand" " rvl, rvl")
7805 (match_operand 6 "const_int_operand" " i, i")
7806 (match_operand 7 "const_int_operand" " i, i")
7807 (reg:SI VL_REGNUM)
7808 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7809 (unspec:<V_EXT_LMUL1> [
7810 (match_operand:VI_QHS 3 "register_operand" " vr, vr")
7811 (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
7812 ] ANY_WREDUC)
7813 (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7814 "TARGET_VECTOR"
7815 "v<reduc_op>.vs\t%0,%3,%4%p1"
7816 [(set_attr "type" "viwred")
7817 (set_attr "mode" "<MODE>")])
7819 ;; Integer Widen Reduction Sum (vwredsum[u].vs)
7820 ;; but for auto vectorizer (see "NOTE for VL0 safe variantreduction" for detail)
7821 (define_insn "@pred_<reduc_op_pat_name><mode>"
7822 [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=vr")
7823 (unspec:<V_EXT_LMUL1>
7824 [(unspec:<VM>
7825 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7826 (match_operand 5 "vector_length_operand" " rvl")
7827 (match_operand 6 "const_int_operand" " i")
7828 (match_operand 7 "const_int_operand" " i")
7829 (reg:SI VL_REGNUM)
7830 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7831 (unspec:<V_EXT_LMUL1> [
7832 (match_operand:VI_QHS 3 "register_operand" " vr")
7833 (match_operand:<V_EXT_LMUL1> 4 "register_operand" " 0")
7834 ] ANY_WREDUC_VL0_SAFE)
7835 (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu")] UNSPEC_REDUC))]
7836 "TARGET_VECTOR"
7837 "v<reduc_op>.vs\t%0,%3,%4%p1"
7838 [(set_attr "type" "viwred")
7839 (set_attr "mode" "<MODE>")])
7841 ;; Float Reduction (vfred(max|min).vs)
7842 (define_insn "@pred_<reduc_op_pat_name><mode>"
7843 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
7844 (unspec:<V_LMUL1>
7845 [(unspec:<VM>
7846 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7847 (match_operand 5 "vector_length_operand" " rvl, rvl")
7848 (match_operand 6 "const_int_operand" " i, i")
7849 (match_operand 7 "const_int_operand" " i, i")
7850 (reg:SI VL_REGNUM)
7851 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7852 (unspec:<V_LMUL1> [
7853 (match_operand:V_VLSF 3 "register_operand" " vr, vr")
7854 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7855 ] ANY_FREDUC)
7856 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7857 "TARGET_VECTOR"
7858 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7859 [(set_attr "type" "vfredu")
7860 (set_attr "mode" "<MODE>")])
7862 ;; Float Reduction (vfred(max|min).vs)
7863 ;; but for auto vectorizer (see "NOTE for VL0 safe variantreduction" for detail)
7864 (define_insn "@pred_<reduc_op_pat_name><mode>"
7865 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr")
7866 (unspec:<V_LMUL1>
7867 [(unspec:<VM>
7868 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7869 (match_operand 5 "vector_length_operand" " rvl")
7870 (match_operand 6 "const_int_operand" " i")
7871 (match_operand 7 "const_int_operand" " i")
7872 (reg:SI VL_REGNUM)
7873 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7874 (unspec:<V_LMUL1> [
7875 (match_operand:V_VLSF 3 "register_operand" " vr")
7876 (match_operand:<V_LMUL1> 4 "register_operand" " 0")
7877 ] ANY_FREDUC_VL0_SAFE)
7878 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu")] UNSPEC_REDUC))]
7879 "TARGET_VECTOR"
7880 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7881 [(set_attr "type" "vfredu")
7882 (set_attr "mode" "<MODE>")])
7884 ;; Float Reduction Sum (vfred[ou]sum.vs)
7885 (define_insn "@pred_<reduc_op_pat_name><mode>"
7886 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr,vr")
7887 (unspec:<V_LMUL1>
7888 [(unspec:<VM>
7889 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7890 (match_operand 5 "vector_length_operand" " rvl, rvl")
7891 (match_operand 6 "const_int_operand" " i, i")
7892 (match_operand 7 "const_int_operand" " i, i")
7893 (match_operand 8 "const_int_operand" " i, i")
7894 (reg:SI VL_REGNUM)
7895 (reg:SI VTYPE_REGNUM)
7896 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7897 (unspec:<V_LMUL1> [
7898 (match_operand:V_VLSF 3 "register_operand" " vr, vr")
7899 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7900 ] ANY_FREDUC_SUM)
7901 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7902 "TARGET_VECTOR"
7903 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7904 [(set_attr "type" "vfred<order>")
7905 (set_attr "mode" "<MODE>")
7906 (set (attr "frm_mode")
7907 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7909 ;; Float Reduction Sum (vfred[ou]sum.vs)
7910 ;; but for auto vectorizer (see "NOTE for VL0 safe variantreduction" for detail)
7911 (define_insn "@pred_<reduc_op_pat_name><mode>"
7912 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr")
7913 (unspec:<V_LMUL1>
7914 [(unspec:<VM>
7915 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7916 (match_operand 5 "vector_length_operand" " rvl")
7917 (match_operand 6 "const_int_operand" " i")
7918 (match_operand 7 "const_int_operand" " i")
7919 (match_operand 8 "const_int_operand" " i")
7920 (reg:SI VL_REGNUM)
7921 (reg:SI VTYPE_REGNUM)
7922 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7923 (unspec:<V_LMUL1> [
7924 (match_operand:V_VLSF 3 "register_operand" " vr")
7925 (match_operand:<V_LMUL1> 4 "register_operand" " 0")
7926 ] ANY_FREDUC_SUM_VL0_SAFE)
7927 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu")] UNSPEC_REDUC))]
7928 "TARGET_VECTOR"
7929 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7930 [(set_attr "type" "vfred<order>")
7931 (set_attr "mode" "<MODE>")
7932 (set (attr "frm_mode")
7933 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7935 ;; Float Widen Reduction Sum (vfwred[ou]sum.vs)
7936 (define_insn "@pred_<reduc_op_pat_name><mode>"
7937 [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=vr, vr")
7938 (unspec:<V_EXT_LMUL1>
7939 [(unspec:<VM>
7940 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7941 (match_operand 5 "vector_length_operand" " rvl, rvl")
7942 (match_operand 6 "const_int_operand" " i, i")
7943 (match_operand 7 "const_int_operand" " i, i")
7944 (match_operand 8 "const_int_operand" " i, i")
7945 (reg:SI VL_REGNUM)
7946 (reg:SI VTYPE_REGNUM)
7947 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7948 (unspec:<V_EXT_LMUL1> [
7949 (match_operand:VF_HS 3 "register_operand" " vr, vr")
7950 (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
7951 ] ANY_FWREDUC_SUM)
7952 (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7953 "TARGET_VECTOR"
7954 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7955 [(set_attr "type" "vfwred<order>")
7956 (set_attr "mode" "<MODE>")
7957 (set (attr "frm_mode")
7958 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7960 ;; Float Widen Reduction Sum (vfwred[ou]sum.vs)
7961 ;; but for auto vectorizer (see "NOTE for VL0 safe variantreduction" for detail)
7962 (define_insn "@pred_<reduc_op_pat_name><mode>"
7963 [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=vr")
7964 (unspec:<V_EXT_LMUL1>
7965 [(unspec:<VM>
7966 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7967 (match_operand 5 "vector_length_operand" " rvl")
7968 (match_operand 6 "const_int_operand" " i")
7969 (match_operand 7 "const_int_operand" " i")
7970 (match_operand 8 "const_int_operand" " i")
7971 (reg:SI VL_REGNUM)
7972 (reg:SI VTYPE_REGNUM)
7973 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7974 (unspec:<V_EXT_LMUL1> [
7975 (match_operand:VF_HS 3 "register_operand" " vr")
7976 (match_operand:<V_EXT_LMUL1> 4 "register_operand" " 0")
7977 ] ANY_FWREDUC_SUM_VL0_SAFE)
7978 (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu")] UNSPEC_REDUC))]
7979 "TARGET_VECTOR"
7980 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7981 [(set_attr "type" "vfwred<order>")
7982 (set_attr "mode" "<MODE>")
7983 (set (attr "frm_mode")
7984 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7986 ;; -------------------------------------------------------------------------------
7987 ;; ---- Predicated permutation operations
7988 ;; -------------------------------------------------------------------------------
7989 ;; Includes:
7990 ;; - 16.1 Integer Scalar Move Instructions
7991 ;; - 16.2 Floating-Point Scalar Move Instructions
7992 ;; - 16.3 Vector Slide Instructions
7993 ;; - 16.4 Vector Register Gather Instructions
7994 ;; - 16.5 Vector Compress Instruction
7995 ;; -------------------------------------------------------------------------------
7997 (define_expand "@pred_extract_first<mode>"
7998 [(set (match_operand:<VEL> 0 "register_operand")
7999 (unspec:<VEL>
8000 [(vec_select:<VEL>
8001 (match_operand:V_VLSI 1 "reg_or_mem_operand")
8002 (parallel [(const_int 0)]))
8003 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
8004 "TARGET_VECTOR"
8005 {
8006 if (MEM_P (operands[1]))
8007 {
8008 /* Combine vle.v + vmv.x.s ==> lw. */
8009 emit_move_insn (operands[0], gen_rtx_MEM (<VEL>mode, XEXP (operands[1], 0)));
8010 DONE;
8011 }
8012 })
8014 (define_insn_and_split "*pred_extract_first<mode>"
8015 [(set (match_operand:<VEL> 0 "register_operand" "=r")
8016 (unspec:<VEL>
8017 [(vec_select:<VEL>
8018 (match_operand:V_VLSI 1 "register_operand" "vr")
8019 (parallel [(const_int 0)]))
8020 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
8021 "TARGET_VECTOR"
8022 "vmv.x.s\t%0,%1"
8023 "known_gt (GET_MODE_BITSIZE (<VEL>mode), GET_MODE_BITSIZE (Pmode))"
8024 [(const_int 0)]
8025 {
8026 /* In rv32 system, we can't use vmv.x.s directly.
8027 Instead, we should generate this following code sequence:
8028 vsrl.vx v16,v8,a0
8029 vmv.x.s a1,v16
8030 vmv.x.s a0,v8 */
8031 rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
8032 rtx high_bits = gen_reg_rtx (<MODE>mode);
8033 emit_insn (gen_pred_scalar (LSHIFTRT, <MODE>mode, high_bits, CONSTM1_RTX (<VM>mode),
8034 RVV_VUNDEF (<MODE>mode), operands[1], nbits, /* vl */ const1_rtx,
8035 gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
8036 gen_int_mode (riscv_vector::MASK_ANY, Pmode),
8037 gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
8038 emit_insn (gen_pred_extract_first_trunc (<MODE>mode,
8039 gen_highpart (SImode, operands[0]), high_bits));
8040 emit_insn (gen_pred_extract_first_trunc (<MODE>mode,
8041 gen_lowpart (SImode, operands[0]), operands[1]));
8042 DONE;
8043 }
8044 [(set_attr "type" "vimovvx")
8045 (set_attr "mode" "<MODE>")])
8047 (define_insn "@pred_extract_first_trunc<mode>"
8048 [(set (match_operand:SI 0 "register_operand" "=r")
8049 (truncate:SI
8050 (unspec:<VEL>
8051 [(vec_select:<VEL>
8052 (match_operand:V_VLSI_D 1 "register_operand" "vr")
8053 (parallel [(const_int 0)]))
8054 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))]
8055 "TARGET_VECTOR"
8056 "vmv.x.s\t%0,%1"
8057 [(set_attr "type" "vimovvx")
8058 (set_attr "mode" "<MODE>")])
8060 (define_expand "@pred_extract_first<mode>"
8061 [(set (match_operand:<VEL> 0 "register_operand")
8062 (unspec:<VEL>
8063 [(vec_select:<VEL>
8064 (match_operand:V_VLSF 1 "reg_or_mem_operand")
8065 (parallel [(const_int 0)]))
8066 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
8067 "TARGET_VECTOR"
8068 {
8069 if (MEM_P (operands[1]))
8070 {
8071 /* Combine vle.v + vmv.f.s ==> flw. */
8072 emit_move_insn (operands[0], gen_rtx_MEM (<VEL>mode, XEXP (operands[1], 0)));
8073 DONE;
8074 }
8075 })
8077 (define_insn "*pred_extract_first<mode>"
8078 [(set (match_operand:<VEL> 0 "register_operand" "=f")
8079 (unspec:<VEL>
8080 [(vec_select:<VEL>
8081 (match_operand:V_VLSF 1 "register_operand" "vr")
8082 (parallel [(const_int 0)]))
8083 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
8084 "TARGET_VECTOR"
8085 "vfmv.f.s\t%0,%1"
8086 [(set_attr "type" "vfmovvf")
8087 (set_attr "mode" "<MODE>")])
8089 ;; vslide instructions
8090 (define_insn "@pred_slide<ud><mode>"
8091 [(set (match_operand:V_VLS 0 "register_operand" "<ud_constraint>")
8092 (unspec:V_VLS
8093 [(unspec:<VM>
8094 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8095 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
8096 (match_operand 6 "const_int_operand" " i, i, i, i")
8097 (match_operand 7 "const_int_operand" " i, i, i, i")
8098 (match_operand 8 "const_int_operand" " i, i, i, i")
8099 (reg:SI VL_REGNUM)
8100 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8101 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0, vu, 0")
8102 (match_operand:V_VLS 3 "register_operand" " vr, vr, vr, vr")
8103 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSLIDES))]
8104 "TARGET_VECTOR"
8105 "vslide<ud>.v%o4\t%0,%3,%4%p1"
8106 [(set_attr "type" "vslide<ud>")
8107 (set_attr "mode" "<MODE>")])
8109 ;; vslide1 instructions
8110 (define_insn "@pred_slide<ud><mode>"
8111 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "<ud_constraint>")
8112 (unspec:V_VLSI_QHS
8113 [(unspec:<VM>
8114 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8115 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
8116 (match_operand 6 "const_int_operand" " i, i, i, i")
8117 (match_operand 7 "const_int_operand" " i, i, i, i")
8118 (match_operand 8 "const_int_operand" " i, i, i, i")
8119 (reg:SI VL_REGNUM)
8120 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8121 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")
8122 (match_operand:V_VLSI_QHS 3 "register_operand" " vr, vr, vr, vr")
8123 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSLIDES1))]
8124 "TARGET_VECTOR"
8125 "vslide<ud>.vx\t%0,%3,%z4%p1"
8126 [(set_attr "type" "vislide<ud>")
8127 (set_attr "mode" "<MODE>")])
8129 (define_expand "@pred_slide<ud><mode>"
8130 [(set (match_operand:V_VLSI_D 0 "register_operand")
8131 (unspec:V_VLSI_D
8132 [(unspec:<VM>
8133 [(match_operand:<VM> 1 "vector_mask_operand")
8134 (match_operand 5 "reg_or_int_operand")
8135 (match_operand 6 "const_int_operand")
8136 (match_operand 7 "const_int_operand")
8137 (match_operand 8 "const_int_operand")
8138 (reg:SI VL_REGNUM)
8139 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8140 (match_operand:V_VLSI_D 2 "vector_merge_operand")
8141 (match_operand:V_VLSI_D 3 "register_operand")
8142 (match_operand:<VEL> 4 "reg_or_int_operand")] VSLIDES1))]
8143 "TARGET_VECTOR"
8144 {
8145 poly_uint64 nunits = GET_MODE_NUNITS (<MODE>mode) * 2;
8146 machine_mode vsimode = riscv_vector::get_vector_mode (SImode, nunits).require ();
8147 machine_mode vbimode = riscv_vector::get_vector_mode (BImode, nunits).require ();
8148 if (riscv_vector::slide1_sew64_helper (<UNSPEC>, <MODE>mode,
8149 vsimode, vbimode,
8150 operands))
8151 DONE;
8152 })
8154 (define_insn "*pred_slide<ud><mode>"
8155 [(set (match_operand:V_VLSI_D 0 "register_operand" "<ud_constraint>")
8156 (unspec:V_VLSI_D
8157 [(unspec:<VM>
8158 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8159 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
8160 (match_operand 6 "const_int_operand" " i, i, i, i")
8161 (match_operand 7 "const_int_operand" " i, i, i, i")
8162 (match_operand 8 "const_int_operand" " i, i, i, i")
8163 (reg:SI VL_REGNUM)
8164 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8165 (match_operand:V_VLSI_D 2 "vector_merge_operand" " vu, 0, vu, 0")
8166 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")
8167 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSLIDES1))]
8168 "TARGET_VECTOR"
8169 "vslide<ud>.vx\t%0,%3,%z4%p1"
8170 [(set_attr "type" "vislide<ud>")
8171 (set_attr "mode" "<MODE>")])
8173 (define_insn "*pred_slide<ud><mode>_extended"
8174 [(set (match_operand:V_VLSI_D 0 "register_operand" "<ud_constraint>")
8175 (unspec:V_VLSI_D
8176 [(unspec:<VM>
8177 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8178 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
8179 (match_operand 6 "const_int_operand" " i, i, i, i")
8180 (match_operand 7 "const_int_operand" " i, i, i, i")
8181 (match_operand 8 "const_int_operand" " i, i, i, i")
8182 (reg:SI VL_REGNUM)
8183 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8184 (match_operand:V_VLSI_D 2 "vector_merge_operand" " vu, 0, vu, 0")
8185 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")
8186 (sign_extend:<VEL>
8187 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSLIDES1))]
8188 "TARGET_VECTOR && !TARGET_64BIT"
8189 "vslide<ud>.vx\t%0,%3,%z4%p1"
8190 [(set_attr "type" "vislide<ud>")
8191 (set_attr "mode" "<MODE>")])
8193 ;; vfslide1 instructions
8194 (define_insn "@pred_slide<ud><mode>"
8195 [(set (match_operand:V_VLSF 0 "register_operand" "<ud_constraint>")
8196 (unspec:V_VLSF
8197 [(unspec:<VM>
8198 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8199 (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
8200 (match_operand 6 "const_int_operand" " i, i, i, i")
8201 (match_operand 7 "const_int_operand" " i, i, i, i")
8202 (match_operand 8 "const_int_operand" " i, i, i, i")
8203 (reg:SI VL_REGNUM)
8204 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8205 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")
8206 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
8207 (match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
8208 "TARGET_VECTOR"
8209 "vfslide<ud>.vf\t%0,%3,%4%p1"
8210 [(set_attr "type" "vfslide<ud>")
8211 (set_attr "mode" "<MODE>")])
8213 ;; vrgather
8214 (define_insn "@pred_gather<mode>"
8215 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8216 (if_then_else:V_VLS
8217 (unspec:<VM>
8218 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8219 (match_operand 5 "vector_length_operand" " rvl, rvl")
8220 (match_operand 6 "const_int_operand" " i, i")
8221 (match_operand 7 "const_int_operand" " i, i")
8222 (match_operand 8 "const_int_operand" " i, i")
8223 (reg:SI VL_REGNUM)
8224 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8225 (unspec:V_VLS
8226 [(match_operand:V_VLS 3 "register_operand" " vr, vr")
8227 (match_operand:<VINDEX> 4 "register_operand" " vr, vr")] UNSPEC_VRGATHER)
8228 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
8229 "TARGET_VECTOR"
8230 "vrgather.vv\t%0,%3,%4%p1"
8231 [(set_attr "type" "vgather")
8232 (set_attr "mode" "<MODE>")])
8234 (define_insn "@pred_gather<mode>_scalar"
8235 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8236 (if_then_else:V_VLS
8237 (unspec:<VM>
8238 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8239 (match_operand 5 "vector_length_operand" " rvl, rvl")
8240 (match_operand 6 "const_int_operand" " i, i")
8241 (match_operand 7 "const_int_operand" " i, i")
8242 (match_operand 8 "const_int_operand" " i, i")
8243 (reg:SI VL_REGNUM)
8244 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8245 (unspec:V_VLS
8246 [(match_operand:V_VLS 3 "register_operand" " vr, vr")
8247 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK")] UNSPEC_VRGATHER)
8248 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
8249 "TARGET_VECTOR"
8250 "vrgather.v%o4\t%0,%3,%4%p1"
8251 [(set_attr "type" "vgather")
8252 (set_attr "mode" "<MODE>")])
8254 ;; vrgatherei16
8255 (define_insn "@pred_gatherei16<mode>"
8256 [(set (match_operand:VEI16 0 "register_operand" "=&vr, &vr")
8257 (if_then_else:VEI16
8258 (unspec:<VM>
8259 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8260 (match_operand 5 "vector_length_operand" " rvl, rvl")
8261 (match_operand 6 "const_int_operand" " i, i")
8262 (match_operand 7 "const_int_operand" " i, i")
8263 (match_operand 8 "const_int_operand" " i, i")
8264 (reg:SI VL_REGNUM)
8265 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8266 (unspec:VEI16
8267 [(match_operand:VEI16 3 "register_operand" " vr, vr")
8268 (match_operand:<VINDEXEI16> 4 "register_operand" " vr, vr")] UNSPEC_VRGATHEREI16)
8269 (match_operand:VEI16 2 "vector_merge_operand" " vu, 0")))]
8270 "TARGET_VECTOR"
8271 "vrgatherei16.vv\t%0,%3,%4%p1"
8272 [(set_attr "type" "vgather")
8273 (set_attr "mode" "<MODE>")])
8275 ;; vcompress
8276 (define_insn "@pred_compress<mode>"
8277 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8278 (unspec:V_VLS
8279 [(unspec:<VM>
8280 [(match_operand:<VM> 3 "register_operand" " vm, vm")
8281 (match_operand 4 "vector_length_operand" " rvl, rvl")
8282 (match_operand 5 "const_int_operand" " i, i")
8283 (match_operand 6 "const_int_operand" " i, i")
8284 (reg:SI VL_REGNUM)
8285 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8286 (match_operand:V_VLS 2 "register_operand" " vr, vr")
8287 (match_operand:V_VLS 1 "vector_merge_operand" " vu, 0")] UNSPEC_VCOMPRESS))]
8288 "TARGET_VECTOR"
8289 "vcompress.vm\t%0,%2,%3"
8290 [(set_attr "type" "vcompress")
8291 (set_attr "mode" "<MODE>")])
8293 ;; -------------------------------------------------------------------------------
8294 ;; ---- Predicated Fault-Only-First loads
8295 ;; -------------------------------------------------------------------------------
8296 ;; Includes:
8297 ;; - 7.7. Unit-stride Fault-Only-First Loads
8298 ;; -------------------------------------------------------------------------------
8300 (define_insn "read_vlsi"
8301 [(set (match_operand:SI 0 "register_operand" "=r")
8302 (reg:SI VL_REGNUM))]
8303 "TARGET_VECTOR"
8304 "csrr\t%0,vl"
8305 [(set_attr "type" "rdvl")
8306 (set_attr "mode" "SI")])
8308 (define_insn "read_vldi_zero_extend"
8309 [(set (match_operand:DI 0 "register_operand" "=r")
8310 (zero_extend:DI (reg:SI VL_REGNUM)))]
8311 "TARGET_VECTOR && TARGET_64BIT"
8312 "csrr\t%0,vl"
8313 [(set_attr "type" "rdvl")
8314 (set_attr "mode" "DI")])
8316 (define_insn "@pred_fault_load<mode>"
8317 [(set (match_operand:V 0 "register_operand" "=vd, vd, vr, vr")
8318 (if_then_else:V
8319 (unspec:<VM>
8320 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, Wc1, Wc1")
8321 (match_operand 4 "vector_length_operand" " rvl, rvl, rvl, rvl")
8322 (match_operand 5 "const_int_operand" " i, i, i, i")
8323 (match_operand 6 "const_int_operand" " i, i, i, i")
8324 (match_operand 7 "const_int_operand" " i, i, i, i")
8325 (reg:SI VL_REGNUM)
8326 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8327 (unspec:V
8328 [(match_operand:V 3 "memory_operand" " m, m, m, m")] UNSPEC_VLEFF)
8329 (match_operand:V 2 "vector_merge_operand" " vu, 0, vu, 0")))
8330 (set (reg:SI VL_REGNUM)
8331 (unspec:SI
8332 [(if_then_else:V
8333 (unspec:<VM>
8334 [(match_dup 1) (match_dup 4) (match_dup 5)
8335 (match_dup 6) (match_dup 7)
8336 (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8337 (unspec:V [(match_dup 3)] UNSPEC_VLEFF)
8338 (match_dup 2))] UNSPEC_MODIFY_VL))]
8339 "TARGET_VECTOR"
8340 "vle<sew>ff.v\t%0,%3%p1"
8341 [(set_attr "type" "vldff")
8342 (set_attr "mode" "<MODE>")])
8345 ;; -------------------------------------------------------------------------------
8346 ;; ---- Predicated Segment loads/stores
8347 ;; -------------------------------------------------------------------------------
8348 ;; Includes:
8349 ;; - 7.8.1. Vector Unit-Stride Segment Loads and Stores
8350 ;; - 7.8.2. Vector Strided Segment Loads and Stores
8351 ;; - 7.8.3. Vector Indexed Segment Loads and Stores
8352 ;; -------------------------------------------------------------------------------
8354 (define_insn "@pred_unit_strided_load<mode>"
8355 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8356 (if_then_else:VT
8357 (unspec:<VM>
8358 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8359 (match_operand 4 "vector_length_operand" " rvl, rvl, rvl")
8360 (match_operand 5 "const_int_operand" " i, i, i")
8361 (match_operand 6 "const_int_operand" " i, i, i")
8362 (match_operand 7 "const_int_operand" " i, i, i")
8363 (reg:SI VL_REGNUM)
8364 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8365 (unspec:VT
8366 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8367 (mem:BLK (scratch))] UNSPEC_UNIT_STRIDED)
8368 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))]
8369 "TARGET_VECTOR"
8370 "vlseg<nf>e<sew>.v\t%0,(%z3)%p1"
8371 [(set_attr "type" "vlsegde")
8372 (set_attr "mode" "<MODE>")])
8374 (define_insn "@pred_unit_strided_store<mode>"
8375 [(set (mem:BLK (scratch))
8376 (unspec:BLK
8377 [(unspec:<VM>
8378 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8379 (match_operand 3 "vector_length_operand" " rvl")
8380 (match_operand 4 "const_int_operand" " i")
8381 (reg:SI VL_REGNUM)
8382 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8383 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8384 (match_operand:VT 2 "register_operand" " vr")
8385 (mem:BLK (scratch))] UNSPEC_UNIT_STRIDED))]
8386 "TARGET_VECTOR"
8387 "vsseg<nf>e<sew>.v\t%2,(%z1)%p0"
8388 [(set_attr "type" "vssegte")
8389 (set_attr "mode" "<MODE>")])
8391 (define_insn "@pred_strided_load<mode>"
8392 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8393 (if_then_else:VT
8394 (unspec:<VM>
8395 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8396 (match_operand 5 "vector_length_operand" " rvl, rvl, rvl")
8397 (match_operand 6 "const_int_operand" " i, i, i")
8398 (match_operand 7 "const_int_operand" " i, i, i")
8399 (match_operand 8 "const_int_operand" " i, i, i")
8400 (reg:SI VL_REGNUM)
8401 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8402 (unspec:VT
8403 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8404 (match_operand 4 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8405 (mem:BLK (scratch))] UNSPEC_STRIDED)
8406 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))]
8407 "TARGET_VECTOR"
8408 "vlsseg<nf>e<sew>.v\t%0,(%z3),%z4%p1"
8409 [(set_attr "type" "vlsegds")
8410 (set_attr "mode" "<MODE>")])
8412 (define_insn "@pred_strided_store<mode>"
8413 [(set (mem:BLK (scratch))
8414 (unspec:BLK
8415 [(unspec:<VM>
8416 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8417 (match_operand 4 "vector_length_operand" " rvl")
8418 (match_operand 5 "const_int_operand" " i")
8419 (reg:SI VL_REGNUM)
8420 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8421 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8422 (match_operand 2 "pmode_reg_or_0_operand" " rJ")
8423 (match_operand:VT 3 "register_operand" " vr")
8424 (mem:BLK (scratch))] UNSPEC_STRIDED))]
8425 "TARGET_VECTOR"
8426 "vssseg<nf>e<sew>.v\t%3,(%z1),%z2%p0"
8427 [(set_attr "type" "vssegts")
8428 (set_attr "mode" "<MODE>")])
8430 (define_insn "@pred_fault_load<mode>"
8431 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8432 (if_then_else:VT
8433 (unspec:<VM>
8434 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8435 (match_operand 4 "vector_length_operand" " rvl, rvl, rvl")
8436 (match_operand 5 "const_int_operand" " i, i, i")
8437 (match_operand 6 "const_int_operand" " i, i, i")
8438 (match_operand 7 "const_int_operand" " i, i, i")
8439 (reg:SI VL_REGNUM)
8440 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8441 (unspec:VT
8442 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8443 (mem:BLK (scratch))] UNSPEC_VLEFF)
8444 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))
8445 (set (reg:SI VL_REGNUM)
8446 (unspec:SI
8447 [(if_then_else:VT
8448 (unspec:<VM>
8449 [(match_dup 1) (match_dup 4) (match_dup 5)
8450 (match_dup 6) (match_dup 7)
8451 (reg:SI VL_REGNUM)
8452 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8453 (unspec:VT
8454 [(match_dup 3) (mem:BLK (scratch))] UNSPEC_VLEFF)
8455 (match_dup 2))] UNSPEC_MODIFY_VL))]
8456 "TARGET_VECTOR"
8457 "vlseg<nf>e<sew>ff.v\t%0,(%z3)%p1"
8458 [(set_attr "type" "vlsegdff")
8459 (set_attr "mode" "<MODE>")])
8461 (define_insn "@pred_indexed_<order>load<V1T:mode><RATIO64I:mode>"
8462 [(set (match_operand:V1T 0 "register_operand" "=&vr, &vr")
8463 (if_then_else:V1T
8464 (unspec:<VM>
8465 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8466 (match_operand 5 "vector_length_operand" " rvl, rvl")
8467 (match_operand 6 "const_int_operand" " i, i")
8468 (match_operand 7 "const_int_operand" " i, i")
8469 (match_operand 8 "const_int_operand" " i, i")
8470 (reg:SI VL_REGNUM)
8471 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8472 (unspec:V1T
8473 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8474 (mem:BLK (scratch))
8475 (match_operand:RATIO64I 4 "register_operand" " vr, vr")] ORDER)
8476 (match_operand:V1T 2 "vector_merge_operand" " vu, 0")))]
8477 "TARGET_VECTOR"
8478 "vl<order>xseg<nf>ei<RATIO64I:sew>.v\t%0,(%z3),%4%p1"
8479 [(set_attr "type" "vlsegd<order>x")
8480 (set_attr "mode" "<V1T:MODE>")])
8482 (define_insn "@pred_indexed_<order>load<V2T:mode><RATIO32I:mode>"
8483 [(set (match_operand:V2T 0 "register_operand" "=&vr, &vr")
8484 (if_then_else:V2T
8485 (unspec:<VM>
8486 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8487 (match_operand 5 "vector_length_operand" " rvl, rvl")
8488 (match_operand 6 "const_int_operand" " i, i")
8489 (match_operand 7 "const_int_operand" " i, i")
8490 (match_operand 8 "const_int_operand" " i, i")
8491 (reg:SI VL_REGNUM)
8492 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8493 (unspec:V2T
8494 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8495 (mem:BLK (scratch))
8496 (match_operand:RATIO32I 4 "register_operand" " vr, vr")] ORDER)
8497 (match_operand:V2T 2 "vector_merge_operand" " vu, 0")))]
8498 "TARGET_VECTOR"
8499 "vl<order>xseg<nf>ei<RATIO32I:sew>.v\t%0,(%z3),%4%p1"
8500 [(set_attr "type" "vlsegd<order>x")
8501 (set_attr "mode" "<V2T:MODE>")])
8503 (define_insn "@pred_indexed_<order>load<V4T:mode><RATIO16I:mode>"
8504 [(set (match_operand:V4T 0 "register_operand" "=&vr, &vr")
8505 (if_then_else:V4T
8506 (unspec:<VM>
8507 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8508 (match_operand 5 "vector_length_operand" " rvl, rvl")
8509 (match_operand 6 "const_int_operand" " i, i")
8510 (match_operand 7 "const_int_operand" " i, i")
8511 (match_operand 8 "const_int_operand" " i, i")
8512 (reg:SI VL_REGNUM)
8513 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8514 (unspec:V4T
8515 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8516 (mem:BLK (scratch))
8517 (match_operand:RATIO16I 4 "register_operand" " vr, vr")] ORDER)
8518 (match_operand:V4T 2 "vector_merge_operand" " vu, 0")))]
8519 "TARGET_VECTOR"
8520 "vl<order>xseg<nf>ei<RATIO16I:sew>.v\t%0,(%z3),%4%p1"
8521 [(set_attr "type" "vlsegd<order>x")
8522 (set_attr "mode" "<V4T:MODE>")])
8524 (define_insn "@pred_indexed_<order>load<V8T:mode><RATIO8I:mode>"
8525 [(set (match_operand:V8T 0 "register_operand" "=&vr, &vr")
8526 (if_then_else:V8T
8527 (unspec:<VM>
8528 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8529 (match_operand 5 "vector_length_operand" " rvl, rvl")
8530 (match_operand 6 "const_int_operand" " i, i")
8531 (match_operand 7 "const_int_operand" " i, i")
8532 (match_operand 8 "const_int_operand" " i, i")
8533 (reg:SI VL_REGNUM)
8534 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8535 (unspec:V8T
8536 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8537 (mem:BLK (scratch))
8538 (match_operand:RATIO8I 4 "register_operand" " vr, vr")] ORDER)
8539 (match_operand:V8T 2 "vector_merge_operand" " vu, 0")))]
8540 "TARGET_VECTOR"
8541 "vl<order>xseg<nf>ei<RATIO8I:sew>.v\t%0,(%z3),%4%p1"
8542 [(set_attr "type" "vlsegd<order>x")
8543 (set_attr "mode" "<V8T:MODE>")])
8545 (define_insn "@pred_indexed_<order>load<V16T:mode><RATIO4I:mode>"
8546 [(set (match_operand:V16T 0 "register_operand" "=&vr, &vr")
8547 (if_then_else:V16T
8548 (unspec:<VM>
8549 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8550 (match_operand 5 "vector_length_operand" " rvl, rvl")
8551 (match_operand 6 "const_int_operand" " i, i")
8552 (match_operand 7 "const_int_operand" " i, i")
8553 (match_operand 8 "const_int_operand" " i, i")
8554 (reg:SI VL_REGNUM)
8555 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8556 (unspec:V16T
8557 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8558 (mem:BLK (scratch))
8559 (match_operand:RATIO4I 4 "register_operand" " vr, vr")] ORDER)
8560 (match_operand:V16T 2 "vector_merge_operand" " vu, 0")))]
8561 "TARGET_VECTOR"
8562 "vl<order>xseg<nf>ei<RATIO4I:sew>.v\t%0,(%z3),%4%p1"
8563 [(set_attr "type" "vlsegd<order>x")
8564 (set_attr "mode" "<V16T:MODE>")])
8566 (define_insn "@pred_indexed_<order>load<V32T:mode><RATIO2I:mode>"
8567 [(set (match_operand:V32T 0 "register_operand" "=&vr, &vr")
8568 (if_then_else:V32T
8569 (unspec:<VM>
8570 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8571 (match_operand 5 "vector_length_operand" " rvl, rvl")
8572 (match_operand 6 "const_int_operand" " i, i")
8573 (match_operand 7 "const_int_operand" " i, i")
8574 (match_operand 8 "const_int_operand" " i, i")
8575 (reg:SI VL_REGNUM)
8576 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8577 (unspec:V32T
8578 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8579 (mem:BLK (scratch))
8580 (match_operand:RATIO2I 4 "register_operand" " vr, vr")] ORDER)
8581 (match_operand:V32T 2 "vector_merge_operand" " vu, 0")))]
8582 "TARGET_VECTOR"
8583 "vl<order>xseg<nf>ei<RATIO2I:sew>.v\t%0,(%z3),%4%p1"
8584 [(set_attr "type" "vlsegd<order>x")
8585 (set_attr "mode" "<V32T:MODE>")])
8587 (define_insn "@pred_indexed_<order>store<V1T:mode><RATIO64I:mode>"
8588 [(set (mem:BLK (scratch))
8589 (unspec:BLK
8590 [(unspec:<VM>
8591 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8592 (match_operand 4 "vector_length_operand" " rvl")
8593 (match_operand 5 "const_int_operand" " i")
8594 (reg:SI VL_REGNUM)
8595 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8596 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8597 (match_operand:RATIO64I 2 "register_operand" " vr")
8598 (match_operand:V1T 3 "register_operand" " vr")] ORDER))]
8599 "TARGET_VECTOR"
8600 "vs<order>xseg<nf>ei<RATIO64I:sew>.v\t%3,(%z1),%2%p0"
8601 [(set_attr "type" "vssegt<order>x")
8602 (set_attr "mode" "<V1T:MODE>")])
8604 (define_insn "@pred_indexed_<order>store<V2T:mode><RATIO32I:mode>"
8605 [(set (mem:BLK (scratch))
8606 (unspec:BLK
8607 [(unspec:<VM>
8608 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8609 (match_operand 4 "vector_length_operand" " rvl")
8610 (match_operand 5 "const_int_operand" " i")
8611 (reg:SI VL_REGNUM)
8612 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8613 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8614 (match_operand:RATIO32I 2 "register_operand" " vr")
8615 (match_operand:V2T 3 "register_operand" " vr")] ORDER))]
8616 "TARGET_VECTOR"
8617 "vs<order>xseg<nf>ei<RATIO32I:sew>.v\t%3,(%z1),%2%p0"
8618 [(set_attr "type" "vssegt<order>x")
8619 (set_attr "mode" "<V2T:MODE>")])
8621 (define_insn "@pred_indexed_<order>store<V4T:mode><RATIO16I:mode>"
8622 [(set (mem:BLK (scratch))
8623 (unspec:BLK
8624 [(unspec:<VM>
8625 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8626 (match_operand 4 "vector_length_operand" " rvl")
8627 (match_operand 5 "const_int_operand" " i")
8628 (reg:SI VL_REGNUM)
8629 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8630 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8631 (match_operand:RATIO16I 2 "register_operand" " vr")
8632 (match_operand:V4T 3 "register_operand" " vr")] ORDER))]
8633 "TARGET_VECTOR"
8634 "vs<order>xseg<nf>ei<RATIO16I:sew>.v\t%3,(%z1),%2%p0"
8635 [(set_attr "type" "vssegt<order>x")
8636 (set_attr "mode" "<V4T:MODE>")])
8638 (define_insn "@pred_indexed_<order>store<V8T:mode><RATIO8I:mode>"
8639 [(set (mem:BLK (scratch))
8640 (unspec:BLK
8641 [(unspec:<VM>
8642 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8643 (match_operand 4 "vector_length_operand" " rvl")
8644 (match_operand 5 "const_int_operand" " i")
8645 (reg:SI VL_REGNUM)
8646 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8647 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8648 (match_operand:RATIO8I 2 "register_operand" " vr")
8649 (match_operand:V8T 3 "register_operand" " vr")] ORDER))]
8650 "TARGET_VECTOR"
8651 "vs<order>xseg<nf>ei<RATIO8I:sew>.v\t%3,(%z1),%2%p0"
8652 [(set_attr "type" "vssegt<order>x")
8653 (set_attr "mode" "<V8T:MODE>")])
8655 (define_insn "@pred_indexed_<order>store<V16T:mode><RATIO4I:mode>"
8656 [(set (mem:BLK (scratch))
8657 (unspec:BLK
8658 [(unspec:<VM>
8659 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8660 (match_operand 4 "vector_length_operand" " rvl")
8661 (match_operand 5 "const_int_operand" " i")
8662 (reg:SI VL_REGNUM)
8663 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8664 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8665 (match_operand:RATIO4I 2 "register_operand" " vr")
8666 (match_operand:V16T 3 "register_operand" " vr")] ORDER))]
8667 "TARGET_VECTOR"
8668 "vs<order>xseg<nf>ei<RATIO4I:sew>.v\t%3,(%z1),%2%p0"
8669 [(set_attr "type" "vssegt<order>x")
8670 (set_attr "mode" "<V16T:MODE>")])
8672 (define_insn "@pred_indexed_<order>store<V32T:mode><RATIO2I:mode>"
8673 [(set (mem:BLK (scratch))
8674 (unspec:BLK
8675 [(unspec:<VM>
8676 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8677 (match_operand 4 "vector_length_operand" " rvl")
8678 (match_operand 5 "const_int_operand" " i")
8679 (reg:SI VL_REGNUM)
8680 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8681 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8682 (match_operand:RATIO2I 2 "register_operand" " vr")
8683 (match_operand:V32T 3 "register_operand" " vr")] ORDER))]
8684 "TARGET_VECTOR"
8685 "vs<order>xseg<nf>ei<RATIO2I:sew>.v\t%3,(%z1),%2%p0"
8686 [(set_attr "type" "vssegt<order>x")
8687 (set_attr "mode" "<V32T:MODE>")])
8689 (include "autovec.md")
8690 (include "autovec-opt.md")
8691 (include "sifive-vector.md")