| blob | da1849cc4433a30bb91ce93f9305e51c665493bf |
1 diff -urN /tmp/a/assembler_solaris_x86.cpp b/src/hotspot/os_cpu/solaris_x86/assembler_solaris_x86.cpp
2 --- /tmp/a/assembler_solaris_x86.cpp 1970-01-01 01:00:00.000000000 +0100
3 +++ b/src/hotspot/os_cpu/solaris_x86/assembler_solaris_x86.cpp 2024-09-17 15:41:04.683552119 +0100
4 @@ -0,0 +1,37 @@
5 +/*
6 + * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
7 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8 + *
9 + * This code is free software; you can redistribute it and/or modify it
10 + * under the terms of the GNU General Public License version 2 only, as
11 + * published by the Free Software Foundation.
12 + *
13 + * This code is distributed in the hope that it will be useful, but WITHOUT
14 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 + * version 2 for more details (a copy is included in the LICENSE file that
17 + * accompanied this code).
18 + *
19 + * You should have received a copy of the GNU General Public License version
20 + * 2 along with this work; if not, write to the Free Software Foundation,
21 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
22 + *
23 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
24 + * or visit www.oracle.com if you need additional information or have any
25 + * questions.
26 + *
27 + */
28 +
29 +#include "precompiled.hpp"
30 +#include "asm/macroAssembler.inline.hpp"
31 +#include "runtime/os.hpp"
32 +
33 +void MacroAssembler::int3() {
34 + push(rax);
35 + push(rdx);
36 + push(rcx);
37 + call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
38 + pop(rcx);
39 + pop(rdx);
40 + pop(rax);
41 +}
42 diff -urN /tmp/a/atomic_solaris_x86.hpp b/src/hotspot/os_cpu/solaris_x86/atomic_solaris_x86.hpp
43 --- /tmp/a/atomic_solaris_x86.hpp 1970-01-01 01:00:00.000000000 +0100
44 +++ b/src/hotspot/os_cpu/solaris_x86/atomic_solaris_x86.hpp 2024-09-17 15:41:04.683762167 +0100
45 @@ -0,0 +1,182 @@
46 +/*
47 + * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved.
48 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
49 + *
50 + * This code is free software; you can redistribute it and/or modify it
51 + * under the terms of the GNU General Public License version 2 only, as
52 + * published by the Free Software Foundation.
53 + *
54 + * This code is distributed in the hope that it will be useful, but WITHOUT
55 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
56 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
57 + * version 2 for more details (a copy is included in the LICENSE file that
58 + * accompanied this code).
59 + *
60 + * You should have received a copy of the GNU General Public License version
61 + * 2 along with this work; if not, write to the Free Software Foundation,
62 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
63 + *
64 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
65 + * or visit www.oracle.com if you need additional information or have any
66 + * questions.
67 + *
68 + */
69 +
70 +#ifndef OS_CPU_SOLARIS_X86_ATOMIC_SOLARIS_X86_HPP
71 +#define OS_CPU_SOLARIS_X86_ATOMIC_SOLARIS_X86_HPP
72 +
73 +inline int32_t _Atomic_add(int32_t add_value, volatile int32_t* dest) {
74 + int32_t rv = add_value;
75 + __asm__ volatile ("lock xaddl %0,(%2)"
76 + : "=r" (rv)
77 + : "0" (rv), "r" (dest)
78 + : "cc", "memory");
79 + return rv + add_value;
80 +}
81 +inline int64_t _Atomic_add_long(int64_t add_value, volatile int64_t* dest) {
82 + int64_t rv = add_value;
83 + __asm__ volatile ("lock xaddq %0,(%2)"
84 + : "=r" (rv)
85 + : "0" (rv), "r" (dest)
86 + : "cc", "memory");
87 + return rv + add_value;
88 +}
89 +inline int32_t _Atomic_xchg(int32_t exchange_value, volatile int32_t* dest) {
90 + __asm__ __volatile__ ("xchgl (%2),%0"
91 + : "=r" (exchange_value)
92 + : "0" (exchange_value), "r" (dest)
93 + : "memory");
94 + return exchange_value;
95 +}
96 +inline int64_t _Atomic_xchg_long(int64_t exchange_value, volatile int64_t* dest) {
97 + __asm__ __volatile__ ("xchgq (%2),%0"
98 + : "=r" (exchange_value)
99 + : "0" (exchange_value), "r" (dest)
100 + : "memory");
101 + return exchange_value;
102 +}
103 +inline int8_t _Atomic_cmpxchg_byte(int8_t exchange_value, volatile int8_t* dest, int8_t compare_value) {
104 + __asm__ volatile ("lock cmpxchgb %1,(%3)"
105 + : "=a" (exchange_value)
106 + : "q" (exchange_value), "a" (compare_value), "r" (dest)
107 + : "cc", "memory");
108 + return exchange_value;
109 +}
110 +inline int32_t _Atomic_cmpxchg(int32_t exchange_value, volatile int32_t* dest, int32_t compare_value) {
111 + __asm__ volatile ("lock cmpxchgl %1,(%3)"
112 + : "=a" (exchange_value)
113 + : "q" (exchange_value), "a" (compare_value), "r" (dest)
114 + : "cc", "memory");
115 + return exchange_value;
116 +}
117 +inline int64_t _Atomic_cmpxchg_long(int64_t exchange_value, volatile int64_t* dest, int64_t compare_value) {
118 + __asm__ volatile ("lock cmpxchgq %1,(%3)"
119 + : "=a" (exchange_value)
120 + : "q" (exchange_value), "a" (compare_value), "r" (dest)
121 + : "cc", "memory");
122 + return exchange_value;
123 +}
124 +
125 +template<size_t byte_size>
126 +struct Atomic::PlatformAdd {
127 + template<typename D, typename I>
128 + D add_then_fetch(D volatile* dest, I add_value, atomic_memory_order order) const;
129 +
130 + template<typename D, typename I>
131 + D fetch_then_add(D volatile* dest, I add_value, atomic_memory_order order) const {
132 + return add_then_fetch(dest, add_value, order) - add_value;
133 + }
134 +};
135 +
136 +// Not using add_using_helper; see comment for cmpxchg.
137 +template<>
138 +template<typename D, typename I>
139 +inline D Atomic::PlatformAdd<4>::add_then_fetch(D volatile* dest, I add_value,
140 + atomic_memory_order order) const {
141 + STATIC_ASSERT(4 == sizeof(I));
142 + STATIC_ASSERT(4 == sizeof(D));
143 + return PrimitiveConversions::cast<D>(
144 + _Atomic_add(PrimitiveConversions::cast<int32_t>(add_value),
145 + reinterpret_cast<int32_t volatile*>(dest)));
146 +}
147 +
148 +// Not using add_using_helper; see comment for cmpxchg.
149 +template<>
150 +template<typename D, typename I>
151 +inline D Atomic::PlatformAdd<8>::add_then_fetch(D volatile* dest, I add_value,
152 + atomic_memory_order order) const {
153 + STATIC_ASSERT(8 == sizeof(I));
154 + STATIC_ASSERT(8 == sizeof(D));
155 + return PrimitiveConversions::cast<D>(
156 + _Atomic_add_long(PrimitiveConversions::cast<int64_t>(add_value),
157 + reinterpret_cast<int64_t volatile*>(dest)));
158 +}
159 +
160 +template<>
161 +template<typename T>
162 +inline T Atomic::PlatformXchg<4>::operator()(T volatile* dest,
163 + T exchange_value,
164 + atomic_memory_order order) const {
165 + STATIC_ASSERT(4 == sizeof(T));
166 + return PrimitiveConversions::cast<T>(
167 + _Atomic_xchg(PrimitiveConversions::cast<int32_t>(exchange_value),
168 + reinterpret_cast<int32_t volatile*>(dest)));
169 +}
170 +
171 +template<>
172 +template<typename T>
173 +inline T Atomic::PlatformXchg<8>::operator()(T volatile* dest,
174 + T exchange_value,
175 + atomic_memory_order order) const {
176 + STATIC_ASSERT(8 == sizeof(T));
177 + return PrimitiveConversions::cast<T>(
178 + _Atomic_xchg_long(PrimitiveConversions::cast<int64_t>(exchange_value),
179 + reinterpret_cast<int64_t volatile*>(dest)));
180 +}
181 +
182 +// Not using cmpxchg_using_helper here, because some configurations of
183 +// Solaris compiler don't deal well with passing a "defined in .il"
184 +// function as an argument. We *should* switch to using gcc-style
185 +// inline assembly, but attempting to do so with Studio 12.4 ran into
186 +// segfaults.
187 +
188 +template<>
189 +template<typename T>
190 +inline T Atomic::PlatformCmpxchg<1>::operator()(T volatile* dest,
191 + T compare_value,
192 + T exchange_value,
193 + atomic_memory_order order) const {
194 + STATIC_ASSERT(1 == sizeof(T));
195 + return PrimitiveConversions::cast<T>(
196 + _Atomic_cmpxchg_byte(PrimitiveConversions::cast<int8_t>(exchange_value),
197 + reinterpret_cast<int8_t volatile*>(dest),
198 + PrimitiveConversions::cast<int8_t>(compare_value)));
199 +}
200 +
201 +template<>
202 +template<typename T>
203 +inline T Atomic::PlatformCmpxchg<4>::operator()(T volatile* dest,
204 + T compare_value,
205 + T exchange_value,
206 + atomic_memory_order order) const {
207 + STATIC_ASSERT(4 == sizeof(T));
208 + return PrimitiveConversions::cast<T>(
209 + _Atomic_cmpxchg(PrimitiveConversions::cast<int32_t>(exchange_value),
210 + reinterpret_cast<int32_t volatile*>(dest),
211 + PrimitiveConversions::cast<int32_t>(compare_value)));
212 +}
213 +
214 +template<>
215 +template<typename T>
216 +inline T Atomic::PlatformCmpxchg<8>::operator()(T volatile* dest,
217 + T compare_value,
218 + T exchange_value,
219 + atomic_memory_order order) const {
220 + STATIC_ASSERT(8 == sizeof(T));
221 + return PrimitiveConversions::cast<T>(
222 + _Atomic_cmpxchg_long(PrimitiveConversions::cast<int64_t>(exchange_value),
223 + reinterpret_cast<int64_t volatile*>(dest),
224 + PrimitiveConversions::cast<int64_t>(compare_value)));
225 +}
226 +
227 +#endif // OS_CPU_SOLARIS_X86_ATOMIC_SOLARIS_X86_HPP
228 diff -urN /tmp/a/bytes_solaris_x86.hpp b/src/hotspot/os_cpu/solaris_x86/bytes_solaris_x86.hpp
229 --- /tmp/a/bytes_solaris_x86.hpp 1970-01-01 01:00:00.000000000 +0100
230 +++ b/src/hotspot/os_cpu/solaris_x86/bytes_solaris_x86.hpp 2024-09-17 15:41:04.683898917 +0100
231 @@ -0,0 +1,60 @@
232 +/*
233 + * Copyright (c) 1998, 2019, Oracle and/or its affiliates. All rights reserved.
234 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
235 + *
236 + * This code is free software; you can redistribute it and/or modify it
237 + * under the terms of the GNU General Public License version 2 only, as
238 + * published by the Free Software Foundation.
239 + *
240 + * This code is distributed in the hope that it will be useful, but WITHOUT
241 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
242 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
243 + * version 2 for more details (a copy is included in the LICENSE file that
244 + * accompanied this code).
245 + *
246 + * You should have received a copy of the GNU General Public License version
247 + * 2 along with this work; if not, write to the Free Software Foundation,
248 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
249 + *
250 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
251 + * or visit www.oracle.com if you need additional information or have any
252 + * questions.
253 + *
254 + */
255 +
256 +#ifndef OS_CPU_SOLARIS_X86_BYTES_SOLARIS_X86_HPP
257 +#define OS_CPU_SOLARIS_X86_BYTES_SOLARIS_X86_HPP
258 +
259 +extern "C" {
260 + inline u2 _raw_swap_u2(u2 x) {
261 + unsigned short int __dest;
262 + __asm__ ("rorw $8, %w0": "=r" (__dest): "0" (x): "cc");
263 + return __dest;
264 + }
265 + inline u4 _raw_swap_u4(u4 x) {
266 + unsigned int __dest;
267 + __asm__ ("bswap %0" : "=r" (__dest) : "0" (x));
268 + return __dest;
269 + }
270 + inline u8 _raw_swap_u8(u8 x) {
271 + unsigned long __dest;
272 + __asm__ ("bswap %q0" : "=r" (__dest) : "0" (x));
273 + return __dest;
274 + }
275 +}
276 +
277 +// Efficient swapping of data bytes from Java byte
278 +// ordering to native byte ordering and vice versa.
279 +inline u2 Bytes::swap_u2(u2 x) {
280 + return _raw_swap_u2(x);
281 +}
282 +
283 +inline u4 Bytes::swap_u4(u4 x) {
284 + return _raw_swap_u4(x);
285 +}
286 +
287 +inline u8 Bytes::swap_u8(u8 x) {
288 + return _raw_swap_u8(x);
289 +}
290 +
291 +#endif // OS_CPU_SOLARIS_X86_BYTES_SOLARIS_X86_HPP
292 diff -urN /tmp/a/copy_solaris_x86.hpp b/src/hotspot/os_cpu/solaris_x86/copy_solaris_x86.hpp
293 --- /tmp/a/copy_solaris_x86.hpp 1970-01-01 01:00:00.000000000 +0100
294 +++ b/src/hotspot/os_cpu/solaris_x86/copy_solaris_x86.hpp 2024-09-17 15:41:04.684012167 +0100
295 @@ -0,0 +1,30 @@
296 +/*
297 + * Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
298 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
299 + *
300 + * This code is free software; you can redistribute it and/or modify it
301 + * under the terms of the GNU General Public License version 2 only, as
302 + * published by the Free Software Foundation.
303 + *
304 + * This code is distributed in the hope that it will be useful, but WITHOUT
305 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
306 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
307 + * version 2 for more details (a copy is included in the LICENSE file that
308 + * accompanied this code).
309 + *
310 + * You should have received a copy of the GNU General Public License version
311 + * 2 along with this work; if not, write to the Free Software Foundation,
312 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
313 + *
314 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
315 + * or visit www.oracle.com if you need additional information or have any
316 + * questions.
317 + *
318 + */
319 +
320 +#ifndef OS_CPU_SOLARIS_X86_COPY_SOLARIS_X86_HPP
321 +#define OS_CPU_SOLARIS_X86_COPY_SOLARIS_X86_HPP
322 +
323 +// now in central copy_x86.hpp
324 +
325 +#endif // OS_CPU_SOLARIS_X86_COPY_SOLARIS_X86_HPP
326 diff -urN /tmp/a/globals_solaris_x86.hpp b/src/hotspot/os_cpu/solaris_x86/globals_solaris_x86.hpp
327 --- /tmp/a/globals_solaris_x86.hpp 1970-01-01 01:00:00.000000000 +0100
328 +++ b/src/hotspot/os_cpu/solaris_x86/globals_solaris_x86.hpp 2024-09-17 15:41:04.684140952 +0100
329 @@ -0,0 +1,40 @@
330 +/*
331 + * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
332 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
333 + *
334 + * This code is free software; you can redistribute it and/or modify it
335 + * under the terms of the GNU General Public License version 2 only, as
336 + * published by the Free Software Foundation.
337 + *
338 + * This code is distributed in the hope that it will be useful, but WITHOUT
339 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
340 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
341 + * version 2 for more details (a copy is included in the LICENSE file that
342 + * accompanied this code).
343 + *
344 + * You should have received a copy of the GNU General Public License version
345 + * 2 along with this work; if not, write to the Free Software Foundation,
346 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
347 + *
348 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
349 + * or visit www.oracle.com if you need additional information or have any
350 + * questions.
351 + *
352 + */
353 +
354 +#ifndef OS_CPU_SOLARIS_X86_GLOBALS_SOLARIS_X86_HPP
355 +#define OS_CPU_SOLARIS_X86_GLOBALS_SOLARIS_X86_HPP
356 +
357 +// Sets the default values for platform dependent flags used by the runtime system.
358 +// (see globals.hpp)
359 +
360 +define_pd_global(bool, DontYieldALot, true); // Determined in the design center
361 +define_pd_global(intx, CompilerThreadStackSize, 1024);
362 +define_pd_global(intx, ThreadStackSize, 1024); // 0 => use system default
363 +define_pd_global(intx, VMThreadStackSize, 1024);
364 +define_pd_global(size_t, JVMInvokeMethodSlack, 8*K);
365 +
366 +// Used on 64 bit platforms for UseCompressedOops base address
367 +define_pd_global(size_t, HeapBaseMinAddress, 2*G);
368 +
369 +#endif // OS_CPU_SOLARIS_X86_GLOBALS_SOLARIS_X86_HPP
370 diff -urN /tmp/a/javaThread_solaris_x86.cpp b/src/hotspot/os_cpu/solaris_x86/javaThread_solaris_x86.cpp
371 --- /tmp/a/javaThread_solaris_x86.cpp 1970-01-01 01:00:00.000000000 +0100
372 +++ b/src/hotspot/os_cpu/solaris_x86/javaThread_solaris_x86.cpp 2024-09-17 15:41:04.685511524 +0100
373 @@ -0,0 +1,97 @@
374 +/*
375 + * Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
376 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
377 + *
378 + * This code is free software; you can redistribute it and/or modify it
379 + * under the terms of the GNU General Public License version 2 only, as
380 + * published by the Free Software Foundation.
381 + *
382 + * This code is distributed in the hope that it will be useful, but WITHOUT
383 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
384 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
385 + * version 2 for more details (a copy is included in the LICENSE file that
386 + * accompanied this code).
387 + *
388 + * You should have received a copy of the GNU General Public License version
389 + * 2 along with this work; if not, write to the Free Software Foundation,
390 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
391 + *
392 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
393 + * or visit www.oracle.com if you need additional information or have any
394 + * questions.
395 + *
396 + */
397 +
398 +#include "precompiled.hpp"
399 +#include "runtime/frame.inline.hpp"
400 +#include "runtime/javaThread.hpp"
401 +
402 +frame JavaThread::pd_last_frame() {
403 + assert(has_last_Java_frame(), "must have last_Java_sp() when suspended");
404 + vmassert(_anchor.last_Java_pc() != NULL, "not walkable");
405 + return frame(_anchor.last_Java_sp(), _anchor.last_Java_fp(), _anchor.last_Java_pc());
406 +}
407 +
408 +// For Forte Analyzer AsyncGetCallTrace profiling support - thread is
409 +// currently interrupted by SIGPROF
410 +bool JavaThread::pd_get_top_frame_for_signal_handler(frame* fr_addr,
411 + void* ucontext, bool isInJava) {
412 + assert(Thread::current() == this, "caller must be current thread");
413 + return pd_get_top_frame(fr_addr, ucontext, isInJava);
414 +}
415 +
416 +bool JavaThread::pd_get_top_frame_for_profiling(frame* fr_addr,
417 + void* ucontext, bool isInJava) {
418 + return pd_get_top_frame(fr_addr, ucontext, isInJava);
419 +}
420 +
421 +bool JavaThread::pd_get_top_frame(frame* fr_addr,
422 + void* ucontext, bool isInJava) {
423 + assert(this->is_Java_thread(), "must be JavaThread");
424 + JavaThread* jt = (JavaThread *)this;
425 +
426 + // There is small window where last_Java_frame is not walkable or safe
427 + if (jt->has_last_Java_frame() && jt->frame_anchor()->walkable()) {
428 + *fr_addr = jt->pd_last_frame();
429 + return true;
430 + }
431 +
432 + ucontext_t* uc = (ucontext_t*) ucontext;
433 +
434 + // We always want to use the initial frame we create from the ucontext as
435 + // it certainly signals where we currently are. However that frame may not
436 + // be safe for calling sender. In that case if we have a last_Java_frame
437 + // then the forte walker will switch to that frame as the virtual sender
438 + // for the frame we create here which is not sender safe.
439 +
440 + intptr_t* ret_fp;
441 + intptr_t* ret_sp;
442 + address addr = os::fetch_frame_from_context(uc, &ret_sp, &ret_fp);
443 +
444 + // Something would really have to be screwed up to get a NULL pc
445 +
446 + if (addr == NULL) {
447 + // ucontext wasn't useful
448 + return false;
449 + }
450 +
451 + // If sp and fp are nonsense just leave them out
452 +
453 + if (!jt->is_in_full_stack((address)ret_sp)) {
454 + ret_sp = NULL;
455 + ret_fp = NULL;
456 + } else {
457 + // sp is reasonable is fp reasonable?
458 + if (!jt->is_in_stack_range_incl((address)ret_fp, (address)ret_sp)) {
459 + ret_fp = NULL;
460 + }
461 + }
462 +
463 + frame ret_frame(ret_sp, ret_fp, addr);
464 +
465 + *fr_addr = ret_frame;
466 + return true;
467 +
468 +}
469 +
470 +void JavaThread::cache_global_variables() { }
471 diff -urN /tmp/a/javaThread_solaris_x86.hpp b/src/hotspot/os_cpu/solaris_x86/javaThread_solaris_x86.hpp
472 --- /tmp/a/javaThread_solaris_x86.hpp 1970-01-01 01:00:00.000000000 +0100
473 +++ b/src/hotspot/os_cpu/solaris_x86/javaThread_solaris_x86.hpp 2024-09-17 15:41:04.685643895 +0100
474 @@ -0,0 +1,59 @@
475 +/*
476 + * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved.
477 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
478 + *
479 + * This code is free software; you can redistribute it and/or modify it
480 + * under the terms of the GNU General Public License version 2 only, as
481 + * published by the Free Software Foundation.
482 + *
483 + * This code is distributed in the hope that it will be useful, but WITHOUT
484 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
485 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
486 + * version 2 for more details (a copy is included in the LICENSE file that
487 + * accompanied this code).
488 + *
489 + * You should have received a copy of the GNU General Public License version
490 + * 2 along with this work; if not, write to the Free Software Foundation,
491 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
492 + *
493 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
494 + * or visit www.oracle.com if you need additional information or have any
495 + * questions.
496 + *
497 + */
498 +
499 +#ifndef OS_CPU_SOLARIS_X86_JAVATHREAD_SOLARIS_X86_HPP
500 +#define OS_CPU_SOLARIS_X86_JAVATHREAD_SOLARIS_X86_HPP
501 +
502 + private:
503 + void pd_initialize() { _anchor.clear(); }
504 +
505 + frame pd_last_frame();
506 +
507 + public:
508 +
509 + void set_base_of_stack_pointer(intptr_t* base_sp) {}
510 +
511 + static ByteSize last_Java_fp_offset() {
512 + return byte_offset_of(JavaThread, _anchor) + JavaFrameAnchor::last_Java_fp_offset();
513 + }
514 +
515 + intptr_t* base_of_stack_pointer() { return NULL; }
516 + void record_base_of_stack_pointer() {}
517 +
518 + bool pd_get_top_frame_for_signal_handler(frame* fr_addr, void* ucontext,
519 + bool isInJava);
520 + bool pd_get_top_frame_for_profiling(frame* fr_addr, void* ucontext,
521 + bool isInJava);
522 +private:
523 + bool pd_get_top_frame(frame* fr_addr, void* ucontext,
524 + bool isInJava);
525 +public:
526 +
527 + // These routines are only used on cpu architectures that
528 + // have separate register stacks (Itanium).
529 + static bool register_stack_overflow() { return false; }
530 + static void enable_register_stack_guard() {}
531 + static void disable_register_stack_guard() {}
532 +
533 +#endif // OS_CPU_SOLARIS_X86_JAVATHREAD_SOLARIS_X86_HPP
534 diff -urN /tmp/a/orderAccess_solaris_x86.hpp b/src/hotspot/os_cpu/solaris_x86/orderAccess_solaris_x86.hpp
535 --- /tmp/a/orderAccess_solaris_x86.hpp 1970-01-01 01:00:00.000000000 +0100
536 +++ b/src/hotspot/os_cpu/solaris_x86/orderAccess_solaris_x86.hpp 2024-09-17 15:41:04.684271373 +0100
537 @@ -0,0 +1,58 @@
538 +/*
539 + * Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
540 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
541 + *
542 + * This code is free software; you can redistribute it and/or modify it
543 + * under the terms of the GNU General Public License version 2 only, as
544 + * published by the Free Software Foundation.
545 + *
546 + * This code is distributed in the hope that it will be useful, but WITHOUT
547 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
548 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
549 + * version 2 for more details (a copy is included in the LICENSE file that
550 + * accompanied this code).
551 + *
552 + * You should have received a copy of the GNU General Public License version
553 + * 2 along with this work; if not, write to the Free Software Foundation,
554 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
555 + *
556 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
557 + * or visit www.oracle.com if you need additional information or have any
558 + * questions.
559 + *
560 + */
561 +
562 +#ifndef OS_CPU_SOLARIS_X86_ORDERACCESS_SOLARIS_X86_HPP
563 +#define OS_CPU_SOLARIS_X86_ORDERACCESS_SOLARIS_X86_HPP
564 +
565 +// Included in orderAccess.hpp header file.
566 +
567 +// Compiler version last used for testing: solaris studio 12u3
568 +// Please update this information when this file changes
569 +
570 +// Implementation of class OrderAccess.
571 +
572 +// A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions
573 +inline void compiler_barrier() {
574 + __asm__ volatile ("" : : : "memory");
575 +}
576 +
577 +inline void OrderAccess::loadload() { compiler_barrier(); }
578 +inline void OrderAccess::storestore() { compiler_barrier(); }
579 +inline void OrderAccess::loadstore() { compiler_barrier(); }
580 +inline void OrderAccess::storeload() { fence(); }
581 +
582 +inline void OrderAccess::acquire() { compiler_barrier(); }
583 +inline void OrderAccess::release() { compiler_barrier(); }
584 +
585 +inline void OrderAccess::fence() {
586 + __asm__ volatile ("lock; addl $0,0(%%rsp)" : : : "cc", "memory");
587 + compiler_barrier();
588 +}
589 +
590 +inline void OrderAccess::cross_modify_fence_impl() {
591 + int idx = 0;
592 + __asm__ volatile ("cpuid " : "+a" (idx) : : "ebx", "ecx", "edx", "memory");
593 +}
594 +
595 +#endif // OS_CPU_SOLARIS_X86_ORDERACCESS_SOLARIS_X86_HPP
596 diff -urN /tmp/a/os_solaris_x86.cpp b/src/hotspot/os_cpu/solaris_x86/os_solaris_x86.cpp
597 --- /tmp/a/os_solaris_x86.cpp 1970-01-01 01:00:00.000000000 +0100
598 +++ b/src/hotspot/os_cpu/solaris_x86/os_solaris_x86.cpp 2024-09-17 15:41:04.751434290 +0100
599 @@ -0,0 +1,608 @@
600 +/*
601 + * Copyright (c) 1999, 2020, Oracle and/or its affiliates. All rights reserved.
602 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
603 + *
604 + * This code is free software; you can redistribute it and/or modify it
605 + * under the terms of the GNU General Public License version 2 only, as
606 + * published by the Free Software Foundation.
607 + *
608 + * This code is distributed in the hope that it will be useful, but WITHOUT
609 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
610 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
611 + * version 2 for more details (a copy is included in the LICENSE file that
612 + * accompanied this code).
613 + *
614 + * You should have received a copy of the GNU General Public License version
615 + * 2 along with this work; if not, write to the Free Software Foundation,
616 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
617 + *
618 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
619 + * or visit www.oracle.com if you need additional information or have any
620 + * questions.
621 + *
622 + */
623 +
624 +// no precompiled headers
625 +#include "jvm.h"
626 +#include "asm/macroAssembler.hpp"
627 +#include "classfile/classLoader.hpp"
628 +#include "classfile/systemDictionary.hpp"
629 +#include "classfile/vmSymbols.hpp"
630 +#include "code/codeCache.hpp"
631 +#include "code/vtableStubs.hpp"
632 +#include "interpreter/interpreter.hpp"
633 +#include "logging/log.hpp"
634 +#include "memory/allocation.inline.hpp"
635 +#include "os_solaris.hpp"
636 +#include "os_posix.hpp"
637 +#include "prims/jniFastGetField.hpp"
638 +#include "prims/jvm_misc.hpp"
639 +#include "runtime/arguments.hpp"
640 +#include "runtime/frame.inline.hpp"
641 +#include "runtime/interfaceSupport.inline.hpp"
642 +#include "runtime/java.hpp"
643 +#include "runtime/javaCalls.hpp"
644 +#include "runtime/mutexLocker.hpp"
645 +#include "runtime/osThread.hpp"
646 +#include "runtime/safepointMechanism.hpp"
647 +#include "runtime/sharedRuntime.hpp"
648 +#include "runtime/stubRoutines.hpp"
649 +#include "runtime/thread.inline.hpp"
650 +#include "runtime/timer.hpp"
651 +#include "signals_posix.hpp"
652 +#include "utilities/align.hpp"
653 +#include "utilities/events.hpp"
654 +#include "utilities/vmError.hpp"
655 +
656 +// put OS-includes here
657 +# include <sys/types.h>
658 +# include <sys/mman.h>
659 +# include <pthread.h>
660 +# include <signal.h>
661 +# include <setjmp.h>
662 +# include <errno.h>
663 +# include <dlfcn.h>
664 +# include <stdio.h>
665 +# include <unistd.h>
666 +# include <sys/resource.h>
667 +# include <thread.h>
668 +# include <sys/stat.h>
669 +# include <sys/time.h>
670 +# include <sys/filio.h>
671 +# include <sys/utsname.h>
672 +# include <sys/systeminfo.h>
673 +# include <sys/socket.h>
674 +# include <sys/trap.h>
675 +# include <sys/lwp.h>
676 +# include <poll.h>
677 +# include <sys/lwp.h>
678 +# include <procfs.h>
679 +
680 +
681 +#define MAX_PATH (2 * K)
682 +
683 +// Minimum usable stack sizes required to get to user code. Space for
684 +// HotSpot guard pages is added later.
685 +#ifdef _LP64
686 +// The adlc generated method 'State::MachNodeGenerator(int)' used by the C2 compiler
687 +// threads requires a large stack with the Solaris Studio C++ compiler version 5.13
688 +// and product VM builds (debug builds require significantly less stack space).
689 +size_t os::_compiler_thread_min_stack_allowed = 325 * K;
690 +size_t os::_java_thread_min_stack_allowed = 48 * K;
691 +size_t os::_vm_internal_thread_min_stack_allowed = 224 * K;
692 +#else
693 +size_t os::_compiler_thread_min_stack_allowed = 32 * K;
694 +size_t os::_java_thread_min_stack_allowed = 32 * K;
695 +size_t os::_vm_internal_thread_min_stack_allowed = 64 * K;
696 +#endif // _LP64
697 +
698 +#ifdef AMD64
699 +#define REG_SP REG_RSP
700 +#define REG_PC REG_RIP
701 +#define REG_FP REG_RBP
702 +#else
703 +#define REG_SP UESP
704 +#define REG_PC EIP
705 +#define REG_FP EBP
706 +// 4900493 counter to prevent runaway LDTR refresh attempt
707 +
708 +static volatile int ldtr_refresh = 0;
709 +// the libthread instruction that faults because of the stale LDTR
710 +
711 +static const unsigned char movlfs[] = { 0x8e, 0xe0 // movl %eax,%fs
712 + };
713 +#endif // AMD64
714 +
715 +char* os::non_memory_address_word() {
716 + // Must never look like an address returned by reserve_memory,
717 + // even in its subfields (as defined by the CPU immediate fields,
718 + // if the CPU splits constants across multiple instructions).
719 + return (char*) -1;
720 +}
721 +
722 +//
723 +// Validate a ucontext retrieved from walking a uc_link of a ucontext.
724 +// There are issues with libthread giving out uc_links for different threads
725 +// on the same uc_link chain and bad or circular links.
726 +//
727 +bool os::Solaris::valid_ucontext(Thread* thread, const ucontext_t* valid, const ucontext_t* suspect) {
728 + if (valid >= suspect ||
729 + valid->uc_stack.ss_flags != suspect->uc_stack.ss_flags ||
730 + valid->uc_stack.ss_sp != suspect->uc_stack.ss_sp ||
731 + valid->uc_stack.ss_size != suspect->uc_stack.ss_size) {
732 + DEBUG_ONLY(tty->print_cr("valid_ucontext: failed test 1");)
733 + return false;
734 + }
735 +
736 + if (thread->is_Java_thread()) {
737 + if (!thread->is_in_full_stack_checked((address)suspect)) {
738 + DEBUG_ONLY(tty->print_cr("valid_ucontext: uc_link not in thread stack");)
739 + return false;
740 + }
741 + if (!thread->is_in_full_stack_checked((address) suspect->uc_mcontext.gregs[REG_SP])) {
742 + DEBUG_ONLY(tty->print_cr("valid_ucontext: stackpointer not in thread stack");)
743 + return false;
744 + }
745 + }
746 + return true;
747 +}
748 +
749 +// We will only follow one level of uc_link since there are libthread
750 +// issues with ucontext linking and it is better to be safe and just
751 +// let caller retry later.
752 +const ucontext_t* os::Solaris::get_valid_uc_in_signal_handler(Thread *thread,
753 + const ucontext_t *uc) {
754 +
755 + const ucontext_t *retuc = NULL;
756 +
757 + if (uc != NULL) {
758 + if (uc->uc_link == NULL) {
759 + // cannot validate without uc_link so accept current ucontext
760 + retuc = uc;
761 + } else if (os::Solaris::valid_ucontext(thread, uc, uc->uc_link)) {
762 + // first ucontext is valid so try the next one
763 + uc = uc->uc_link;
764 + if (uc->uc_link == NULL) {
765 + // cannot validate without uc_link so accept current ucontext
766 + retuc = uc;
767 + } else if (os::Solaris::valid_ucontext(thread, uc, uc->uc_link)) {
768 + // the ucontext one level down is also valid so return it
769 + retuc = uc;
770 + }
771 + }
772 + }
773 + return retuc;
774 +}
775 +
776 +void os::Posix::ucontext_set_pc(ucontext_t* uc, address pc) {
777 + uc->uc_mcontext.gregs [REG_PC] = (greg_t) pc;
778 +}
779 +
780 +// Assumes ucontext is valid
781 +intptr_t* os::Solaris::ucontext_get_sp(const ucontext_t *uc) {
782 + return (intptr_t*)uc->uc_mcontext.gregs[REG_SP];
783 +}
784 +
785 +// Assumes ucontext is valid
786 +intptr_t* os::Solaris::ucontext_get_fp(const ucontext_t *uc) {
787 + return (intptr_t*)uc->uc_mcontext.gregs[REG_FP];
788 +}
789 +
790 +address os::Posix::ucontext_get_pc(const ucontext_t *uc) {
791 + return (address) uc->uc_mcontext.gregs[REG_PC];
792 +}
793 +
794 +address os::fetch_frame_from_context(const void* ucVoid,
795 + intptr_t** ret_sp, intptr_t** ret_fp) {
796 +
797 + address epc;
798 + const ucontext_t *uc = (const ucontext_t*)ucVoid;
799 +
800 + if (uc != NULL) {
801 + epc = os::Posix::ucontext_get_pc(uc);
802 + if (ret_sp) *ret_sp = os::Solaris::ucontext_get_sp(uc);
803 + if (ret_fp) *ret_fp = os::Solaris::ucontext_get_fp(uc);
804 + } else {
805 + epc = NULL;
806 + if (ret_sp) *ret_sp = (intptr_t *)NULL;
807 + if (ret_fp) *ret_fp = (intptr_t *)NULL;
808 + }
809 +
810 + return epc;
811 +}
812 +
813 +frame os::fetch_frame_from_context(const void* ucVoid) {
814 + intptr_t* sp;
815 + intptr_t* fp;
816 + address epc = fetch_frame_from_context(ucVoid, &sp, &fp);
817 + return frame(sp, fp, epc);
818 +}
819 +
820 +frame os::fetch_compiled_frame_from_context(const void* ucVoid) {
821 + const ucontext_t* uc = (const ucontext_t*)ucVoid;
822 + frame fr = os::fetch_frame_from_context(uc);
823 + // in compiled code, the stack banging is performed just after the return pc
824 + // has been pushed on the stack
825 + return frame(fr.sp() + 1, fr.fp(), (address)*(fr.sp()));
826 +}
827 +
828 +frame os::get_sender_for_C_frame(frame* fr) {
829 + return frame(fr->sender_sp(), fr->link(), fr->sender_pc());
830 +}
831 +
832 +extern "C" intptr_t *_get_current_sp() {
833 + register intptr_t *rsp __asm__ ("rsp");
834 + return rsp;
835 +}
836 +
837 +address os::current_stack_pointer() {
838 + return (address)_get_current_sp();
839 +}
840 +
841 +extern "C" intptr_t *_get_current_fp() {
842 + register intptr_t **rbp __asm__ ("rbp");
843 + return (intptr_t*) *rbp;
844 +}
845 +
846 +frame os::current_frame() {
847 + intptr_t* fp = _get_current_fp(); // it's inlined so want current fp
848 + // fp is for os::current_frame. We want the fp for our caller.
849 + frame myframe((intptr_t*)os::current_stack_pointer(),
850 + (intptr_t*)fp,
851 + CAST_FROM_FN_PTR(address, os::current_frame));
852 + frame caller_frame = os::get_sender_for_C_frame(&myframe);
853 +
854 + if (os::is_first_C_frame(&caller_frame)) {
855 + // stack is not walkable
856 + frame ret; // This will be a null useless frame
857 + return ret;
858 + } else {
859 + // return frame for our caller's caller
860 + return os::get_sender_for_C_frame(&caller_frame);
861 + }
862 +}
863 +
864 +
865 +juint os::cpu_microcode_revision() {
866 + juint result = 0;
867 + // to implement this, look at the source for ucodeadm -v
868 + return result;
869 +}
870 +
871 +bool PosixSignals::pd_hotspot_signal_handler(int sig, siginfo_t* info,
872 + ucontext_t* uc, JavaThread* thread) {
873 +
874 + if (info == NULL || info->si_code <= 0 || info->si_code == SI_NOINFO) {
875 + // can't decode this kind of signal
876 + info = NULL;
877 + } else {
878 + assert(sig == info->si_signo, "bad siginfo");
879 + }
880 +
881 + // decide if this trap can be handled by a stub
882 + address stub = NULL;
883 +
884 + address pc = NULL;
885 +
886 + //%note os_trap_1
887 + if (info != NULL && uc != NULL && thread != NULL) {
888 + // factor me: getPCfromContext
889 + pc = (address) uc->uc_mcontext.gregs[REG_PC];
890 +
891 + // Handle ALL stack overflow variations here
892 + if (sig == SIGSEGV && info->si_code == SEGV_ACCERR) {
893 + address addr = (address) info->si_addr;
894 + if (thread->is_in_full_stack(addr)) {
895 + // stack overflow
896 + if (os::Posix::handle_stack_overflow(thread, addr, pc, uc, &stub)) {
897 + return true; // continue
898 + }
899 + }
900 + }
901 +
902 + if ((sig == SIGSEGV) && VM_Version::is_cpuinfo_segv_addr(pc)) {
903 + // Verify that OS save/restore AVX registers.
904 + stub = VM_Version::cpuinfo_cont_addr();
905 + }
906 +
907 + if (thread->thread_state() == _thread_in_vm ||
908 + thread->thread_state() == _thread_in_native) {
909 + if (sig == SIGBUS && info->si_code == BUS_OBJERR && thread->doing_unsafe_access()) {
910 + address next_pc = Assembler::locate_next_instruction(pc);
911 + if (UnsafeMemoryAccess::contains_pc(pc)) {
912 + next_pc = UnsafeMemoryAccess::page_error_continue_pc(pc);
913 + }
914 + stub = SharedRuntime::handle_unsafe_access(thread, next_pc);
915 + }
916 + }
917 +
918 + if (thread->thread_state() == _thread_in_Java) {
919 + // Support Safepoint Polling
920 + if ( sig == SIGSEGV && SafepointMechanism::is_poll_address((address)info->si_addr)) {
921 + stub = SharedRuntime::get_poll_stub(pc);
922 + }
923 + else if (sig == SIGBUS && info->si_code == BUS_OBJERR) {
924 + // BugId 4454115: A read from a MappedByteBuffer can fault
925 + // here if the underlying file has been truncated.
926 + // Do not crash the VM in such a case.
927 + CodeBlob* cb = CodeCache::find_blob(pc);
928 + if (cb != NULL) {
929 + nmethod* nm = cb->as_nmethod_or_null();
930 + bool is_unsafe_memory_access = thread->doing_unsafe_access() && UnsafeMemoryAccess::contains_pc(pc);
931 + if ((nm != NULL && nm->has_unsafe_access()) || is_unsafe_memory_access) {
932 + address next_pc = Assembler::locate_next_instruction(pc);
933 + if (is_unsafe_memory_access) {
934 + next_pc = UnsafeMemoryAccess::page_error_continue_pc(pc);
935 + }
936 + stub = SharedRuntime::handle_unsafe_access(thread, next_pc);
937 + }
938 + }
939 + } else
940 + if (sig == SIGFPE && info->si_code == FPE_INTDIV) {
941 + // integer divide by zero
942 + stub = SharedRuntime::continuation_for_implicit_exception(thread, pc, SharedRuntime::IMPLICIT_DIVIDE_BY_ZERO);
943 + }
944 +#ifndef AMD64
945 + else if (sig == SIGFPE && info->si_code == FPE_FLTDIV) {
946 + // floating-point divide by zero
947 + stub = SharedRuntime::continuation_for_implicit_exception(thread, pc, SharedRuntime::IMPLICIT_DIVIDE_BY_ZERO);
948 + }
949 + else if (sig == SIGFPE && info->si_code == FPE_FLTINV) {
950 + // The encoding of D2I in i486.ad can cause an exception prior
951 + // to the fist instruction if there was an invalid operation
952 + // pending. We want to dismiss that exception. From the win_32
953 + // side it also seems that if it really was the fist causing
954 + // the exception that we do the d2i by hand with different
955 + // rounding. Seems kind of weird. QQQ TODO
956 + // Note that we take the exception at the NEXT floating point instruction.
957 + if (pc[0] == 0xDB) {
958 + assert(pc[0] == 0xDB, "not a FIST opcode");
959 + assert(pc[1] == 0x14, "not a FIST opcode");
960 + assert(pc[2] == 0x24, "not a FIST opcode");
961 + return true;
962 + } else {
963 + assert(pc[-3] == 0xDB, "not an flt invalid opcode");
964 + assert(pc[-2] == 0x14, "not an flt invalid opcode");
965 + assert(pc[-1] == 0x24, "not an flt invalid opcode");
966 + }
967 + }
968 + else if (sig == SIGFPE ) {
969 + tty->print_cr("caught SIGFPE, info 0x%x.", info->si_code);
970 + }
971 +#endif // !AMD64
972 +
973 + // QQQ It doesn't seem that we need to do this on x86 because we should be able
974 + // to return properly from the handler without this extra stuff on the back side.
975 +
976 + else if (sig == SIGSEGV && info->si_code > 0 &&
977 + MacroAssembler::uses_implicit_null_check(info->si_addr)) {
978 + // Determination of interpreter/vtable stub/compiled code null exception
979 + stub = SharedRuntime::continuation_for_implicit_exception(thread, pc, SharedRuntime::IMPLICIT_NULL);
980 + }
981 + }
982 +
983 + // jni_fast_Get<Primitive>Field can trap at certain pc's if a GC kicks in
984 + // and the heap gets shrunk before the field access.
985 + if ((sig == SIGSEGV) || (sig == SIGBUS)) {
986 + address addr = JNI_FastGetField::find_slowcase_pc(pc);
987 + if (addr != (address)-1) {
988 + stub = addr;
989 + }
990 + }
991 + }
992 +
993 + // Execution protection violation
994 + //
995 + // Preventative code for future versions of Solaris which may
996 + // enable execution protection when running the 32-bit VM on AMD64.
997 + //
998 + // This should be kept as the last step in the triage. We don't
999 + // have a dedicated trap number for a no-execute fault, so be
1000 + // conservative and allow other handlers the first shot.
1001 + //
1002 + // Note: We don't test that info->si_code == SEGV_ACCERR here.
1003 + // this si_code is so generic that it is almost meaningless; and
1004 + // the si_code for this condition may change in the future.
1005 + // Furthermore, a false-positive should be harmless.
1006 + if (UnguardOnExecutionViolation > 0 &&
1007 + (sig == SIGSEGV || sig == SIGBUS) &&
1008 + uc->uc_mcontext.gregs[TRAPNO] == T_PGFLT) { // page fault
1009 + int page_size = os::vm_page_size();
1010 + address addr = (address) info->si_addr;
1011 + address pc = (address) uc->uc_mcontext.gregs[REG_PC];
1012 + // Make sure the pc and the faulting address are sane.
1013 + //
1014 + // If an instruction spans a page boundary, and the page containing
1015 + // the beginning of the instruction is executable but the following
1016 + // page is not, the pc and the faulting address might be slightly
1017 + // different - we still want to unguard the 2nd page in this case.
1018 + //
1019 + // 15 bytes seems to be a (very) safe value for max instruction size.
1020 + bool pc_is_near_addr =
1021 + (pointer_delta((void*) addr, (void*) pc, sizeof(char)) < 15);
1022 + bool instr_spans_page_boundary =
1023 + (align_down((intptr_t) pc ^ (intptr_t) addr,
1024 + (intptr_t) page_size) > 0);
1025 +
1026 + if (pc == addr || (pc_is_near_addr && instr_spans_page_boundary)) {
1027 + static volatile address last_addr =
1028 + (address) os::non_memory_address_word();
1029 +
1030 + // In conservative mode, don't unguard unless the address is in the VM
1031 + if (addr != last_addr &&
1032 + (UnguardOnExecutionViolation > 1 || os::address_is_in_vm(addr))) {
1033 +
1034 + // Make memory rwx and retry
1035 + address page_start = align_down(addr, page_size);
1036 + bool res = os::protect_memory((char*) page_start, page_size,
1037 + os::MEM_PROT_RWX);
1038 +
1039 + log_debug(os)("Execution protection violation "
1040 + "at " INTPTR_FORMAT
1041 + ", unguarding " INTPTR_FORMAT ": %s, errno=%d", p2i(addr),
1042 + p2i(page_start), (res ? "success" : "failed"), errno);
1043 + stub = pc;
1044 +
1045 + // Set last_addr so if we fault again at the same address, we don't end
1046 + // up in an endless loop.
1047 + //
1048 + // There are two potential complications here. Two threads trapping at
1049 + // the same address at the same time could cause one of the threads to
1050 + // think it already unguarded, and abort the VM. Likely very rare.
1051 + //
1052 + // The other race involves two threads alternately trapping at
1053 + // different addresses and failing to unguard the page, resulting in
1054 + // an endless loop. This condition is probably even more unlikely than
1055 + // the first.
1056 + //
1057 + // Although both cases could be avoided by using locks or thread local
1058 + // last_addr, these solutions are unnecessary complication: this
1059 + // handler is a best-effort safety net, not a complete solution. It is
1060 + // disabled by default and should only be used as a workaround in case
1061 + // we missed any no-execute-unsafe VM code.
1062 +
1063 + last_addr = addr;
1064 + }
1065 + }
1066 + }
1067 +
1068 + if (stub != NULL) {
1069 + // save all thread context in case we need to restore it
1070 +
1071 + if (thread != NULL) thread->set_saved_exception_pc(pc);
1072 + // 12/02/99: On Sparc it appears that the full context is also saved
1073 + // but as yet, no one looks at or restores that saved context
1074 + os::Posix::ucontext_set_pc(uc, stub);
1075 + return true;
1076 + }
1077 +
1078 + return false;
1079 +}
1080 +
1081 +void os::print_context(outputStream *st, const void *context) {
1082 + if (context == NULL) return;
1083 +
1084 + const ucontext_t *uc = (const ucontext_t*)context;
1085 + st->print_cr("Registers:");
1086 +#ifdef AMD64
1087 + st->print( "RAX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RAX]);
1088 + st->print(", RBX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RBX]);
1089 + st->print(", RCX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RCX]);
1090 + st->print(", RDX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RDX]);
1091 + st->cr();
1092 + st->print( "RSP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RSP]);
1093 + st->print(", RBP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RBP]);
1094 + st->print(", RSI=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RSI]);
1095 + st->print(", RDI=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RDI]);
1096 + st->cr();
1097 + st->print( "R8 =" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R8]);
1098 + st->print(", R9 =" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R9]);
1099 + st->print(", R10=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R10]);
1100 + st->print(", R11=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R11]);
1101 + st->cr();
1102 + st->print( "R12=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R12]);
1103 + st->print(", R13=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R13]);
1104 + st->print(", R14=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R14]);
1105 + st->print(", R15=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_R15]);
1106 + st->cr();
1107 + st->print( "RIP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RIP]);
1108 + st->print(", RFLAGS=" INTPTR_FORMAT, uc->uc_mcontext.gregs[REG_RFL]);
1109 +#else
1110 + st->print( "EAX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EAX]);
1111 + st->print(", EBX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EBX]);
1112 + st->print(", ECX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[ECX]);
1113 + st->print(", EDX=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EDX]);
1114 + st->cr();
1115 + st->print( "ESP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[UESP]);
1116 + st->print(", EBP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EBP]);
1117 + st->print(", ESI=" INTPTR_FORMAT, uc->uc_mcontext.gregs[ESI]);
1118 + st->print(", EDI=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EDI]);
1119 + st->cr();
1120 + st->print( "EIP=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EIP]);
1121 + st->print(", EFLAGS=" INTPTR_FORMAT, uc->uc_mcontext.gregs[EFL]);
1122 +#endif // AMD64
1123 + st->cr();
1124 + st->cr();
1125 +}
1126 +
1127 +void os::print_tos_pc(outputStream *st, const void *context) {
1128 + if (context == NULL) return;
1129 +
1130 + const ucontext_t* uc = (const ucontext_t*)context;
1131 +
1132 + intptr_t *sp = (intptr_t *)os::Solaris::ucontext_get_sp(uc);
1133 + st->print_cr("Top of Stack: (sp=" INTPTR_FORMAT ")", (intptr_t)sp);
1134 + print_hex_dump(st, (address)sp, (address)(sp + 8*sizeof(intptr_t)), sizeof(intptr_t));
1135 + st->cr();
1136 +
1137 + // Note: it may be unsafe to inspect memory near pc. For example, pc may
1138 + // point to garbage if entry point in an nmethod is corrupted. Leave
1139 + // this at the end, and hope for the best.
1140 + address pc = os::Posix::ucontext_get_pc(uc);
1141 + print_instructions(st, pc, sizeof(char));
1142 + st->cr();
1143 +}
1144 +
1145 +void os::print_register_info(outputStream *st, const void *context, int& continuation) {
1146 + const int register_count = AMD64_ONLY(16) NOT_AMD64(8);
1147 + int n = continuation;
1148 + assert(n >= 0 && n <= register_count, "Invalid continuation value");
1149 + if (context == nullptr || n == register_count) {
1150 + return;
1151 + }
1152 +
1153 + const ucontext_t *uc = (const ucontext_t*)context;
1154 + while (n < register_count) {
1155 + // Update continuation with next index before printing location
1156 + continuation = n + 1;
1157 +# define CASE_PRINT_REG(n, str, id) case n: st->print(str); print_location(st, uc->uc_mcontext.gregs[REG_##id]);
1158 + switch (n) {
1159 +#ifdef AMD64
1160 + CASE_PRINT_REG( 0, "RAX=", RAX); break;
1161 + CASE_PRINT_REG( 1, "RBX=", RBX); break;
1162 + CASE_PRINT_REG( 2, "RCX=", RCX); break;
1163 + CASE_PRINT_REG( 3, "RDX=", RDX); break;
1164 + CASE_PRINT_REG( 4, "RSP=", RSP); break;
1165 + CASE_PRINT_REG( 5, "RBP=", RBP); break;
1166 + CASE_PRINT_REG( 6, "RSI=", RSI); break;
1167 + CASE_PRINT_REG( 7, "RDI=", RDI); break;
1168 + CASE_PRINT_REG( 8, "R8 =", R8); break;
1169 + CASE_PRINT_REG( 9, "R9 =", R9); break;
1170 + CASE_PRINT_REG(10, "R10=", R10); break;
1171 + CASE_PRINT_REG(11, "R11=", R11); break;
1172 + CASE_PRINT_REG(12, "R12=", R12); break;
1173 + CASE_PRINT_REG(13, "R13=", R13); break;
1174 + CASE_PRINT_REG(14, "R14=", R14); break;
1175 + CASE_PRINT_REG(15, "R15=", R15); break;
1176 +#else
1177 + CASE_PRINT_REG(0, "EAX=", EAX); break;
1178 + CASE_PRINT_REG(1, "EBX=", EBX); break;
1179 + CASE_PRINT_REG(2, "ECX=", ECX); break;
1180 + CASE_PRINT_REG(3, "EDX=", EDX); break;
1181 + CASE_PRINT_REG(4, "ESP=", ESP); break;
1182 + CASE_PRINT_REG(5, "EBP=", EBP); break;
1183 + CASE_PRINT_REG(6, "ESI=", ESI); break;
1184 + CASE_PRINT_REG(7, "EDI=", EDI); break;
1185 +#endif // AMD64
1186 + }
1187 +# undef CASE_PRINT_REG
1188 + ++n;
1189 + }
1190 +}
1191 +
1192 +
1193 +void os::Solaris::init_thread_fpu_state(void) {
1194 + // Nothing to do
1195 +}
1196 +void os::setup_fpu() {}
1197 +
1198 +#ifndef PRODUCT
1199 +void os::verify_stack_alignment() {
1200 + assert(((intptr_t)os::current_stack_pointer() & (StackAlignmentInBytes-1)) == 0, "incorrect stack alignment");
1201 +}
1202 +#endif
1203 +
1204 +int os::extra_bang_size_in_bytes() {
1205 + // JDK-8050147 requires the full cache line bang for x86.
1206 + return VM_Version::L1_line_size();
1207 +}
1208 diff -urN /tmp/a/os_solaris_x86.hpp b/src/hotspot/os_cpu/solaris_x86/os_solaris_x86.hpp
1209 --- /tmp/a/os_solaris_x86.hpp 1970-01-01 01:00:00.000000000 +0100
1210 +++ b/src/hotspot/os_cpu/solaris_x86/os_solaris_x86.hpp 2024-09-17 15:41:04.733069950 +0100
1211 @@ -0,0 +1,57 @@
1212 +/*
1213 + * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved.
1214 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1215 + *
1216 + * This code is free software; you can redistribute it and/or modify it
1217 + * under the terms of the GNU General Public License version 2 only, as
1218 + * published by the Free Software Foundation.
1219 + *
1220 + * This code is distributed in the hope that it will be useful, but WITHOUT
1221 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1222 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1223 + * version 2 for more details (a copy is included in the LICENSE file that
1224 + * accompanied this code).
1225 + *
1226 + * You should have received a copy of the GNU General Public License version
1227 + * 2 along with this work; if not, write to the Free Software Foundation,
1228 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1229 + *
1230 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1231 + * or visit www.oracle.com if you need additional information or have any
1232 + * questions.
1233 + *
1234 + */
1235 +
1236 +#ifndef OS_CPU_SOLARIS_X86_OS_SOLARIS_X86_HPP
1237 +#define OS_CPU_SOLARIS_X86_OS_SOLARIS_X86_HPP
1238 +
1239 + //
1240 + // NOTE: we are back in class os here, not Solaris
1241 + //
1242 +#ifdef AMD64
1243 + static void setup_fpu() {}
1244 +#else
1245 + static int32_t (*atomic_xchg_func) (int32_t, volatile int32_t*);
1246 + static int32_t (*atomic_cmpxchg_func) (int32_t, volatile int32_t*, int32_t);
1247 + static int64_t (*atomic_cmpxchg_long_func)(int64_t, volatile int64_t*, int64_t);
1248 + static int32_t (*atomic_add_func) (int32_t, volatile int32_t*);
1249 +
1250 + static int32_t atomic_xchg_bootstrap (int32_t, volatile int32_t*);
1251 + static int32_t atomic_cmpxchg_bootstrap (int32_t, volatile int32_t*, int32_t);
1252 + static int64_t atomic_cmpxchg_long_bootstrap(int64_t, volatile int64_t*, int64_t);
1253 + static int32_t atomic_add_bootstrap (int32_t, volatile int32_t*);
1254 +
1255 + static void setup_fpu();
1256 +#endif // AMD64
1257 +
1258 + static juint cpu_microcode_revision();
1259 +
1260 + static jlong rdtsc();
1261 +
1262 + static bool is_allocatable(size_t bytes);
1263 +
1264 + // Used to register dynamic code cache area with the OS
1265 + // Note: Currently only used in 64 bit Windows implementations
1266 + static bool register_code_area(char *low, char *high) { return true; }
1267 +
1268 +#endif // OS_CPU_SOLARIS_X86_OS_SOLARIS_X86_HPP
1269 diff -urN /tmp/a/os_solaris_x86.inline.hpp b/src/hotspot/os_cpu/solaris_x86/os_solaris_x86.inline.hpp
1270 --- /tmp/a/os_solaris_x86.inline.hpp 1970-01-01 01:00:00.000000000 +0100
1271 +++ b/src/hotspot/os_cpu/solaris_x86/os_solaris_x86.inline.hpp 2024-09-17 15:41:04.684958901 +0100
1272 @@ -0,0 +1,39 @@
1273 +/*
1274 + * Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved.
1275 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1276 + *
1277 + * This code is free software; you can redistribute it and/or modify it
1278 + * under the terms of the GNU General Public License version 2 only, as
1279 + * published by the Free Software Foundation.
1280 + *
1281 + * This code is distributed in the hope that it will be useful, but WITHOUT
1282 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1283 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1284 + * version 2 for more details (a copy is included in the LICENSE file that
1285 + * accompanied this code).
1286 + *
1287 + * You should have received a copy of the GNU General Public License version
1288 + * 2 along with this work; if not, write to the Free Software Foundation,
1289 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1290 + *
1291 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1292 + * or visit www.oracle.com if you need additional information or have any
1293 + * questions.
1294 + *
1295 + */
1296 +
1297 +#ifndef OS_CPU_SOLARIS_X86_OS_SOLARIS_X86_INLINE_HPP
1298 +#define OS_CPU_SOLARIS_X86_OS_SOLARIS_X86_INLINE_HPP
1299 +
1300 +#include "runtime/os.hpp"
1301 +
1302 +// See http://www.technovelty.org/code/c/reading-rdtsc.htl for details
1303 +inline jlong os::rdtsc() {
1304 + uint64_t res;
1305 + uint32_t ts1, ts2;
1306 + __asm__ __volatile__ ("rdtsc" : "=a" (ts1), "=d" (ts2));
1307 + res = ((uint64_t)ts1 | (uint64_t)ts2 << 32);
1308 + return (jlong)res;
1309 +}
1310 +
1311 +#endif // OS_CPU_SOLARIS_X86_OS_SOLARIS_X86_INLINE_HPP
1312 diff -urN /tmp/a/prefetch_solaris_x86.inline.hpp b/src/hotspot/os_cpu/solaris_x86/prefetch_solaris_x86.inline.hpp
1313 --- /tmp/a/prefetch_solaris_x86.inline.hpp 1970-01-01 01:00:00.000000000 +0100
1314 +++ b/src/hotspot/os_cpu/solaris_x86/prefetch_solaris_x86.inline.hpp 2024-09-17 15:41:04.685088699 +0100
1315 @@ -0,0 +1,42 @@
1316 +/*
1317 + * Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
1318 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1319 + *
1320 + * This code is free software; you can redistribute it and/or modify it
1321 + * under the terms of the GNU General Public License version 2 only, as
1322 + * published by the Free Software Foundation.
1323 + *
1324 + * This code is distributed in the hope that it will be useful, but WITHOUT
1325 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1326 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1327 + * version 2 for more details (a copy is included in the LICENSE file that
1328 + * accompanied this code).
1329 + *
1330 + * You should have received a copy of the GNU General Public License version
1331 + * 2 along with this work; if not, write to the Free Software Foundation,
1332 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1333 + *
1334 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1335 + * or visit www.oracle.com if you need additional information or have any
1336 + * questions.
1337 + *
1338 + */
1339 +
1340 +#ifndef OS_CPU_SOLARIS_X86_PREFETCH_SOLARIS_X86_INLINE_HPP
1341 +#define OS_CPU_SOLARIS_X86_PREFETCH_SOLARIS_X86_INLINE_HPP
1342 +
1343 +#include "runtime/prefetch.hpp"
1344 +
1345 +inline void Prefetch::read (const void *loc, intx interval) {
1346 +#ifdef AMD64
1347 + __asm__ ("prefetcht0 (%0,%1,1)" : : "r" (loc), "r" (interval));
1348 +#endif // AMD64
1349 +}
1350 +
1351 +inline void Prefetch::write(void *loc, intx interval) {
1352 +#ifdef AMD64
1353 + __asm__ ("prefetcht0 (%0,%1,1)" : : "r" (loc), "r" (interval));
1354 +#endif // AMD64
1355 +}
1356 +
1357 +#endif // OS_CPU_SOLARIS_X86_PREFETCH_SOLARIS_X86_INLINE_HPP
1358 diff -urN /tmp/a/safefetch_solaris_x86_64.S b/src/hotspot/os_cpu/solaris_x86/safefetch_solaris_x86_64.S
1359 --- /tmp/a/safefetch_solaris_x86_64.S 1970-01-01 01:00:00.000000000 +0100
1360 +++ b/src/hotspot/os_cpu/solaris_x86/safefetch_solaris_x86_64.S 2024-09-17 15:41:04.756804071 +0100
1361 @@ -0,0 +1,58 @@
1362 +#
1363 +# Copyright (c) 2022 SAP SE. All rights reserved.
1364 +# Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved.
1365 +# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1366 +#
1367 +# This code is free software; you can redistribute it and/or modify it
1368 +# under the terms of the GNU General Public License version 2 only, as
1369 +# published by the Free Software Foundation.
1370 +#
1371 +# This code is distributed in the hope that it will be useful, but WITHOUT
1372 +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1373 +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1374 +# version 2 for more details (a copy is included in the LICENSE file that
1375 +# accompanied this code).
1376 +#
1377 +# You should have received a copy of the GNU General Public License version
1378 +# 2 along with this work; if not, write to the Free Software Foundation,
1379 +# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1380 +#
1381 +# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1382 +# or visit www.oracle.com if you need additional information or have any
1383 +# questions.
1384 +#
1385 + .globl SafeFetch32_impl
1386 + .globl SafeFetchN_impl
1387 + .globl _SafeFetch32_fault
1388 + .globl _SafeFetchN_fault
1389 + .globl _SafeFetch32_continuation
1390 + .globl _SafeFetchN_continuation
1391 +
1392 + .text
1393 +
1394 +
1395 + # Support for int SafeFetch32(int* address, int defaultval);
1396 + #
1397 + # %rdi : address
1398 + # %esi : defaultval
1399 + .type SafeFetch32_impl,@function
1400 +SafeFetch32_impl:
1401 +_SafeFetch32_fault:
1402 + movl (%rdi), %eax # load target value, may fault
1403 + ret
1404 +_SafeFetch32_continuation:
1405 + movl %esi, %eax # return default
1406 + ret
1407 +
1408 + # Support for intptr_t SafeFetchN(intptr_t* address, intptr_t defaultval);
1409 + #
1410 + # %rdi : address
1411 + # %rsi : defaultval
1412 + .type SafeFetchN_impl,@function
1413 +SafeFetchN_impl:
1414 +_SafeFetchN_fault:
1415 + movq (%rdi), %rax # load target value, may fault
1416 + ret
1417 +_SafeFetchN_continuation:
1418 + movq %rsi, %rax # return default
1419 + ret
1420 diff -urN /tmp/a/solaris_x86_64.S b/src/hotspot/os_cpu/solaris_x86/solaris_x86_64.S
1421 --- /tmp/a/solaris_x86_64.S 1970-01-01 01:00:00.000000000 +0100
1422 +++ b/src/hotspot/os_cpu/solaris_x86/solaris_x86_64.S 2024-09-17 15:41:04.685358762 +0100
1423 @@ -0,0 +1,386 @@
1424 +#
1425 +# Copyright (c) 2004, 2013, Oracle and/or its affiliates. All rights reserved.
1426 +# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1427 +#
1428 +# This code is free software; you can redistribute it and/or modify it
1429 +# under the terms of the GNU General Public License version 2 only, as
1430 +# published by the Free Software Foundation.
1431 +#
1432 +# This code is distributed in the hope that it will be useful, but WITHOUT
1433 +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1434 +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1435 +# version 2 for more details (a copy is included in the LICENSE file that
1436 +# accompanied this code).
1437 +#
1438 +# You should have received a copy of the GNU General Public License version
1439 +# 2 along with this work; if not, write to the Free Software Foundation,
1440 +# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1441 +#
1442 +# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1443 +# or visit www.oracle.com if you need additional information or have any
1444 +# questions.
1445 +#
1446 +
1447 + .globl fs_load
1448 + .globl fs_thread
1449 +
1450 + ## NOTE WELL! The _Copy functions are called directly
1451 + ## from server-compiler-generated code via CallLeafNoFP,
1452 + ## which means that they *must* either not use floating
1453 + ## point or use it in the same manner as does the server
1454 + ## compiler.
1455 +
1456 + .globl _Copy_arrayof_conjoint_bytes
1457 + .globl _Copy_conjoint_jshorts_atomic
1458 + .globl _Copy_arrayof_conjoint_jshorts
1459 + .globl _Copy_conjoint_jints_atomic
1460 + .globl _Copy_arrayof_conjoint_jints
1461 + .globl _Copy_conjoint_jlongs_atomic
1462 + .globl _Copy_arrayof_conjoint_jlongs
1463 +
1464 + .section .text,"ax"
1465 +
1466 + # Fast thread accessors, used by threadLS_solaris_amd64.cpp
1467 + .align 16
1468 +fs_load:
1469 + movq %fs:(%rdi),%rax
1470 + ret
1471 +
1472 + .align 16
1473 +fs_thread:
1474 + movq %fs:0x0,%rax
1475 + ret
1476 +
1477 + .globl SpinPause
1478 + .align 16
1479 +SpinPause:
1480 + rep
1481 + nop
1482 + movq $1, %rax
1483 + ret
1484 +
1485 +
1486 + # Support for void Copy::arrayof_conjoint_bytes(void* from,
1487 + # void* to,
1488 + # size_t count)
1489 + # rdi - from
1490 + # rsi - to
1491 + # rdx - count, treated as ssize_t
1492 + #
1493 + .align 16
1494 +_Copy_arrayof_conjoint_bytes:
1495 + movq %rdx,%r8 # byte count
1496 + shrq $3,%rdx # qword count
1497 + cmpq %rdi,%rsi
1498 + leaq -1(%rdi,%r8,1),%rax # from + bcount*1 - 1
1499 + jbe acb_CopyRight
1500 + cmpq %rax,%rsi
1501 + jbe acb_CopyLeft
1502 +acb_CopyRight:
1503 + leaq -8(%rdi,%rdx,8),%rax # from + qcount*8 - 8
1504 + leaq -8(%rsi,%rdx,8),%rcx # to + qcount*8 - 8
1505 + negq %rdx
1506 + jmp 7f
1507 + .align 16
1508 +1: movq 8(%rax,%rdx,8),%rsi
1509 + movq %rsi,8(%rcx,%rdx,8)
1510 + addq $1,%rdx
1511 + jnz 1b
1512 +2: testq $4,%r8 # check for trailing dword
1513 + jz 3f
1514 + movl 8(%rax),%esi # copy trailing dword
1515 + movl %esi,8(%rcx)
1516 + addq $4,%rax
1517 + addq $4,%rcx # original %rsi is trashed, so we
1518 + # can't use it as a base register
1519 +3: testq $2,%r8 # check for trailing word
1520 + jz 4f
1521 + movw 8(%rax),%si # copy trailing word
1522 + movw %si,8(%rcx)
1523 + addq $2,%rcx
1524 +4: testq $1,%r8 # check for trailing byte
1525 + jz 5f
1526 + movb -1(%rdi,%r8,1),%al # copy trailing byte
1527 + movb %al,8(%rcx)
1528 +5: ret
1529 + .align 16
1530 +6: movq -24(%rax,%rdx,8),%rsi
1531 + movq %rsi,-24(%rcx,%rdx,8)
1532 + movq -16(%rax,%rdx,8),%rsi
1533 + movq %rsi,-16(%rcx,%rdx,8)
1534 + movq -8(%rax,%rdx,8),%rsi
1535 + movq %rsi,-8(%rcx,%rdx,8)
1536 + movq (%rax,%rdx,8),%rsi
1537 + movq %rsi,(%rcx,%rdx,8)
1538 +7: addq $4,%rdx
1539 + jle 6b
1540 + subq $4,%rdx
1541 + jl 1b
1542 + jmp 2b
1543 +acb_CopyLeft:
1544 + testq $1,%r8 # check for trailing byte
1545 + jz 1f
1546 + movb -1(%rdi,%r8,1),%cl # copy trailing byte
1547 + movb %cl,-1(%rsi,%r8,1)
1548 + subq $1,%r8 # adjust for possible trailing word
1549 +1: testq $2,%r8 # check for trailing word
1550 + jz 2f
1551 + movw -2(%rdi,%r8,1),%cx # copy trailing word
1552 + movw %cx,-2(%rsi,%r8,1)
1553 +2: testq $4,%r8 # check for trailing dword
1554 + jz 5f
1555 + movl (%rdi,%rdx,8),%ecx # copy trailing dword
1556 + movl %ecx,(%rsi,%rdx,8)
1557 + jmp 5f
1558 + .align 16
1559 +3: movq -8(%rdi,%rdx,8),%rcx
1560 + movq %rcx,-8(%rsi,%rdx,8)
1561 + subq $1,%rdx
1562 + jnz 3b
1563 + ret
1564 + .align 16
1565 +4: movq 24(%rdi,%rdx,8),%rcx
1566 + movq %rcx,24(%rsi,%rdx,8)
1567 + movq 16(%rdi,%rdx,8),%rcx
1568 + movq %rcx,16(%rsi,%rdx,8)
1569 + movq 8(%rdi,%rdx,8),%rcx
1570 + movq %rcx,8(%rsi,%rdx,8)
1571 + movq (%rdi,%rdx,8),%rcx
1572 + movq %rcx,(%rsi,%rdx,8)
1573 +5: subq $4,%rdx
1574 + jge 4b
1575 + addq $4,%rdx
1576 + jg 3b
1577 + ret
1578 +
1579 + # Support for void Copy::arrayof_conjoint_jshorts(void* from,
1580 + # void* to,
1581 + # size_t count)
1582 + # Equivalent to
1583 + # conjoint_jshorts_atomic
1584 + #
1585 + # If 'from' and/or 'to' are aligned on 4- or 2-byte boundaries, we
1586 + # let the hardware handle it. The tow or four words within dwords
1587 + # or qwords that span cache line boundaries will still be loaded
1588 + # and stored atomically.
1589 + #
1590 + # rdi - from
1591 + # rsi - to
1592 + # rdx - count, treated as ssize_t
1593 + #
1594 + .align 16
1595 +_Copy_arrayof_conjoint_jshorts:
1596 +_Copy_conjoint_jshorts_atomic:
1597 + movq %rdx,%r8 # word count
1598 + shrq $2,%rdx # qword count
1599 + cmpq %rdi,%rsi
1600 + leaq -2(%rdi,%r8,2),%rax # from + wcount*2 - 2
1601 + jbe acs_CopyRight
1602 + cmpq %rax,%rsi
1603 + jbe acs_CopyLeft
1604 +acs_CopyRight:
1605 + leaq -8(%rdi,%rdx,8),%rax # from + qcount*8 - 8
1606 + leaq -8(%rsi,%rdx,8),%rcx # to + qcount*8 - 8
1607 + negq %rdx
1608 + jmp 6f
1609 +1: movq 8(%rax,%rdx,8),%rsi
1610 + movq %rsi,8(%rcx,%rdx,8)
1611 + addq $1,%rdx
1612 + jnz 1b
1613 +2: testq $2,%r8 # check for trailing dword
1614 + jz 3f
1615 + movl 8(%rax),%esi # copy trailing dword
1616 + movl %esi,8(%rcx)
1617 + addq $4,%rcx # original %rsi is trashed, so we
1618 + # can't use it as a base register
1619 +3: testq $1,%r8 # check for trailing word
1620 + jz 4f
1621 + movw -2(%rdi,%r8,2),%si # copy trailing word
1622 + movw %si,8(%rcx)
1623 +4: ret
1624 + .align 16
1625 +5: movq -24(%rax,%rdx,8),%rsi
1626 + movq %rsi,-24(%rcx,%rdx,8)
1627 + movq -16(%rax,%rdx,8),%rsi
1628 + movq %rsi,-16(%rcx,%rdx,8)
1629 + movq -8(%rax,%rdx,8),%rsi
1630 + movq %rsi,-8(%rcx,%rdx,8)
1631 + movq (%rax,%rdx,8),%rsi
1632 + movq %rsi,(%rcx,%rdx,8)
1633 +6: addq $4,%rdx
1634 + jle 5b
1635 + subq $4,%rdx
1636 + jl 1b
1637 + jmp 2b
1638 +acs_CopyLeft:
1639 + testq $1,%r8 # check for trailing word
1640 + jz 1f
1641 + movw -2(%rdi,%r8,2),%cx # copy trailing word
1642 + movw %cx,-2(%rsi,%r8,2)
1643 +1: testq $2,%r8 # check for trailing dword
1644 + jz 4f
1645 + movl (%rdi,%rdx,8),%ecx # copy trailing dword
1646 + movl %ecx,(%rsi,%rdx,8)
1647 + jmp 4f
1648 +2: movq -8(%rdi,%rdx,8),%rcx
1649 + movq %rcx,-8(%rsi,%rdx,8)
1650 + subq $1,%rdx
1651 + jnz 2b
1652 + ret
1653 + .align 16
1654 +3: movq 24(%rdi,%rdx,8),%rcx
1655 + movq %rcx,24(%rsi,%rdx,8)
1656 + movq 16(%rdi,%rdx,8),%rcx
1657 + movq %rcx,16(%rsi,%rdx,8)
1658 + movq 8(%rdi,%rdx,8),%rcx
1659 + movq %rcx,8(%rsi,%rdx,8)
1660 + movq (%rdi,%rdx,8),%rcx
1661 + movq %rcx,(%rsi,%rdx,8)
1662 +4: subq $4,%rdx
1663 + jge 3b
1664 + addq $4,%rdx
1665 + jg 2b
1666 + ret
1667 +
1668 + # Support for void Copy::arrayof_conjoint_jints(jint* from,
1669 + # jint* to,
1670 + # size_t count)
1671 + # Equivalent to
1672 + # conjoint_jints_atomic
1673 + #
1674 + # If 'from' and/or 'to' are aligned on 4-byte boundaries, we let
1675 + # the hardware handle it. The two dwords within qwords that span
1676 + # cache line boundaries will still be loaded and stored atomically.
1677 + #
1678 + # rdi - from
1679 + # rsi - to
1680 + # rdx - count, treated as ssize_t
1681 + #
1682 + .align 16
1683 +_Copy_arrayof_conjoint_jints:
1684 +_Copy_conjoint_jints_atomic:
1685 + movq %rdx,%r8 # dword count
1686 + shrq %rdx # qword count
1687 + cmpq %rdi,%rsi
1688 + leaq -4(%rdi,%r8,4),%rax # from + dcount*4 - 4
1689 + jbe aci_CopyRight
1690 + cmpq %rax,%rsi
1691 + jbe aci_CopyLeft
1692 +aci_CopyRight:
1693 + leaq -8(%rdi,%rdx,8),%rax # from + qcount*8 - 8
1694 + leaq -8(%rsi,%rdx,8),%rcx # to + qcount*8 - 8
1695 + negq %rdx
1696 + jmp 5f
1697 + .align 16
1698 +1: movq 8(%rax,%rdx,8),%rsi
1699 + movq %rsi,8(%rcx,%rdx,8)
1700 + addq $1,%rdx
1701 + jnz 1b
1702 +2: testq $1,%r8 # check for trailing dword
1703 + jz 3f
1704 + movl 8(%rax),%esi # copy trailing dword
1705 + movl %esi,8(%rcx)
1706 +3: ret
1707 + .align 16
1708 +4: movq -24(%rax,%rdx,8),%rsi
1709 + movq %rsi,-24(%rcx,%rdx,8)
1710 + movq -16(%rax,%rdx,8),%rsi
1711 + movq %rsi,-16(%rcx,%rdx,8)
1712 + movq -8(%rax,%rdx,8),%rsi
1713 + movq %rsi,-8(%rcx,%rdx,8)
1714 + movq (%rax,%rdx,8),%rsi
1715 + movq %rsi,(%rcx,%rdx,8)
1716 +5: addq $4,%rdx
1717 + jle 4b
1718 + subq $4,%rdx
1719 + jl 1b
1720 + jmp 2b
1721 +aci_CopyLeft:
1722 + testq $1,%r8 # check for trailing dword
1723 + jz 3f
1724 + movl -4(%rdi,%r8,4),%ecx # copy trailing dword
1725 + movl %ecx,-4(%rsi,%r8,4)
1726 + jmp 3f
1727 +1: movq -8(%rdi,%rdx,8),%rcx
1728 + movq %rcx,-8(%rsi,%rdx,8)
1729 + subq $1,%rdx
1730 + jnz 1b
1731 + ret
1732 + .align 16
1733 +2: movq 24(%rdi,%rdx,8),%rcx
1734 + movq %rcx,24(%rsi,%rdx,8)
1735 + movq 16(%rdi,%rdx,8),%rcx
1736 + movq %rcx,16(%rsi,%rdx,8)
1737 + movq 8(%rdi,%rdx,8),%rcx
1738 + movq %rcx,8(%rsi,%rdx,8)
1739 + movq (%rdi,%rdx,8),%rcx
1740 + movq %rcx,(%rsi,%rdx,8)
1741 +3: subq $4,%rdx
1742 + jge 2b
1743 + addq $4,%rdx
1744 + jg 1b
1745 + ret
1746 +
1747 + # Support for void Copy::arrayof_conjoint_jlongs(jlong* from,
1748 + # jlong* to,
1749 + # size_t count)
1750 + # Equivalent to
1751 + # conjoint_jlongs_atomic
1752 + # arrayof_conjoint_oops
1753 + # conjoint_oops_atomic
1754 + #
1755 + # rdi - from
1756 + # rsi - to
1757 + # rdx - count, treated as ssize_t
1758 + #
1759 + .align 16
1760 +_Copy_arrayof_conjoint_jlongs:
1761 +_Copy_conjoint_jlongs_atomic:
1762 + cmpq %rdi,%rsi
1763 + leaq -8(%rdi,%rdx,8),%rax # from + count*8 - 8
1764 + jbe acl_CopyRight
1765 + cmpq %rax,%rsi
1766 + jbe acl_CopyLeft
1767 +acl_CopyRight:
1768 + leaq -8(%rsi,%rdx,8),%rcx # to + count*8 - 8
1769 + negq %rdx
1770 + jmp 3f
1771 +1: movq 8(%rax,%rdx,8),%rsi
1772 + movq %rsi,8(%rcx,%rdx,8)
1773 + addq $1,%rdx
1774 + jnz 1b
1775 + ret
1776 + .align 16
1777 +2: movq -24(%rax,%rdx,8),%rsi
1778 + movq %rsi,-24(%rcx,%rdx,8)
1779 + movq -16(%rax,%rdx,8),%rsi
1780 + movq %rsi,-16(%rcx,%rdx,8)
1781 + movq -8(%rax,%rdx,8),%rsi
1782 + movq %rsi,-8(%rcx,%rdx,8)
1783 + movq (%rax,%rdx,8),%rsi
1784 + movq %rsi,(%rcx,%rdx,8)
1785 +3: addq $4,%rdx
1786 + jle 2b
1787 + subq $4,%rdx
1788 + jl 1b
1789 + ret
1790 +4: movq -8(%rdi,%rdx,8),%rcx
1791 + movq %rcx,-8(%rsi,%rdx,8)
1792 + subq $1,%rdx
1793 + jnz 4b
1794 + ret
1795 + .align 16
1796 +5: movq 24(%rdi,%rdx,8),%rcx
1797 + movq %rcx,24(%rsi,%rdx,8)
1798 + movq 16(%rdi,%rdx,8),%rcx
1799 + movq %rcx,16(%rsi,%rdx,8)
1800 + movq 8(%rdi,%rdx,8),%rcx
1801 + movq %rcx,8(%rsi,%rdx,8)
1802 + movq (%rdi,%rdx,8),%rcx
1803 + movq %rcx,(%rsi,%rdx,8)
1804 +acl_CopyLeft:
1805 + subq $4,%rdx
1806 + jge 5b
1807 + addq $4,%rdx
1808 + jg 4b
1809 + ret
1810 diff -urN /tmp/a/vmStructs_solaris_x86.hpp b/src/hotspot/os_cpu/solaris_x86/vmStructs_solaris_x86.hpp
1811 --- /tmp/a/vmStructs_solaris_x86.hpp 1970-01-01 01:00:00.000000000 +0100
1812 +++ b/src/hotspot/os_cpu/solaris_x86/vmStructs_solaris_x86.hpp 2024-09-17 15:41:04.685774270 +0100
1813 @@ -0,0 +1,40 @@
1814 +/*
1815 + * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
1816 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1817 + *
1818 + * This code is free software; you can redistribute it and/or modify it
1819 + * under the terms of the GNU General Public License version 2 only, as
1820 + * published by the Free Software Foundation.
1821 + *
1822 + * This code is distributed in the hope that it will be useful, but WITHOUT
1823 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1824 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1825 + * version 2 for more details (a copy is included in the LICENSE file that
1826 + * accompanied this code).
1827 + *
1828 + * You should have received a copy of the GNU General Public License version
1829 + * 2 along with this work; if not, write to the Free Software Foundation,
1830 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1831 + *
1832 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1833 + * or visit www.oracle.com if you need additional information or have any
1834 + * questions.
1835 + *
1836 + */
1837 +
1838 +#ifndef OS_CPU_SOLARIS_X86_VMSTRUCTS_SOLARIS_X86_HPP
1839 +#define OS_CPU_SOLARIS_X86_VMSTRUCTS_SOLARIS_X86_HPP
1840 +
1841 +// These are the OS and CPU-specific fields, types and integer
1842 +// constants required by the Serviceability Agent. This file is
1843 +// referenced by vmStructs.cpp.
1844 +
1845 +#define VM_STRUCTS_OS_CPU(nonstatic_field, static_field, unchecked_nonstatic_field, volatile_nonstatic_field, nonproduct_nonstatic_field, c2_nonstatic_field, unchecked_c1_static_field, unchecked_c2_static_field)
1846 +
1847 +#define VM_TYPES_OS_CPU(declare_type, declare_toplevel_type, declare_oop_type, declare_integer_type, declare_unsigned_integer_type, declare_c1_toplevel_type, declare_c2_type, declare_c2_toplevel_type)
1848 +
1849 +#define VM_INT_CONSTANTS_OS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant)
1850 +
1851 +#define VM_LONG_CONSTANTS_OS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant)
1852 +
1853 +#endif // OS_CPU_SOLARIS_X86_VMSTRUCTS_SOLARIS_X86_HPP
1854 diff -urN /tmp/a/vm_version_solaris_x86.cpp b/src/hotspot/os_cpu/solaris_x86/vm_version_solaris_x86.cpp
1855 --- /tmp/a/vm_version_solaris_x86.cpp 1970-01-01 01:00:00.000000000 +0100
1856 +++ b/src/hotspot/os_cpu/solaris_x86/vm_version_solaris_x86.cpp 2024-09-17 15:41:04.685894613 +0100
1857 @@ -0,0 +1,28 @@
1858 +/*
1859 + * Copyright (c) 2006, 2019, Oracle and/or its affiliates. All rights reserved.
1860 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1861 + *
1862 + * This code is free software; you can redistribute it and/or modify it
1863 + * under the terms of the GNU General Public License version 2 only, as
1864 + * published by the Free Software Foundation.
1865 + *
1866 + * This code is distributed in the hope that it will be useful, but WITHOUT
1867 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1868 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1869 + * version 2 for more details (a copy is included in the LICENSE file that
1870 + * accompanied this code).
1871 + *
1872 + * You should have received a copy of the GNU General Public License version
1873 + * 2 along with this work; if not, write to the Free Software Foundation,
1874 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1875 + *
1876 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1877 + * or visit www.oracle.com if you need additional information or have any
1878 + * questions.
1879 + *
1880 + */
1881 +
1882 +#include "precompiled.hpp"
1883 +#include "runtime/os.hpp"
1884 +#include "runtime/vm_version.hpp"
1885 +