| blob | a8beea47890f994cbf7c4d25db5ab3289ad508c5 |
1 diff -Nur linux-5.10.93.orig/arch/nds32/boot/dts/ag101p.dts linux-5.10.93/arch/nds32/boot/dts/ag101p.dts
2 --- linux-5.10.93.orig/arch/nds32/boot/dts/ag101p.dts 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-5.10.93/arch/nds32/boot/dts/ag101p.dts 2022-01-21 03:39:21.936044612 +0100
4 @@ -0,0 +1,60 @@
5 +/dts-v1/;
6 +/ {
7 + compatible = "nds32 ag101p";
8 + #address-cells = <1>;
9 + #size-cells = <1>;
10 + interrupt-parent = <&intc>;
11 +
12 + chosen {
13 + bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug loglevel=7";
14 + };
15 +
16 + memory@0 {
17 + device_type = "memory";
18 + reg = <0x00000000 0x40000000>;
19 + };
20 +
21 + cpus {
22 + cpu@0 {
23 + device_type = "cpu";
24 + compatible = "andestech,n13";
25 + next-level-cache = <&L2>;
26 + };
27 + };
28 +
29 + intc: interrupt-controller {
30 + compatible = "andestech,atnointc010";
31 + #interrupt-cells = <2>;
32 + interrupt-controller;
33 + };
34 +
35 + serial0: serial@99600000 {
36 + compatible = "andestech,uart16550", "ns16550a";
37 + reg = <0x99600000 0x1000>;
38 + interrupts = <7 4>;
39 + clock-frequency = <14745600>;
40 + reg-shift = <2>;
41 + no-loopback-test = <1>;
42 + };
43 +
44 + timer0: timer@98400000 {
45 + compatible = "andestech,atftmr010";
46 + reg = <0x98400000 0x1000>;
47 + interrupts = <19 4>;
48 + clock-frequency = <15000000>;
49 + cycle-count-offset = <0x20>;
50 + };
51 +
52 + mac0: mac@90900000 {
53 + compatible = "andestech,atmac100";
54 + reg = <0x90900000 0x1000>;
55 + interrupts = <25 4>;
56 + };
57 +
58 + L2: l2-cache {
59 + compatible = "andestech,atl2c";
60 + reg = <0x90f00000 0x1000>;
61 + cache-unified;
62 + cache-level = <2>;
63 + };
64 +};