drivers/pci.h

   1 #ifndef PCI_H
   2 #define PCI_H
   3
   4 #define PCI_VENDOR_ID           0x00
   5 #define PCI_DEVICE_ID           0x02
   6
   7 #define PCI_COMMAND             0x04
   8 #define  PCI_COMMAND_IO         0x01
   9 #define  PCI_COMMAND_MEMORY     0x02
  10
  11 #define PCI_STATUS              0x06    /* 16 bits */
  12 #define  PCI_STATUS_CAP_LIST    0x10    /* Support Capability List */
  13 #define  PCI_STATUS_66MHZ       0x20    /* Support 66 Mhz PCI 2.1 bus */
  14 #define  PCI_STATUS_UDF         0x40    /* Support User Definable Features
  15                                            [obsolete] */
  16 #define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
  17 #define  PCI_STATUS_PARITY      0x100   /* Detected parity error */
  18 #define  PCI_STATUS_DEVSEL_MASK 0x600   /* DEVSEL timing */
  19 #define  PCI_STATUS_DEVSEL_FAST 0x000
  20 #define  PCI_STATUS_DEVSEL_MEDIUM 0x200
  21 #define  PCI_STATUS_DEVSEL_SLOW 0x400
  22 #define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
  23 #define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
  24 #define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
  25 #define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
  26 #define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
  27
  28
  29 #define PCI_REVISION_ID         0x08    /* Revision ID */
  30 #define PCI_CLASS_PROG          0x09
  31 #define PCI_CLASS_DEVICE        0x0a
  32 #define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
  33 #define PCI_HEADER_TYPE         0x0e
  34 #define  PCI_HEADER_TYPE_NORMAL 0x00
  35 #define  PCI_HEADER_TYPE_BRIDGE 0x01
  36 #define  PCI_HEADER_TYPE_CARDBUS 0x02
  37 #define PCI_PRIMARY_BUS     0x18
  38 #define PCI_SECONDARY_BUS   0x19
  39 #define PCI_SUBORDINATE_BUS 0x1A
  40 #define PCI_BASE_ADDR_0         0x10
  41 #define PCI_BASE_ADDR_1         0x14
  42 #define PCI_BASE_ADDR_2         0x18
  43 #define PCI_BASE_ADDR_3         0x1c
  44 #define PCI_BASE_ADDR_4         0x20
  45 #define PCI_BASE_ADDR_5         0x24
  46
  47 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
  48 #define PCI_SUBSYSTEM_ID        0x2e
  49
  50 #define PCI_ROM_ADDRESS         0x30    /* Bits 31..11 are address, 10..1 reserved */
  51 #define PCI_ROM_ADDRESS_ENABLE  0x01
  52 #define PCI_ROM_ADDRESS_MASK    (~0x7ffUL)
  53 #define PCI_ROM_ADDRESS1        0x38    /* ROM_ADDRESS in bridge header */
  54
  55 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
  56 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
  57 #define PCI_MIN_GNT             0x3e    /* 8 bits */
  58 #define PCI_MAX_LAT             0x3f    /* 8 bits */
  59
  60 typedef struct {
  61         u16     signature;
  62         u8      reserved[0x16];
  63         u16     dptr;
  64 } rom_header_t;
  65
  66 typedef struct {
  67         u32     signature;
  68         u16     vendor;
  69         u16     device;
  70         u16     reserved_1;
  71         u16     dlen;
  72         u8      drevision;
  73         u8      class_hi;
  74         u16     class_lo;
  75         u16     ilen;
  76         u16     irevision;
  77         u8      type;
  78         u8      indicator;
  79         u16     reserved_2;
  80 } pci_data_t;
  81
  82
  83 #include "asm/pci.h"
  84
  85 #endif /* PCI_H */