drivers/vga.h

   1 /*
   2  *
   3  * modified
   4  * by Steve M. Gehlbach <steve@kesa.com>
   5  *
   6  * Originally  from linux/drivers/video/vga16.c by
   7  * Ben Pfaff <pfaffben@debian.org> and Petr Vandrovec <VANDROVE@vc.cvut.cz>
   8  * Copyright 1999 Ben Pfaff <pfaffben@debian.org> and Petr Vandrovec <VANDROVE@vc.cvut.cz>
   9  * Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm
  10  * Based on VESA framebuffer (c) 1998 Gerd Knorr <kraxel@goldbach.in-berlin.de>
  11  *
  12  */
  13
  14 #ifndef VGA_H_INCL
  15 #define VGA_H_INCL 1
  16
  17 #include "drivers/vga.h"
  18
  19 //#include <cpu/p5/io.h>
  20
  21 #define u8 unsigned char
  22 #define u16 unsigned short
  23 #define u32 unsigned int
  24 #define __u32 u32
  25
  26 #define VERROR -1
  27 #define CHAR_HEIGHT 16
  28 #define LINES 25
  29 #define COLS 80
  30
  31 // macros for writing to vga regs
  32 #define write_crtc(data,addr) outb(addr,CRT_IC); outb(data,CRT_DC)
  33 #define write_att(data,addr) inb(IS1_RC); inb(0x80); outb(addr,ATT_IW); inb(0x80); outb(data,ATT_IW); inb(0x80)
  34 #define write_seq(data,addr) outb(addr,SEQ_I); outb(data,SEQ_D)
  35 #define write_gra(data,addr) outb(addr,GRA_I); outb(data,GRA_D)
  36 u8 read_seq_b(u16 addr);
  37 u8 read_gra_b(u16 addr);
  38 u8 read_crtc_b(u16 addr);
  39 u8 read_att_b(u16 addr);
  40
  41
  42 #ifdef VGA_HARDWARE_FIXUP
  43 void vga_hardware_fixup(void);
  44 #else
  45 #define vga_hardware_fixup() do{} while(0)
  46 #endif
  47
  48 #define SYNC_HOR_HIGH_ACT    1       /* horizontal sync high active  */
  49 #define SYNC_VERT_HIGH_ACT   2       /* vertical sync high active    */
  50 #define SYNC_EXT             4       /* external sync                */
  51 #define SYNC_COMP_HIGH_ACT   8       /* composite sync high active   */
  52 #define SYNC_BROADCAST       16      /* broadcast video timings      */
  53                                         /* vtotal = 144d/288n/576i => PAL  */
  54                                         /* vtotal = 121d/242n/484i => NTSC */
  55
  56 #define SYNC_ON_GREEN        32      /* sync on green */
  57
  58 #define VMODE_NONINTERLACED  0       /* non interlaced */
  59 #define VMODE_INTERLACED     1       /* interlaced   */
  60 #define VMODE_DOUBLE         2       /* double scan */
  61 #define VMODE_MASK           255
  62
  63 #define VMODE_YWRAP          256     /* ywrap instead of panning     */
  64 #define VMODE_SMOOTH_XPAN    512     /* smooth xpan possible (internally used) */
  65 #define VMODE_CONUPDATE      512     /* don't update x/yoffset       */
  66
  67 /* VGA data register ports */
  68 #define CRT_DC  0x3D5           /* CRT Controller Data Register - color emulation */
  69 #define CRT_DM  0x3B5           /* CRT Controller Data Register - mono emulation */
  70 #define ATT_R   0x3C1           /* Attribute Controller Data Read Register */
  71 #define GRA_D   0x3CF           /* Graphics Controller Data Register */
  72 #define SEQ_D   0x3C5           /* Sequencer Data Register */
  73
  74 #define MIS_R   0x3CC           // Misc Output Read Register
  75 #define MIS_W   0x3C2           // Misc Output Write Register
  76
  77 #define IS1_RC  0x3DA           /* Input Status Register 1 - color emulation */
  78 #define IS1_RM  0x3BA           /* Input Status Register 1 - mono emulation */
  79 #define PEL_D   0x3C9           /* PEL Data Register */
  80 #define PEL_MSK 0x3C6           /* PEL mask register */
  81
  82 /* EGA-specific registers */
  83 #define GRA_E0  0x3CC           /* Graphics enable processor 0 */
  84 #define GRA_E1  0x3CA           /* Graphics enable processor 1 */
  85
  86
  87 /* VGA index register ports */
  88 #define CRT_IC  0x3D4           /* CRT Controller Index - color emulation */
  89 #define CRT_IM  0x3B4           /* CRT Controller Index - mono emulation */
  90 #define ATT_IW  0x3C0           /* Attribute Controller Index & Data Write Register */
  91 #define GRA_I   0x3CE           /* Graphics Controller Index */
  92 #define SEQ_I   0x3C4           /* Sequencer Index */
  93 #define PEL_IW  0x3C8           /* PEL Write Index */
  94 #define PEL_IR  0x3C7           /* PEL Read Index */
  95 #define DAC_REG 0x3C8           /* DAC register */
  96 #define DAC_VAL 0x3C9           /* DAC value */
  97
  98 /* standard VGA indexes max counts */
  99 #define CRTC_C   25              /* 25 CRT Controller Registers sequentially set*/
 100                                                                  // the remainder are not in the par array
 101 #define ATT_C   21              /* 21 Attribute Controller Registers */
 102 #define GRA_C   9               /* 9  Graphics Controller Registers */
 103 #define SEQ_C   5               /* 5  Sequencer Registers */
 104 #define MIS_C   1               /* 1  Misc Output Register */
 105
 106 #define CRTC_H_TOTAL            0
 107 #define CRTC_H_DISP             1
 108 #define CRTC_H_BLANK_START      2
 109 #define CRTC_H_BLANK_END        3
 110 #define CRTC_H_SYNC_START       4
 111 #define CRTC_H_SYNC_END         5
 112 #define CRTC_V_TOTAL            6
 113 #define CRTC_OVERFLOW           7
 114 #define CRTC_PRESET_ROW         8
 115 #define CRTC_MAX_SCAN           9
 116 #define CRTC_CURSOR_START       0x0A
 117 #define CRTC_CURSOR_END         0x0B
 118 #define CRTC_START_HI           0x0C
 119 #define CRTC_START_LO           0x0D
 120 #define CRTC_CURSOR_HI          0x0E
 121 #define CRTC_CURSOR_LO          0x0F
 122 #define CRTC_V_SYNC_START       0x10
 123 #define CRTC_V_SYNC_END         0x11
 124 #define CRTC_V_DISP_END         0x12
 125 #define CRTC_OFFSET             0x13
 126 #define CRTC_UNDERLINE          0x14
 127 #define CRTC_V_BLANK_START      0x15
 128 #define CRTC_V_BLANK_END        0x16
 129 #define CRTC_MODE               0x17
 130 #define CRTC_LINE_COMPARE       0x18
 131
 132 #define ATC_MODE                0x10
 133 #define ATC_OVERSCAN            0x11
 134 #define ATC_PLANE_ENABLE        0x12
 135 #define ATC_PEL                 0x13
 136 #define ATC_COLOR_PAGE          0x14
 137
 138 #define SEQ_CLOCK_MODE          0x01
 139 #define SEQ_PLANE_WRITE         0x02
 140 #define SEQ_CHARACTER_MAP       0x03
 141 #define SEQ_MEMORY_MODE         0x04
 142
 143 #define GDC_SR_VALUE            0x00
 144 #define GDC_SR_ENABLE           0x01
 145 #define GDC_COMPARE_VALUE       0x02
 146 #define GDC_DATA_ROTATE         0x03
 147 #define GDC_PLANE_READ          0x04
 148 #define GDC_MODE                0x05
 149 #define GDC_MISC                0x06
 150 #define GDC_COMPARE_MASK        0x07
 151 #define GDC_BIT_MASK            0x08
 152
 153 // text attributes
 154 #define VGA_ATTR_CLR_RED 0x4
 155 #define VGA_ATTR_CLR_GRN 0x2
 156 #define VGA_ATTR_CLR_BLU 0x1
 157 #define VGA_ATTR_CLR_YEL (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN)
 158 #define VGA_ATTR_CLR_CYN (VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU)
 159 #define VGA_ATTR_CLR_MAG (VGA_ATTR_CLR_BLU | VGA_ATTR_CLR_RED)
 160 #define VGA_ATTR_CLR_BLK 0
 161 #define VGA_ATTR_CLR_WHT (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU)
 162 #define VGA_ATTR_BNK     0x80
 163 #define VGA_ATTR_ITN     0x08
 164
 165 /*
 166  * vga register parameters
 167  * these are copied to the
 168  * registers.
 169  *
 170  */
 171 struct vga_par {
 172         u8 crtc[CRTC_C];
 173         u8 atc[ATT_C];
 174         u8 gdc[GRA_C];
 175         u8 seq[SEQ_C];
 176         u8 misc; // the misc register, MIS_W
 177         u8 vss;
 178 };
 179
 180
 181 /* Interpretation of offset for color fields: All offsets are from the right,
 182  * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
 183  * can use the offset as right argument to <<). A pixel afterwards is a bit
 184  * stream and is written to video memory as that unmodified. This implies
 185  * big-endian byte order if bits_per_pixel is greater than 8.
 186  */
 187 struct fb_bitfield {
 188         __u32 offset;                   /* beginning of bitfield        */
 189         __u32 length;                   /* length of bitfield           */
 190         __u32 msb_right;                /* != 0 : Most significant bit is */
 191                                         /* right */
 192 };
 193
 194 struct screeninfo {
 195         __u32 xres;                     /* visible resolution           */
 196         __u32 yres;
 197         __u32 xres_virtual;             /* virtual resolution           */
 198         __u32 yres_virtual;
 199         __u32 xoffset;                  /* offset from virtual to visible */
 200         __u32 yoffset;                  /* resolution                   */
 201
 202         __u32 bits_per_pixel;           /* guess what                   */
 203         __u32 grayscale;                /* != 0 Graylevels instead of colors */
 204
 205         struct fb_bitfield red;         /* bitfield in fb mem if true color, */
 206         struct fb_bitfield green;       /* else only length is significant */
 207         struct fb_bitfield blue;
 208         struct fb_bitfield transp;      /* transparency                 */
 209
 210         __u32 nonstd;                   /* != 0 Non standard pixel format */
 211
 212         __u32 activate;                 /* see FB_ACTIVATE_*            */
 213
 214         __u32 height;                   /* height of picture in mm    */
 215         __u32 width;                    /* width of picture in mm     */
 216
 217         __u32 accel_flags;              /* acceleration flags (hints)   */
 218
 219         /* Timing: All values in pixclocks, except pixclock (of course) */
 220         __u32 pixclock;                 /* pixel clock in ps (pico seconds) */
 221         __u32 left_margin;              /* time from sync to picture    */
 222         __u32 right_margin;             /* time from picture to sync    */
 223         __u32 upper_margin;             /* time from sync to picture    */
 224         __u32 lower_margin;
 225         __u32 hsync_len;                /* length of horizontal sync    */
 226         __u32 vsync_len;                /* length of vertical sync      */
 227         __u32 sync;                     /* sync polarity                */
 228         __u32 vmode;                    /* interlaced etc                               */
 229         __u32 reserved[6];              /* Reserved for future compatibility */
 230 };
 231 #endif