drivers/esp.h

   1 /* $Id: esp.h,v 1.28 2000/03/30 01:33:17 davem Exp $
   2  * esp.h:  Defines and structures for the Sparc ESP (Enhanced SCSI
   3  *         Processor) driver under Linux.
   4  *
   5  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   6  */
   7
   8 #ifndef _SPARC_ESP_H
   9 #define _SPARC_ESP_H
  10
  11 /* For dvma controller register definitions. */
  12 #include "asm/dma.h"
  13
  14 /* The ESP SCSI controllers have their register sets in three
  15  * "classes":
  16  *
  17  * 1) Registers which are both read and write.
  18  * 2) Registers which are read only.
  19  * 3) Registers which are write only.
  20  *
  21  * Yet, they all live within the same IO space.
  22  */
  23
  24 /* All the ESP registers are one byte each and are accessed longwords
  25  * apart with a big-endian ordering to the bytes.
  26  */
  27                                         /* Access    Description              Offset */
  28 #define ESP_TCLOW       0x00UL          /* rw  Low bits of the transfer count 0x00   */
  29 #define ESP_TCMED       0x04UL          /* rw  Mid bits of the transfer count 0x04   */
  30 #define ESP_FDATA       0x08UL          /* rw  FIFO data bits                 0x08   */
  31 #define ESP_CMD         0x0cUL          /* rw  SCSI command bits              0x0c   */
  32 #define ESP_STATUS      0x10UL          /* ro  ESP status register            0x10   */
  33 #define ESP_BUSID       ESP_STATUS      /* wo  Bus ID for select/reselect     0x10   */
  34 #define ESP_INTRPT      0x14UL          /* ro  Kind of interrupt              0x14   */
  35 #define ESP_TIMEO       ESP_INTRPT      /* wo  Timeout value for select/resel 0x14   */
  36 #define ESP_SSTEP       0x18UL          /* ro  Sequence step register         0x18   */
  37 #define ESP_STP         ESP_SSTEP       /* wo  Transfer period per sync       0x18   */
  38 #define ESP_FFLAGS      0x1cUL          /* ro  Bits of current FIFO info      0x1c   */
  39 #define ESP_SOFF        ESP_FFLAGS      /* wo  Sync offset                    0x1c   */
  40 #define ESP_CFG1        0x20UL          /* rw  First configuration register   0x20   */
  41 #define ESP_CFACT       0x24UL          /* wo  Clock conversion factor        0x24   */
  42 #define ESP_STATUS2     ESP_CFACT       /* ro  HME status2 register           0x24   */
  43 #define ESP_CTEST       0x28UL          /* wo  Chip test register             0x28   */
  44 #define ESP_CFG2        0x2cUL          /* rw  Second configuration register  0x2c   */
  45 #define ESP_CFG3        0x30UL          /* rw  Third configuration register   0x30   */
  46 #define ESP_TCHI        0x38UL          /* rw  High bits of transfer count    0x38   */
  47 #define ESP_UID         ESP_TCHI        /* ro  Unique ID code                 0x38   */
  48 #define FAS_RLO         ESP_TCHI        /* rw  HME extended counter           0x38   */
  49 #define ESP_FGRND       0x3cUL          /* rw  Data base for fifo             0x3c   */
  50 #define FAS_RHI         ESP_FGRND       /* rw  HME extended counter           0x3c   */
  51 #define ESP_REG_SIZE    0x40UL
  52
  53 /* Various revisions of the ESP board. */
  54 enum esp_rev {
  55         esp100     = 0x00,  /* NCR53C90 - very broken */
  56         esp100a    = 0x01,  /* NCR53C90A */
  57         esp236     = 0x02,
  58         fas236     = 0x03,
  59         fas100a    = 0x04,
  60         fast       = 0x05,
  61         fashme     = 0x06,
  62         espunknown = 0x07
  63 };
  64
  65 /* Bitfield meanings for the above registers. */
  66
  67 /* ESP config reg 1, read-write, found on all ESP chips */
  68 #define ESP_CONFIG1_ID        0x07             /* My BUS ID bits */
  69 #define ESP_CONFIG1_CHTEST    0x08             /* Enable ESP chip tests */
  70 #define ESP_CONFIG1_PENABLE   0x10             /* Enable parity checks */
  71 #define ESP_CONFIG1_PARTEST   0x20             /* Parity test mode enabled? */
  72 #define ESP_CONFIG1_SRRDISAB  0x40             /* Disable SCSI reset reports */
  73 #define ESP_CONFIG1_SLCABLE   0x80             /* Enable slow cable mode */
  74
  75 /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */
  76 #define ESP_CONFIG2_DMAPARITY 0x01             /* enable DMA Parity (200,236) */
  77 #define ESP_CONFIG2_REGPARITY 0x02             /* enable reg Parity (200,236) */
  78 #define ESP_CONFIG2_BADPARITY 0x04             /* Bad parity target abort  */
  79 #define ESP_CONFIG2_SCSI2ENAB 0x08             /* Enable SCSI-2 features (tmode only) */
  80 #define ESP_CONFIG2_HI        0x10             /* High Impedance DREQ ???  */
  81 #define ESP_CONFIG2_HMEFENAB  0x10             /* HME features enable */
  82 #define ESP_CONFIG2_BCM       0x20             /* Enable byte-ctrl (236)   */
  83 #define ESP_CONFIG2_DISPINT   0x20             /* Disable pause irq (hme) */
  84 #define ESP_CONFIG2_FENAB     0x40             /* Enable features (fas100,esp216)      */
  85 #define ESP_CONFIG2_SPL       0x40             /* Enable status-phase latch (esp236)   */
  86 #define ESP_CONFIG2_MKDONE    0x40             /* HME magic feature */
  87 #define ESP_CONFIG2_HME32     0x80             /* HME 32 extended */
  88 #define ESP_CONFIG2_MAGIC     0xe0             /* Invalid bits... */
  89
  90 /* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */
  91 #define ESP_CONFIG3_FCLOCK    0x01             /* FAST SCSI clock rate (esp100a/hme) */
  92 #define ESP_CONFIG3_TEM       0x01             /* Enable thresh-8 mode (esp/fas236)  */
  93 #define ESP_CONFIG3_FAST      0x02             /* Enable FAST SCSI     (esp100a/hme) */
  94 #define ESP_CONFIG3_ADMA      0x02             /* Enable alternate-dma (esp/fas236)  */
  95 #define ESP_CONFIG3_TENB      0x04             /* group2 SCSI2 support (esp100a/hme) */
  96 #define ESP_CONFIG3_SRB       0x04             /* Save residual byte   (esp/fas236)  */
  97 #define ESP_CONFIG3_TMS       0x08             /* Three-byte msg's ok  (esp100a/hme) */
  98 #define ESP_CONFIG3_FCLK      0x08             /* Fast SCSI clock rate (esp/fas236)  */
  99 #define ESP_CONFIG3_IDMSG     0x10             /* ID message checking  (esp100a/hme) */
 100 #define ESP_CONFIG3_FSCSI     0x10             /* Enable FAST SCSI     (esp/fas236)  */
 101 #define ESP_CONFIG3_GTM       0x20             /* group2 SCSI2 support (esp/fas236)  */
 102 #define ESP_CONFIG3_IDBIT3    0x20             /* Bit 3 of HME SCSI-ID (hme)         */
 103 #define ESP_CONFIG3_TBMS      0x40             /* Three-byte msg's ok  (esp/fas236)  */
 104 #define ESP_CONFIG3_EWIDE     0x40             /* Enable Wide-SCSI     (hme)         */
 105 #define ESP_CONFIG3_IMS       0x80             /* ID msg chk'ng        (esp/fas236)  */
 106 #define ESP_CONFIG3_OBPUSH    0x80             /* Push odd-byte to dma (hme)         */
 107
 108 /* ESP command register read-write */
 109 /* Group 1 commands:  These may be sent at any point in time to the ESP
 110  *                    chip.  None of them can generate interrupts 'cept
 111  *                    the "SCSI bus reset" command if you have not disabled
 112  *                    SCSI reset interrupts in the config1 ESP register.
 113  */
 114 #define ESP_CMD_NULL          0x00             /* Null command, ie. a nop */
 115 #define ESP_CMD_FLUSH         0x01             /* FIFO Flush */
 116 #define ESP_CMD_RC            0x02             /* Chip reset */
 117 #define ESP_CMD_RS            0x03             /* SCSI bus reset */
 118
 119 /* Group 2 commands:  ESP must be an initiator and connected to a target
 120  *                    for these commands to work.
 121  */
 122 #define ESP_CMD_TI            0x10             /* Transfer Information */
 123 #define ESP_CMD_ICCSEQ        0x11             /* Initiator cmd complete sequence */
 124 #define ESP_CMD_MOK           0x12             /* Message okie-dokie */
 125 #define ESP_CMD_TPAD          0x18             /* Transfer Pad */
 126 #define ESP_CMD_SATN          0x1a             /* Set ATN */
 127 #define ESP_CMD_RATN          0x1b             /* De-assert ATN */
 128
 129 /* Group 3 commands:  ESP must be in the MSGOUT or MSGIN state and be connected
 130  *                    to a target as the initiator for these commands to work.
 131  */
 132 #define ESP_CMD_SMSG          0x20             /* Send message */
 133 #define ESP_CMD_SSTAT         0x21             /* Send status */
 134 #define ESP_CMD_SDATA         0x22             /* Send data */
 135 #define ESP_CMD_DSEQ          0x23             /* Discontinue Sequence */
 136 #define ESP_CMD_TSEQ          0x24             /* Terminate Sequence */
 137 #define ESP_CMD_TCCSEQ        0x25             /* Target cmd cmplt sequence */
 138 #define ESP_CMD_DCNCT         0x27             /* Disconnect */
 139 #define ESP_CMD_RMSG          0x28             /* Receive Message */
 140 #define ESP_CMD_RCMD          0x29             /* Receive Command */
 141 #define ESP_CMD_RDATA         0x2a             /* Receive Data */
 142 #define ESP_CMD_RCSEQ         0x2b             /* Receive cmd sequence */
 143
 144 /* Group 4 commands:  The ESP must be in the disconnected state and must
 145  *                    not be connected to any targets as initiator for
 146  *                    these commands to work.
 147  */
 148 #define ESP_CMD_RSEL          0x40             /* Reselect */
 149 #define ESP_CMD_SEL           0x41             /* Select w/o ATN */
 150 #define ESP_CMD_SELA          0x42             /* Select w/ATN */
 151 #define ESP_CMD_SELAS         0x43             /* Select w/ATN & STOP */
 152 #define ESP_CMD_ESEL          0x44             /* Enable selection */
 153 #define ESP_CMD_DSEL          0x45             /* Disable selections */
 154 #define ESP_CMD_SA3           0x46             /* Select w/ATN3 */
 155 #define ESP_CMD_RSEL3         0x47             /* Reselect3 */
 156
 157 /* This bit enables the ESP's DMA on the SBus */
 158 #define ESP_CMD_DMA           0x80             /* Do DMA? */
 159
 160
 161 /* ESP status register read-only */
 162 #define ESP_STAT_PIO          0x01             /* IO phase bit */
 163 #define ESP_STAT_PCD          0x02             /* CD phase bit */
 164 #define ESP_STAT_PMSG         0x04             /* MSG phase bit */
 165 #define ESP_STAT_PMASK        0x07             /* Mask of phase bits */
 166 #define ESP_STAT_TDONE        0x08             /* Transfer Completed */
 167 #define ESP_STAT_TCNT         0x10             /* Transfer Counter Is Zero */
 168 #define ESP_STAT_PERR         0x20             /* Parity error */
 169 #define ESP_STAT_SPAM         0x40             /* Real bad error */
 170 /* This indicates the 'interrupt pending' condition on esp236, it is a reserved
 171  * bit on other revs of the ESP.
 172  */
 173 #define ESP_STAT_INTR         0x80             /* Interrupt */
 174
 175 /* HME only: status 2 register */
 176 #define ESP_STAT2_SCHBIT      0x01 /* Upper bits 3-7 of sstep enabled */
 177 #define ESP_STAT2_FFLAGS      0x02 /* The fifo flags are now latched */
 178 #define ESP_STAT2_XCNT        0x04 /* The transfer counter is latched */
 179 #define ESP_STAT2_CREGA       0x08 /* The command reg is active now */
 180 #define ESP_STAT2_WIDE        0x10 /* Interface on this adapter is wide */
 181 #define ESP_STAT2_F1BYTE      0x20 /* There is one byte at top of fifo */
 182 #define ESP_STAT2_FMSB        0x40 /* Next byte in fifo is most significant */
 183 #define ESP_STAT2_FEMPTY      0x80 /* FIFO is empty */
 184
 185 /* The status register can be masked with ESP_STAT_PMASK and compared
 186  * with the following values to determine the current phase the ESP
 187  * (at least thinks it) is in.  For our purposes we also add our own
 188  * software 'done' bit for our phase management engine.
 189  */
 190 #define ESP_DOP   (0)                                       /* Data Out  */
 191 #define ESP_DIP   (ESP_STAT_PIO)                            /* Data In   */
 192 #define ESP_CMDP  (ESP_STAT_PCD)                            /* Command   */
 193 #define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO)               /* Status    */
 194 #define ESP_MOP   (ESP_STAT_PMSG|ESP_STAT_PCD)              /* Message Out */
 195 #define ESP_MIP   (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */
 196
 197 /* ESP interrupt register read-only */
 198 #define ESP_INTR_S            0x01             /* Select w/o ATN */
 199 #define ESP_INTR_SATN         0x02             /* Select w/ATN */
 200 #define ESP_INTR_RSEL         0x04             /* Reselected */
 201 #define ESP_INTR_FDONE        0x08             /* Function done */
 202 #define ESP_INTR_BSERV        0x10             /* Bus service */
 203 #define ESP_INTR_DC           0x20             /* Disconnect */
 204 #define ESP_INTR_IC           0x40             /* Illegal command given */
 205 #define ESP_INTR_SR           0x80             /* SCSI bus reset detected */
 206
 207 /* Interrupt status macros */
 208 #define ESP_SRESET_IRQ(esp)  ((esp)->intreg & (ESP_INTR_SR))
 209 #define ESP_ILLCMD_IRQ(esp)  ((esp)->intreg & (ESP_INTR_IC))
 210 #define ESP_SELECT_WITH_ATN_IRQ(esp)     ((esp)->intreg & (ESP_INTR_SATN))
 211 #define ESP_SELECT_WITHOUT_ATN_IRQ(esp)  ((esp)->intreg & (ESP_INTR_S))
 212 #define ESP_SELECTION_IRQ(esp)  ((ESP_SELECT_WITH_ATN_IRQ(esp)) ||         \
 213                                  (ESP_SELECT_WITHOUT_ATN_IRQ(esp)))
 214 #define ESP_RESELECTION_IRQ(esp)         ((esp)->intreg & (ESP_INTR_RSEL))
 215
 216 /* ESP sequence step register read-only */
 217 #define ESP_STEP_VBITS        0x07             /* Valid bits */
 218 #define ESP_STEP_ASEL         0x00             /* Selection&Arbitrate cmplt */
 219 #define ESP_STEP_SID          0x01             /* One msg byte sent */
 220 #define ESP_STEP_NCMD         0x02             /* Was not in command phase */
 221 #define ESP_STEP_PPC          0x03             /* Early phase chg caused cmnd
 222                                                 * bytes to be lost
 223                                                 */
 224 #define ESP_STEP_FINI4        0x04             /* Command was sent ok */
 225
 226 /* Ho hum, some ESP's set the step register to this as well... */
 227 #define ESP_STEP_FINI5        0x05
 228 #define ESP_STEP_FINI6        0x06
 229 #define ESP_STEP_FINI7        0x07
 230
 231 /* ESP chip-test register read-write */
 232 #define ESP_TEST_TARG         0x01             /* Target test mode */
 233 #define ESP_TEST_INI          0x02             /* Initiator test mode */
 234 #define ESP_TEST_TS           0x04             /* Tristate test mode */
 235
 236 /* ESP unique ID register read-only, found on fas236+fas100a only */
 237 #define ESP_UID_F100A         0x00             /* ESP FAS100A  */
 238 #define ESP_UID_F236          0x02             /* ESP FAS236   */
 239 #define ESP_UID_REV           0x07             /* ESP revision */
 240 #define ESP_UID_FAM           0xf8             /* ESP family   */
 241
 242 /* ESP fifo flags register read-only */
 243 /* Note that the following implies a 16 byte FIFO on the ESP. */
 244 #define ESP_FF_FBYTES         0x1f             /* Num bytes in FIFO */
 245 #define ESP_FF_ONOTZERO       0x20             /* offset ctr not zero (esp100) */
 246 #define ESP_FF_SSTEP          0xe0             /* Sequence step */
 247
 248 /* ESP clock conversion factor register write-only */
 249 #define ESP_CCF_F0            0x00             /* 35.01MHz - 40MHz */
 250 #define ESP_CCF_NEVER         0x01             /* Set it to this and die */
 251 #define ESP_CCF_F2            0x02             /* 10MHz */
 252 #define ESP_CCF_F3            0x03             /* 10.01MHz - 15MHz */
 253 #define ESP_CCF_F4            0x04             /* 15.01MHz - 20MHz */
 254 #define ESP_CCF_F5            0x05             /* 20.01MHz - 25MHz */
 255 #define ESP_CCF_F6            0x06             /* 25.01MHz - 30MHz */
 256 #define ESP_CCF_F7            0x07             /* 30.01MHz - 35MHz */
 257
 258 /* HME only... */
 259 #define ESP_BUSID_RESELID     0x10
 260 #define ESP_BUSID_CTR32BIT    0x40
 261
 262 #define ESP_BUS_TIMEOUT        275             /* In milli-seconds */
 263 #define ESP_TIMEO_CONST       8192
 264 #define ESP_NEG_DEFP(mhz, cfact) \
 265         ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
 266 #define ESP_MHZ_TO_CYCLE(mhertz)  ((1000000000) / ((mhertz) / 1000))
 267 #define ESP_TICK(ccf, cycle)  ((7682 * (ccf) * (cycle) / 1000))
 268
 269 #endif /* !(_SPARC_ESP_H) */