1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2007,2008 Øyvind Harboe *
8 * oyvind.harboe@zylin.com *
10 * Copyright (C) 2011 by Drasko DRASKOVIC *
11 * drasko.draskovic@gmail.com *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
33 #include "breakpoints.h"
34 #include "algorithm.h"
37 static char* mips32_core_reg_list
[] =
39 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
40 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
41 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
42 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
43 "status", "lo", "hi", "badvaddr", "cause", "pc"
46 static const char *mips_isa_strings
[] =
51 static struct mips32_core_reg mips32_core_reg_list_arch_info
[MIPS32NUMCOREREGS
] =
94 /* number of mips dummy fp regs fp0 - fp31 + fsr and fir
95 * we also add 18 unknown registers to handle gdb requests */
97 #define MIPS32NUMFPREGS 34 + 18
99 static uint8_t mips32_gdb_dummy_fp_value
[] = {0, 0, 0, 0};
101 static struct reg mips32_gdb_dummy_fp_reg
=
103 .name
= "GDB dummy floating-point register",
104 .value
= mips32_gdb_dummy_fp_value
,
111 static int mips32_get_core_reg(struct reg
*reg
)
114 struct mips32_core_reg
*mips32_reg
= reg
->arch_info
;
115 struct target
*target
= mips32_reg
->target
;
116 struct mips32_common
*mips32_target
= target_to_mips32(target
);
118 if (target
->state
!= TARGET_HALTED
)
120 return ERROR_TARGET_NOT_HALTED
;
123 retval
= mips32_target
->read_core_reg(target
, mips32_reg
->num
);
128 static int mips32_set_core_reg(struct reg
*reg
, uint8_t *buf
)
130 struct mips32_core_reg
*mips32_reg
= reg
->arch_info
;
131 struct target
*target
= mips32_reg
->target
;
132 uint32_t value
= buf_get_u32(buf
, 0, 32);
134 if (target
->state
!= TARGET_HALTED
)
136 return ERROR_TARGET_NOT_HALTED
;
139 buf_set_u32(reg
->value
, 0, 32, value
);
146 static int mips32_read_core_reg(struct target
*target
, int num
)
150 /* get pointers to arch-specific information */
151 struct mips32_common
*mips32
= target_to_mips32(target
);
153 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
154 return ERROR_COMMAND_SYNTAX_ERROR
;
156 reg_value
= mips32
->core_regs
[num
];
157 buf_set_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
158 mips32
->core_cache
->reg_list
[num
].valid
= 1;
159 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
164 static int mips32_write_core_reg(struct target
*target
, int num
)
168 /* get pointers to arch-specific information */
169 struct mips32_common
*mips32
= target_to_mips32(target
);
171 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
172 return ERROR_COMMAND_SYNTAX_ERROR
;
174 reg_value
= buf_get_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32);
175 mips32
->core_regs
[num
] = reg_value
;
176 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", num
, reg_value
);
177 mips32
->core_cache
->reg_list
[num
].valid
= 1;
178 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
183 int mips32_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[], int *reg_list_size
)
185 /* get pointers to arch-specific information */
186 struct mips32_common
*mips32
= target_to_mips32(target
);
189 /* include floating point registers */
190 *reg_list_size
= MIPS32NUMCOREREGS
+ MIPS32NUMFPREGS
;
191 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
193 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
195 (*reg_list
)[i
] = &mips32
->core_cache
->reg_list
[i
];
198 /* add dummy floating points regs */
199 for (i
= MIPS32NUMCOREREGS
; i
< (MIPS32NUMCOREREGS
+ MIPS32NUMFPREGS
); i
++)
201 (*reg_list
)[i
] = &mips32_gdb_dummy_fp_reg
;
207 int mips32_save_context(struct target
*target
)
211 /* get pointers to arch-specific information */
212 struct mips32_common
*mips32
= target_to_mips32(target
);
213 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
215 /* read core registers */
216 mips32_pracc_read_regs(ejtag_info
, mips32
->core_regs
);
218 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
220 if (!mips32
->core_cache
->reg_list
[i
].valid
)
222 mips32
->read_core_reg(target
, i
);
229 int mips32_restore_context(struct target
*target
)
233 /* get pointers to arch-specific information */
234 struct mips32_common
*mips32
= target_to_mips32(target
);
235 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
237 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
239 if (mips32
->core_cache
->reg_list
[i
].dirty
)
241 mips32
->write_core_reg(target
, i
);
245 /* write core regs */
246 mips32_pracc_write_regs(ejtag_info
, mips32
->core_regs
);
251 int mips32_arch_state(struct target
*target
)
253 struct mips32_common
*mips32
= target_to_mips32(target
);
255 LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32
"",
256 mips_isa_strings
[mips32
->isa_mode
],
257 debug_reason_name(target
),
258 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
263 static const struct reg_arch_type mips32_reg_type
= {
264 .get
= mips32_get_core_reg
,
265 .set
= mips32_set_core_reg
,
268 struct reg_cache
*mips32_build_reg_cache(struct target
*target
)
270 /* get pointers to arch-specific information */
271 struct mips32_common
*mips32
= target_to_mips32(target
);
273 int num_regs
= MIPS32NUMCOREREGS
;
274 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
275 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
276 struct reg
*reg_list
= malloc(sizeof(struct reg
) * num_regs
);
277 struct mips32_core_reg
*arch_info
= malloc(sizeof(struct mips32_core_reg
) * num_regs
);
280 register_init_dummy(&mips32_gdb_dummy_fp_reg
);
282 /* Build the process context cache */
283 cache
->name
= "mips32 registers";
285 cache
->reg_list
= reg_list
;
286 cache
->num_regs
= num_regs
;
288 mips32
->core_cache
= cache
;
290 for (i
= 0; i
< num_regs
; i
++)
292 arch_info
[i
] = mips32_core_reg_list_arch_info
[i
];
293 arch_info
[i
].target
= target
;
294 arch_info
[i
].mips32_common
= mips32
;
295 reg_list
[i
].name
= mips32_core_reg_list
[i
];
296 reg_list
[i
].size
= 32;
297 reg_list
[i
].value
= calloc(1, 4);
298 reg_list
[i
].dirty
= 0;
299 reg_list
[i
].valid
= 0;
300 reg_list
[i
].type
= &mips32_reg_type
;
301 reg_list
[i
].arch_info
= &arch_info
[i
];
307 int mips32_init_arch_info(struct target
*target
, struct mips32_common
*mips32
, struct jtag_tap
*tap
)
309 target
->arch_info
= mips32
;
310 mips32
->common_magic
= MIPS32_COMMON_MAGIC
;
311 mips32
->fast_data_area
= NULL
;
313 /* has breakpoint/watchpint unit been scanned */
314 mips32
->bp_scanned
= 0;
315 mips32
->data_break_list
= NULL
;
317 mips32
->ejtag_info
.tap
= tap
;
318 mips32
->read_core_reg
= mips32_read_core_reg
;
319 mips32
->write_core_reg
= mips32_write_core_reg
;
324 /* run to exit point. return error if exit point was not reached. */
325 static int mips32_run_and_wait(struct target
*target
, uint32_t entry_point
,
326 int timeout_ms
, uint32_t exit_point
, struct mips32_common
*mips32
)
330 /* This code relies on the target specific resume() and poll()->debug_entry()
331 * sequence to write register values to the processor and the read them back */
332 if ((retval
= target_resume(target
, 0, entry_point
, 0, 1)) != ERROR_OK
)
337 retval
= target_wait_state(target
, TARGET_HALTED
, timeout_ms
);
338 /* If the target fails to halt due to the breakpoint, force a halt */
339 if (retval
!= ERROR_OK
|| target
->state
!= TARGET_HALTED
)
341 if ((retval
= target_halt(target
)) != ERROR_OK
)
343 if ((retval
= target_wait_state(target
, TARGET_HALTED
, 500)) != ERROR_OK
)
347 return ERROR_TARGET_TIMEOUT
;
350 pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
351 if (exit_point
&& (pc
!= exit_point
))
353 LOG_DEBUG("failed algorithm halted at 0x%" PRIx32
" ", pc
);
354 return ERROR_TARGET_TIMEOUT
;
360 int mips32_run_algorithm(struct target
*target
, int num_mem_params
,
361 struct mem_param
*mem_params
, int num_reg_params
,
362 struct reg_param
*reg_params
, uint32_t entry_point
,
363 uint32_t exit_point
, int timeout_ms
, void *arch_info
)
365 struct mips32_common
*mips32
= target_to_mips32(target
);
366 struct mips32_algorithm
*mips32_algorithm_info
= arch_info
;
367 enum mips32_isa_mode isa_mode
= mips32
->isa_mode
;
369 uint32_t context
[MIPS32NUMCOREREGS
];
371 int retval
= ERROR_OK
;
373 LOG_DEBUG("Running algorithm");
375 /* NOTE: mips32_run_algorithm requires that each algorithm uses a software breakpoint
376 * at the exit point */
378 if (mips32
->common_magic
!= MIPS32_COMMON_MAGIC
)
380 LOG_ERROR("current target isn't a MIPS32 target");
381 return ERROR_TARGET_INVALID
;
384 if (target
->state
!= TARGET_HALTED
)
386 LOG_WARNING("target not halted");
387 return ERROR_TARGET_NOT_HALTED
;
390 /* refresh core register cache */
391 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
393 if (!mips32
->core_cache
->reg_list
[i
].valid
)
394 mips32
->read_core_reg(target
, i
);
395 context
[i
] = buf_get_u32(mips32
->core_cache
->reg_list
[i
].value
, 0, 32);
398 for (i
= 0; i
< num_mem_params
; i
++)
400 if ((retval
= target_write_buffer(target
, mem_params
[i
].address
,
401 mem_params
[i
].size
, mem_params
[i
].value
)) != ERROR_OK
)
407 for (i
= 0; i
< num_reg_params
; i
++)
409 struct reg
*reg
= register_get_by_name(mips32
->core_cache
, reg_params
[i
].reg_name
, 0);
413 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
414 return ERROR_COMMAND_SYNTAX_ERROR
;
417 if (reg
->size
!= reg_params
[i
].size
)
419 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
420 reg_params
[i
].reg_name
);
421 return ERROR_COMMAND_SYNTAX_ERROR
;
424 mips32_set_core_reg(reg
, reg_params
[i
].value
);
427 mips32
->isa_mode
= mips32_algorithm_info
->isa_mode
;
429 retval
= mips32_run_and_wait(target
, entry_point
, timeout_ms
, exit_point
, mips32
);
431 if (retval
!= ERROR_OK
)
434 for (i
= 0; i
< num_mem_params
; i
++)
436 if (mem_params
[i
].direction
!= PARAM_OUT
)
438 if ((retval
= target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
,
439 mem_params
[i
].value
)) != ERROR_OK
)
446 for (i
= 0; i
< num_reg_params
; i
++)
448 if (reg_params
[i
].direction
!= PARAM_OUT
)
450 struct reg
*reg
= register_get_by_name(mips32
->core_cache
, reg_params
[i
].reg_name
, 0);
453 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
454 return ERROR_COMMAND_SYNTAX_ERROR
;
457 if (reg
->size
!= reg_params
[i
].size
)
459 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
460 reg_params
[i
].reg_name
);
461 return ERROR_COMMAND_SYNTAX_ERROR
;
464 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
468 /* restore everything we saved before */
469 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
472 regvalue
= buf_get_u32(mips32
->core_cache
->reg_list
[i
].value
, 0, 32);
473 if (regvalue
!= context
[i
])
475 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32
,
476 mips32
->core_cache
->reg_list
[i
].name
, context
[i
]);
477 buf_set_u32(mips32
->core_cache
->reg_list
[i
].value
,
479 mips32
->core_cache
->reg_list
[i
].valid
= 1;
480 mips32
->core_cache
->reg_list
[i
].dirty
= 1;
484 mips32
->isa_mode
= isa_mode
;
489 int mips32_examine(struct target
*target
)
491 struct mips32_common
*mips32
= target_to_mips32(target
);
493 if (!target_was_examined(target
))
495 target_set_examined(target
);
497 /* we will configure later */
498 mips32
->bp_scanned
= 0;
499 mips32
->num_inst_bpoints
= 0;
500 mips32
->num_data_bpoints
= 0;
501 mips32
->num_inst_bpoints_avail
= 0;
502 mips32
->num_data_bpoints_avail
= 0;
508 int mips32_configure_break_unit(struct target
*target
)
510 /* get pointers to arch-specific information */
511 struct mips32_common
*mips32
= target_to_mips32(target
);
513 uint32_t dcr
, bpinfo
;
516 if (mips32
->bp_scanned
)
519 /* get info about breakpoint support */
520 if ((retval
= target_read_u32(target
, EJTAG_DCR
, &dcr
)) != ERROR_OK
)
523 if (dcr
& EJTAG_DCR_IB
)
525 /* get number of inst breakpoints */
526 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &bpinfo
)) != ERROR_OK
)
529 mips32
->num_inst_bpoints
= (bpinfo
>> 24) & 0x0F;
530 mips32
->num_inst_bpoints_avail
= mips32
->num_inst_bpoints
;
531 mips32
->inst_break_list
= calloc(mips32
->num_inst_bpoints
, sizeof(struct mips32_comparator
));
532 for (i
= 0; i
< mips32
->num_inst_bpoints
; i
++)
534 mips32
->inst_break_list
[i
].reg_address
= EJTAG_IBA1
+ (0x100 * i
);
538 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
542 if (dcr
& EJTAG_DCR_DB
)
544 /* get number of data breakpoints */
545 if ((retval
= target_read_u32(target
, EJTAG_DBS
, &bpinfo
)) != ERROR_OK
)
548 mips32
->num_data_bpoints
= (bpinfo
>> 24) & 0x0F;
549 mips32
->num_data_bpoints_avail
= mips32
->num_data_bpoints
;
550 mips32
->data_break_list
= calloc(mips32
->num_data_bpoints
, sizeof(struct mips32_comparator
));
551 for (i
= 0; i
< mips32
->num_data_bpoints
; i
++)
553 mips32
->data_break_list
[i
].reg_address
= EJTAG_DBA1
+ (0x100 * i
);
557 if ((retval
= target_write_u32(target
, EJTAG_DBS
, 0)) != ERROR_OK
)
561 /* check if target endianness settings matches debug control register */
562 if ( ( (dcr
& EJTAG_DCR_ENM
) && (target
->endianness
== TARGET_LITTLE_ENDIAN
) ) ||
563 ( !(dcr
& EJTAG_DCR_ENM
) && (target
->endianness
== TARGET_BIG_ENDIAN
) ) )
565 LOG_WARNING("DCR endianness settings does not match target settings");
568 LOG_DEBUG("DCR 0x%" PRIx32
" numinst %i numdata %i", dcr
, mips32
->num_inst_bpoints
,
569 mips32
->num_data_bpoints
);
571 mips32
->bp_scanned
= 1;
576 int mips32_enable_interrupts(struct target
*target
, int enable
)
582 /* read debug control register */
583 if ((retval
= target_read_u32(target
, EJTAG_DCR
, &dcr
)) != ERROR_OK
)
588 if (!(dcr
& EJTAG_DCR_INTE
))
590 /* enable interrupts */
591 dcr
|= EJTAG_DCR_INTE
;
597 if (dcr
& EJTAG_DCR_INTE
)
599 /* disable interrupts */
600 dcr
&= ~EJTAG_DCR_INTE
;
607 if ((retval
= target_write_u32(target
, EJTAG_DCR
, dcr
)) != ERROR_OK
)
614 int mips32_checksum_memory(struct target
*target
, uint32_t address
,
615 uint32_t count
, uint32_t* checksum
)
617 struct working_area
*crc_algorithm
;
618 struct reg_param reg_params
[2];
619 struct mips32_algorithm mips32_info
;
623 /* see contib/loaders/checksum/mips32.s for src */
625 static const uint32_t mips_crc_code
[] =
627 0x248C0000, /* addiu $t4, $a0, 0 */
628 0x24AA0000, /* addiu $t2, $a1, 0 */
629 0x2404FFFF, /* addiu $a0, $zero, 0xffffffff */
630 0x10000010, /* beq $zero, $zero, ncomp */
631 0x240B0000, /* addiu $t3, $zero, 0 */
633 0x81850000, /* lb $a1, ($t4) */
634 0x218C0001, /* addi $t4, $t4, 1 */
635 0x00052E00, /* sll $a1, $a1, 24 */
636 0x3C0204C1, /* lui $v0, 0x04c1 */
637 0x00852026, /* xor $a0, $a0, $a1 */
638 0x34471DB7, /* ori $a3, $v0, 0x1db7 */
639 0x00003021, /* addu $a2, $zero, $zero */
641 0x00044040, /* sll $t0, $a0, 1 */
642 0x24C60001, /* addiu $a2, $a2, 1 */
643 0x28840000, /* slti $a0, $a0, 0 */
644 0x01074826, /* xor $t1, $t0, $a3 */
645 0x0124400B, /* movn $t0, $t1, $a0 */
646 0x28C30008, /* slti $v1, $a2, 8 */
647 0x1460FFF9, /* bne $v1, $zero, loop */
648 0x01002021, /* addu $a0, $t0, $zero */
650 0x154BFFF0, /* bne $t2, $t3, nbyte */
651 0x256B0001, /* addiu $t3, $t3, 1 */
652 0x7000003F, /* sdbbp */
655 /* make sure we have a working area */
656 if (target_alloc_working_area(target
, sizeof(mips_crc_code
), &crc_algorithm
) != ERROR_OK
)
658 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
661 /* convert flash writing code into a buffer in target endianness */
662 for (i
= 0; i
< ARRAY_SIZE(mips_crc_code
); i
++)
663 target_write_u32(target
, crc_algorithm
->address
+ i
*sizeof(uint32_t), mips_crc_code
[i
]);
665 mips32_info
.common_magic
= MIPS32_COMMON_MAGIC
;
666 mips32_info
.isa_mode
= MIPS32_ISA_MIPS32
;
668 init_reg_param(®_params
[0], "a0", 32, PARAM_IN_OUT
);
669 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
671 init_reg_param(®_params
[1], "a1", 32, PARAM_OUT
);
672 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
674 int timeout
= 20000 * (1 + (count
/ (1024 * 1024)));
676 if ((retval
= target_run_algorithm(target
, 0, NULL
, 2, reg_params
,
677 crc_algorithm
->address
, crc_algorithm
->address
+ (sizeof(mips_crc_code
)-4), timeout
,
678 &mips32_info
)) != ERROR_OK
)
680 destroy_reg_param(®_params
[0]);
681 destroy_reg_param(®_params
[1]);
682 target_free_working_area(target
, crc_algorithm
);
686 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
688 destroy_reg_param(®_params
[0]);
689 destroy_reg_param(®_params
[1]);
691 target_free_working_area(target
, crc_algorithm
);
696 /** Checks whether a memory region is zeroed. */
697 int mips32_blank_check_memory(struct target
*target
,
698 uint32_t address
, uint32_t count
, uint32_t* blank
)
700 struct working_area
*erase_check_algorithm
;
701 struct reg_param reg_params
[3];
702 struct mips32_algorithm mips32_info
;
706 static const uint32_t erase_check_code
[] =
709 0x80880000, /* lb $t0, ($a0) */
710 0x00C83024, /* and $a2, $a2, $t0 */
711 0x24A5FFFF, /* addiu $a1, $a1, -1 */
712 0x14A0FFFC, /* bne $a1, $zero, nbyte */
713 0x24840001, /* addiu $a0, $a0, 1 */
714 0x7000003F /* sdbbp */
717 /* make sure we have a working area */
718 if (target_alloc_working_area(target
, sizeof(erase_check_code
), &erase_check_algorithm
) != ERROR_OK
)
720 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
723 /* convert flash writing code into a buffer in target endianness */
724 for (i
= 0; i
< ARRAY_SIZE(erase_check_code
); i
++)
726 target_write_u32(target
, erase_check_algorithm
->address
+ i
*sizeof(uint32_t),
727 erase_check_code
[i
]);
730 mips32_info
.common_magic
= MIPS32_COMMON_MAGIC
;
731 mips32_info
.isa_mode
= MIPS32_ISA_MIPS32
;
733 init_reg_param(®_params
[0], "a0", 32, PARAM_OUT
);
734 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
736 init_reg_param(®_params
[1], "a1", 32, PARAM_OUT
);
737 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
739 init_reg_param(®_params
[2], "a2", 32, PARAM_IN_OUT
);
740 buf_set_u32(reg_params
[2].value
, 0, 32, 0xff);
742 if ((retval
= target_run_algorithm(target
, 0, NULL
, 3, reg_params
,
743 erase_check_algorithm
->address
,
744 erase_check_algorithm
->address
+ (sizeof(erase_check_code
)-2),
745 10000, &mips32_info
)) != ERROR_OK
)
747 destroy_reg_param(®_params
[0]);
748 destroy_reg_param(®_params
[1]);
749 destroy_reg_param(®_params
[2]);
750 target_free_working_area(target
, erase_check_algorithm
);
754 *blank
= buf_get_u32(reg_params
[2].value
, 0, 32);
756 destroy_reg_param(®_params
[0]);
757 destroy_reg_param(®_params
[1]);
758 destroy_reg_param(®_params
[2]);
760 target_free_working_area(target
, erase_check_algorithm
);
765 static int mips32_verify_pointer(struct command_context
*cmd_ctx
,
766 struct mips32_common
*mips32
)
768 if (mips32
->common_magic
!= MIPS32_COMMON_MAGIC
) {
769 command_print(cmd_ctx
, "target is not an MIPS32");
770 return ERROR_TARGET_INVALID
;
776 * MIPS32 targets expose command interface
777 * to manipulate CP0 registers
779 COMMAND_HANDLER(mips32_handle_cp0_command
)
782 struct target
*target
= get_current_target(CMD_CTX
);
783 struct mips32_common
*mips32
= target_to_mips32(target
);
784 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
787 retval
= mips32_verify_pointer(CMD_CTX
, mips32
);
788 if (retval
!= ERROR_OK
)
791 if (target
->state
!= TARGET_HALTED
)
793 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
797 /* two or more argument, access a single register/select (write if third argument is given) */
800 command_print(CMD_CTX
, "command requires more arguments.");
804 uint32_t cp0_reg
, cp0_sel
;
805 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], cp0_reg
);
806 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], cp0_sel
);
812 if ((retval
= mips32_cp0_read(ejtag_info
, &value
, cp0_reg
, cp0_sel
)) != ERROR_OK
)
814 command_print(CMD_CTX
,
815 "couldn't access reg %" PRIi32
,
819 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
824 command_print(CMD_CTX
, "cp0 reg %" PRIi32
", select %" PRIi32
": %8.8" PRIx32
,
825 cp0_reg
, cp0_sel
, value
);
827 else if (CMD_ARGC
== 3)
830 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
831 if ((retval
= mips32_cp0_write(ejtag_info
, value
, cp0_reg
, cp0_sel
)) != ERROR_OK
)
833 command_print(CMD_CTX
,
834 "couldn't access cp0 reg %" PRIi32
", select %" PRIi32
,
838 command_print(CMD_CTX
, "cp0 reg %" PRIi32
", select %" PRIi32
": %8.8" PRIx32
,
839 cp0_reg
, cp0_sel
, value
);
846 static const struct command_registration mips32_exec_command_handlers
[] = {
849 .handler
= mips32_handle_cp0_command
,
850 .mode
= COMMAND_EXEC
,
851 .usage
= "regnum select [value]",
852 .help
= "display/modify cp0 register",
854 COMMAND_REGISTRATION_DONE
857 const struct command_registration mips32_command_handlers
[] = {
861 .help
= "mips32 command group",
862 .chain
= mips32_exec_command_handlers
,
864 COMMAND_REGISTRATION_DONE