usr/src/uts/common/sys/miiregs.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  */
  25
  26 /*
  27  * Definitions for MII registers from 802.3u and vendor documentation
  28  */
  29
  30 #ifndef _MIIREGS_H
  31 #define _MIIREGS_H
  32
  33 #pragma ident   "%Z%%M% %I%     %E% SMI"
  34
  35 #ifdef __cplusplus
  36 extern "C" {
  37 #endif
  38
  39 /* Register addresses: Section 22.2.4 */
  40 #define MII_CONTROL             0
  41 #define MII_STATUS              1
  42 #define MII_PHYIDH              2
  43 #define MII_PHYIDL              3
  44 #define MII_AN_ADVERT           4       /* Auto negotiation advertisement. */
  45 #define MII_AN_LPABLE           5       /* Auto neg. Link Partner Ability  */
  46 #define MII_AN_EXPANSION        6       /* Auto neg. Expansion.            */
  47 #define MII_AN_NXTPGXMIT        7       /* Auto neg. Next Page Transmit    */
  48 #define MII_RESERVED            8       /* Reserved up to 16               */
  49 #define MII_VENDOR(x)           (16+(x)) /* Vendor specific                */
  50
  51 /* Control register: 22.2.4.1 */
  52 #define MII_CONTROL_RESET       (1<<15)
  53 #define MII_CONTROL_LOOPBACK    (1<<14)
  54 #define MII_CONTROL_100MB       (1<<13)
  55 #define MII_CONTROL_ANE         (1<<12)
  56 #define MII_CONTROL_PWRDN       (1<<11)
  57 #define MII_CONTROL_ISOLATE     (1<<10)
  58 #define MII_CONTROL_RSAN        (1<<9)
  59 #define MII_CONTROL_FDUPLEX     (1<<8)
  60 #define MII_CONTROL_COLTST      (1<<7)
  61 #define MII_CONTROL_RESERVED    0x7f
  62
  63 /* Status register: 22.2.4.2 */
  64 #define MII_STATUS_100_BASE_T4  (1<<15)
  65 #define MII_STATUS_100_BASEX_FD (1<<14)
  66 #define MII_STATUS_100_BASEX    (1<<13)
  67 #define MII_STATUS_10_FD        (1<<12)
  68 #define MII_STATUS_10           (1<<11)
  69 #define MII_STATUS_RESERVED     (0xf<<7)
  70 #define MII_STATUS_MFPRMBLSUPR  (1<<6)
  71 #define MII_STATUS_ANDONE       (1<<5)
  72 #define MII_STATUS_REMFAULT     (1<<4)
  73 #define MII_STATUS_CANAUTONEG   (1<<3)
  74 #define MII_STATUS_LINKUP       (1<<2)
  75 #define MII_STATUS_JABBERING    (1<<1)
  76 #define MII_STATUS_EXTENDED     (1<<0)
  77
  78 /* Advertisement/Partner ability registers: 28.2.4.1.3/4 */
  79
  80 #define MII_AN_ADVERT_NP        (1<<15)
  81 #define MII_AN_ADVERT_ACK       (1<<14)
  82 #define MII_AN_ADVERT_REMFAULT  (1<<13)
  83 #define MII_AN_ADVERT_RESERVED  (3<<11)
  84 #define MII_AN_ADVERT_FCS       (1<<10)
  85 #define MII_AN_ADVERT_TECHABLE  (0xff<<5)
  86 #define MII_AN_ADVERT_SELECTOR  (0x1f)
  87
  88 /* Technology field bits (above). From Annex 28B */
  89 #define MII_ABILITY_10BASE_T    (1<<5)
  90 #define MII_ABILITY_10BASE_T_FD (1<<6)
  91 #define MII_ABILITY_100BASE_TX  (1<<7)
  92 #define MII_ABILITY_100BASE_TX_FD (1<<8)
  93 #define MII_ABILITY_100BASE_T4  (1<<9)
  94
  95 /* Expansion register 28.2.4.1.5 */
  96 #define MII_AN_EXP_PARFAULT     (1<<4)  /* fault detected                 */
  97 #define MII_AN_EXP_LPCANNXTP    (1<<3)  /* Link partner is Next Page able */
  98 #define MII_AN_EXP_CANNXTPP     (1<<2)  /* Local is next page able        */
  99 #define MII_AN_EXP_PAGERCVD     (1<<1)  /* A new page has been recvd.     */
 100 #define MII_AN_EXP_LPCANAN      (1<<0)  /* LP can auto-negotiate          */
 101
 102 /*
 103  * Truncated OUIs as found in the PHY Identifier ( 22.2.4.3.1 ),
 104  * and known models (and their registers) from those manufacturers
 105  */
 106
 107 #define PHY_MANUFACTURER(x)     (((x) >> 10) & 0x3fffff) /* 22 bits, 10-31 */
 108 #define PHY_MODEL(x)            (((x) >> 4) & 0x3f)      /* 6 bits,4-9     */
 109 #define PHY_REVISION(x)         ((x) & 0xf)              /* 4 bits, 0-3    */
 110
 111 #define OUI_NATIONAL_SEMICONDUCTOR 0x80017
 112 #define NS_DP83840              0x00
 113 #define MII_83840_ADDR          25
 114 #define NS83840_ADDR_SPEED10    (1<<6)
 115 #define NS83840_ADDR_CONSTAT    (1<<5)
 116 #define NS83840_ADDR_ADDR       (0x1f<<0)
 117
 118 #define OUI_INTEL               0x0aa00
 119 #define INTEL_82553_CSTEP       0x35    /* A and B steps are non-standard */
 120 #define MII_82553_EX0           16
 121 #define I82553_EX0_FDUPLEX      (1<<0)
 122 #define I82553_EX0_100MB        (1<<1)
 123 #define I82553_EX0_WAKE         (1<<2)
 124 #define I82553_EX0_SQUELCH      (3<<3) /* 3:4 */
 125 #define I82553_EX0_REVCNTR      (7<<5) /* 5:7 */
 126 #define I82553_EX0_FRCFAIL      (1<<8)
 127 #define I82553_EX0_TEST         (0x1f<<9) /* 13:9 */
 128 #define I82553_EX0_LINKDIS      (1<<14)
 129 #define I82553_EX0_JABDIS       (1<<15)
 130
 131 #define MII_82553_EX1
 132 #define I82553_EX1_RESERVE      (0x1ff<<0) /* 0:8 */
 133 #define I82553_EX1_CH2EOF       (1<<9)
 134 #define I82553_EX1_MNCHSTR      (1<<10)
 135 #define I82553_EX1_EOP          (1<<11)
 136 #define I82553_EX1_BADCODE      (1<<12)
 137 #define I82553_EX1_INVALCODE    (1<<13)
 138 #define I82553_EX1_DCBALANCE    (1<<14)
 139 #define I82553_EX1_PAIRSKEW     (1<<15)
 140
 141 #define INTEL_82555             0x15
 142 #define INTEL_82562_EH          0x33
 143 #define INTEL_82562_ET          0x32
 144 #define INTEL_82562_EM          0x31
 145
 146 #define OUI_ICS                 0x57d
 147 #define ICS_1890                2
 148 #define ICS_1889                1
 149 #define ICS_EXCTRL              16
 150 #define ICS_EXCTRL_CMDOVRD      (1<<15)
 151 #define ICS_EXCTRL_PHYADDR      (0x1f<<6)
 152 #define ICS_EXCTRL_SCSTEST      (1<<5)
 153 #define ICS_EXCTRL_INVECTEST    (1<<2)
 154 #define ICS_EXCTRL_SCDISABLE    (1<<0)
 155
 156 #define ICS_QUICKPOLL           17
 157 #define ICS_QUICKPOLL_100MB     (1<<15)
 158 #define ICS_QUICKPOLL_FDUPLEX   (1<<14)
 159 #define ICS_QUICKPOLL_ANPROG    (7<<11)
 160 #define ICS_QUICKPOLL_RSE       (1<<10)
 161 #define ICS_QUICKPOLL_PLLLOCK   (1<<9)
 162 #define ICS_QUICKPOLL_FALSECD   (1<<8)
 163 #define ICS_QUICKPOLL_SYMINVAL  (1<<7)
 164 #define ICS_QUICKPOLL_SYMHALT   (1<<6)
 165 #define ICS_QUICKPOLL_PREMEND   (1<<5)
 166 #define ICS_QUICKPOLL_ANDONE    (1<<4)
 167 #define ICS_QUICKPOLL_RESERVED  (1<<3)
 168 #define ICS_QUICKPOLL_JABBER    (1<<2)
 169 #define ICS_QUICKPOLL_REMFAULT  (1<<1)
 170 #define ICS_QUICKPOLL_LINKSTAT  (1<<0)
 171
 172 #define ICS_10BASET             18
 173 #define ICS_10BASET_REMJABBER   (1<<15)
 174 #define ICS_10BASET_REVPOLARITY (1<<14)
 175 #define ICS_10BASET_RESERVED    (0xff<<6)
 176 #define ICS_10BASET_NOJABBER    (1<<5)
 177 #define ICS_10BASET_NORMLOOP    (1<<4)
 178 #define ICS_10BASET_NOAUTOPOLL  (1<<3)
 179 #define ICS_10BASET_NOSQE       (1<<2)
 180 #define ICS_10BASET_NOLINKLOSS  (1<<1)
 181 #define ICS_10BASET_NOSQUELCH   (1<<0)
 182
 183 #define ICS_EXCTRL2             19
 184 #define ICS_EXCTRL2_ISREPEATER  (1<<15)
 185 #define ICS_EXCTRL2_SOFTPRI     (1<<14)
 186 #define ICS_EXCTRL2_LPCANREMF   (1<<13)
 187 #define ICS_EXCTRL2_RMFSXMITED  (1<<10)
 188 #define ICS_EXCTRL2_ANPWRREMF   (1<<4)
 189 #define ICS_EXCTRL2_10BASETQUAL (1<<2)
 190 #define ICS_EXCTRL2_AUTOPWRDN   (1<<0)
 191
 192 #define OUI_DAVICOM             0x0606e
 193
 194 #define DM_SCR                  16
 195 #define DM_SCR_F_TX             (1<<10)
 196 #define DM_SCR_UTP              (1<<9)
 197 #define DM_SCR_F_LINK_100       (1<<7)
 198 #define DM_SCR_LED_CTL          (1<<5)
 199 #define DM_SCR_SMRST            (1<<3)
 200 #define DM_SCR_MFPSC            (1<<2)
 201 #define DM_SCR_SLEEP            (1<<1)
 202 #define DM_SCR_RLOUT            (1<<0)
 203
 204 #define DM_SCSR                 17
 205 #define DM_SCSR_100FDX          (1<<15)
 206 #define DM_SCSR_100HDX          (1<<14)
 207 #define DM_SCSR_10FDX           (1<<13)
 208 #define DM_SCSR_10HDX           (1<<12)
 209 #define DM_SCSR_PHYAD           (0x1f<<4)
 210 #define DM_SCSR_ANMB            (0x0f)
 211
 212 #define DM_10BT                 18
 213 #define DM_10BT_LB_EN           (1<<14)
 214 #define DM_10BT_HBE             (1<<13)
 215 #define DM_10BT_JABEN           (1<<11)
 216
 217 #ifdef __cplusplus
 218 }
 219 #endif
 220
 221 #endif /* _MIIREGS_H */