radio/src/targets/horus/sdram_driver.c

   1 /*
   2  * Copyright (C) OpenTX
   3  *
   4  * Based on code named
   5  *   th9x - http://code.google.com/p/th9x
   6  *   er9x - http://code.google.com/p/er9x
   7  *   gruvin9x - http://code.google.com/p/gruvin9x
   8  *
   9  * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  */
  20
  21 #include "board.h"
  22
  23 #define SDRAM_MEMORY_WIDTH    FMC_SDMemory_Width_16b
  24
  25 #define SDRAM_CAS_LATENCY    FMC_CAS_Latency_3
  26
  27 #define SDCLOCK_PERIOD    FMC_SDClock_Period_2
  28
  29 #define SDRAM_TIMEOUT     ((uint32_t)0xFFFF)
  30
  31 /**
  32   * @brief  FMC SDRAM Mode definition register defines
  33   */
  34 #define SDRAM_MODEREG_BURST_LENGTH_1             ((uint16_t)0x0000)
  35 #define SDRAM_MODEREG_BURST_LENGTH_2             ((uint16_t)0x0001)
  36 #define SDRAM_MODEREG_BURST_LENGTH_4             ((uint16_t)0x0002)
  37 #define SDRAM_MODEREG_BURST_LENGTH_8             ((uint16_t)0x0004)
  38 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
  39 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
  40 #define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
  41 #define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
  42 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
  43 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
  44 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
  45
  46 /**
  47   * @brief  FMC SDRAM Memory Read Burst feature
  48   */
  49 #define SDRAM_READBURST    FMC_Read_Burst_Disable
  50
  51 static void __Delay(__IO uint32_t nCount)
  52 {
  53   __IO uint32_t index = 0;
  54   for(index = (100000 * nCount); index != 0; index--)
  55   {
  56   }
  57 }
  58
  59 /**
  60   * @brief  Configures all SDRAM memory I/Os pins.
  61   * @param  None.
  62   * @retval None.
  63   */
  64 void SDRAM_GPIOConfig(void)
  65 {
  66         GPIO_InitTypeDef GPIO_InitStructure;
  67
  68         /* Enable GPIOs clock */
  69         RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD |
  70                                                  RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOG|RCC_AHB1Periph_GPIOH, ENABLE);
  71
  72         /*-- GPIOs Configuration -----------------------------------------------------*/
  73         /*
  74         +-------------------+--------------------+--------------------+--------------------+
  75         +                       SDRAM pins assignment                                      +
  76         +-------------------+--------------------+--------------------+--------------------+
  77         | PD0  <-> FMC_D2   | PE0  <-> FMC_NBL0  | PF0  <-> FMC_A0    | PG0  <-> FMC_A10   |
  78         | PD1  <-> FMC_D3   | PE1  <-> FMC_NBL1  | PF1  <-> FMC_A1    | PG1  <-> FMC_A11   |
  79         | PD8  <-> FMC_D13  | PE7  <-> FMC_D4    | PF2  <-> FMC_A2    | PG8  <-> FMC_SDCLK |
  80         | PD9  <-> FMC_D14  | PE8  <-> FMC_D5    | PF3  <-> FMC_A3    | PG15 <-> FMC_NCAS  |
  81         | PD10 <-> FMC_D15  | PE9  <-> FMC_D6    | PF4  <-> FMC_A4    |--------------------+
  82         | PD14 <-> FMC_D0   | PE10 <-> FMC_D7    | PF5  <-> FMC_A5    |
  83         | PD15 <-> FMC_D1   | PE11 <-> FMC_D8    | PF11 <-> FMC_NRAS  |
  84         +-------------------| PE12 <-> FMC_D9    | PF12 <-> FMC_A6    |
  85                                          | PE13 <-> FMC_D10   | PF13 <-> FMC_A7    |
  86                                          | PE14 <-> FMC_D11   | PF14 <-> FMC_A8    |
  87                                          | PE15 <-> FMC_D12   | PF15 <-> FMC_A9    |
  88         +-------------------+--------------------+--------------------+
  89         | PB5 <-> FMC_SDCKE1|
  90         | PB6 <-> FMC_SDNE1 |
  91         | PH5 <-> FMC_SDNWE |///////
  92         +-------------------+
  93
  94         */
  95
  96         /* Common GPIO configuration */
  97         GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AF;
  98         GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  99         GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
 100         GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
 101
 102         /* GPIOB configuration */
 103         GPIO_PinAFConfig(GPIOB, GPIO_PinSource5 , GPIO_AF_FMC);
 104
 105         GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 ;
 106
 107         GPIO_Init(GPIOB, &GPIO_InitStructure);
 108
 109         /* GPIOC configuration */
 110         GPIO_PinAFConfig(GPIOH, GPIO_PinSource5 , GPIO_AF_FMC);
 111
 112         GPIO_PinAFConfig(GPIOH, GPIO_PinSource6 , GPIO_AF_FMC);
 113
 114         GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6;
 115
 116         GPIO_Init(GPIOH, &GPIO_InitStructure);
 117
 118         /* GPIOD configuration */
 119         GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC);
 120         GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC);
 121         GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC);
 122         GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC);
 123         GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC);
 124         GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC);
 125         GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC);
 126
 127         GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1  | GPIO_Pin_8 |
 128                                                                 GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 |
 129                                                                 GPIO_Pin_15;
 130
 131         GPIO_Init(GPIOD, &GPIO_InitStructure);
 132
 133         /* GPIOE configuration */
 134         GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC);
 135         GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC);
 136         GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC);
 137         GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC);
 138         GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC);
 139         GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC);
 140         GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC);
 141         GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC);
 142         GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC);
 143         GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC);
 144         GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC);
 145
 146         GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0  | GPIO_Pin_1  | GPIO_Pin_7 |
 147                                                                 GPIO_Pin_8  | GPIO_Pin_9  | GPIO_Pin_10 |
 148                                                                 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
 149                                                                 GPIO_Pin_14 | GPIO_Pin_15;
 150
 151         GPIO_Init(GPIOE, &GPIO_InitStructure);
 152
 153         /* GPIOF configuration */
 154         GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC);
 155         GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC);
 156         GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC);
 157         GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC);
 158         GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC);
 159         GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC);
 160         GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC);
 161         GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC);
 162         GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC);
 163         GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC);
 164         GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC);
 165
 166         GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0  | GPIO_Pin_1 | GPIO_Pin_2 |
 167                                                                 GPIO_Pin_3  | GPIO_Pin_4 | GPIO_Pin_5 |
 168                                                                 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
 169                                                                 GPIO_Pin_14 | GPIO_Pin_15;
 170
 171         GPIO_Init(GPIOF, &GPIO_InitStructure);
 172
 173         /* GPIOG configuration */
 174         GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC);
 175         GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC);
 176         GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC);
 177         GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC);
 178         GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC);
 179         GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC);
 180
 181
 182         GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 |
 183                                                                 GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15;
 184
 185         GPIO_Init(GPIOG, &GPIO_InitStructure);
 186 }
 187
 188 /**
 189   * @brief  Executes the SDRAM memory initialization sequence.
 190   * @param  None.
 191   * @retval None.
 192   */
 193 void SDRAM_InitSequence(void)
 194 {
 195   FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
 196   uint32_t tmpr = 0;
 197   uint32_t timeout = SDRAM_TIMEOUT;
 198
 199   /* Step 3 --------------------------------------------------------------------*/
 200   /* Configure a clock configuration enable command */
 201   FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled;
 202   FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1;
 203   FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
 204   FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
 205   /* Wait until the SDRAM controller is ready */
 206   while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0))
 207   {
 208     timeout--;
 209   }
 210   /* Send the command */
 211   FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
 212
 213   /* Step 4 --------------------------------------------------------------------*/
 214   /* Insert 100 ms delay */
 215   __Delay(10);
 216
 217   /* Step 5 --------------------------------------------------------------------*/
 218   /* Configure a PALL (precharge all) command */
 219   FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL;
 220   FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1;
 221   FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
 222   FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
 223
 224   /* Wait until the SDRAM controller is ready */
 225   timeout = SDRAM_TIMEOUT;
 226   while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0))
 227   {
 228     timeout--;
 229   }
 230   /* Send the command */
 231   FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
 232
 233 /* Step 6 --------------------------------------------------------------------*/
 234   /* Configure a Auto-Refresh command */
 235   FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh;
 236   FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1;
 237   FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 8;
 238   FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
 239
 240   /* Wait until the SDRAM controller is ready */
 241   timeout = SDRAM_TIMEOUT;
 242   while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0))
 243   {
 244     timeout--;
 245   }
 246   /* Send the command */
 247   FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
 248
 249 /* Step 7 --------------------------------------------------------------------*/
 250   /* Program the external memory mode register */
 251   tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1          |
 252                    SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL   |
 253                    SDRAM_MODEREG_CAS_LATENCY_3           |
 254                    SDRAM_MODEREG_OPERATING_MODE_STANDARD |
 255                    SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
 256
 257   /* Configure a load Mode register command*/
 258   FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode;
 259   FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1;
 260   FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
 261   FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr;
 262
 263   /* Wait until the SDRAM controller is ready */
 264   timeout = SDRAM_TIMEOUT;
 265   while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0))
 266   {
 267     timeout--;
 268   }
 269   /* Send the command */
 270   FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
 271
 272   /* Step 8 --------------------------------------------------------------------*/
 273
 274   /* Set the refresh rate counter */
 275   /* (15.62 us x Freq) - 20 */
 276   /* Set the device refresh counter */
 277   FMC_SetRefreshCount(1385);
 278
 279   /* Wait until the SDRAM controller is ready */
 280   timeout = SDRAM_TIMEOUT;
 281   while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0))
 282   {
 283     timeout--;
 284   }
 285 }
 286
 287 /**
 288   * @brief  Executes the SDRAM memory initialization sequence.
 289   * @param  None.
 290   * @retval None.
 291   */
 292 void SDRAMTest_InitSequence(void)
 293 {
 294   FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
 295   uint32_t tmpr = 0;
 296
 297 /* Step 3 --------------------------------------------------------------------*/
 298   /* Configure a clock configuration enable command */
 299   FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled;
 300   FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
 301   FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
 302   FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
 303   /* Wait until the SDRAM controller is ready */
 304   while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
 305   {
 306   }
 307   /* Send the command */
 308   FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
 309
 310 /* Step 4 --------------------------------------------------------------------*/
 311   /* Insert 100 ms delay */
 312   __Delay(10);
 313
 314 /* Step 5 --------------------------------------------------------------------*/
 315   /* Configure a PALL (precharge all) command */
 316   FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL;
 317   FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
 318   FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
 319   FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
 320   /* Wait until the SDRAM controller is ready */
 321   while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
 322   {
 323   }
 324   /* Send the command */
 325   FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
 326
 327 /* Step 6 --------------------------------------------------------------------*/
 328   /* Configure a Auto-Refresh command */
 329   FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh;
 330   FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
 331   FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4;
 332   FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
 333   /* Wait until the SDRAM controller is ready */
 334   while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
 335   {
 336   }
 337   /* Send the  first command */
 338   FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
 339
 340   /* Wait until the SDRAM controller is ready */
 341   while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
 342   {
 343   }
 344   /* Send the second command */
 345   FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
 346
 347 /* Step 7 --------------------------------------------------------------------*/
 348   /* Program the external memory mode register */
 349   tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2          |
 350                    SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL   |
 351                    SDRAM_MODEREG_CAS_LATENCY_3           |
 352                    SDRAM_MODEREG_OPERATING_MODE_STANDARD |
 353                    SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
 354
 355   /* Configure a load Mode register command*/
 356   FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode;
 357   FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
 358   FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
 359   FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr;
 360   /* Wait until the SDRAM controller is ready */
 361   while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
 362   {
 363   }
 364   /* Send the command */
 365   FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
 366
 367 /* Step 8 --------------------------------------------------------------------*/
 368
 369   /* Set the refresh rate counter */
 370   /* (15.62 us x Freq) - 20 */
 371   /* Set the device refresh counter */
 372   FMC_SetRefreshCount(1386);
 373   /* Wait until the SDRAM controller is ready */
 374   while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
 375   {
 376   }
 377 }
 378
 379 void SDRAM_Init(void)
 380 {
 381   FMC_SDRAMInitTypeDef  FMC_SDRAMInitStructure;
 382   FMC_SDRAMTimingInitTypeDef  FMC_SDRAMTimingInitStructure;
 383
 384   /* GPIO configuration for FMC SDRAM bank */
 385   SDRAM_GPIOConfig();
 386
 387   /* Enable FMC clock */
 388   RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
 389
 390   /* FMC Configuration ---------------------------------------------------------*/
 391   /* FMC SDRAM Bank configuration */
 392   /* Timing configuration for 90 Mhz of SD clock frequency (168Mhz/2) */
 393   /* TMRD: 2 Clock cycles */
 394   FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay    = 2;
 395   /* TXSR: min=70ns (7x11.11ns) */
 396   FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7;
 397   /* TRAS: min=42ns (4x11.11ns) max=120k (ns) */
 398   FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime      = 4;
 399   /* TRC:  min=70 (7x11.11ns) */
 400   FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay        = 7;
 401   /* TWR:  min=1+ 7ns (1+1x11.11ns) */
 402   FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime    = 2;
 403   /* TRP:  20ns => 2x11.11ns */
 404   FMC_SDRAMTimingInitStructure.FMC_RPDelay              = 2;
 405   /* TRCD: 20ns => 2x11.11ns */
 406   FMC_SDRAMTimingInitStructure.FMC_RCDDelay             = 2;
 407
 408   /* FMC SDRAM control configuration */
 409   FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM;
 410   /* Row addressing: [7:0] */
 411   FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
 412   /* Column addressing: [11:0] */
 413   FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b;
 414   FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH;
 415   FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
 416   FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY;
 417   FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
 418   FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD;
 419   FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST;
 420   FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_0;
 421   FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
 422
 423   /* FMC SDRAM bank initialization */
 424   FMC_SDRAMInit(&FMC_SDRAMInitStructure);
 425
 426   /* FMC SDRAM device initialization sequence */
 427   SDRAMTest_InitSequence();
 428 }
 429
 430 #if 0
 431 void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize)
 432 {
 433   __IO uint32_t write_pointer = (uint32_t)uwWriteAddress;
 434
 435   FMC_SDRAMWriteProtectionConfig(FMC_Bank1_SDRAM, DISABLE);
 436
 437   while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET)
 438   {
 439   }
 440
 441   for (; uwBufferSize != 0; uwBufferSize--)
 442   {
 443
 444     *(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++;
 445
 446     write_pointer += 4;
 447   }
 448
 449 }
 450
 451 void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize)
 452 {
 453   __IO uint32_t write_pointer = (uint32_t)uwReadAddress;
 454
 455   while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET)
 456   {
 457   }
 458
 459   for(; uwBufferSize != 0x00; uwBufferSize--)
 460   {
 461    *pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer );
 462
 463     write_pointer += 4;
 464   }
 465 }
 466 #endif