rtl/verilog/or1200_ctrl.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  OR1200's Instruction decode                                 ////
   4 ////                                                              ////
   5 ////  This file is part of the OpenRISC 1200 project              ////
   6 ////  http://www.opencores.org/cores/or1k/                        ////
   7 ////                                                              ////
   8 ////  Description                                                 ////
   9 ////  Majority of instruction decoding is performed here.         ////
  10 ////                                                              ////
  11 ////  To Do:                                                      ////
  12 ////   - make it smaller and faster                               ////
  13 ////                                                              ////
  14 ////  Author(s):                                                  ////
  15 ////      - Damjan Lampret, lampret@opencores.org                 ////
  16 ////                                                              ////
  17 //////////////////////////////////////////////////////////////////////
  18 ////                                                              ////
  19 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
  20 ////                                                              ////
  21 //// This source file may be used and distributed without         ////
  22 //// restriction provided that this copyright statement is not    ////
  23 //// removed from the file and that any derivative work contains  ////
  24 //// the original copyright notice and the associated disclaimer. ////
  25 ////                                                              ////
  26 //// This source file is free software; you can redistribute it   ////
  27 //// and/or modify it under the terms of the GNU Lesser General   ////
  28 //// Public License as published by the Free Software Foundation; ////
  29 //// either version 2.1 of the License, or (at your option) any   ////
  30 //// later version.                                               ////
  31 ////                                                              ////
  32 //// This source is distributed in the hope that it will be       ////
  33 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  34 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  35 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  36 //// details.                                                     ////
  37 ////                                                              ////
  38 //// You should have received a copy of the GNU Lesser General    ////
  39 //// Public License along with this source; if not, download it   ////
  40 //// from http://www.opencores.org/lgpl.shtml                     ////
  41 ////                                                              ////
  42 //////////////////////////////////////////////////////////////////////
  43 //
  44 // CVS Revision History
  45 //
  46 // $Log$
  47 // Revision 1.6  2002/03/29 15:16:54  lampret
  48 // Some of the warnings fixed.
  49 //
  50 // Revision 1.5  2002/02/01 19:56:54  lampret
  51 // Fixed combinational loops.
  52 //
  53 // Revision 1.4  2002/01/28 01:15:59  lampret
  54 // Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
  55 //
  56 // Revision 1.3  2002/01/18 14:21:43  lampret
  57 // Fixed 'the NPC single-step fix'.
  58 //
  59 // Revision 1.2  2002/01/14 06:18:22  lampret
  60 // Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
  61 //
  62 // Revision 1.1  2002/01/03 08:16:15  lampret
  63 // New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
  64 //
  65 // Revision 1.14  2001/11/30 18:59:17  simons
  66 // force_dslot_fetch does not work -  allways zero.
  67 //
  68 // Revision 1.13  2001/11/20 18:46:15  simons
  69 // Break point bug fixed
  70 //
  71 // Revision 1.12  2001/11/18 08:36:28  lampret
  72 // For GDB changed single stepping and disabled trap exception.
  73 //
  74 // Revision 1.11  2001/11/13 10:02:21  lampret
  75 // Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
  76 //
  77 // Revision 1.10  2001/11/12 01:45:40  lampret
  78 // Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
  79 //
  80 // Revision 1.9  2001/11/10 03:43:57  lampret
  81 // Fixed exceptions.
  82 //
  83 // Revision 1.8  2001/10/21 17:57:16  lampret
  84 // Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
  85 //
  86 // Revision 1.7  2001/10/14 13:12:09  lampret
  87 // MP3 version.
  88 //
  89 // Revision 1.1.1.1  2001/10/06 10:18:36  igorm
  90 // no message
  91 //
  92 // Revision 1.2  2001/08/13 03:36:20  lampret
  93 // Added cfg regs. Moved all defines into one defines.v file. More cleanup.
  94 //
  95 // Revision 1.1  2001/08/09 13:39:33  lampret
  96 // Major clean-up.
  97 //
  98 //
  99
 100 // synopsys translate_off
 101 `include "timescale.v"
 102 // synopsys translate_on
 103 `include "or1200_defines.v"
 104
 105 module or1200_ctrl(
 106         // Clock and reset
 107         clk, rst,
 108
 109         // Internal i/f
 110         id_freeze, ex_freeze, wb_freeze, flushpipe, if_insn, ex_insn, branch_op, branch_taken,
 111         rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, rf_addrw, rfwb_op,
 112         wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
 113         multicycle, spr_addrimm, wbforw_valid, sig_syscall, sig_trap,
 114         force_dslot_fetch, no_more_dslot, ex_void, id_macrc_op, ex_macrc_op, rfe, except_illegal
 115 );
 116
 117 //
 118 // I/O
 119 //
 120 input                                   clk;
 121 input                                   rst;
 122 input                                   id_freeze;
 123 input                                   ex_freeze;
 124 input                                   wb_freeze;
 125 input                                   flushpipe;
 126 input   [31:0]                          if_insn;
 127 output  [31:0]                          ex_insn;
 128 output  [`OR1200_BRANCHOP_WIDTH-1:0]            branch_op;
 129 input                                           branch_taken;
 130 output  [`OR1200_REGFILE_ADDR_WIDTH-1:0]        rf_addrw;
 131 output  [`OR1200_REGFILE_ADDR_WIDTH-1:0]        rf_addra;
 132 output  [`OR1200_REGFILE_ADDR_WIDTH-1:0]        rf_addrb;
 133 output                                  rf_rda;
 134 output                                  rf_rdb;
 135 output  [`OR1200_ALUOP_WIDTH-1:0]               alu_op;
 136 output  [`OR1200_MACOP_WIDTH-1:0]               mac_op;
 137 output  [`OR1200_SHROTOP_WIDTH-1:0]             shrot_op;
 138 output  [`OR1200_RFWBOP_WIDTH-1:0]              rfwb_op;
 139 output  [31:0]                          wb_insn;
 140 output  [31:0]                          simm;
 141 output  [31:2]                          branch_addrofs;
 142 output  [31:0]                          lsu_addrofs;
 143 output  [`OR1200_SEL_WIDTH-1:0]         sel_a;
 144 output  [`OR1200_SEL_WIDTH-1:0]         sel_b;
 145 output  [`OR1200_LSUOP_WIDTH-1:0]               lsu_op;
 146 output  [`OR1200_COMPOP_WIDTH-1:0]              comp_op;
 147 output  [`OR1200_MULTICYCLE_WIDTH-1:0]          multicycle;
 148 output  [15:0]                          spr_addrimm;
 149 input                                   wbforw_valid;
 150 output                                  sig_syscall;
 151 output                                  sig_trap;
 152 output                                  force_dslot_fetch;
 153 output                                  no_more_dslot;
 154 output                                  ex_void;
 155 output                                  id_macrc_op;
 156 output                                  ex_macrc_op;
 157 output                                  rfe;
 158 output                                  except_illegal;
 159
 160 //
 161 // Internal wires and regs
 162 //
 163 reg     [`OR1200_BRANCHOP_WIDTH-1:0]            pre_branch_op;
 164 reg     [`OR1200_BRANCHOP_WIDTH-1:0]            branch_op;
 165 reg     [`OR1200_ALUOP_WIDTH-1:0]               alu_op;
 166 reg     [`OR1200_MACOP_WIDTH-1:0]               mac_op;
 167 reg     [`OR1200_SHROTOP_WIDTH-1:0]             shrot_op;
 168 reg     [31:0]                          id_insn;
 169 reg     [31:0]                          ex_insn;
 170 reg     [31:0]                          wb_insn;
 171 reg     [`OR1200_REGFILE_ADDR_WIDTH-1:0]        rf_addrw;
 172 reg     [`OR1200_REGFILE_ADDR_WIDTH-1:0]        wb_rfaddrw;
 173 reg     [`OR1200_RFWBOP_WIDTH-1:0]              rfwb_op;
 174 reg     [31:0]                          lsu_addrofs;
 175 reg     [`OR1200_SEL_WIDTH-1:0]         sel_a;
 176 reg     [`OR1200_SEL_WIDTH-1:0]         sel_b;
 177 reg                                     sel_imm;
 178 reg     [`OR1200_LSUOP_WIDTH-1:0]               lsu_op;
 179 reg     [`OR1200_COMPOP_WIDTH-1:0]              comp_op;
 180 reg     [`OR1200_MULTICYCLE_WIDTH-1:0]          multicycle;
 181 reg                                     imm_signextend;
 182 reg     [15:0]                          spr_addrimm;
 183 reg                                     sig_syscall;
 184 reg                                     sig_trap;
 185 reg                                     except_illegal;
 186 reg                                     ex_macrc_op;
 187 wire                                    id_void;
 188
 189 //
 190 // Register file read addresses
 191 //
 192 assign rf_addra = if_insn[20:16];
 193 assign rf_addrb = if_insn[15:11];
 194 assign rf_rda = if_insn[31];
 195 assign rf_rdb = if_insn[30];
 196
 197 //
 198 // Force fetch of delay slot instruction when jump/branch is preceeded by load/store
 199 // instructions
 200 //
 201 // SIMON
 202 // assign force_dslot_fetch = ((|pre_branch_op) & (|lsu_op));
 203 assign force_dslot_fetch = 1'b0;
 204 assign no_more_dslot = |branch_op & !id_void & branch_taken | (branch_op == `OR1200_BRANCHOP_RFE);
 205 assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16];
 206 assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16];
 207
 208 //
 209 // Sign/Zero extension of immediates
 210 //
 211 assign simm = (imm_signextend == 1'b1) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
 212
 213 //
 214 // Sign extension of branch offset
 215 //
 216 assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};
 217
 218 //
 219 // l.macrc in ID stage
 220 //
 221 assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MOVHI) & id_insn[16];
 222
 223 //
 224 //
 225 //
 226 assign rfe = (pre_branch_op == `OR1200_BRANCHOP_RFE) | (branch_op == `OR1200_BRANCHOP_RFE);
 227
 228 //
 229 // Generation of sel_a
 230 //
 231 always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
 232         if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
 233                 sel_a = `OR1200_SEL_EX_FORW;
 234         else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)
 235                 sel_a = `OR1200_SEL_WB_FORW;
 236         else
 237                 sel_a = `OR1200_SEL_RF;
 238
 239 //
 240 // Generation of sel_b
 241 //
 242 always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
 243         if (sel_imm)
 244                 sel_b = `OR1200_SEL_IMM;
 245         else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
 246                 sel_b = `OR1200_SEL_EX_FORW;
 247         else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
 248                 sel_b = `OR1200_SEL_WB_FORW;
 249         else
 250                 sel_b = `OR1200_SEL_RF;
 251
 252 //
 253 // l.macrc in EX stage
 254 //
 255 always @(posedge clk or posedge rst) begin
 256         if (rst)
 257                 ex_macrc_op <= #1 1'b0;
 258         else if (!ex_freeze & id_freeze | flushpipe)
 259                 ex_macrc_op <= #1 1'b0;
 260         else if (!ex_freeze)
 261                 ex_macrc_op <= #1 id_macrc_op;
 262 end
 263
 264 //
 265 // Decode of spr_addrimm
 266 //
 267 always @(posedge clk or posedge rst) begin
 268         if (rst)
 269                 spr_addrimm <= #1 16'h0000;
 270         else if (!ex_freeze & id_freeze | flushpipe)
 271                 spr_addrimm <= #1 16'h0000;
 272         else if (!ex_freeze) begin
 273                 case (id_insn[31:26])   // synopsys parallel_case
 274                         // l.mfspr
 275                         `OR1200_OR32_MFSPR:
 276                                 spr_addrimm <= #1 id_insn[15:0];
 277                         // l.mtspr
 278                         default:
 279                                 spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};
 280                 endcase
 281         end
 282 end
 283
 284 //
 285 // Decode of multicycle
 286 //
 287 always @(id_insn) begin
 288   case (id_insn[31:26])         // synopsys parallel_case
 289 `ifdef UNUSED
 290     // l.lwz
 291     `OR1200_OR32_LWZ:
 292       multicycle = `OR1200_TWO_CYCLES;
 293
 294     // l.lbz
 295     `OR1200_OR32_LBZ:
 296       multicycle = `OR1200_TWO_CYCLES;
 297
 298     // l.lbs
 299     `OR1200_OR32_LBS:
 300       multicycle = `OR1200_TWO_CYCLES;
 301
 302     // l.lhz
 303     `OR1200_OR32_LHZ:
 304       multicycle = `OR1200_TWO_CYCLES;
 305
 306     // l.lhs
 307     `OR1200_OR32_LHS:
 308       multicycle = `OR1200_TWO_CYCLES;
 309
 310     // l.sw
 311     `OR1200_OR32_SW:
 312       multicycle = `OR1200_TWO_CYCLES;
 313
 314     // l.sb
 315     `OR1200_OR32_SB:
 316       multicycle = `OR1200_TWO_CYCLES;
 317
 318     // l.sh
 319     `OR1200_OR32_SH:
 320       multicycle = `OR1200_TWO_CYCLES;
 321 `endif
 322     // ALU instructions except the one with immediate
 323     `OR1200_OR32_ALU:
 324       multicycle = id_insn[`OR1200_ALUMCYC_POS];
 325
 326     // Single cycle instructions
 327     default: begin
 328       multicycle = `OR1200_ONE_CYCLE;
 329     end
 330
 331   endcase
 332
 333 end
 334
 335 //
 336 // Decode of imm_signextend
 337 //
 338 always @(id_insn) begin
 339   case (id_insn[31:26])         // synopsys parallel_case
 340
 341         // l.addi
 342         `OR1200_OR32_ADDI:
 343                 imm_signextend = 1'b1;
 344
 345         // l.addic
 346         `OR1200_OR32_ADDIC:
 347                 imm_signextend = 1'b1;
 348
 349         // l.xori
 350         `OR1200_OR32_XORI:
 351                 imm_signextend = 1'b1;
 352
 353         // l.muli
 354         `OR1200_OR32_MULI:
 355                 imm_signextend = 1'b1;
 356
 357         // l.maci
 358         `OR1200_OR32_MACI:
 359                 imm_signextend = 1'b1;
 360
 361         // SFXX insns with immediate
 362         `OR1200_OR32_SFXXI:
 363                 imm_signextend = 1'b1;
 364
 365         // Instructions with no or zero extended immediate
 366         default: begin
 367                 imm_signextend = 1'b0;
 368         end
 369
 370 endcase
 371
 372 end
 373
 374 //
 375 // LSU addr offset
 376 //
 377 always @(lsu_op or ex_insn) begin
 378         lsu_addrofs[10:0] = ex_insn[10:0];
 379         case(lsu_op)    // synopsys parallel_case
 380                 `OR1200_LSUOP_SW, `OR1200_LSUOP_SH, `OR1200_LSUOP_SB :
 381                         lsu_addrofs[31:11] = {{16{ex_insn[25]}}, ex_insn[25:21]};
 382                 default :
 383                         lsu_addrofs[31:11] = {{16{ex_insn[15]}}, ex_insn[15:11]};
 384         endcase
 385 end
 386
 387 //
 388 // Register file write address
 389 //
 390 always @(posedge clk or posedge rst) begin
 391         if (rst)
 392                 rf_addrw <= #1 5'd0;
 393         else if (!ex_freeze & id_freeze)
 394                 rf_addrw <= #1 5'd00;
 395         else if (!ex_freeze)
 396                 case (pre_branch_op)    // synopsys parallel_case
 397                         `OR1200_BRANCHOP_JR, `OR1200_BRANCHOP_BAL:
 398                                 rf_addrw <= #1 5'd09;   // link register r9
 399                         default:
 400                                 rf_addrw <= #1 id_insn[25:21];
 401                 endcase
 402 end
 403
 404 //
 405 // rf_addrw in wb stage (used in forwarding logic)
 406 //
 407 always @(posedge clk or posedge rst) begin
 408         if (rst)
 409                 wb_rfaddrw <= #1 5'd0;
 410         else if (!wb_freeze)
 411                 wb_rfaddrw <= #1 rf_addrw;
 412 end
 413
 414 //
 415 // Instruction latch in id_insn
 416 //
 417 always @(posedge clk or posedge rst) begin
 418         if (rst)
 419                 id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
 420         else if (flushpipe)
 421                 id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};        // id_insn[16] must be 1
 422         else if (!id_freeze) begin
 423                 id_insn <= #1 if_insn;
 424 `ifdef OR1200_VERBOSE
 425 // synopsys translate_off
 426                 $display("%t: id_insn <= %h", $time, if_insn);
 427 // synopsys translate_on
 428 `endif
 429         end
 430 end
 431
 432 //
 433 // Instruction latch in ex_insn
 434 //
 435 always @(posedge clk or posedge rst) begin
 436         if (rst)
 437                 ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
 438         else if (!ex_freeze & id_freeze | flushpipe)
 439                 ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // ex_insn[16] must be 1
 440         else if (!ex_freeze) begin
 441                 ex_insn <= #1 id_insn;
 442 `ifdef OR1200_VERBOSE
 443 // synopsys translate_off
 444                 $display("%t: ex_insn <= %h", $time, id_insn);
 445 // synopsys translate_on
 446 `endif
 447         end
 448 end
 449
 450 //
 451 // Instruction latch in wb_insn
 452 //
 453 always @(posedge clk or posedge rst) begin
 454         if (rst)
 455                 wb_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
 456         else if (flushpipe)
 457                 wb_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // wb_insn[16] must be 1
 458         else if (!wb_freeze) begin
 459                 wb_insn <= #1 ex_insn;
 460         end
 461 end
 462
 463 //
 464 // Decode of sel_imm
 465 //
 466 always @(posedge clk or posedge rst) begin
 467         if (rst)
 468                 sel_imm <= #1 1'b0;
 469         else if (!id_freeze) begin
 470           case (if_insn[31:26])         // synopsys parallel_case
 471
 472             // j.jalr
 473             `OR1200_OR32_JALR:
 474               sel_imm <= #1 1'b0;
 475
 476             // l.jr
 477             `OR1200_OR32_JR:
 478               sel_imm <= #1 1'b0;
 479
 480             // l.rfe
 481             `OR1200_OR32_RFE:
 482               sel_imm <= #1 1'b0;
 483
 484             // l.mfspr
 485             `OR1200_OR32_MFSPR:
 486               sel_imm <= #1 1'b0;
 487
 488             // l.mtspr
 489             `OR1200_OR32_MTSPR:
 490               sel_imm <= #1 1'b0;
 491
 492             // l.sys, l.brk and all three sync insns
 493             `OR1200_OR32_XSYNC:
 494               sel_imm <= #1 1'b0;
 495
 496             // l.mac/l.msb
 497             `OR1200_OR32_MACMSB:
 498               sel_imm <= #1 1'b0;
 499
 500             // l.sw
 501             `OR1200_OR32_SW:
 502               sel_imm <= #1 1'b0;
 503
 504             // l.sb
 505             `OR1200_OR32_SB:
 506               sel_imm <= #1 1'b0;
 507
 508             // l.sh
 509             `OR1200_OR32_SH:
 510               sel_imm <= #1 1'b0;
 511
 512             // ALU instructions except the one with immediate
 513             `OR1200_OR32_ALU:
 514               sel_imm <= #1 1'b0;
 515
 516             // SFXX instructions
 517             `OR1200_OR32_SFXX:
 518               sel_imm <= #1 1'b0;
 519
 520             // l.nop
 521             `OR1200_OR32_NOP:
 522               sel_imm <= #1 1'b0;
 523
 524             // All instructions with immediates
 525             default: begin
 526               sel_imm <= #1 1'b1;
 527             end
 528
 529           endcase
 530
 531         end
 532 end
 533
 534 //
 535 // Decode of except_illegal
 536 //
 537 always @(posedge clk or posedge rst) begin
 538         if (rst)
 539                 except_illegal <= #1 1'b0;
 540         else if (!ex_freeze & id_freeze | flushpipe)
 541                 except_illegal <= #1 1'b0;
 542         else if (!ex_freeze) begin
 543           case (id_insn[31:26])         // synopsys parallel_case
 544
 545             `OR1200_OR32_J,
 546             `OR1200_OR32_JAL,
 547             `OR1200_OR32_JALR,
 548             `OR1200_OR32_JR,
 549             `OR1200_OR32_BNF,
 550             `OR1200_OR32_BF,
 551             `OR1200_OR32_RFE,
 552             `OR1200_OR32_MOVHI,
 553             `OR1200_OR32_MFSPR,
 554             `OR1200_OR32_XSYNC,
 555             `OR1200_OR32_MACI,
 556             `OR1200_OR32_LWZ,
 557             `OR1200_OR32_LBZ,
 558             `OR1200_OR32_LBS,
 559             `OR1200_OR32_LHZ,
 560             `OR1200_OR32_LHS,
 561             `OR1200_OR32_ADDI,
 562             `OR1200_OR32_ADDIC,
 563             `OR1200_OR32_ANDI,
 564             `OR1200_OR32_ORI,
 565             `OR1200_OR32_XORI,
 566             `OR1200_OR32_MULI,
 567             `OR1200_OR32_SH_ROTI,
 568             `OR1200_OR32_SFXXI,
 569             `OR1200_OR32_MTSPR,
 570             `OR1200_OR32_MACMSB,
 571             `OR1200_OR32_SW,
 572             `OR1200_OR32_SB,
 573             `OR1200_OR32_SH,
 574             `OR1200_OR32_ALU,
 575             `OR1200_OR32_SFXX,
 576             `OR1200_OR32_NOP:
 577                 except_illegal <= #1 1'b0;
 578
 579             // Illegal and OR1200 unsupported instructions
 580             default:
 581               except_illegal <= #1 1'b1;
 582
 583           endcase
 584
 585         end
 586 end
 587
 588 //
 589 // Decode of alu_op
 590 //
 591 always @(posedge clk or posedge rst) begin
 592         if (rst)
 593                 alu_op <= #1 `OR1200_ALUOP_NOP;
 594         else if (!ex_freeze & id_freeze | flushpipe)
 595                 alu_op <= #1 `OR1200_ALUOP_NOP;
 596         else if (!ex_freeze) begin
 597           case (id_insn[31:26])         // synopsys parallel_case
 598
 599             // l.j
 600             `OR1200_OR32_J:
 601               alu_op <= #1 `OR1200_ALUOP_IMM;
 602
 603             // j.jal
 604             `OR1200_OR32_JAL:
 605               alu_op <= #1 `OR1200_ALUOP_IMM;
 606
 607             // l.bnf
 608             `OR1200_OR32_BNF:
 609               alu_op <= #1 `OR1200_ALUOP_NOP;
 610
 611             // l.bf
 612             `OR1200_OR32_BF:
 613               alu_op <= #1 `OR1200_ALUOP_NOP;
 614
 615             // l.movhi
 616             `OR1200_OR32_MOVHI:
 617               alu_op <= #1 `OR1200_ALUOP_MOVHI;
 618
 619             // l.mfspr
 620             `OR1200_OR32_MFSPR:
 621               alu_op <= #1 `OR1200_ALUOP_MFSR;
 622
 623             // l.mtspr
 624             `OR1200_OR32_MTSPR:
 625               alu_op <= #1 `OR1200_ALUOP_MTSR;
 626
 627             // l.addi
 628             `OR1200_OR32_ADDI:
 629               alu_op <= #1 `OR1200_ALUOP_ADD;
 630
 631             // l.addic
 632             `OR1200_OR32_ADDIC:
 633               alu_op <= #1 `OR1200_ALUOP_ADD;
 634
 635             // l.andi
 636             `OR1200_OR32_ANDI:
 637               alu_op <= #1 `OR1200_ALUOP_AND;
 638
 639             // l.ori
 640             `OR1200_OR32_ORI:
 641               alu_op <= #1 `OR1200_ALUOP_OR;
 642
 643             // l.xori
 644             `OR1200_OR32_XORI:
 645               alu_op <= #1 `OR1200_ALUOP_XOR;
 646
 647             // l.muli
 648             `OR1200_OR32_MULI:
 649               alu_op <= #1 `OR1200_ALUOP_MUL;
 650
 651             // Shift and rotate insns with immediate
 652             `OR1200_OR32_SH_ROTI:
 653               alu_op <= #1 `OR1200_ALUOP_SHROT;
 654
 655             // SFXX insns with immediate
 656             `OR1200_OR32_SFXXI:
 657               alu_op <= #1 `OR1200_ALUOP_COMP;
 658
 659             // ALU instructions except the one with immediate
 660             `OR1200_OR32_ALU:
 661               alu_op <= #1 id_insn[3:0];
 662
 663             // SFXX instructions
 664             `OR1200_OR32_SFXX:
 665               alu_op <= #1 `OR1200_ALUOP_COMP;
 666
 667             // Default
 668             default: begin
 669               alu_op <= #1 `OR1200_ALUOP_NOP;
 670             end
 671
 672           endcase
 673
 674         end
 675 end
 676
 677 //
 678 // Decode of mac_op
 679 //
 680 always @(posedge clk or posedge rst) begin
 681         if (rst)
 682                 mac_op <= #1 `OR1200_MACOP_NOP;
 683         else if (!ex_freeze & id_freeze | flushpipe)
 684                 mac_op <= #1 `OR1200_MACOP_NOP;
 685         else if (!ex_freeze)
 686           case (id_insn[31:26])         // synopsys parallel_case
 687
 688             // l.maci
 689             `OR1200_OR32_MACI:
 690               mac_op <= #1 `OR1200_MACOP_MAC;
 691
 692             // l.nop
 693             `OR1200_OR32_MACMSB:
 694               mac_op <= #1 id_insn[1:0];
 695
 696             // Illegal and OR1200 unsupported instructions
 697             default: begin
 698               mac_op <= #1 `OR1200_MACOP_NOP;
 699             end
 700
 701           endcase
 702         else
 703                 mac_op <= #1 `OR1200_MACOP_NOP;
 704 end
 705
 706 //
 707 // Decode of shrot_op
 708 //
 709 always @(posedge clk or posedge rst) begin
 710         if (rst)
 711                 shrot_op <= #1 `OR1200_SHROTOP_NOP;
 712         else if (!ex_freeze & id_freeze | flushpipe)
 713                 shrot_op <= #1 `OR1200_SHROTOP_NOP;
 714         else if (!ex_freeze) begin
 715                 shrot_op <= #1 id_insn[`OR1200_SHROTOP_POS];
 716         end
 717 end
 718
 719 //
 720 // Decode of rfwb_op
 721 //
 722 always @(posedge clk or posedge rst) begin
 723         if (rst)
 724                 rfwb_op <= #1 `OR1200_RFWBOP_NOP;
 725         else  if (!ex_freeze & id_freeze | flushpipe)
 726                 rfwb_op <= #1 `OR1200_RFWBOP_NOP;
 727         else  if (!ex_freeze) begin
 728                 case (id_insn[31:26])           // synopsys parallel_case
 729
 730                   // j.jal
 731                   `OR1200_OR32_JAL:
 732                     rfwb_op <= #1 `OR1200_RFWBOP_LR;
 733
 734                   // j.jalr
 735                   `OR1200_OR32_JALR:
 736                     rfwb_op <= #1 `OR1200_RFWBOP_LR;
 737
 738                   // l.movhi
 739                   `OR1200_OR32_MOVHI:
 740                     rfwb_op <= #1 `OR1200_RFWBOP_ALU;
 741
 742                   // l.mfspr
 743                   `OR1200_OR32_MFSPR:
 744                     rfwb_op <= #1 `OR1200_RFWBOP_SPRS;
 745
 746                   // l.lwz
 747                   `OR1200_OR32_LWZ:
 748                     rfwb_op <= #1 `OR1200_RFWBOP_LSU;
 749
 750                   // l.lbz
 751                   `OR1200_OR32_LBZ:
 752                     rfwb_op <= #1 `OR1200_RFWBOP_LSU;
 753
 754                   // l.lbs
 755                   `OR1200_OR32_LBS:
 756                     rfwb_op <= #1 `OR1200_RFWBOP_LSU;
 757
 758                   // l.lhz
 759                   `OR1200_OR32_LHZ:
 760                     rfwb_op <= #1 `OR1200_RFWBOP_LSU;
 761
 762                   // l.lhs
 763                   `OR1200_OR32_LHS:
 764                     rfwb_op <= #1 `OR1200_RFWBOP_LSU;
 765
 766                   // l.addi
 767                   `OR1200_OR32_ADDI:
 768                     rfwb_op <= #1 `OR1200_RFWBOP_ALU;
 769
 770                   // l.addic
 771                   `OR1200_OR32_ADDIC:
 772                     rfwb_op <= #1 `OR1200_RFWBOP_ALU;
 773
 774                   // l.andi
 775                   `OR1200_OR32_ANDI:
 776                     rfwb_op <= #1 `OR1200_RFWBOP_ALU;
 777
 778                   // l.ori
 779                   `OR1200_OR32_ORI:
 780                     rfwb_op <= #1 `OR1200_RFWBOP_ALU;
 781
 782                   // l.xori
 783                   `OR1200_OR32_XORI:
 784                     rfwb_op <= #1 `OR1200_RFWBOP_ALU;
 785
 786                   // l.muli
 787                   `OR1200_OR32_MULI:
 788                     rfwb_op <= #1 `OR1200_RFWBOP_ALU;
 789
 790                   // Shift and rotate insns with immediate
 791                   `OR1200_OR32_SH_ROTI:
 792                     rfwb_op <= #1 `OR1200_RFWBOP_ALU;
 793
 794                   // ALU instructions except the one with immediate
 795                   `OR1200_OR32_ALU:
 796                     rfwb_op <= #1 `OR1200_RFWBOP_ALU;
 797
 798                   // Instructions w/o register-file write-back
 799                   default: begin
 800                     rfwb_op <= #1 `OR1200_RFWBOP_NOP;
 801                   end
 802
 803                 endcase
 804         end
 805 end
 806
 807 //
 808 // Decode of pre_branch_op
 809 //
 810 always @(posedge clk or posedge rst) begin
 811         if (rst)
 812                 pre_branch_op <= #1 `OR1200_BRANCHOP_NOP;
 813         else if (flushpipe)
 814                 pre_branch_op <= #1 `OR1200_BRANCHOP_NOP;
 815         else if (!id_freeze) begin
 816                 case (if_insn[31:26])           // synopsys parallel_case
 817
 818                   // l.j
 819                   `OR1200_OR32_J:
 820                     pre_branch_op <= #1 `OR1200_BRANCHOP_BAL;
 821
 822                   // j.jal
 823                   `OR1200_OR32_JAL:
 824                     pre_branch_op <= #1 `OR1200_BRANCHOP_BAL;
 825
 826                   // j.jalr
 827                   `OR1200_OR32_JALR:
 828                     pre_branch_op <= #1 `OR1200_BRANCHOP_JR;
 829
 830                   // l.jr
 831                   `OR1200_OR32_JR:
 832                     pre_branch_op <= #1 `OR1200_BRANCHOP_JR;
 833
 834                   // l.bnf
 835                   `OR1200_OR32_BNF:
 836                     pre_branch_op <= #1 `OR1200_BRANCHOP_BNF;
 837
 838                   // l.bf
 839                   `OR1200_OR32_BF:
 840                     pre_branch_op <= #1 `OR1200_BRANCHOP_BF;
 841
 842                   // l.rfe
 843                   `OR1200_OR32_RFE:
 844                     pre_branch_op <= #1 `OR1200_BRANCHOP_RFE;
 845
 846                   // Non branch instructions
 847                   default: begin
 848                     pre_branch_op <= #1 `OR1200_BRANCHOP_NOP;
 849                   end
 850                 endcase
 851         end
 852 end
 853
 854 //
 855 // Generation of branch_op
 856 //
 857 always @(posedge clk or posedge rst)
 858         if (rst)
 859                 branch_op <= #1 `OR1200_BRANCHOP_NOP;
 860         else if (!ex_freeze & id_freeze | flushpipe)
 861                 branch_op <= #1 `OR1200_BRANCHOP_NOP;
 862         else if (!ex_freeze)
 863                 branch_op <= #1 pre_branch_op;
 864
 865 //
 866 // Decode of lsu_op
 867 //
 868 always @(posedge clk or posedge rst) begin
 869         if (rst)
 870                 lsu_op <= #1 `OR1200_LSUOP_NOP;
 871         else if (!ex_freeze & id_freeze | flushpipe)
 872                 lsu_op <= #1 `OR1200_LSUOP_NOP;
 873         else if (!ex_freeze)  begin
 874           case (id_insn[31:26])         // synopsys parallel_case
 875
 876             // l.lwz
 877             `OR1200_OR32_LWZ:
 878               lsu_op <= #1 `OR1200_LSUOP_LWZ;
 879
 880             // l.lbz
 881             `OR1200_OR32_LBZ:
 882               lsu_op <= #1 `OR1200_LSUOP_LBZ;
 883
 884             // l.lbs
 885             `OR1200_OR32_LBS:
 886               lsu_op <= #1 `OR1200_LSUOP_LBS;
 887
 888             // l.lhz
 889             `OR1200_OR32_LHZ:
 890               lsu_op <= #1 `OR1200_LSUOP_LHZ;
 891
 892             // l.lhs
 893             `OR1200_OR32_LHS:
 894               lsu_op <= #1 `OR1200_LSUOP_LHS;
 895
 896             // l.sw
 897             `OR1200_OR32_SW:
 898               lsu_op <= #1 `OR1200_LSUOP_SW;
 899
 900             // l.sb
 901             `OR1200_OR32_SB:
 902               lsu_op <= #1 `OR1200_LSUOP_SB;
 903
 904             // l.sh
 905             `OR1200_OR32_SH:
 906               lsu_op <= #1 `OR1200_LSUOP_SH;
 907
 908             // Non load/store instructions
 909             default: begin
 910               lsu_op <= #1 `OR1200_LSUOP_NOP;
 911             end
 912           endcase
 913         end
 914 end
 915
 916 //
 917 // Decode of comp_op
 918 //
 919 always @(posedge clk or posedge rst) begin
 920         if (rst) begin
 921                 comp_op <= #1 4'd0;
 922         end else if (!ex_freeze & id_freeze | flushpipe)
 923                 comp_op <= #1 4'd0;
 924         else if (!ex_freeze)
 925                 comp_op <= #1 id_insn[24:21];
 926 end
 927
 928 //
 929 // Decode of l.sys
 930 //
 931 always @(posedge clk or posedge rst) begin
 932         if (rst)
 933                 sig_syscall <= #1 1'b0;
 934         else if (!ex_freeze & id_freeze | flushpipe)
 935                 sig_syscall <= #1 1'b0;
 936         else if (!ex_freeze) begin
 937 `ifdef OR1200_VERBOSE
 938 // synopsys translate_off
 939                 if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000})
 940                         $display("Generating sig_syscall");
 941 // synopsys translate_on
 942 `endif
 943                 sig_syscall <= #1 (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000});
 944         end
 945 end
 946
 947 //
 948 // Decode of l.trap
 949 //
 950 always @(posedge clk or posedge rst) begin
 951         if (rst)
 952                 sig_trap <= #1 1'b0;
 953         else if (!ex_freeze & id_freeze | flushpipe)
 954                 sig_trap <= #1 1'b0;
 955         else if (!ex_freeze) begin
 956 `ifdef OR1200_VERBOSE
 957 // synopsys translate_off
 958                 if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
 959                         $display("Generating sig_trap");
 960 // synopsys translate_on
 961 `endif
 962                 sig_trap <= #1 (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010});
 963         end
 964 end
 965
 966 endmodule